//===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //==-----------------------------------------------------------------------===// // // This file defines an instruction selector for the AMDIL target. // //===----------------------------------------------------------------------===// #include "AMDGPUISelLowering.h" // For AMDGPUISD #include "AMDILDevices.h" #include "AMDILUtilityFunctions.h" #include "llvm/ADT/ValueMap.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Support/Compiler.h" #include #include using namespace llvm; //===----------------------------------------------------------------------===// // Instruction Selector Implementation //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // AMDILDAGToDAGISel - AMDIL specific code to select AMDIL machine instructions // //for SelectionDAG operations. // namespace { class AMDILDAGToDAGISel : public SelectionDAGISel { // Subtarget - Keep a pointer to the AMDIL Subtarget around so that we can // make the right decision when generating code for different targets. const AMDILSubtarget &Subtarget; public: AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL); virtual ~AMDILDAGToDAGISel(); SDNode *Select(SDNode *N); virtual const char *getPassName() const; private: inline SDValue getSmallIPtrImm(unsigned Imm); // Complex pattern selectors bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2); bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2); bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2); static bool checkType(const Value *ptr, unsigned int addrspace); static const Value *getBasePointerValue(const Value *V); static bool isGlobalStore(const StoreSDNode *N); static bool isPrivateStore(const StoreSDNode *N); static bool isLocalStore(const StoreSDNode *N); static bool isRegionStore(const StoreSDNode *N); static bool isCPLoad(const LoadSDNode *N); static bool isConstantLoad(const LoadSDNode *N, int cbID); static bool isGlobalLoad(const LoadSDNode *N); static bool isPrivateLoad(const LoadSDNode *N); static bool isLocalLoad(const LoadSDNode *N); static bool isRegionLoad(const LoadSDNode *N); bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset); bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset); bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset); // Include the pieces autogenerated from the target description. #include "AMDGPUGenDAGISel.inc" }; } // end anonymous namespace // createAMDILISelDag - This pass converts a legalized DAG into a AMDIL-specific // DAG, ready for instruction scheduling. // FunctionPass *llvm::createAMDILISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL) { return new AMDILDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR); } AMDILDAGToDAGISel::AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL) : SelectionDAGISel(TM AMDIL_OPT_LEVEL_VAR), Subtarget(TM.getSubtarget()) { } AMDILDAGToDAGISel::~AMDILDAGToDAGISel() { } SDValue AMDILDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } bool AMDILDAGToDAGISel::SelectADDRParam( SDValue Addr, SDValue& R1, SDValue& R2) { if (Addr.getOpcode() == ISD::FrameIndex) { if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); R2 = CurDAG->getTargetConstant(0, MVT::i32); } else { R1 = Addr; R2 = CurDAG->getTargetConstant(0, MVT::i32); } } else if (Addr.getOpcode() == ISD::ADD) { R1 = Addr.getOperand(0); R2 = Addr.getOperand(1); } else { R1 = Addr; R2 = CurDAG->getTargetConstant(0, MVT::i32); } return true; } bool AMDILDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) { if (Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress) { return false; } return SelectADDRParam(Addr, R1, R2); } bool AMDILDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) { if (Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress) { return false; } if (Addr.getOpcode() == ISD::FrameIndex) { if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64); R2 = CurDAG->getTargetConstant(0, MVT::i64); } else { R1 = Addr; R2 = CurDAG->getTargetConstant(0, MVT::i64); } } else if (Addr.getOpcode() == ISD::ADD) { R1 = Addr.getOperand(0); R2 = Addr.getOperand(1); } else { R1 = Addr; R2 = CurDAG->getTargetConstant(0, MVT::i64); } return true; } SDNode *AMDILDAGToDAGISel::Select(SDNode *N) { unsigned int Opc = N->getOpcode(); if (N->isMachineOpcode()) { return NULL; // Already selected. } switch (Opc) { default: break; case ISD::FrameIndex: { if (FrameIndexSDNode *FIN = dyn_cast(N)) { unsigned int FI = FIN->getIndex(); EVT OpVT = N->getValueType(0); unsigned int NewOpc = AMDIL::COPY; SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32); return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI); } } break; } return SelectCode(N); } bool AMDILDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) { if (!ptr) { return false; } Type *ptrType = ptr->getType(); return dyn_cast(ptrType)->getAddressSpace() == addrspace; } const Value * AMDILDAGToDAGISel::getBasePointerValue(const Value *V) { if (!V) { return NULL; } const Value *ret = NULL; ValueMap ValueBitMap; std::queue > ValueQueue; ValueQueue.push(V); while (!ValueQueue.empty()) { V = ValueQueue.front(); if (ValueBitMap.find(V) == ValueBitMap.end()) { ValueBitMap[V] = true; if (dyn_cast(V) && dyn_cast(V->getType())) { ret = V; break; } else if (dyn_cast(V)) { ret = V; break; } else if (dyn_cast(V)) { const ConstantExpr *CE = dyn_cast(V); if (CE) { ValueQueue.push(CE->getOperand(0)); } } else if (const AllocaInst *AI = dyn_cast(V)) { ret = AI; break; } else if (const Instruction *I = dyn_cast(V)) { uint32_t numOps = I->getNumOperands(); for (uint32_t x = 0; x < numOps; ++x) { ValueQueue.push(I->getOperand(x)); } } else { // assert(0 && "Found a Value that we didn't know how to handle!"); } } ValueQueue.pop(); } return ret; } bool AMDILDAGToDAGISel::isGlobalStore(const StoreSDNode *N) { return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS); } bool AMDILDAGToDAGISel::isPrivateStore(const StoreSDNode *N) { return (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS)); } bool AMDILDAGToDAGISel::isLocalStore(const StoreSDNode *N) { return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS); } bool AMDILDAGToDAGISel::isRegionStore(const StoreSDNode *N) { return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS); } bool AMDILDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) { if (checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)) { return true; } MachineMemOperand *MMO = N->getMemOperand(); const Value *V = MMO->getValue(); const Value *BV = getBasePointerValue(V); if (MMO && MMO->getValue() && ((V && dyn_cast(V)) || (BV && dyn_cast( getBasePointerValue(MMO->getValue()))))) { return checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS); } else { return false; } } bool AMDILDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) { return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS); } bool AMDILDAGToDAGISel::isLocalLoad(const LoadSDNode *N) { return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS); } bool AMDILDAGToDAGISel::isRegionLoad(const LoadSDNode *N) { return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS); } bool AMDILDAGToDAGISel::isCPLoad(const LoadSDNode *N) { MachineMemOperand *MMO = N->getMemOperand(); if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) { if (MMO) { const Value *V = MMO->getValue(); const PseudoSourceValue *PSV = dyn_cast(V); if (PSV && PSV == PseudoSourceValue::getConstantPool()) { return true; } } } return false; } bool AMDILDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) { if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) { // Check to make sure we are not a constant pool load or a constant load // that is marked as a private load if (isCPLoad(N) || isConstantLoad(N, -1)) { return false; } } if (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::PARAM_D_ADDRESS) && !checkType(N->getSrcValue(), AMDILAS::PARAM_I_ADDRESS)) { return true; } return false; } const char *AMDILDAGToDAGISel::getPassName() const { return "AMDIL DAG->DAG Pattern Instruction Selection"; } #ifdef DEBUGTMP #undef INT64_C #endif #undef DEBUGTMP ///==== AMDGPU Functions ====/// bool AMDILDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset) { if (Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress) { return false; } if (Addr.getOpcode() == ISD::ADD) { bool Match = false; // Find the base ptr and the offset for (unsigned i = 0; i < Addr.getNumOperands(); i++) { SDValue Arg = Addr.getOperand(i); ConstantSDNode * OffsetNode = dyn_cast(Arg); // This arg isn't a constant so it must be the base PTR. if (!OffsetNode) { Base = Addr.getOperand(i); continue; } // Check if the constant argument fits in 8-bits. The offset is in bytes // so we need to convert it to dwords. if (isInt<8>(OffsetNode->getZExtValue() >> 2)) { Match = true; Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2, MVT::i32); } } return Match; } // Default case, no offset Base = Addr; Offset = CurDAG->getTargetConstant(0, MVT::i32); return true; } bool AMDILDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset) { ConstantSDNode * IMMOffset; if (Addr.getOpcode() == ISD::ADD && (IMMOffset = dyn_cast(Addr.getOperand(1))) && isInt<16>(IMMOffset->getZExtValue())) { Base = Addr.getOperand(0); Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32); return true; // If the pointer address is constant, we can move it to the offset field. } else if ((IMMOffset = dyn_cast(Addr)) && isInt<16>(IMMOffset->getZExtValue())) { Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), CurDAG->getEntryNode().getDebugLoc(), AMDIL::ZERO, MVT::i32); Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32); return true; } // Default case, no offset Base = Addr; Offset = CurDAG->getTargetConstant(0, MVT::i32); return true; } bool AMDILDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset) { if (Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress || Addr.getOpcode() != ISD::ADD) { return false; } Base = Addr.getOperand(0); Offset = Addr.getOperand(1); return false; }