//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains instruction defs that are common to all hw codegen
// targets.
//
//===----------------------------------------------------------------------===//

include "AMDGPUInstrEnums.td"

class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
  field bits<16> AMDILOp = 0;
  field bits<3> Gen = 0;

  let Namespace = "AMDIL";
  let OutOperandList = outs;
  let InOperandList = ins;
  let AsmString = asm;
  let Pattern = pattern;
  let TSFlags{42-40} = Gen;
  let TSFlags{63-48} = AMDILOp;
}

class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
    : AMDGPUInst<outs, ins, asm, pattern> {

  field bits<32> Inst = 0xffffffff;

}

let isCodeGenOnly = 1 in {

  def MASK_WRITE : AMDGPUShaderInst <
    (outs),
    (ins GPRF32:$src),
    "MASK_WRITE $src",
    []
  >;
}

/* Generic helper patterns for intrinsics */
/* -------------------------------------- */

class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
                  RegisterClass rc> : Pat <
  (int_AMDGPU_pow rc:$src0, rc:$src1),
  (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
>;

/* Other helper patterns */
/* --------------------- */

/* Extract element pattern */
class Extract_Element <ValueType sub_type, ValueType vec_type,
                     RegisterClass vec_class, int sub_idx, 
                     SubRegIndex sub_reg>: Pat<
  (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
  (EXTRACT_SUBREG vec_class:$src, sub_reg)
>;

/* Insert element pattern */
class Insert_Element <ValueType elem_type, ValueType vec_type,
                      RegisterClass elem_class, RegisterClass vec_class,
                      int sub_idx, SubRegIndex sub_reg> : Pat <

  (vec_type (vector_insert (vec_type vec_class:$vec),
                           (elem_type elem_class:$elem), sub_idx)),
  (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
>;

include "R600Instructions.td"

include "SIInstrInfo.td"