#ifndef STATE_3D_XML #define STATE_3D_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng headergen tool in this git repository: http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - state.xml ( 26666 bytes, from 2019-08-12 13:32:55) - common.xml ( 35468 bytes, from 2019-08-09 17:16:20) - common_3d.xml ( 14991 bytes, from 2019-09-12 20:32:47) - state_hi.xml ( 30396 bytes, from 2019-09-12 20:21:39) - copyright.xml ( 1597 bytes, from 2019-08-09 17:34:08) - state_2d.xml ( 51552 bytes, from 2019-08-09 17:34:00) - state_3d.xml ( 83069 bytes, from 2019-09-12 20:28:49) - state_blt.xml ( 14252 bytes, from 2019-09-12 20:21:39) - state_vg.xml ( 5975 bytes, from 2019-08-09 17:33:52) Copyright (C) 2012-2019 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach - Russell King Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define STENCIL_OP_KEEP 0x00000000 #define STENCIL_OP_ZERO 0x00000001 #define STENCIL_OP_REPLACE 0x00000002 #define STENCIL_OP_INCR 0x00000003 #define STENCIL_OP_DECR 0x00000004 #define STENCIL_OP_INVERT 0x00000005 #define STENCIL_OP_INCR_WRAP 0x00000006 #define STENCIL_OP_DECR_WRAP 0x00000007 #define BLEND_EQ_ADD 0x00000000 #define BLEND_EQ_SUBTRACT 0x00000001 #define BLEND_EQ_REVERSE_SUBTRACT 0x00000002 #define BLEND_EQ_MIN 0x00000003 #define BLEND_EQ_MAX 0x00000004 #define BLEND_FUNC_ZERO 0x00000000 #define BLEND_FUNC_ONE 0x00000001 #define BLEND_FUNC_SRC_COLOR 0x00000002 #define BLEND_FUNC_ONE_MINUS_SRC_COLOR 0x00000003 #define BLEND_FUNC_SRC_ALPHA 0x00000004 #define BLEND_FUNC_ONE_MINUS_SRC_ALPHA 0x00000005 #define BLEND_FUNC_DST_ALPHA 0x00000006 #define BLEND_FUNC_ONE_MINUS_DST_ALPHA 0x00000007 #define BLEND_FUNC_DST_COLOR 0x00000008 #define BLEND_FUNC_ONE_MINUS_DST_COLOR 0x00000009 #define BLEND_FUNC_SRC_ALPHA_SATURATE 0x0000000a #define BLEND_FUNC_CONSTANT_ALPHA 0x0000000b #define BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA 0x0000000c #define BLEND_FUNC_CONSTANT_COLOR 0x0000000d #define BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR 0x0000000e #define RS_FORMAT_X4R4G4B4 0x00000000 #define RS_FORMAT_A4R4G4B4 0x00000001 #define RS_FORMAT_X1R5G5B5 0x00000002 #define RS_FORMAT_A1R5G5B5 0x00000003 #define RS_FORMAT_R5G6B5 0x00000004 #define RS_FORMAT_X8R8G8B8 0x00000005 #define RS_FORMAT_A8R8G8B8 0x00000006 #define RS_FORMAT_YUY2 0x00000007 #define RS_FORMAT_64BPP_CLEAR 0x00000015 #define PE_FORMAT_X4R4G4B4 0x00000000 #define PE_FORMAT_A4R4G4B4 0x00000001 #define PE_FORMAT_X1R5G5B5 0x00000002 #define PE_FORMAT_A1R5G5B5 0x00000003 #define PE_FORMAT_R5G6B5 0x00000004 #define PE_FORMAT_X8R8G8B8 0x00000005 #define PE_FORMAT_A8R8G8B8 0x00000006 #define PE_FORMAT_YUY2 0x00000007 #define PE_FORMAT_A8 0x00000010 #define PE_FORMAT_R16F 0x00000011 #define PE_FORMAT_G16R16F 0x00000012 #define PE_FORMAT_A16B16G16R16F 0x00000013 #define PE_FORMAT_R32F 0x00000014 #define PE_FORMAT_G32R32F 0x00000015 #define PE_FORMAT_A2B10G10R10 0x00000016 #define PE_FORMAT_R8I 0x00000017 #define PE_FORMAT_G8R8I 0x00000018 #define PE_FORMAT_A8B8G8R8I 0x00000019 #define PE_FORMAT_R16I 0x0000001a #define PE_FORMAT_G16R16I 0x0000001b #define PE_FORMAT_A16B16G16R16I 0x0000001c #define PE_FORMAT_B10G11R11F 0x0000001d #define PE_FORMAT_A2B10G10R10UI 0x0000001e #define PE_FORMAT_G8R8 0x0000001f #define PE_FORMAT_R8 0x00000023 #define LOGIC_OP_CLEAR 0x00000000 #define LOGIC_OP_NOR 0x00000001 #define LOGIC_OP_AND_INVERTED 0x00000002 #define LOGIC_OP_COPY_INVERTED 0x00000003 #define LOGIC_OP_AND_REVERSE 0x00000004 #define LOGIC_OP_INVERT 0x00000005 #define LOGIC_OP_XOR 0x00000006 #define LOGIC_OP_NAND 0x00000007 #define LOGIC_OP_AND 0x00000008 #define LOGIC_OP_EQUIV 0x00000009 #define LOGIC_OP_NOOP 0x0000000a #define LOGIC_OP_OR_INVERTED 0x0000000b #define LOGIC_OP_COPY 0x0000000c #define LOGIC_OP_OR_REVERSE 0x0000000d #define LOGIC_OP_OR 0x0000000e #define LOGIC_OP_SET 0x0000000f #define COLOR_OUTPUT_MODE_NORMAL 0x00000000 #define COLOR_OUTPUT_MODE_A2B10G10R10UI 0x00000001 #define COLOR_OUTPUT_MODE_UIF32 0x00000002 #define COLOR_OUTPUT_MODE_U8 0x00000003 #define COLOR_OUTPUT_MODE_U16 0x00000004 #define COLOR_OUTPUT_MODE_I8 0x00000005 #define COLOR_OUTPUT_MODE_I16 0x00000006 #define VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007 #define VARYING_NUM_COMPONENTS_VAR0__SHIFT 0 #define VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK) #define VARYING_NUM_COMPONENTS_VAR1__MASK 0x00000070 #define VARYING_NUM_COMPONENTS_VAR1__SHIFT 4 #define VARYING_NUM_COMPONENTS_VAR1(x) (((x) << VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VARYING_NUM_COMPONENTS_VAR1__MASK) #define VARYING_NUM_COMPONENTS_VAR2__MASK 0x00000700 #define VARYING_NUM_COMPONENTS_VAR2__SHIFT 8 #define VARYING_NUM_COMPONENTS_VAR2(x) (((x) << VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VARYING_NUM_COMPONENTS_VAR2__MASK) #define VARYING_NUM_COMPONENTS_VAR3__MASK 0x00007000 #define VARYING_NUM_COMPONENTS_VAR3__SHIFT 12 #define VARYING_NUM_COMPONENTS_VAR3(x) (((x) << VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VARYING_NUM_COMPONENTS_VAR3__MASK) #define VARYING_NUM_COMPONENTS_VAR4__MASK 0x00070000 #define VARYING_NUM_COMPONENTS_VAR4__SHIFT 16 #define VARYING_NUM_COMPONENTS_VAR4(x) (((x) << VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VARYING_NUM_COMPONENTS_VAR4__MASK) #define VARYING_NUM_COMPONENTS_VAR5__MASK 0x00700000 #define VARYING_NUM_COMPONENTS_VAR5__SHIFT 20 #define VARYING_NUM_COMPONENTS_VAR5(x) (((x) << VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VARYING_NUM_COMPONENTS_VAR5__MASK) #define VARYING_NUM_COMPONENTS_VAR6__MASK 0x07000000 #define VARYING_NUM_COMPONENTS_VAR6__SHIFT 24 #define VARYING_NUM_COMPONENTS_VAR6(x) (((x) << VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VARYING_NUM_COMPONENTS_VAR6__MASK) #define VARYING_NUM_COMPONENTS_VAR7__MASK 0x70000000 #define VARYING_NUM_COMPONENTS_VAR7__SHIFT 28 #define VARYING_NUM_COMPONENTS_VAR7(x) (((x) << VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VARYING_NUM_COMPONENTS_VAR7__MASK) #define VIVS_VS 0x00000000 #define VIVS_VS_END_PC 0x00000800 #define VIVS_VS_OUTPUT_COUNT 0x00000804 #define VIVS_VS_INPUT_COUNT 0x00000808 #define VIVS_VS_INPUT_COUNT_COUNT__MASK 0x0000000f #define VIVS_VS_INPUT_COUNT_COUNT__SHIFT 0 #define VIVS_VS_INPUT_COUNT_COUNT(x) (((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK) #define VIVS_VS_INPUT_COUNT_UNK8__MASK 0x00001f00 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT 8 #define VIVS_VS_INPUT_COUNT_UNK8(x) (((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK) #define VIVS_VS_TEMP_REGISTER_CONTROL 0x0000080c #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) #define VIVS_VS_OUTPUT(i0) (0x00000810 + 0x4*(i0)) #define VIVS_VS_OUTPUT__ESIZE 0x00000004 #define VIVS_VS_OUTPUT__LEN 0x00000004 #define VIVS_VS_OUTPUT_O0__MASK 0x000000ff #define VIVS_VS_OUTPUT_O0__SHIFT 0 #define VIVS_VS_OUTPUT_O0(x) (((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK) #define VIVS_VS_OUTPUT_O1__MASK 0x0000ff00 #define VIVS_VS_OUTPUT_O1__SHIFT 8 #define VIVS_VS_OUTPUT_O1(x) (((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK) #define VIVS_VS_OUTPUT_O2__MASK 0x00ff0000 #define VIVS_VS_OUTPUT_O2__SHIFT 16 #define VIVS_VS_OUTPUT_O2(x) (((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK) #define VIVS_VS_OUTPUT_O3__MASK 0xff000000 #define VIVS_VS_OUTPUT_O3__SHIFT 24 #define VIVS_VS_OUTPUT_O3(x) (((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK) #define VIVS_VS_INPUT(i0) (0x00000820 + 0x4*(i0)) #define VIVS_VS_INPUT__ESIZE 0x00000004 #define VIVS_VS_INPUT__LEN 0x00000004 #define VIVS_VS_INPUT_I0__MASK 0x000000ff #define VIVS_VS_INPUT_I0__SHIFT 0 #define VIVS_VS_INPUT_I0(x) (((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK) #define VIVS_VS_INPUT_I1__MASK 0x0000ff00 #define VIVS_VS_INPUT_I1__SHIFT 8 #define VIVS_VS_INPUT_I1(x) (((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK) #define VIVS_VS_INPUT_I2__MASK 0x00ff0000 #define VIVS_VS_INPUT_I2__SHIFT 16 #define VIVS_VS_INPUT_I2(x) (((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK) #define VIVS_VS_INPUT_I3__MASK 0xff000000 #define VIVS_VS_INPUT_I3__SHIFT 24 #define VIVS_VS_INPUT_I3(x) (((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK) #define VIVS_VS_LOAD_BALANCING 0x00000830 #define VIVS_VS_LOAD_BALANCING_A__MASK 0x000000ff #define VIVS_VS_LOAD_BALANCING_A__SHIFT 0 #define VIVS_VS_LOAD_BALANCING_A(x) (((x) << VIVS_VS_LOAD_BALANCING_A__SHIFT) & VIVS_VS_LOAD_BALANCING_A__MASK) #define VIVS_VS_LOAD_BALANCING_B__MASK 0x0000ff00 #define VIVS_VS_LOAD_BALANCING_B__SHIFT 8 #define VIVS_VS_LOAD_BALANCING_B(x) (((x) << VIVS_VS_LOAD_BALANCING_B__SHIFT) & VIVS_VS_LOAD_BALANCING_B__MASK) #define VIVS_VS_LOAD_BALANCING_C__MASK 0x00ff0000 #define VIVS_VS_LOAD_BALANCING_C__SHIFT 16 #define VIVS_VS_LOAD_BALANCING_C(x) (((x) << VIVS_VS_LOAD_BALANCING_C__SHIFT) & VIVS_VS_LOAD_BALANCING_C__MASK) #define VIVS_VS_LOAD_BALANCING_D__MASK 0xff000000 #define VIVS_VS_LOAD_BALANCING_D__SHIFT 24 #define VIVS_VS_LOAD_BALANCING_D(x) (((x) << VIVS_VS_LOAD_BALANCING_D__SHIFT) & VIVS_VS_LOAD_BALANCING_D__MASK) #define VIVS_VS_PERF_COUNTER 0x00000834 #define VIVS_VS_START_PC 0x00000838 #define VIVS_VS_UNK00850 0x00000850 #define VIVS_VS_UNK00854 0x00000854 #define VIVS_VS_UNK00858 0x00000858 #define VIVS_VS_RANGE 0x0000085c #define VIVS_VS_RANGE_LOW__MASK 0x0000ffff #define VIVS_VS_RANGE_LOW__SHIFT 0 #define VIVS_VS_RANGE_LOW(x) (((x) << VIVS_VS_RANGE_LOW__SHIFT) & VIVS_VS_RANGE_LOW__MASK) #define VIVS_VS_RANGE_HIGH__MASK 0xffff0000 #define VIVS_VS_RANGE_HIGH__SHIFT 16 #define VIVS_VS_RANGE_HIGH(x) (((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK) #define VIVS_VS_UNIFORM_CACHE 0x00000860 #define VIVS_VS_UNIFORM_CACHE_FLUSH 0x00000001 #define VIVS_VS_UNIFORM_CACHE_PS 0x00000010 #define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING 0x00001000 #define VIVS_VS_UNIFORM_BASE 0x00000864 #define VIVS_VS_ICACHE_CONTROL 0x00000868 #define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001 #define VIVS_VS_ICACHE_CONTROL_FLUSH_VS 0x00000010 #define VIVS_VS_ICACHE_CONTROL_FLUSH_PS 0x00000020 #define VIVS_VS_INST_ADDR 0x0000086c #define VIVS_VS_HALTI5_OUTPUT_COUNT 0x00000870 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK 0x000003ff #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT 0 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK) #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK 0x0007ff00 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT 8 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B(x) (((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK) #define VIVS_VS_NEWRANGE_LOW 0x00000874 #define VIVS_VS_HALTI5_UNK00878 0x00000878 #define VIVS_VS_HALTI5_UNK00880 0x00000880 #define VIVS_VS_HALTI1_UNK00884 0x00000884 #define VIVS_VS_ICACHE_PREFETCH 0x0000088c #define VIVS_VS_ICACHE_UNK00890 0x00000890 #define VIVS_VS_HALTI5_UNK00898(i0) (0x00000898 + 0x4*(i0)) #define VIVS_VS_HALTI5_UNK00898__ESIZE 0x00000004 #define VIVS_VS_HALTI5_UNK00898__LEN 0x00000002 #define VIVS_VS_HALTI5_UNK008A0 0x000008a0 #define VIVS_VS_HALTI5_UNK008A0_A__MASK 0x0000003f #define VIVS_VS_HALTI5_UNK008A0_A__SHIFT 0 #define VIVS_VS_HALTI5_UNK008A0_A(x) (((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK) #define VIVS_VS_HALTI5_UNK008A0_B__MASK 0x0007f000 #define VIVS_VS_HALTI5_UNK008A0_B__SHIFT 12 #define VIVS_VS_HALTI5_UNK008A0_B(x) (((x) << VIVS_VS_HALTI5_UNK008A0_B__SHIFT) & VIVS_VS_HALTI5_UNK008A0_B__MASK) #define VIVS_VS_HALTI5_UNK008A0_C__MASK 0x1ff00000 #define VIVS_VS_HALTI5_UNK008A0_C__SHIFT 20 #define VIVS_VS_HALTI5_UNK008A0_C(x) (((x) << VIVS_VS_HALTI5_UNK008A0_C__SHIFT) & VIVS_VS_HALTI5_UNK008A0_C__MASK) #define VIVS_VS_SAMPLER_BASE 0x000008a8 #define VIVS_VS_ICACHE_INVALIDATE 0x000008b0 #define VIVS_VS_ICACHE_INVALIDATE_UNK0 0x00000001 #define VIVS_VS_ICACHE_INVALIDATE_UNK1 0x00000002 #define VIVS_VS_ICACHE_INVALIDATE_UNK2 0x00000004 #define VIVS_VS_ICACHE_INVALIDATE_UNK3 0x00000008 #define VIVS_VS_ICACHE_INVALIDATE_UNK4 0x00000010 #define VIVS_VS_HALTI5_UNK008B8 0x000008b8 #define VIVS_VS_NEWRANGE_HIGH 0x000008bc #define VIVS_VS_HALTI5_INPUT(i0) (0x000008c0 + 0x4*(i0)) #define VIVS_VS_HALTI5_INPUT__ESIZE 0x00000004 #define VIVS_VS_HALTI5_INPUT__LEN 0x00000008 #define VIVS_VS_HALTI5_INPUT_I0__MASK 0x000000ff #define VIVS_VS_HALTI5_INPUT_I0__SHIFT 0 #define VIVS_VS_HALTI5_INPUT_I0(x) (((x) << VIVS_VS_HALTI5_INPUT_I0__SHIFT) & VIVS_VS_HALTI5_INPUT_I0__MASK) #define VIVS_VS_HALTI5_INPUT_I1__MASK 0x0000ff00 #define VIVS_VS_HALTI5_INPUT_I1__SHIFT 8 #define VIVS_VS_HALTI5_INPUT_I1(x) (((x) << VIVS_VS_HALTI5_INPUT_I1__SHIFT) & VIVS_VS_HALTI5_INPUT_I1__MASK) #define VIVS_VS_HALTI5_INPUT_I2__MASK 0x00ff0000 #define VIVS_VS_HALTI5_INPUT_I2__SHIFT 16 #define VIVS_VS_HALTI5_INPUT_I2(x) (((x) << VIVS_VS_HALTI5_INPUT_I2__SHIFT) & VIVS_VS_HALTI5_INPUT_I2__MASK) #define VIVS_VS_HALTI5_INPUT_I3__MASK 0xff000000 #define VIVS_VS_HALTI5_INPUT_I3__SHIFT 24 #define VIVS_VS_HALTI5_INPUT_I3(x) (((x) << VIVS_VS_HALTI5_INPUT_I3__SHIFT) & VIVS_VS_HALTI5_INPUT_I3__MASK) #define VIVS_VS_HALTI5_OUTPUT(i0) (0x000008e0 + 0x4*(i0)) #define VIVS_VS_HALTI5_OUTPUT__ESIZE 0x00000004 #define VIVS_VS_HALTI5_OUTPUT__LEN 0x00000008 #define VIVS_VS_HALTI5_OUTPUT_O0__MASK 0x000000ff #define VIVS_VS_HALTI5_OUTPUT_O0__SHIFT 0 #define VIVS_VS_HALTI5_OUTPUT_O0(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O0__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O0__MASK) #define VIVS_VS_HALTI5_OUTPUT_O1__MASK 0x0000ff00 #define VIVS_VS_HALTI5_OUTPUT_O1__SHIFT 8 #define VIVS_VS_HALTI5_OUTPUT_O1(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O1__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O1__MASK) #define VIVS_VS_HALTI5_OUTPUT_O2__MASK 0x00ff0000 #define VIVS_VS_HALTI5_OUTPUT_O2__SHIFT 16 #define VIVS_VS_HALTI5_OUTPUT_O2(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O2__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O2__MASK) #define VIVS_VS_HALTI5_OUTPUT_O3__MASK 0xff000000 #define VIVS_VS_HALTI5_OUTPUT_O3__SHIFT 24 #define VIVS_VS_HALTI5_OUTPUT_O3(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O3__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O3__MASK) #define VIVS_VS_INST_MEM(i0) (0x00004000 + 0x4*(i0)) #define VIVS_VS_INST_MEM__ESIZE 0x00000004 #define VIVS_VS_INST_MEM__LEN 0x00000400 #define VIVS_VS_UNIFORMS(i0) (0x00005000 + 0x4*(i0)) #define VIVS_VS_UNIFORMS__ESIZE 0x00000004 #define VIVS_VS_UNIFORMS__LEN 0x00000400 #define VIVS_VS_ICACHE_COUNT 0x00015604 #define VIVS_CL 0x00000000 #define VIVS_CL_CONFIG 0x00000900 #define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 #define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 #define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) #define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK 0x00000070 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT 4 #define VIVS_CL_CONFIG_TRAVERSE_ORDER(x) (((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK) #define VIVS_CL_CONFIG_ENABLE_SWATH_X 0x00000100 #define VIVS_CL_CONFIG_ENABLE_SWATH_Y 0x00000200 #define VIVS_CL_CONFIG_ENABLE_SWATH_Z 0x00000400 #define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK 0x0000f000 #define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT 12 #define VIVS_CL_CONFIG_SWATH_SIZE_X(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK) #define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK 0x000f0000 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT 16 #define VIVS_CL_CONFIG_SWATH_SIZE_Y(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK) #define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK 0x00f00000 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT 20 #define VIVS_CL_CONFIG_SWATH_SIZE_Z(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK) #define VIVS_CL_CONFIG_VALUE_ORDER__MASK 0x07000000 #define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT 24 #define VIVS_CL_CONFIG_VALUE_ORDER(x) (((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK) #define VIVS_CL_GLOBAL_X 0x00000904 #define VIVS_CL_GLOBAL_X_SIZE__MASK 0x0000ffff #define VIVS_CL_GLOBAL_X_SIZE__SHIFT 0 #define VIVS_CL_GLOBAL_X_SIZE(x) (((x) << VIVS_CL_GLOBAL_X_SIZE__SHIFT) & VIVS_CL_GLOBAL_X_SIZE__MASK) #define VIVS_CL_GLOBAL_X_OFFSET__MASK 0xffff0000 #define VIVS_CL_GLOBAL_X_OFFSET__SHIFT 16 #define VIVS_CL_GLOBAL_X_OFFSET(x) (((x) << VIVS_CL_GLOBAL_X_OFFSET__SHIFT) & VIVS_CL_GLOBAL_X_OFFSET__MASK) #define VIVS_CL_GLOBAL_Y 0x00000908 #define VIVS_CL_GLOBAL_Y_SIZE__MASK 0x0000ffff #define VIVS_CL_GLOBAL_Y_SIZE__SHIFT 0 #define VIVS_CL_GLOBAL_Y_SIZE(x) (((x) << VIVS_CL_GLOBAL_Y_SIZE__SHIFT) & VIVS_CL_GLOBAL_Y_SIZE__MASK) #define VIVS_CL_GLOBAL_Y_OFFSET__MASK 0xffff0000 #define VIVS_CL_GLOBAL_Y_OFFSET__SHIFT 16 #define VIVS_CL_GLOBAL_Y_OFFSET(x) (((x) << VIVS_CL_GLOBAL_Y_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Y_OFFSET__MASK) #define VIVS_CL_GLOBAL_Z 0x0000090c #define VIVS_CL_GLOBAL_Z_SIZE__MASK 0x0000ffff #define VIVS_CL_GLOBAL_Z_SIZE__SHIFT 0 #define VIVS_CL_GLOBAL_Z_SIZE(x) (((x) << VIVS_CL_GLOBAL_Z_SIZE__SHIFT) & VIVS_CL_GLOBAL_Z_SIZE__MASK) #define VIVS_CL_GLOBAL_Z_OFFSET__MASK 0xffff0000 #define VIVS_CL_GLOBAL_Z_OFFSET__SHIFT 16 #define VIVS_CL_GLOBAL_Z_OFFSET(x) (((x) << VIVS_CL_GLOBAL_Z_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Z_OFFSET__MASK) #define VIVS_CL_WORKGROUP_X 0x00000910 #define VIVS_CL_WORKGROUP_X_SIZE__MASK 0x000003ff #define VIVS_CL_WORKGROUP_X_SIZE__SHIFT 0 #define VIVS_CL_WORKGROUP_X_SIZE(x) (((x) << VIVS_CL_WORKGROUP_X_SIZE__SHIFT) & VIVS_CL_WORKGROUP_X_SIZE__MASK) #define VIVS_CL_WORKGROUP_X_COUNT__MASK 0xffff0000 #define VIVS_CL_WORKGROUP_X_COUNT__SHIFT 16 #define VIVS_CL_WORKGROUP_X_COUNT(x) (((x) << VIVS_CL_WORKGROUP_X_COUNT__SHIFT) & VIVS_CL_WORKGROUP_X_COUNT__MASK) #define VIVS_CL_WORKGROUP_Y 0x00000914 #define VIVS_CL_WORKGROUP_Y_SIZE__MASK 0x000003ff #define VIVS_CL_WORKGROUP_Y_SIZE__SHIFT 0 #define VIVS_CL_WORKGROUP_Y_SIZE(x) (((x) << VIVS_CL_WORKGROUP_Y_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Y_SIZE__MASK) #define VIVS_CL_WORKGROUP_Y_COUNT__MASK 0xffff0000 #define VIVS_CL_WORKGROUP_Y_COUNT__SHIFT 16 #define VIVS_CL_WORKGROUP_Y_COUNT(x) (((x) << VIVS_CL_WORKGROUP_Y_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Y_COUNT__MASK) #define VIVS_CL_WORKGROUP_Z 0x00000918 #define VIVS_CL_WORKGROUP_Z_SIZE__MASK 0x000003ff #define VIVS_CL_WORKGROUP_Z_SIZE__SHIFT 0 #define VIVS_CL_WORKGROUP_Z_SIZE(x) (((x) << VIVS_CL_WORKGROUP_Z_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Z_SIZE__MASK) #define VIVS_CL_WORKGROUP_Z_COUNT__MASK 0xffff0000 #define VIVS_CL_WORKGROUP_Z_COUNT__SHIFT 16 #define VIVS_CL_WORKGROUP_Z_COUNT(x) (((x) << VIVS_CL_WORKGROUP_Z_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Z_COUNT__MASK) #define VIVS_CL_THREAD_ALLOCATION 0x0000091c #define VIVS_CL_KICKER 0x00000920 #define VIVS_CL_UNK00924 0x00000924 #define VIVS_CL_UNK00940 0x00000940 #define VIVS_CL_UNK00944 0x00000944 #define VIVS_CL_UNK00948 0x00000948 #define VIVS_CL_UNK0094C 0x0000094c #define VIVS_CL_UNK00950 0x00000950 #define VIVS_CL_UNK00954 0x00000954 #define VIVS_CL_HALTI5_UNK00958 0x00000958 #define VIVS_CL_HALTI5_UNK0095C 0x0000095c #define VIVS_CL_HALTI5_UNK00960 0x00000960 #define VIVS_PA 0x00000000 #define VIVS_PA_VIEWPORT_SCALE_X 0x00000a00 #define VIVS_PA_VIEWPORT_SCALE_Y 0x00000a04 #define VIVS_PA_VIEWPORT_SCALE_Z 0x00000a08 #define VIVS_PA_VIEWPORT_OFFSET_X 0x00000a0c #define VIVS_PA_VIEWPORT_OFFSET_Y 0x00000a10 #define VIVS_PA_VIEWPORT_OFFSET_Z 0x00000a14 #define VIVS_PA_LINE_WIDTH 0x00000a18 #define VIVS_PA_POINT_SIZE 0x00000a1c #define VIVS_PA_UNK00A24 0x00000a24 #define VIVS_PA_SYSTEM_MODE 0x00000a28 #define VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST 0x00000001 #define VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER 0x00000010 #define VIVS_PA_W_CLIP_LIMIT 0x00000a2c #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT 0x00000a30 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK 0x000000ff #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT 0 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x) (((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK) #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK 0x0000ff00 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT 8 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x) (((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK) #define VIVS_PA_CONFIG 0x00000a34 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE 0x00000004 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE_MASK 0x00000008 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE 0x00000010 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE_MASK 0x00000020 #define VIVS_PA_CONFIG_CULL_FACE_MODE__MASK 0x00000300 #define VIVS_PA_CONFIG_CULL_FACE_MODE__SHIFT 8 #define VIVS_PA_CONFIG_CULL_FACE_MODE_OFF 0x00000000 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CW 0x00000100 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CCW 0x00000200 #define VIVS_PA_CONFIG_CULL_FACE_MODE_MASK 0x00000400 #define VIVS_PA_CONFIG_FILL_MODE__MASK 0x00003000 #define VIVS_PA_CONFIG_FILL_MODE__SHIFT 12 #define VIVS_PA_CONFIG_FILL_MODE_POINT 0x00000000 #define VIVS_PA_CONFIG_FILL_MODE_WIREFRAME 0x00001000 #define VIVS_PA_CONFIG_FILL_MODE_SOLID 0x00002000 #define VIVS_PA_CONFIG_FILL_MODE_MASK 0x00004000 #define VIVS_PA_CONFIG_SHADE_MODEL__MASK 0x00030000 #define VIVS_PA_CONFIG_SHADE_MODEL__SHIFT 16 #define VIVS_PA_CONFIG_SHADE_MODEL_FLAT 0x00000000 #define VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH 0x00010000 #define VIVS_PA_CONFIG_SHADE_MODEL_MASK 0x00040000 #define VIVS_PA_CONFIG_WIDE_LINE 0x00400000 #define VIVS_PA_CONFIG_WIDE_LINE_MASK 0x00800000 #define VIVS_PA_WIDE_LINE_WIDTH0 0x00000a38 #define VIVS_PA_WIDE_LINE_WIDTH1 0x00000a3c #define VIVS_PA_SHADER_ATTRIBUTES(i0) (0x00000a40 + 0x4*(i0)) #define VIVS_PA_SHADER_ATTRIBUTES__ESIZE 0x00000004 #define VIVS_PA_SHADER_ATTRIBUTES__LEN 0x0000000a #define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT 0x00000001 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK 0x000000f0 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT 4 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4(x) (((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK) #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK 0x00000f00 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT 8 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x) (((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK) #define VIVS_PA_VIEWPORT_UNK00A80 0x00000a80 #define VIVS_PA_VIEWPORT_UNK00A84 0x00000a84 #define VIVS_PA_FLAGS 0x00000a88 #define VIVS_PA_FLAGS_UNK24 0x01000000 #define VIVS_PA_FLAGS_ZCONVERT_BYPASS 0x40000000 #define VIVS_PA_ZFARCLIPPING 0x00000a8c #define VIVS_PA_VARYING_NUM_COMPONENTS(i0) (0x00000a90 + 0x4*(i0)) #define VIVS_PA_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 #define VIVS_PA_VARYING_NUM_COMPONENTS__LEN 0x00000004 #define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8 #define VIVS_SE 0x00000000 #define VIVS_SE_SCISSOR_LEFT 0x00000c00 #define VIVS_SE_SCISSOR_TOP 0x00000c04 #define VIVS_SE_SCISSOR_RIGHT 0x00000c08 #define VIVS_SE_SCISSOR_BOTTOM 0x00000c0c #define VIVS_SE_DEPTH_SCALE 0x00000c10 #define VIVS_SE_DEPTH_BIAS 0x00000c14 #define VIVS_SE_CONFIG 0x00000c18 #define VIVS_SE_CONFIG_LAST_PIXEL_ENABLE 0x00000001 #define VIVS_SE_UNK00C1C 0x00000c1c #define VIVS_SE_CLIP_RIGHT 0x00000c20 #define VIVS_SE_CLIP_BOTTOM 0x00000c24 #define VIVS_RA 0x00000000 #define VIVS_RA_CONTROL 0x00000e00 #define VIVS_RA_CONTROL_UNK0 0x00000001 #define VIVS_RA_CONTROL_LAST_VARYING_2X 0x00000002 #define VIVS_RA_MULTISAMPLE_UNK00E04 0x00000e04 #define VIVS_RA_EARLY_DEPTH 0x00000e08 #define VIVS_RA_UNK00E0C 0x00000e0c #define VIVS_RA_MULTISAMPLE_UNK00E10(i0) (0x00000e10 + 0x4*(i0)) #define VIVS_RA_MULTISAMPLE_UNK00E10__ESIZE 0x00000004 #define VIVS_RA_MULTISAMPLE_UNK00E10__LEN 0x00000004 #define VIVS_RA_HDEPTH_CONTROL 0x00000e20 #define VIVS_RA_HDEPTH_CONTROL_UNK0 0x00000001 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK 0x00007000 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT 12 #define VIVS_RA_HDEPTH_CONTROL_COMPARE(x) (((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK) #define VIVS_RA_UNK00E24 0x00000e24 #define VIVS_RA_HALTI5_UNK00E34 0x00000e34 #define VIVS_RA_CENTROID_TABLE(i0) (0x00000e40 + 0x4*(i0)) #define VIVS_RA_CENTROID_TABLE__ESIZE 0x00000004 #define VIVS_RA_CENTROID_TABLE__LEN 0x00000010 #define VIVS_PS 0x00000000 #define VIVS_PS_END_PC 0x00001000 #define VIVS_PS_OUTPUT_REG 0x00001004 #define VIVS_PS_INPUT_COUNT 0x00001008 #define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000000f #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0 #define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK) #define VIVS_PS_INPUT_COUNT_UNK8__MASK 0x00001f00 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT 8 #define VIVS_PS_INPUT_COUNT_UNK8(x) (((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK) #define VIVS_PS_INPUT_COUNT_DUAL16 0x00010000 #define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) #define VIVS_PS_CONTROL 0x00001010 #define VIVS_PS_CONTROL_BYPASS 0x00000001 #define VIVS_PS_CONTROL_SATURATE_RT0 0x00000002 #define VIVS_PS_CONTROL_SATURATE_RT1 0x00000004 #define VIVS_PS_CONTROL_SATURATE_RT2 0x00000008 #define VIVS_PS_CONTROL_SATURATE_RT3 0x00000010 #define VIVS_PS_CONTROL_RT_COUNT__MASK 0x00000700 #define VIVS_PS_CONTROL_RT_COUNT__SHIFT 8 #define VIVS_PS_CONTROL_RT_COUNT(x) (((x) << VIVS_PS_CONTROL_RT_COUNT__SHIFT) & VIVS_PS_CONTROL_RT_COUNT__MASK) #define VIVS_PS_PERF_COUNTER 0x00001014 #define VIVS_PS_START_PC 0x00001018 #define VIVS_PS_RANGE 0x0000101c #define VIVS_PS_RANGE_LOW__MASK 0x0000ffff #define VIVS_PS_RANGE_LOW__SHIFT 0 #define VIVS_PS_RANGE_LOW(x) (((x) << VIVS_PS_RANGE_LOW__SHIFT) & VIVS_PS_RANGE_LOW__MASK) #define VIVS_PS_RANGE_HIGH__MASK 0xffff0000 #define VIVS_PS_RANGE_HIGH__SHIFT 16 #define VIVS_PS_RANGE_HIGH(x) (((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK) #define VIVS_PS_UNIFORM_BASE 0x00001024 #define VIVS_PS_INST_ADDR 0x00001028 #define VIVS_PS_CONTROL2 0x0000102c #define VIVS_PS_CONTROL2_SATURATE_RT4 0x00000080 #define VIVS_PS_CONTROL2_SATURATE_RT5 0x00008000 #define VIVS_PS_CONTROL2_SATURATE_RT6 0x00800000 #define VIVS_PS_CONTROL2_SATURATE_RT7 0x80000000 #define VIVS_PS_CONTROL_EXT 0x00001030 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK 0x00000007 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT 0 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK 0x00000070 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT 4 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK 0x00000700 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT 8 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK 0x00007000 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT 12 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK 0x00070000 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT 16 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK 0x00700000 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT 20 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK 0x07000000 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT 24 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK) #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK 0x70000000 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT 28 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK) #define VIVS_PS_UNK01034 0x00001034 #define VIVS_PS_UNK01038 0x00001038 #define VIVS_PS_HALTI3_UNK0103C 0x0000103c #define VIVS_PS_UNK01040(i0) (0x00001040 + 0x4*(i0)) #define VIVS_PS_UNK01040__ESIZE 0x00000004 #define VIVS_PS_UNK01040__LEN 0x00000002 #define VIVS_PS_ICACHE_PREFETCH 0x00001048 #define VIVS_PS_ICACHE_UNK0104C 0x0000104c #define VIVS_PS_MSAA_CONFIG 0x00001054 #define VIVS_PS_SAMPLER_BASE 0x00001058 #define VIVS_PS_VARYING_NUM_COMPONENTS(i0) (0x00001080 + 0x4*(i0)) #define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 #define VIVS_PS_VARYING_NUM_COMPONENTS__LEN 0x00000004 #define VIVS_PS_NEWRANGE_LOW 0x0000087c #define VIVS_PS_NEWRANGE_HIGH 0x00001090 #define VIVS_PS_ICACHE_COUNT 0x00001094 #define VIVS_PS_HALTI5_UNK01098 0x00001098 #define VIVS_PS_INST_MEM(i0) (0x00006000 + 0x4*(i0)) #define VIVS_PS_INST_MEM__ESIZE 0x00000004 #define VIVS_PS_INST_MEM__LEN 0x00000400 #define VIVS_PS_UNIFORMS(i0) (0x00007000 + 0x4*(i0)) #define VIVS_PS_UNIFORMS__ESIZE 0x00000004 #define VIVS_PS_UNIFORMS__LEN 0x00000400 #define VIVS_GS 0x00000000 #define VIVS_GS_UNK01100 0x00001100 #define VIVS_GS_UNK01104 0x00001104 #define VIVS_GS_UNK01108 0x00001108 #define VIVS_GS_UNK0110C 0x0000110c #define VIVS_GS_UNK01110 0x00001110 #define VIVS_GS_UNK01114 0x00001114 #define VIVS_GS_ICACHE_PREFETCH 0x00001118 #define VIVS_GS_UNK0111C 0x0000111c #define VIVS_GS_UNK01120(i0) (0x00001120 + 0x4*(i0)) #define VIVS_GS_UNK01120__ESIZE 0x00000004 #define VIVS_GS_UNK01120__LEN 0x00000008 #define VIVS_GS_UNK01140 0x00001140 #define VIVS_GS_UNK01144 0x00001144 #define VIVS_GS_UNK01148 0x00001148 #define VIVS_GS_UNK0114C 0x0000114c #define VIVS_GS_UNK01154 0x00001154 #define VIVS_TCS 0x00000000 #define VIVS_TCS_UNK007C0 0x000007c0 #define VIVS_TCS_UNK14A00 0x00014a00 #define VIVS_TCS_UNK14A04 0x00014a04 #define VIVS_TCS_UNK14A08 0x00014a08 #define VIVS_TCS_ICACHE_PREFETCH 0x00014a0c #define VIVS_TCS_UNK14A10 0x00014a10 #define VIVS_TCS_UNK14A14 0x00014a14 #define VIVS_TCS_UNK14A18 0x00014a18 #define VIVS_TCS_UNK14A1C 0x00014a1c #define VIVS_TCS_UNK14A20(i0) (0x00014a20 + 0x4*(i0)) #define VIVS_TCS_UNK14A20__ESIZE 0x00000004 #define VIVS_TCS_UNK14A20__LEN 0x00000008 #define VIVS_TCS_UNK14A40 0x00014a40 #define VIVS_TCS_UNK14A44 0x00014a44 #define VIVS_TCS_UNK14A4C 0x00014a4c #define VIVS_TES 0x00000000 #define VIVS_TES_UNK14B00 0x00014b00 #define VIVS_TES_UNK14B04 0x00014b04 #define VIVS_TES_UNK14B08 0x00014b08 #define VIVS_TES_UNK14B0C 0x00014b0c #define VIVS_TES_ICACHE_PREFETCH 0x00014b10 #define VIVS_TES_UNK14B14 0x00014b14 #define VIVS_TES_UNK14B18 0x00014b18 #define VIVS_TES_UNK14B1C 0x00014b1c #define VIVS_TES_UNK14B20 0x00014b20 #define VIVS_TES_UNK14B24 0x00014b24 #define VIVS_TES_UNK14B2C 0x00014b2c #define VIVS_TES_UNK14B34 0x00014b34 #define VIVS_TES_UNK14B40(i0) (0x00014b40 + 0x4*(i0)) #define VIVS_TES_UNK14B40__ESIZE 0x00000004 #define VIVS_TES_UNK14B40__LEN 0x00000008 #define VIVS_TFB 0x00000000 #define VIVS_TFB_UNK1C000 0x0001c000 #define VIVS_TFB_UNK1C008 0x0001c008 #define VIVS_TFB_FLUSH 0x0001c00c #define VIVS_TFB_UNK1C014 0x0001c014 #define VIVS_TFB_UNK1C040(i0) (0x0001c040 + 0x4*(i0)) #define VIVS_TFB_UNK1C040__ESIZE 0x00000004 #define VIVS_TFB_UNK1C040__LEN 0x00000004 #define VIVS_TFB_UNK1C080(i0) (0x0001c080 + 0x4*(i0)) #define VIVS_TFB_UNK1C080__ESIZE 0x00000004 #define VIVS_TFB_UNK1C080__LEN 0x00000004 #define VIVS_TFB_UNK1C0C0(i0) (0x0001c0c0 + 0x4*(i0)) #define VIVS_TFB_UNK1C0C0__ESIZE 0x00000004 #define VIVS_TFB_UNK1C0C0__LEN 0x00000004 #define VIVS_TFB_UNK1C100(i0) (0x0001c100 + 0x4*(i0)) #define VIVS_TFB_UNK1C100__ESIZE 0x00000004 #define VIVS_TFB_UNK1C100__LEN 0x00000004 #define VIVS_TFB_UNK1C800(i0) (0x0001c800 + 0x4*(i0)) #define VIVS_TFB_UNK1C800__ESIZE 0x00000004 #define VIVS_TFB_UNK1C800__LEN 0x00000200 #define VIVS_PE 0x00000000 #define VIVS_PE_DEPTH_CONFIG 0x00001400 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__MASK 0x00000003 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__SHIFT 0 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE 0x00000000 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z 0x00000001 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_W 0x00000002 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_MASK 0x00000008 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__MASK 0x00000010 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__SHIFT 4 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 0x00000000 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8 0x00000010 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK 0x00000020 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK 0x00000700 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT 8 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x) (((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK) #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK 0x00000800 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE 0x00001000 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK 0x00002000 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z 0x00010000 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z_MASK 0x00020000 #define VIVS_PE_DEPTH_CONFIG_UNK18 0x00040000 #define VIVS_PE_DEPTH_CONFIG_UNK18_MASK 0x00080000 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH 0x00100000 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH_MASK 0x00200000 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS 0x01000000 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS_MASK 0x02000000 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED 0x04000000 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED_MASK 0x08000000 #define VIVS_PE_DEPTH_NEAR 0x00001404 #define VIVS_PE_DEPTH_FAR 0x00001408 #define VIVS_PE_DEPTH_NORMALIZE 0x0000140c #define VIVS_PE_DEPTH_ADDR 0x00001410 #define VIVS_PE_DEPTH_STRIDE 0x00001414 #define VIVS_PE_STENCIL_OP 0x00001418 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK 0x00000007 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT 0 #define VIVS_PE_STENCIL_OP_FUNC_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK) #define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK 0x00000008 #define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK 0x00000070 #define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT 4 #define VIVS_PE_STENCIL_OP_PASS_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK) #define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK 0x00000080 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK 0x00000700 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT 8 #define VIVS_PE_STENCIL_OP_FAIL_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK) #define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK 0x00000800 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK 0x00007000 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT 12 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK) #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK 0x00008000 #define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK 0x00070000 #define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT 16 #define VIVS_PE_STENCIL_OP_FUNC_BACK(x) (((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK) #define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK 0x00080000 #define VIVS_PE_STENCIL_OP_PASS_BACK__MASK 0x00700000 #define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT 20 #define VIVS_PE_STENCIL_OP_PASS_BACK(x) (((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK) #define VIVS_PE_STENCIL_OP_PASS_BACK_MASK 0x00800000 #define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK 0x07000000 #define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT 24 #define VIVS_PE_STENCIL_OP_FAIL_BACK(x) (((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK) #define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK 0x08000000 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK 0x70000000 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT 28 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x) (((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK) #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK 0x80000000 #define VIVS_PE_STENCIL_CONFIG 0x0000141c #define VIVS_PE_STENCIL_CONFIG_MODE__MASK 0x00000003 #define VIVS_PE_STENCIL_CONFIG_MODE__SHIFT 0 #define VIVS_PE_STENCIL_CONFIG_MODE_DISABLED 0x00000000 #define VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED 0x00000001 #define VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED 0x00000002 #define VIVS_PE_STENCIL_CONFIG_MODE_MASK 0x00000010 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT_MASK 0x00000020 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT_MASK 0x00000040 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK 0x00000080 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK 0x0000ff00 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT 8 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK) #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK 0x00ff0000 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT 16 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK) #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK 0xff000000 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT 24 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK) #define VIVS_PE_ALPHA_OP 0x00001420 #define VIVS_PE_ALPHA_OP_ALPHA_TEST 0x00000001 #define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK 0x00000002 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK 0x00000070 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT 4 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK) #define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK 0x00000080 #define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK 0x0000ff00 #define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT 8 #define VIVS_PE_ALPHA_OP_ALPHA_REF(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK) #define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK 0x00010000 #define VIVS_PE_ALPHA_BLEND_COLOR 0x00001424 #define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK 0x000000ff #define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT 0 #define VIVS_PE_ALPHA_BLEND_COLOR_B(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK) #define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK 0x0000ff00 #define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT 8 #define VIVS_PE_ALPHA_BLEND_COLOR_G(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK) #define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK 0x00ff0000 #define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT 16 #define VIVS_PE_ALPHA_BLEND_COLOR_R(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK) #define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK 0xff000000 #define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT 24 #define VIVS_PE_ALPHA_BLEND_COLOR_A(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK) #define VIVS_PE_ALPHA_CONFIG 0x00001428 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR 0x00000001 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK 0x00000002 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK 0x00000004 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK 0x00000008 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK 0x000000f0 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT 4 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK) #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK 0x00000f00 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT 8 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK) #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK 0x00007000 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT 12 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK) #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK 0x00008000 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA 0x00010000 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK 0x00020000 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK 0x00040000 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK 0x00080000 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK 0x00f00000 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT 20 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK) #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK 0x0f000000 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT 24 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK) #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK 0x70000000 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT 28 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK) #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK 0x80000000 #define VIVS_PE_COLOR_FORMAT 0x0000142c #define VIVS_PE_COLOR_FORMAT_FORMAT__MASK 0x0000000f #define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT 0 #define VIVS_PE_COLOR_FORMAT_FORMAT(x) (((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK) #define VIVS_PE_COLOR_FORMAT_FORMAT_MASK 0x00000010 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK 0x00000f00 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT 8 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x) (((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK) #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW 0x00002000 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK 0x00001000 #define VIVS_PE_COLOR_FORMAT_OVERWRITE 0x00010000 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK 0x00020000 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED 0x00100000 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK 0x00200000 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK 0x7f000000 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT 24 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT(x) (((x) << VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK) #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT_MASK 0x80000000 #define VIVS_PE_COLOR_ADDR 0x00001430 #define VIVS_PE_COLOR_STRIDE 0x00001434 #define VIVS_PE_HDEPTH_CONTROL 0x00001454 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__MASK 0x0000000f #define VIVS_PE_HDEPTH_CONTROL_FORMAT__SHIFT 0 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED 0x00000000 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D16 0x00000005 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D24S8 0x00000008 #define VIVS_PE_HDEPTH_ADDR 0x00001458 #define VIVS_PE_UNK0145C 0x0000145c #define VIVS_PE_PIPE(i0) (0x00000000 + 0x4*(i0)) #define VIVS_PE_PIPE__ESIZE 0x00000004 #define VIVS_PE_PIPE__LEN 0x00000008 #define VIVS_PE_PIPE_COLOR_ADDR(i0) (0x00001460 + 0x4*(i0)) #define VIVS_PE_PIPE_DEPTH_ADDR(i0) (0x00001480 + 0x4*(i0)) #define VIVS_PE_PIPE_ADDR_UNK01500(i0) (0x00001500 + 0x4*(i0)) #define VIVS_PE_PIPE_ADDR_UNK01520(i0) (0x00001520 + 0x4*(i0)) #define VIVS_PE_PIPE_ADDR_UNK01540(i0) (0x00001540 + 0x4*(i0)) #define VIVS_PE_STENCIL_CONFIG_EXT 0x000014a0 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK 0x000000ff #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT 0 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK) #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK 0x00000100 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK 0x00000200 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK 0xffff0000 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT 16 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK) #define VIVS_PE_LOGIC_OP 0x000014a4 #define VIVS_PE_LOGIC_OP_OP__MASK 0x0000000f #define VIVS_PE_LOGIC_OP_OP__SHIFT 0 #define VIVS_PE_LOGIC_OP_OP(x) (((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK) #define VIVS_PE_LOGIC_OP_OP_MASK 0x00000010 #define VIVS_PE_LOGIC_OP_DITHER_MODE__MASK 0x00000060 #define VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT 5 #define VIVS_PE_LOGIC_OP_DITHER_MODE(x) (((x) << VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT) & VIVS_PE_LOGIC_OP_DITHER_MODE__MASK) #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER_MASK 0x00000080 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK 0x00000300 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT 8 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER(x) (((x) << VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT) & VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK) #define VIVS_PE_LOGIC_OP_DITHER_MODE_MASK 0x00000400 #define VIVS_PE_LOGIC_OP_UNK11 0x00000800 #define VIVS_PE_LOGIC_OP_UNK20__MASK 0x00300000 #define VIVS_PE_LOGIC_OP_UNK20__SHIFT 20 #define VIVS_PE_LOGIC_OP_UNK20(x) (((x) << VIVS_PE_LOGIC_OP_UNK20__SHIFT) & VIVS_PE_LOGIC_OP_UNK20__MASK) #define VIVS_PE_LOGIC_OP_UNK20_MASK 0x00800000 #define VIVS_PE_LOGIC_OP_UNK24__MASK 0x07000000 #define VIVS_PE_LOGIC_OP_UNK24__SHIFT 24 #define VIVS_PE_LOGIC_OP_UNK24(x) (((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK) #define VIVS_PE_LOGIC_OP_UNK24_MASK 0x08000000 #define VIVS_PE_LOGIC_OP_SRGB_MASK 0x40000000 #define VIVS_PE_LOGIC_OP_SRGB 0x80000000 #define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0)) #define VIVS_PE_DITHER__ESIZE 0x00000004 #define VIVS_PE_DITHER__LEN 0x00000002 #define VIVS_PE_ALPHA_COLOR_EXT0 0x000014b0 #define VIVS_PE_ALPHA_COLOR_EXT0_B__MASK 0x0000ffff #define VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT 0 #define VIVS_PE_ALPHA_COLOR_EXT0_B(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_B__MASK) #define VIVS_PE_ALPHA_COLOR_EXT0_G__MASK 0xffff0000 #define VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT 16 #define VIVS_PE_ALPHA_COLOR_EXT0_G(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_G__MASK) #define VIVS_PE_ALPHA_COLOR_EXT1 0x000014b4 #define VIVS_PE_ALPHA_COLOR_EXT1_R__MASK 0x0000ffff #define VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT 0 #define VIVS_PE_ALPHA_COLOR_EXT1_R(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_R__MASK) #define VIVS_PE_ALPHA_COLOR_EXT1_A__MASK 0xffff0000 #define VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT 16 #define VIVS_PE_ALPHA_COLOR_EXT1_A(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_A__MASK) #define VIVS_PE_STENCIL_CONFIG_EXT2 0x000014b8 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK 0x000000ff #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT 0 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK) #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK 0x0000ff00 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT 8 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK) #define VIVS_PE_MEM_CONFIG 0x000014bc #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK 0x01000000 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT 24 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK) #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK 0x04000000 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT 26 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK) #define VIVS_PE_HALTI4_UNK014C0 0x000014c0 #define VIVS_PE_ROBUSTNESS_UNK014C4 0x000014c4 #define VIVS_PE_UNK01580(i0) (0x00001580 + 0x4*(i0)) #define VIVS_PE_UNK01580__ESIZE 0x00000004 #define VIVS_PE_UNK01580__LEN 0x00000003 #define VIVS_PE_RT_ADDR(i0) (0x00000000 + 0x20*(i0)) #define VIVS_PE_RT_ADDR__ESIZE 0x00000020 #define VIVS_PE_RT_ADDR__LEN 0x00000008 #define VIVS_PE_RT_ADDR_PIPE(i0, i1) (0x00014800 + 0x20*(i0) + 0x4*(i1)) #define VIVS_PE_RT_ADDR_PIPE__ESIZE 0x00000004 #define VIVS_PE_RT_ADDR_PIPE__LEN 0x00000008 #define VIVS_PE_RT_CONFIG(i0) (0x00014900 + 0x4*(i0)) #define VIVS_PE_RT_CONFIG__ESIZE 0x00000004 #define VIVS_PE_RT_CONFIG__LEN 0x00000008 #define VIVS_PE_RT_CONFIG_STRIDE__MASK 0x0000ffff #define VIVS_PE_RT_CONFIG_STRIDE__SHIFT 0 #define VIVS_PE_RT_CONFIG_STRIDE(x) (((x) << VIVS_PE_RT_CONFIG_STRIDE__SHIFT) & VIVS_PE_RT_CONFIG_STRIDE__MASK) #define VIVS_PE_RT_CONFIG_FORMAT__MASK 0x001f0000 #define VIVS_PE_RT_CONFIG_FORMAT__SHIFT 16 #define VIVS_PE_RT_CONFIG_FORMAT(x) (((x) << VIVS_PE_RT_CONFIG_FORMAT__SHIFT) & VIVS_PE_RT_CONFIG_FORMAT__MASK) #define VIVS_PE_RT_CONFIG_SUPER_TILED 0x04000000 #define VIVS_PE_RT_CONFIG_UNK28 0x10000000 #define VIVS_PE_HALTI5_UNK14920(i0) (0x00014920 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK14920__ESIZE 0x00000004 #define VIVS_PE_HALTI5_UNK14920__LEN 0x00000007 #define VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK 0x000000f0 #define VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT 4 #define VIVS_PE_HALTI5_UNK14920_COMPONENTS(x) (((x) << VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK) #define VIVS_PE_HALTI5_UNK14920_UNK8 0x00000100 #define VIVS_PE_HALTI5_UNK14940(i0) (0x00014940 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK14940__ESIZE 0x00000004 #define VIVS_PE_HALTI5_UNK14940__LEN 0x00000007 #define VIVS_PE_HALTI5_UNK14960(i0) (0x00014960 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK14960__ESIZE 0x00000004 #define VIVS_PE_HALTI5_UNK14960__LEN 0x00000007 #define VIVS_PE_HALTI5_UNK14980(i0) (0x00014980 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK14980__ESIZE 0x00000004 #define VIVS_PE_HALTI5_UNK14980__LEN 0x00000007 #define VIVS_PE_HALTI5_UNK149A0(i0) (0x000149a0 + 0x4*(i0)) #define VIVS_PE_HALTI5_UNK149A0__ESIZE 0x00000004 #define VIVS_PE_HALTI5_UNK149A0__LEN 0x00000007 #define VIVS_PE_ROBUSTNESS_UNK149C0(i0) (0x000149c0 + 0x4*(i0)) #define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE 0x00000004 #define VIVS_PE_ROBUSTNESS_UNK149C0__LEN 0x00000008 #define VIVS_CO 0x00000000 #define VIVS_CO_UNK03008 0x00003008 #define VIVS_CO_KICKER 0x0000300c #define VIVS_CO_UNK03010 0x00003010 #define VIVS_CO_UNK03014 0x00003014 #define VIVS_CO_UNK03018 0x00003018 #define VIVS_CO_UNK0301C 0x0000301c #define VIVS_CO_UNK03020 0x00003020 #define VIVS_CO_UNK03024 0x00003024 #define VIVS_CO_UNK03040 0x00003040 #define VIVS_CO_UNK03044 0x00003044 #define VIVS_CO_UNK03048 0x00003048 #define VIVS_CO_ICACHE_UNK0304C 0x0000304c #define VIVS_CO_SAMPLER(i0) (0x00000000 + 0x4*(i0)) #define VIVS_CO_SAMPLER__ESIZE 0x00000004 #define VIVS_CO_SAMPLER__LEN 0x00000008 #define VIVS_CO_SAMPLER_UNK03060(i0) (0x00003060 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK03080(i0) (0x00003080 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK030A0(i0) (0x000030a0 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK030C0(i0) (0x000030c0 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK030E0(i0) (0x000030e0 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK03100(i0) (0x00003100 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK03120(i0) (0x00003120 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK03140(i0) (0x00003140 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK03160(i0) (0x00003160 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK03180(i0) (0x00003180 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK031A0(i0) (0x000031a0 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK031C0(i0) (0x000031c0 + 0x4*(i0)) #define VIVS_CO_SAMPLER_UNK031E0(i0) (0x000031e0 + 0x4*(i0)) #define VIVS_CO_ADDR_UNK03200(i0) (0x00003200 + 0x20*(i0)) #define VIVS_CO_ADDR_UNK03200__ESIZE 0x00000020 #define VIVS_CO_ADDR_UNK03200__LEN 0x00000008 #define VIVS_CO_ADDR_UNK03200_PPIPE(i0, i1) (0x00003200 + 0x20*(i0) + 0x4*(i1)) #define VIVS_CO_ADDR_UNK03200_PPIPE__ESIZE 0x00000004 #define VIVS_CO_ADDR_UNK03200_PPIPE__LEN 0x00000008 #define VIVS_RS 0x00000000 #define VIVS_RS_KICKER 0x00001600 #define VIVS_RS_CONFIG 0x00001604 #define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK 0x0000001f #define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT 0 #define VIVS_RS_CONFIG_SOURCE_FORMAT(x) (((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK) #define VIVS_RS_CONFIG_DOWNSAMPLE_X 0x00000020 #define VIVS_RS_CONFIG_DOWNSAMPLE_Y 0x00000040 #define VIVS_RS_CONFIG_SOURCE_TILED 0x00000080 #define VIVS_RS_CONFIG_DEST_FORMAT__MASK 0x00001f00 #define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT 8 #define VIVS_RS_CONFIG_DEST_FORMAT(x) (((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK) #define VIVS_RS_CONFIG_DEST_TILED 0x00004000 #define VIVS_RS_CONFIG_SWAP_RB 0x20000000 #define VIVS_RS_CONFIG_FLIP 0x40000000 #define VIVS_RS_SOURCE_ADDR 0x00001608 #define VIVS_RS_SOURCE_STRIDE 0x0000160c #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK 0x0003ffff #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT 0 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x) (((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK) #define VIVS_RS_SOURCE_STRIDE_MULTI 0x40000000 #define VIVS_RS_SOURCE_STRIDE_TILING 0x80000000 #define VIVS_RS_DEST_ADDR 0x00001610 #define VIVS_RS_DEST_STRIDE 0x00001614 #define VIVS_RS_DEST_STRIDE_STRIDE__MASK 0x0003ffff #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT 0 #define VIVS_RS_DEST_STRIDE_STRIDE(x) (((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK) #define VIVS_RS_DEST_STRIDE_MULTI 0x40000000 #define VIVS_RS_DEST_STRIDE_TILING 0x80000000 #define VIVS_RS_WINDOW_SIZE 0x00001620 #define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK 0xffff0000 #define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT 16 #define VIVS_RS_WINDOW_SIZE_HEIGHT(x) (((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK) #define VIVS_RS_WINDOW_SIZE_WIDTH__MASK 0x0000ffff #define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT 0 #define VIVS_RS_WINDOW_SIZE_WIDTH(x) (((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK) #define VIVS_RS_DITHER(i0) (0x00001630 + 0x4*(i0)) #define VIVS_RS_DITHER__ESIZE 0x00000004 #define VIVS_RS_DITHER__LEN 0x00000002 #define VIVS_RS_CLEAR_CONTROL 0x0000163c #define VIVS_RS_CLEAR_CONTROL_BITS__MASK 0x0000ffff #define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT 0 #define VIVS_RS_CLEAR_CONTROL_BITS(x) (((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK) #define VIVS_RS_CLEAR_CONTROL_MODE__MASK 0x00030000 #define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT 16 #define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED 0x00000000 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 0x00010000 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4 0x00020000 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2 0x00030000 #define VIVS_RS_FILL_VALUE(i0) (0x00001640 + 0x4*(i0)) #define VIVS_RS_FILL_VALUE__ESIZE 0x00000004 #define VIVS_RS_FILL_VALUE__LEN 0x00000004 #define VIVS_RS_EXTRA_CONFIG 0x000016a0 #define VIVS_RS_EXTRA_CONFIG_AA__MASK 0x00000003 #define VIVS_RS_EXTRA_CONFIG_AA__SHIFT 0 #define VIVS_RS_EXTRA_CONFIG_AA(x) (((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK) #define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK 0x00000300 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT 8 #define VIVS_RS_EXTRA_CONFIG_ENDIAN(x) (((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK) #define VIVS_RS_EXTRA_CONFIG_UNK20 0x00100000 #define VIVS_RS_EXTRA_CONFIG_UNK28 0x10000000 #define VIVS_RS_KICKER_INPLACE 0x000016b0 #define VIVS_RS_UNK016B4 0x000016b4 #define VIVS_RS_SINGLE_BUFFER 0x000016b8 #define VIVS_RS_SINGLE_BUFFER_ENABLE 0x00000001 #define VIVS_RS_PIPE(i0) (0x00000000 + 0x4*(i0)) #define VIVS_RS_PIPE__ESIZE 0x00000004 #define VIVS_RS_PIPE__LEN 0x00000008 #define VIVS_RS_PIPE_SOURCE_ADDR(i0) (0x000016c0 + 0x4*(i0)) #define VIVS_RS_PIPE_DEST_ADDR(i0) (0x000016e0 + 0x4*(i0)) #define VIVS_RS_PIPE_OFFSET(i0) (0x00001700 + 0x4*(i0)) #define VIVS_RS_PIPE_OFFSET_X__MASK 0x0000ffff #define VIVS_RS_PIPE_OFFSET_X__SHIFT 0 #define VIVS_RS_PIPE_OFFSET_X(x) (((x) << VIVS_RS_PIPE_OFFSET_X__SHIFT) & VIVS_RS_PIPE_OFFSET_X__MASK) #define VIVS_RS_PIPE_OFFSET_Y__MASK 0xffff0000 #define VIVS_RS_PIPE_OFFSET_Y__SHIFT 16 #define VIVS_RS_PIPE_OFFSET_Y(x) (((x) << VIVS_RS_PIPE_OFFSET_Y__SHIFT) & VIVS_RS_PIPE_OFFSET_Y__MASK) #define VIVS_TS 0x00000000 #define VIVS_TS_FLUSH_CACHE 0x00001650 #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 #define VIVS_TS_MEM_CONFIG 0x00001654 #define VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR 0x00000001 #define VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR 0x00000002 #define VIVS_TS_MEM_CONFIG_DEPTH_16BPP 0x00000008 #define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE 0x00000010 #define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE 0x00000020 #define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION 0x00000040 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION 0x00000080 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK 0x00000f00 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT 8 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK) #define VIVS_TS_MEM_CONFIG_UNK12 0x00001000 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE 0x00002000 #define VIVS_TS_MEM_CONFIG_STENCIL_ENABLE 0x00004000 #define VIVS_TS_MEM_CONFIG_UNK21 0x00200000 #define VIVS_TS_COLOR_STATUS_BASE 0x00001658 #define VIVS_TS_COLOR_SURFACE_BASE 0x0000165c #define VIVS_TS_COLOR_CLEAR_VALUE 0x00001660 #define VIVS_TS_DEPTH_STATUS_BASE 0x00001664 #define VIVS_TS_DEPTH_SURFACE_BASE 0x00001668 #define VIVS_TS_DEPTH_CLEAR_VALUE 0x0000166c #define VIVS_TS_DEPTH_AUTO_DISABLE_COUNT 0x00001670 #define VIVS_TS_COLOR_AUTO_DISABLE_COUNT 0x00001674 #define VIVS_TS_HDEPTH_STATUS_BASE 0x000016a4 #define VIVS_TS_HDEPTH_CLEAR_VALUE 0x000016a8 #define VIVS_TS_HDEPTH_SIZE 0x000016ac #define VIVS_TS_COLOR_CLEAR_VALUE_EXT 0x000016bc #define VIVS_TS_SAMPLER(i0) (0x00000000 + 0x4*(i0)) #define VIVS_TS_SAMPLER__ESIZE 0x00000004 #define VIVS_TS_SAMPLER__LEN 0x00000008 #define VIVS_TS_SAMPLER_CONFIG(i0) (0x00001720 + 0x4*(i0)) #define VIVS_TS_SAMPLER_CONFIG_ENABLE 0x00000001 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION 0x00000002 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK 0x000000f0 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT 4 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK) #define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK 0x00003800 #define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT 11 #define VIVS_TS_SAMPLER_CONFIG_UNK11(x) (((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK) #define VIVS_TS_SAMPLER_STATUS_BASE(i0) (0x00001740 + 0x4*(i0)) #define VIVS_TS_SAMPLER_CLEAR_VALUE(i0) (0x00001760 + 0x4*(i0)) #define VIVS_TS_SAMPLER_CLEAR_VALUE2(i0) (0x00001780 + 0x4*(i0)) #define VIVS_TS_SAMPLER_SURFACE_BASE(i0) (0x00001a80 + 0x4*(i0)) #define VIVS_TS_RT(i0) (0x00000000 + 0x4*(i0)) #define VIVS_TS_RT__ESIZE 0x00000004 #define VIVS_TS_RT__LEN 0x00000008 #define VIVS_TS_RT_UNK017A0(i0) (0x000017a0 + 0x4*(i0)) #define VIVS_TS_RT_STATUS_BASE(i0) (0x000017c0 + 0x4*(i0)) #define VIVS_TS_RT_SURFACE_BASE(i0) (0x000017e0 + 0x4*(i0)) #define VIVS_TS_RT_CLEAR_VALUE(i0) (0x00001a00 + 0x4*(i0)) #define VIVS_TS_RT_CLEAR_VALUE2(i0) (0x00001a20 + 0x4*(i0)) #define VIVS_TS_RT_UNK01A40(i0) (0x00001a40 + 0x4*(i0)) #define VIVS_YUV 0x00000000 #define VIVS_YUV_CONFIG 0x00001678 #define VIVS_YUV_CONFIG_ENABLE 0x00000001 #define VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK 0x00000030 #define VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT 4 #define VIVS_YUV_CONFIG_SOURCE_FORMAT(x) (((x) << VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK) #define VIVS_YUV_CONFIG_UV_SWAP 0x00000100 #define VIVS_YUV_WINDOW_SIZE 0x0000167c #define VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK 0xffff0000 #define VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT 16 #define VIVS_YUV_WINDOW_SIZE_HEIGHT(x) (((x) << VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK) #define VIVS_YUV_WINDOW_SIZE_WIDTH__MASK 0x0000ffff #define VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT 0 #define VIVS_YUV_WINDOW_SIZE_WIDTH(x) (((x) << VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_YUV_WINDOW_SIZE_WIDTH__MASK) #define VIVS_YUV_Y_BASE 0x00001680 #define VIVS_YUV_Y_STRIDE 0x00001684 #define VIVS_YUV_U_BASE 0x00001688 #define VIVS_YUV_U_STRIDE 0x0000168c #define VIVS_YUV_V_BASE 0x00001690 #define VIVS_YUV_V_STRIDE 0x00001694 #define VIVS_YUV_DEST_BASE 0x00001698 #define VIVS_YUV_DEST_STRIDE 0x0000169c #define VIVS_TE 0x00000000 #define VIVS_TE_SAMPLER(i0) (0x00000000 + 0x4*(i0)) #define VIVS_TE_SAMPLER__ESIZE 0x00000004 #define VIVS_TE_SAMPLER__LEN 0x0000000c #define VIVS_TE_SAMPLER_CONFIG0(i0) (0x00002000 + 0x4*(i0)) #define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK 0x00000007 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT 0 #define VIVS_TE_SAMPLER_CONFIG0_TYPE(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK) #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK 0x00000018 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT 3 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK) #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK 0x00000060 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT 5 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK) #define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK 0x00000180 #define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT 7 #define VIVS_TE_SAMPLER_CONFIG0_MIN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK) #define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK 0x00000600 #define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT 9 #define VIVS_TE_SAMPLER_CONFIG0_MIP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK) #define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK 0x00001800 #define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT 11 #define VIVS_TE_SAMPLER_CONFIG0_MAG(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK) #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK 0x0003e000 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT 13 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK) #define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV 0x00080000 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK 0x00300000 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT 20 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK) #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK) #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK 0xff000000 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT 24 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK) #define VIVS_TE_SAMPLER_SIZE(i0) (0x00002040 + 0x4*(i0)) #define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK 0x0000ffff #define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT 0 #define VIVS_TE_SAMPLER_SIZE_WIDTH(x) (((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK) #define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK 0xffff0000 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT 16 #define VIVS_TE_SAMPLER_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK) #define VIVS_TE_SAMPLER_LOG_SIZE(i0) (0x00002080 + 0x4*(i0)) #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK 0x000003ff #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT 0 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK) #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK) #define VIVS_TE_SAMPLER_LOG_SIZE_ASTC 0x10000000 #define VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000 #define VIVS_TE_SAMPLER_LOG_SIZE_SRGB 0x80000000 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0) (0x000020c0 + 0x4*(i0)) #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE 0x00000001 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK 0x000007fe #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT 1 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK) #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK 0x001ff800 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT 11 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK) #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK 0x7fe00000 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT 21 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK) #define VIVS_TE_SAMPLER_UNK02100(i0) (0x00002100 + 0x4*(i0)) #define VIVS_TE_SAMPLER_UNK02140(i0) (0x00002140 + 0x4*(i0)) #define VIVS_TE_SAMPLER_3D_CONFIG(i0) (0x00002180 + 0x4*(i0)) #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK) #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK) #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK) #define VIVS_TE_SAMPLER_CONFIG1(i0) (0x000021c0 + 0x4*(i0)) #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT 8 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK) #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK 0x00007000 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT 12 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK) #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK 0x00070000 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT 16 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK) #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK 0x00800000 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT 23 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK) #define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000 #define VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP 0x02000000 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT 26 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK) #define VIVS_TE_SAMPLER_CONFIG1_USE_TS 0x40000000 #define VIVS_TE_SAMPLER_UNK02200(i0) (0x00002200 + 0x4*(i0)) #define VIVS_TE_SAMPLER_UNK02240(i0) (0x00002240 + 0x4*(i0)) #define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1) (0x00002400 + 0x4*(i0) + 0x40*(i1)) #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE 0x00000040 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN 0x0000000e #define VIVS_TE_SAMPLER_LINEAR_STRIDE(i0, i1) (0x00002c00 + 0x4*(i0) + 0x40*(i1)) #define VIVS_TE_SAMPLER_LINEAR_STRIDE__ESIZE 0x00000040 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN 0x0000000e #define VIVS_NTE 0x00000000 #define VIVS_NTE_SAMPLER(i0) (0x00000000 + 0x4*(i0)) #define VIVS_NTE_SAMPLER__ESIZE 0x00000004 #define VIVS_NTE_SAMPLER__LEN 0x00000020 #define VIVS_NTE_SAMPLER_CONFIG0(i0) (0x00010000 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK 0x00000007 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT 0 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK 0x00000018 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT 3 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK 0x00000060 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT 5 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK 0x00000180 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT 7 #define VIVS_NTE_SAMPLER_CONFIG0_MIN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK 0x00000600 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT 9 #define VIVS_NTE_SAMPLER_CONFIG0_MIP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK 0x00001800 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT 11 #define VIVS_NTE_SAMPLER_CONFIG0_MAG(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK 0x0003e000 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT 13 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV 0x00080000 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK 0x00300000 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT 20 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK) #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK 0xff000000 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT 24 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK) #define VIVS_NTE_SAMPLER_SIZE(i0) (0x00010080 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK 0x0000ffff #define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT 0 #define VIVS_NTE_SAMPLER_SIZE_WIDTH(x) (((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK) #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK 0xffff0000 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT 16 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK) #define VIVS_NTE_SAMPLER_LOG_SIZE(i0) (0x00010100 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK 0x000003ff #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT 0 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK) #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK) #define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC 0x10000000 #define VIVS_NTE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000 #define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB 0x80000000 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0) (0x00010180 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE 0x00000001 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK 0x000007fe #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT 1 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK) #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK 0x001ff800 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT 11 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK) #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK 0x7fe00000 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT 21 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK) #define VIVS_NTE_SAMPLER_UNK10200(i0) (0x00010200 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_UNK10280(i0) (0x00010280 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_3D_CONFIG(i0) (0x00010300 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK) #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK) #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK) #define VIVS_NTE_SAMPLER_CONFIG1(i0) (0x00010380 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT 8 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK 0x00007000 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT 12 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK 0x00070000 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT 16 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK 0x00800000 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT 23 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000 #define VIVS_NTE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP 0x02000000 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT 26 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK) #define VIVS_NTE_SAMPLER_CONFIG1_USE_TS 0x40000000 #define VIVS_NTE_SAMPLER_UNK10400(i0) (0x00010400 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_ASTC0(i0) (0x00010500 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK) #define VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT 8 #define VIVS_NTE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK) #define VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK 0x00ff0000 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT 16 #define VIVS_NTE_SAMPLER_ASTC0_UNK16(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK) #define VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK 0xff000000 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT 24 #define VIVS_NTE_SAMPLER_ASTC0_UNK24(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK) #define VIVS_NTE_SAMPLER_ASTC1(i0) (0x00010580 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_ASTC2(i0) (0x00010600 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010600 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_BASELOD(i0) (0x00010700 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK 0x0000000f #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT 0 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK) #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK 0x00000f00 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT 8 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK) #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE 0x00010000 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK 0x00700000 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT 20 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK) #define VIVS_NTE_SAMPLER_BASELOD_BASELOD_ENABLE 0x00800000 #define VIVS_NTE_SAMPLER_UNK10780(i0) (0x00010780 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_FRAC_UNK11000(i0) (0x00011000 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_FRAC_UNK11080(i0) (0x00011080 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_FRAC_UNK11100(i0) (0x00011100 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_FRAC_UNK11180(i0) (0x00011180 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_HALTI4_UNK11200(i0) (0x00011200 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_HALTI4_UNK11280(i0) (0x00011280 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_FRAC_UNK11300(i0) (0x00011300 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_ADDR(i0) (0x00010800 + 0x40*(i0)) #define VIVS_NTE_SAMPLER_ADDR__ESIZE 0x00000040 #define VIVS_NTE_SAMPLER_ADDR__LEN 0x00000020 #define VIVS_NTE_SAMPLER_ADDR_LOD(i0, i1) (0x00010800 + 0x40*(i0) + 0x4*(i1)) #define VIVS_NTE_SAMPLER_ADDR_LOD__ESIZE 0x00000004 #define VIVS_NTE_SAMPLER_ADDR_LOD__LEN 0x0000000e #define VIVS_NTE_UNK12000(i0) (0x00012000 + 0x4*(i0)) #define VIVS_NTE_UNK12000__ESIZE 0x00000004 #define VIVS_NTE_UNK12000__LEN 0x00000100 #define VIVS_NTE_UNK12400(i0) (0x00012400 + 0x4*(i0)) #define VIVS_NTE_UNK12400__ESIZE 0x00000004 #define VIVS_NTE_UNK12400__LEN 0x00000100 #define VIVS_NTE_HALTI3_UNK14C00(i0) (0x00014c00 + 0x4*(i0)) #define VIVS_NTE_HALTI3_UNK14C00__ESIZE 0x00000004 #define VIVS_NTE_HALTI3_UNK14C00__LEN 0x00000010 #define VIVS_NTE_DESCRIPTOR_UNK14C40 0x00014c40 #define VIVS_NTE_DESCRIPTOR_UNK14C40_UNK0 0x00000001 #define VIVS_NTE_DESCRIPTOR_FLUSH 0x00014c44 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK 0xf0000000 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT 28 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x) (((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK) #define VIVS_NTE_DESCRIPTOR_INVALIDATE 0x00014c48 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK 0x000001ff #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT 0 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX(x) (((x) << VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT) & VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK) #define VIVS_NTE_DESCRIPTOR_INVALIDATE_UNK29 0x20000000 #define VIVS_NTE_DESCRIPTOR(i0) (0x00000000 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR__ESIZE 0x00000004 #define VIVS_NTE_DESCRIPTOR__LEN 0x00000080 #define VIVS_NTE_DESCRIPTOR_ADDR_MIRROR(i0) (0x00015800 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_TX_CTRL_MIRROR(i0) (0x00015a00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_ADDR(i0) (0x00015c00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0) (0x00015e00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK 0x00000001 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT 0 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK) #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE 0x00000002 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK 0x0000001c #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT 2 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0) (0x00016000 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_MIRROR(i0) (0x00016200 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIRROR(i0) (0x00016400 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0) (0x00016600 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_UNK17400_MIRROR(i0) (0x00016800 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0) (0x00016c00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK 0x00000007 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT 0 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK 0x00000038 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT 3 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK 0x000001c0 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT 6 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK 0x00000600 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT 9 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK 0x00001800 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT 11 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK 0x00006000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT 13 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_ENABLE 0x00020000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK 0x001c0000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT 18 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22 0x00400000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER 0x00800000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0) (0x00016e00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1 0x00000002 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_SRGB 0x00000004 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK3 0x00000008 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK 0x00000030 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT 4 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(i0) (0x00017000 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK 0x0000ffff #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT 0 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK 0xffff0000 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT 16 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(i0) (0x00017200 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK 0x0000ffff #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT 0 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE 0x00010000 #define VIVS_NTE_DESCRIPTOR_UNK17400(i0) (0x00017400 + 0x4*(i0)) #define VIVS_SH 0x00000000 #define VIVS_SH_CONFIG 0x00015600 #define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002 #define VIVS_SH_CONFIG_DUAL16 0x00000004 #define VIVS_SH_UNK20000(i0) (0x00020000 + 0x4*(i0)) #define VIVS_SH_UNK20000__ESIZE 0x00000004 #define VIVS_SH_UNK20000__LEN 0x00002000 #define VIVS_SH_INST_MEM(i0) (0x0000c000 + 0x4*(i0)) #define VIVS_SH_INST_MEM__ESIZE 0x00000004 #define VIVS_SH_INST_MEM__LEN 0x00001000 #define VIVS_SH_INST_MEM_MIRROR(i0) (0x00008000 + 0x4*(i0)) #define VIVS_SH_INST_MEM_MIRROR__ESIZE 0x00000004 #define VIVS_SH_INST_MEM_MIRROR__LEN 0x00001000 #define VIVS_SH_UNIFORMS(i0) (0x00030000 + 0x4*(i0)) #define VIVS_SH_UNIFORMS__ESIZE 0x00000004 #define VIVS_SH_UNIFORMS__LEN 0x00000800 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR(i0) (0x00034000 + 0x4*(i0)) #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__ESIZE 0x00000004 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__LEN 0x00000800 #define VIVS_SH_HALTI5_UNIFORMS(i0) (0x00036000 + 0x4*(i0)) #define VIVS_SH_HALTI5_UNIFORMS__ESIZE 0x00000004 #define VIVS_SH_HALTI5_UNIFORMS__LEN 0x00000800 #endif /* STATE_3D_XML */