initialize CP's micro-engine skip N 32-bit words to get to the next packet indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB indirect buffer dispatch. same as IB, but init is pipelined wait for the IDLE state of the engine wait until a register or memory location is a specific value wait until a register location is equal to a specific value wait until a register location is >= a specific value wait until a read completes wait until all base/size writes from an IB_PFD packet have completed register read/modify/write Set binning configuration registers reads register in chip and writes to memory write N 32-bit words to memory write CP_PROG_COUNTER value to memory conditional execution of a sequence of packets conditional write to memory or register generate an event that creates a write to memory when completed generate a VS|PS_done event generate a cache flush done event generate a z_pass done event not sure the real name, but this seems to be what is used for opencl, instead of CP_DRAW_INDX.. initiate fetch of index buffer and draw draw using supplied indices in packet initiate fetch of index buffer and binIDs and draw initiate fetch of bin IDs and draw using supplied indices begin/end initiator for viz query extent processing fetch state sub-blocks and initiate shader code DMAs load constant into chip and to memory load sequencer instruction memory (pointer-based) load sequencer instruction memory (code embedded in packet) load constants from a location in memory selective invalidation of state pointers dynamically changes shader instruction memory partition sets the 64-bit BIN_MASK register in the PFP sets the 64-bit BIN_SELECT register in the PFP updates the current context, if needed generate interrupt from the command stream copy sequencer instruction memory to system memory sets draw initiator flags register in PFP, gets bitwise-ORed into every draw initiator sets the register protection mode load high level sequencer command Conditionally load a IB based on a flag, prefetch enabled Conditionally load a IB based on a flag, prefetch disabled Load a buffer with pre-fetch enabled Set bin (?) test 2 memory locations to dword values specified Write register, ignoring context state for context sensitive registers Record the real-time when this packet is processed by PFP PFP waits until the FIFO between the PFP and the ME is empty Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple groups of registers. Looks like it can be used to create state objects in GPU memory, and on state change only emit pointer (via CP_SET_DRAW_STATE), which should be nice for reducing CPU overhead: (A4x) save PM4 stream pointers to execute upon a visible draw set to 1 for fastclear..: for A4xx Write to register with address that does not fit into type-0 pkt copy from ME scratch RAM to a register Copy from REG to ME scratch RAM Wait for memory writes to complete Conditional execution based on register comparison Memory to REG copy for a5xx Tells CP the current mode of GPU operation Instruct CP to set a few internal CP registers Load state, a3xx (and later?) inline with the CP_LOAD_STATE packet in buffer pointed to by EXT_SRC_ADDR Load state, a4xx+ Load state, a6xx+ value at offset 0 always seems to be 0x00000000.. " " Tell CP the current operation mode, indicates save and restore procedure Set internal CP registers, used to indicate context save data addresses Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. So: opcode: CP_REG_TEST (39) (2 dwords) { REG = 0xc10 | BIT = 0 } 0000: 70b90001 00000c10 opcode: CP_COND_REG_EXEC (47) (3 dwords) 0000: 70c70002 10000000 00000004 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) Will execute the CP_INDIRECT_BUFFER only if b0 in the register at offset 0x0c10 is 1