From e87c63f2889fcbeb5a8bbd91eda1333d7ed44bf2 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Fri, 28 Sep 2012 15:38:26 -0700 Subject: i965: brwInitVtbl needs to know the chipset generation Fixes major regressions since de958de. Signed-off-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_context.c | 5 +++++ src/mesa/drivers/dri/i965/brw_vtbl.c | 1 + 2 files changed, 6 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 418c8737145..e94df2658ce 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -140,6 +140,11 @@ brwCreateContext(int api, return false; } + /* brwInitVtbl needs to know the chipset generation so that it can set the + * right pointers. + */ + brw->intel.gen = screen->gen; + brwInitVtbl( brw ); brwInitDriverFunctions(screen, &functions); diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 9951e7da2cc..ca2e7a9a5ba 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -249,6 +249,7 @@ void brwInitVtbl( struct brw_context *brw ) brw->intel.vtbl.render_target_supported = brw_render_target_supported; brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format; + assert(brw->intel.gen >= 4); if (brw->intel.gen >= 7) { gen7_init_vtable_surface_functions(brw); } else if (brw->intel.gen >= 4) { -- cgit v1.2.3