From dd119a4263452a36e9d4938a39ddbc8d6bf298f7 Mon Sep 17 00:00:00 2001 From: Timothy Arceri Date: Tue, 12 Dec 2017 13:49:41 +1100 Subject: st/glsl_to_nir: skip forced array splitting for tcs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nir_lower_io_to_temporaries() does not support tcs so we cannot assume there are no indirects here. Also the radeonsi backend (the only backend to support tess) has support for tcs indirects so there is no need to lower them anyway. Reviewed-by: Nicolai Hähnle --- src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp index 36adf55cd45..7357eebae0c 100644 --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp @@ -642,7 +642,8 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog, NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_lower_var_copies); - NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects); + if (nir->info.stage != MESA_SHADER_TESS_CTRL) + NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects); if (nir->info.stage == MESA_SHADER_VERTEX) { /* Needs special handling so drvloc matches the vbo state: */ -- cgit v1.2.3