From db31bc5cfb7c08c1a32067b09d769c880bc4e954 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 7 Feb 2013 18:46:18 -0800 Subject: i965: Don't flush the batch at the end of blorp. Improves GLB2.7 performance 0.13% +/- 0.09% (n=104/105, outliers removed). More importantly, once color glClear()s are done through blorp in the next commit, this reduces regression in GLES3 conformance tests that rely on queueing up many glClear()s and having the GPU report being still busy in an ARB_sync query after that. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 19 +++++++++++++++++++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 9 --------- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 9 --------- 3 files changed, 19 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index c60f4f15382..8a044c1a271 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -21,6 +21,7 @@ * IN THE SOFTWARE. */ +#include "intel_batchbuffer.h" #include "intel_fbo.h" #include "brw_blorp.h" @@ -163,6 +164,8 @@ intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt, void brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params) { + struct brw_context *brw = brw_context(&intel->ctx); + switch (intel->gen) { case 6: gen6_blorp_exec(intel, params); @@ -175,6 +178,22 @@ brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params) assert(false); break; } + + if (unlikely(intel->always_flush_batch)) + intel_batchbuffer_flush(intel); + + /* We've smashed all state compared to what the normal 3D pipeline + * rendering tracks for GL. + */ + brw->state.dirty.brw = ~0; + brw->state.dirty.cache = ~0; + brw->state_batch_count = 0; + intel->batch.need_workaround_flush = true; + + /* Flush the sampler cache so any texturing from the destination is + * coherent. + */ + intel_batchbuffer_emit_mi_flush(intel); } brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt, diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index b6fbd44d3b6..872c408f28c 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -1093,14 +1093,5 @@ gen6_blorp_exec(struct intel_context *intel, gen6_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); gen6_blorp_emit_primitive(brw, params); - - /* See comments above at first invocation of intel_flush() in - * gen6_blorp_emit_batch_head(). - */ - intel_flush(ctx); - - /* Be safe. */ - brw->state.dirty.brw = ~0; - brw->state.dirty.cache = ~0; } diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 290ad359cf7..99e7e58cd93 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -807,13 +807,4 @@ gen7_blorp_exec(struct intel_context *intel, gen7_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); gen7_blorp_emit_primitive(brw, params); - - /* See comments above at first invocation of intel_flush() in - * gen6_blorp_emit_batch_head(). - */ - intel_flush(ctx); - - /* Be safe. */ - brw->state.dirty.brw = ~0; - brw->state.dirty.cache = ~0; } -- cgit v1.2.3