From c17d5de593fbfee91b799894b1c1a8a37a6a9c95 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 18 Aug 2010 11:57:28 +0300 Subject: r600: implement DP2 opcode --- src/mesa/drivers/dri/r600/r700_assembler.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 94bc26145d6..4902f7630ca 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3017,7 +3017,14 @@ GLboolean assemble_DOT(r700_AssemblerBase *pAsm) return GL_FALSE; } - if(OPCODE_DP3 == pAsm->pILInst[pAsm->uiCurInst].Opcode) + if(OPCODE_DP2 == pAsm->pILInst[pAsm->uiCurInst].Opcode) + { + zerocomp_PVSSRC(&(pAsm->S[0].src),2); + zerocomp_PVSSRC(&(pAsm->S[0].src),3); + zerocomp_PVSSRC(&(pAsm->S[1].src),2); + zerocomp_PVSSRC(&(pAsm->S[1].src),3); + } + else if(OPCODE_DP3 == pAsm->pILInst[pAsm->uiCurInst].Opcode) { zerocomp_PVSSRC(&(pAsm->S[0].src), 3); zerocomp_PVSSRC(&(pAsm->S[1].src), 3); @@ -5694,6 +5701,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; break; + case OPCODE_DP2: case OPCODE_DP3: case OPCODE_DP4: case OPCODE_DPH: @@ -6019,7 +6027,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_TRUE; default: - radeon_error("internal: unknown instruction\n"); + radeon_error("r600: unknown instruction %d\n", pILInst[i].Opcode); return GL_FALSE; } } -- cgit v1.2.3