From be07cc43a2cd315a275e4b2f0cb384798c4a0dd4 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Mon, 28 May 2018 23:18:41 -0700 Subject: i965/draw: Set the r8stencil flag after drawing Fixes the regresion introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd "i965: Use ISL for emitting depth/stencil/hiz state on gen6+" Found by inspection. Prevents regressing the piglit test, fbo-depth-array stencil-draw, later on in this series. Cc: Jason Ekstrand Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 18aa12feaef..271456e0f7d 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -576,6 +576,9 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw, * If the depth buffer was written to and if it has an accompanying HiZ * buffer, then mark that it needs a depth resolve. * + * If the stencil buffer was written to then mark that it may need to be + * copied to an R8 texture. + * * If the color buffer is a multisample window system buffer, then * mark that it needs a downsample. * @@ -619,8 +622,15 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) brw_depth_cache_add_bo(brw, depth_irb->mt->bo); } - if (stencil_irb && brw->stencil_write_enabled) + if (stencil_irb && brw->stencil_write_enabled) { brw_depth_cache_add_bo(brw, stencil_irb->mt->bo); + struct intel_mipmap_tree *stencil_mt = + stencil_irb->mt->stencil_mt != NULL ? + stencil_irb->mt->stencil_mt : stencil_irb->mt; + intel_miptree_finish_write(brw, stencil_mt, stencil_irb->mt_level, + stencil_irb->mt_layer, + stencil_irb->layer_count, ISL_AUX_USAGE_NONE); + } for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { struct intel_renderbuffer *irb = -- cgit v1.2.3