From aeaba24fcb98839be73a59f6bb74a39523d79a3d Mon Sep 17 00:00:00 2001 From: Jason Ekstrand <jason.ekstrand@intel.com> Date: Thu, 21 Feb 2019 10:14:17 -0600 Subject: intel/compiler: Drop unused surface opcodes The unused typed surface read/write support in the vec4 back-end has been dropped and the fs back-end now uses SHADER_OPCODE_SEND for all image and buffer ops. There's no reason to keep these opcodes around anymore. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> --- src/intel/compiler/brw_eu_defines.h | 6 ------ src/intel/compiler/brw_fs.cpp | 18 ------------------ src/intel/compiler/brw_fs_copy_propagation.cpp | 6 ------ src/intel/compiler/brw_fs_dead_code_eliminate.cpp | 2 -- src/intel/compiler/brw_schedule_instructions.cpp | 4 ---- src/intel/compiler/brw_shader.cpp | 18 ------------------ src/intel/compiler/brw_vec4.cpp | 6 ------ 7 files changed, 60 deletions(-) (limited to 'src') diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 05649344f48..bd5e71e1419 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -404,7 +404,6 @@ enum opcode { */ SHADER_OPCODE_UNTYPED_ATOMIC, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, - SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT, SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, SHADER_OPCODE_UNTYPED_SURFACE_READ, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, @@ -426,11 +425,8 @@ enum opcode { SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL, - SHADER_OPCODE_TYPED_ATOMIC, SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, - SHADER_OPCODE_TYPED_SURFACE_READ, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, - SHADER_OPCODE_TYPED_SURFACE_WRITE, SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, SHADER_OPCODE_RND_MODE, @@ -442,9 +438,7 @@ enum opcode { * opcode, but instead of taking a single payload blog they expect their * arguments separately as individual sources, like untyped write/read. */ - SHADER_OPCODE_BYTE_SCATTERED_READ, SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, - SHADER_OPCODE_BYTE_SCATTERED_WRITE, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, SHADER_OPCODE_MEMORY_FENCE, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 02579747d41..ff7af516b08 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -222,14 +222,8 @@ fs_inst::is_send_from_grf() const case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: case SHADER_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE: - case SHADER_OPCODE_BYTE_SCATTERED_READ: - case SHADER_OPCODE_TYPED_ATOMIC: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: case SHADER_OPCODE_URB_WRITE_SIMD8: case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: @@ -287,14 +281,8 @@ fs_inst::is_control_source(unsigned arg) const case SHADER_OPCODE_TG4_OFFSET: case SHADER_OPCODE_SAMPLEINFO: case SHADER_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_BYTE_SCATTERED_READ: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE: - case SHADER_OPCODE_TYPED_ATOMIC: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: return arg == 1 || arg == 2; case SHADER_OPCODE_SEND: @@ -966,16 +954,10 @@ fs_inst::size_read(int arg) const case SHADER_OPCODE_URB_READ_SIMD8: case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case SHADER_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_TYPED_ATOMIC: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: case FS_OPCODE_INTERPOLATE_AT_SAMPLE: case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE: - case SHADER_OPCODE_BYTE_SCATTERED_READ: if (arg == 0) return mlen * REG_SIZE; break; diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp index c23ce1ef426..6756694eca6 100644 --- a/src/intel/compiler/brw_fs_copy_propagation.cpp +++ b/src/intel/compiler/brw_fs_copy_propagation.cpp @@ -710,14 +710,8 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) break; case SHADER_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_TYPED_ATOMIC: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE: - case SHADER_OPCODE_BYTE_SCATTERED_READ: /* We only propagate into the surface argument of the * instruction. Everything else goes through LOAD_PAYLOAD. */ diff --git a/src/intel/compiler/brw_fs_dead_code_eliminate.cpp b/src/intel/compiler/brw_fs_dead_code_eliminate.cpp index eeb71dd2b92..ea460c3e264 100644 --- a/src/intel/compiler/brw_fs_dead_code_eliminate.cpp +++ b/src/intel/compiler/brw_fs_dead_code_eliminate.cpp @@ -55,9 +55,7 @@ can_omit_write(const fs_inst *inst) switch (inst->opcode) { case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return true; default: diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 861b2abfff2..4a516223cf9 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -368,8 +368,6 @@ schedule_node::set_latency_gen7(bool is_haswell) break; case SHADER_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: - case SHADER_OPCODE_TYPED_ATOMIC: /* Test code: * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q }; * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all }; @@ -389,8 +387,6 @@ schedule_node::set_latency_gen7(bool is_haswell) case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: /* Test code: * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q }; * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all }; diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 7b1a835e65b..2afb6699d7e 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -280,8 +280,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) return "untyped_atomic"; case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: return "untyped_atomic_logical"; - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: - return "untyped_atomic_float"; case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: return "untyped_atomic_float_logical"; case SHADER_OPCODE_UNTYPED_SURFACE_READ: @@ -304,16 +302,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) return "a64_untyped_atomic_logical"; case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL: return "a64_untyped_atomic_float_logical"; - case SHADER_OPCODE_TYPED_ATOMIC: - return "typed_atomic"; case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return "typed_atomic_logical"; - case SHADER_OPCODE_TYPED_SURFACE_READ: - return "typed_surface_read"; case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: return "typed_surface_read_logical"; - case SHADER_OPCODE_TYPED_SURFACE_WRITE: - return "typed_surface_write"; case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: return "typed_surface_write_logical"; case SHADER_OPCODE_MEMORY_FENCE: @@ -322,12 +314,8 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) /* For an interlock we actually issue a memory fence via sendc. */ return "interlock"; - case SHADER_OPCODE_BYTE_SCATTERED_READ: - return "byte_scattered_read"; case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: return "byte_scattered_read_logical"; - case SHADER_OPCODE_BYTE_SCATTERED_WRITE: - return "byte_scattered_write"; case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: return "byte_scattered_write_logical"; @@ -1015,7 +1003,6 @@ backend_instruction::has_side_effects() const case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: @@ -1024,11 +1011,8 @@ backend_instruction::has_side_effects() const case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_MEMORY_FENCE: case SHADER_OPCODE_INTERLOCK: @@ -1058,9 +1042,7 @@ backend_instruction::is_volatile() const case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_READ: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_READ: case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 4489c682d01..74f3539af2d 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -156,9 +156,6 @@ vec4_instruction::is_send_from_grf() case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_TYPED_ATOMIC: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: case VEC4_OPCODE_URB_READ: case TCS_OPCODE_URB_WRITE: case TCS_OPCODE_RELEASE_INPUT: @@ -215,9 +212,6 @@ vec4_instruction::size_read(unsigned arg) const case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_TYPED_ATOMIC: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: case TCS_OPCODE_URB_WRITE: if (arg == 0) return mlen * REG_SIZE; -- cgit v1.2.3