From a2b2cd81d16b929a9699ebebc8023aec258622fd Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sat, 14 Jan 2017 18:39:41 -0500 Subject: gallium: add TGSI_PROPERTY_MUL_ZERO_WINS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will be useful for proper D3D9 emulation, where this behavior is expected by some shaders. Signed-off-by: Ilia Mirkin Reviewed-by: Nicolai Hähnle Reviewed-by: Axel Davy --- src/gallium/auxiliary/tgsi/tgsi_strings.c | 3 ++- src/gallium/docs/source/tgsi.rst | 17 +++++++++++++++-- src/gallium/include/pipe/p_shader_tokens.h | 1 + 3 files changed, 18 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c b/src/gallium/auxiliary/tgsi/tgsi_strings.c index 536a4c8f3a9..cebc1b49d98 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_strings.c +++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c @@ -148,7 +148,8 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] = "NEXT_SHADER", "CS_FIXED_BLOCK_WIDTH", "CS_FIXED_BLOCK_HEIGHT", - "CS_FIXED_BLOCK_DEPTH" + "CS_FIXED_BLOCK_DEPTH", + "MUL_ZERO_WINS", }; const char *tgsi_return_type_names[TGSI_RETURN_TYPE_COUNT] = diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index b981278821c..341b41fb2da 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -3547,13 +3547,26 @@ Which shader stage will MOST LIKELY follow after this shader when the shader is bound. This is only a hint to the driver and doesn't have to be precise. Only set for VS and TES. -TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH / HEIGHT / DEPTH -""""""""""""""""""""""""""""""""""""""""""""""""""" +CS_FIXED_BLOCK_WIDTH / HEIGHT / DEPTH +""""""""""""""""""""""""""""""""""""" Threads per block in each dimension, if known at compile time. If the block size is known all three should be at least 1. If it is unknown they should all be set to 0 or not set. +MUL_ZERO_WINS +""""""""""""" + +The MUL TGSI operation (FP32 multiplication) will return 0 if either +of the operands are equal to 0. That means that 0 * Inf = 0. This +should be set the same way for an entire pipeline. Note that this +applies not only to the literal MUL TGSI opcode, but all FP32 +multiplications implied by other operations, such as MAD, FMA, DP2, +DP3, DP4, DPH, DST, LOG, LRP, XPD, and possibly others. If there is a +mismatch between shaders, then it is unspecified whether this behavior +will be enabled. + + Texture Sampling and Texture Formats ------------------------------------ diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index b2d440a0b91..1c8d87cce90 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -290,6 +290,7 @@ enum tgsi_property_name { TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, + TGSI_PROPERTY_MUL_ZERO_WINS, TGSI_PROPERTY_COUNT, }; -- cgit v1.2.3