From e5d5dab8c03f72097ec3e5b465fe93b6e369bb2d Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 5 Nov 2008 14:31:46 +0100 Subject: r300: bo and cs abstraction. This abstract memory management and command stream building so we can use different backend either legacy one which use old pathway or a new one like with a new memory manager. This works was done by : Nicolai Haehnle Dave Airlie Jerome Glisse --- src/mesa/drivers/dri/r300/Makefile | 16 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 306 ++++----- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 126 ++-- src/mesa/drivers/dri/r300/r300_context.c | 135 +--- src/mesa/drivers/dri/r300/r300_context.h | 151 ++--- src/mesa/drivers/dri/r300/r300_emit.c | 164 ++--- src/mesa/drivers/dri/r300/r300_emit.h | 130 +--- src/mesa/drivers/dri/r300/r300_ioctl.c | 854 +++++++++---------------- src/mesa/drivers/dri/r300/r300_ioctl.h | 13 +- src/mesa/drivers/dri/r300/r300_mem.c | 385 ----------- src/mesa/drivers/dri/r300/r300_mem.h | 37 -- src/mesa/drivers/dri/r300/r300_mipmap_tree.c | 316 +++++++++ src/mesa/drivers/dri/r300/r300_mipmap_tree.h | 97 +++ src/mesa/drivers/dri/r300/r300_reg.h | 7 + src/mesa/drivers/dri/r300/r300_render.c | 116 ++-- src/mesa/drivers/dri/r300/r300_state.c | 66 +- src/mesa/drivers/dri/r300/r300_state.h | 12 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 164 ++--- src/mesa/drivers/dri/r300/r300_tex.c | 779 ++++++++++------------ src/mesa/drivers/dri/r300/r300_tex.h | 7 +- src/mesa/drivers/dri/r300/r300_texmem.c | 513 +-------------- src/mesa/drivers/dri/r300/r300_texstate.c | 535 +++++----------- src/mesa/drivers/dri/r300/radeon_context.c | 122 +++- src/mesa/drivers/dri/r300/radeon_context.h | 3 +- src/mesa/drivers/dri/r300/radeon_ioctl.c | 36 +- src/mesa/drivers/dri/r300/radeon_lock.c | 27 +- src/mesa/drivers/dri/r300/radeon_span.c | 166 +++-- src/mesa/drivers/dri/r300/radeon_state.c | 8 - src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 718 +++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_bo_legacy.h | 47 ++ src/mesa/drivers/dri/radeon/radeon_buffer.h | 47 ++ src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 376 +++++++++++ src/mesa/drivers/dri/radeon/radeon_cs_legacy.h | 40 ++ src/mesa/drivers/dri/radeon/radeon_screen.c | 171 ++++- src/mesa/drivers/dri/radeon/radeon_screen.h | 5 +- src/mesa/drivers/dri/radeon/radeon_span.h | 8 +- 36 files changed, 3360 insertions(+), 3343 deletions(-) delete mode 100644 src/mesa/drivers/dri/r300/r300_mem.c delete mode 100644 src/mesa/drivers/dri/r300/r300_mem.h create mode 100644 src/mesa/drivers/dri/r300/r300_mipmap_tree.c create mode 100644 src/mesa/drivers/dri/r300/r300_mipmap_tree.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_bo_legacy.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_bo_legacy.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_buffer.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_cs_legacy.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_cs_legacy.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 6ca934204f3..f1141523c07 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -21,13 +21,14 @@ COMMON_SOURCES = \ ../common/dri_util.c DRIVER_SOURCES = \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ radeon_screen.c \ radeon_context.c \ radeon_ioctl.c \ radeon_lock.c \ radeon_span.c \ radeon_state.c \ - r300_mem.c \ r300_context.c \ r300_ioctl.c \ r300_cmdbuf.c \ @@ -36,6 +37,7 @@ DRIVER_SOURCES = \ r300_texmem.c \ r300_tex.c \ r300_texstate.c \ + r300_mipmap_tree.c \ radeon_program.c \ radeon_program_alu.c \ radeon_program_pair.c \ @@ -54,7 +56,10 @@ DRIVER_SOURCES = \ C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) DRIVER_DEFINES = -DCOMPILE_R300 -DR200_MERGED=0 \ - -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300 + -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300 \ +# -DRADEON_BO_TRACK_OPEN \ +# -DRADEON_BO_TRACK_REF \ + -Wall SYMLINKS = \ server/radeon_dri.c \ @@ -68,7 +73,12 @@ COMMON_SYMLINKS = \ radeon_chipset.h \ radeon_screen.c \ radeon_screen.h \ - radeon_span.h + radeon_span.h \ + radeon_buffer.h \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ + radeon_bo_legacy.h \ + radeon_cs_legacy.h ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index c9e1dfe9774..7d7fed4e5d6 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" +#include "radeon_buffer.h" #include "radeon_ioctl.h" #include "r300_context.h" #include "r300_ioctl.h" @@ -51,62 +52,33 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_reg.h" #include "r300_cmdbuf.h" #include "r300_emit.h" +#include "r300_mipmap_tree.h" #include "r300_state.h" +#include "radeon_cs_legacy.h" // Set this to 1 for extremely verbose debugging of command buffers #define DEBUG_CMDBUF 0 +/** # of dwords reserved for additional instructions that may need to be written + * during flushing. + */ +#define SPACE_FOR_FLUSHING 4 + /** * Send the current command buffer via ioctl to the hardware. */ int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller) { int ret; - int i; - drm_radeon_cmd_buffer_t cmd; - int start; - - if (r300->radeon.lost_context) { - start = 0; - r300->radeon.lost_context = GL_FALSE; - } else - start = r300->cmdbuf.count_reemit; - - if (RADEON_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "%s from %s - %i cliprects\n", - __FUNCTION__, caller, r300->radeon.numClipRects); - - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_VERBOSE) - for (i = start; i < r300->cmdbuf.count_used; ++i) - fprintf(stderr, "%d: %08x\n", i, - r300->cmdbuf.cmd_buf[i]); - } - - cmd.buf = (char *)(r300->cmdbuf.cmd_buf + start); - cmd.bufsz = (r300->cmdbuf.count_used - start) * 4; - - if (r300->radeon.state.scissor.enabled) { - cmd.nbox = r300->radeon.state.scissor.numClipRects; - cmd.boxes = - (drm_clip_rect_t *) r300->radeon.state.scissor.pClipRects; - } else { - cmd.nbox = r300->radeon.numClipRects; - cmd.boxes = (drm_clip_rect_t *) r300->radeon.pClipRects; - } - ret = drmCommandWrite(r300->radeon.dri.fd, - DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); - - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "Syncing in %s (from %s)\n\n", - __FUNCTION__, caller); - radeonWaitForIdleLocked(&r300->radeon); + if (r300->cmdbuf.flushing) { + fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n"); + exit(-1); } - - r300->dma.nr_released_bufs = 0; - r300->cmdbuf.count_used = 0; - r300->cmdbuf.count_reemit = 0; - + r300->cmdbuf.flushing = 1; + ret = radeon_cs_emit(r300->cmdbuf.cs); + radeon_cs_erase(r300->cmdbuf.cs); + r300->cmdbuf.flushing = 0; return ret; } @@ -115,9 +87,7 @@ int r300FlushCmdBuf(r300ContextPtr r300, const char *caller) int ret; LOCK_HARDWARE(&r300->radeon); - ret = r300FlushCmdBufLocked(r300, caller); - UNLOCK_HARDWARE(&r300->radeon); if (ret) { @@ -128,13 +98,44 @@ int r300FlushCmdBuf(r300ContextPtr r300, const char *caller) return ret; } -static void r300PrintStateAtom(r300ContextPtr r300, struct r300_state_atom *state) +/** + * Make sure that enough space is available in the command buffer + * by flushing if necessary. + * + * \param dwords The number of dwords we need to be free on the command buffer + */ +void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller) +{ + assert(dwords < r300->cmdbuf.size); + + if ((r300->cmdbuf.cs->cdw + dwords + 128) > r300->cmdbuf.size || + radeon_cs_need_flush(r300->cmdbuf.cs)) { + r300FlushCmdBuf(r300, caller); + } +} + +void r300BeginBatch(r300ContextPtr r300, int n, + int dostate, + const char *file, + const char *function, + int line) +{ + r300EnsureCmdBufSpace(r300, n, function); + if (!r300->cmdbuf.cs->cdw && dostate) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "Reemit state after flush (from %s)\n", function); + r300EmitState(r300); + } + radeon_cs_begin(r300->cmdbuf.cs, n, file, function, line); +} + +static void r300PrintStateAtom(r300ContextPtr r300, + struct r300_state_atom *state) { int i; int dwords = (*state->check) (r300, state); - fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, - state->cmd_size); + fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); if (RADEON_DEBUG & DEBUG_VERBOSE) { for (i = 0; i < dwords; i++) { @@ -152,33 +153,18 @@ static void r300PrintStateAtom(r300ContextPtr r300, struct r300_state_atom *stat */ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) { + BATCH_LOCALS(r300); struct r300_state_atom *atom; - uint32_t *dest; int dwords; - dest = r300->cmdbuf.cmd_buf + r300->cmdbuf.count_used; - - /* Emit WAIT */ - *dest = cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN); - dest++; - r300->cmdbuf.count_used++; - - /* Emit cache flush */ - *dest = cmdpacket0(R300_TX_INVALTAGS, 1); - dest++; - r300->cmdbuf.count_used++; - - *dest = R300_TX_FLUSH; - dest++; - r300->cmdbuf.count_used++; - - /* Emit END3D */ - *dest = cmdpacify(); - dest++; - r300->cmdbuf.count_used++; + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH(cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN)); + OUT_BATCH(cmdpacket0(R300_TX_INVALTAGS, 1)); + OUT_BATCH(R300_TX_FLUSH); + OUT_BATCH(cmdpacify()); + END_BATCH(); /* Emit actual atoms */ - foreach(atom, &r300->hw.atomlist) { if ((atom->dirty || r300->hw.all_dirty) == dirty) { dwords = (*atom->check) (r300, atom); @@ -186,9 +172,13 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { r300PrintStateAtom(r300, atom); } - memcpy(dest, atom->cmd, dwords * 4); - dest += dwords; - r300->cmdbuf.count_used += dwords; + if (atom->emit) { + (*atom->emit)(r300); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } atom->dirty = GL_FALSE; } else { if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { @@ -198,6 +188,8 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) } } } + + COMMIT_BATCH(); } /** @@ -211,31 +203,26 @@ void r300EmitState(r300ContextPtr r300) if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); - if (r300->cmdbuf.count_used && !r300->hw.is_dirty + if (r300->cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty) return; /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state, and inline the - * r300AllocCmdBuf code here without all the checks. + * for enough space for the case of emitting all state. */ r300EnsureCmdBufSpace(r300, r300->hw.max_state_size, __FUNCTION__); - if (!r300->cmdbuf.count_used) { + if (!r300->cmdbuf.cs->cdw) { if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "Begin reemit state\n"); r300EmitAtoms(r300, GL_FALSE); - r300->cmdbuf.count_reemit = r300->cmdbuf.count_used; } if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "Begin dirty state\n"); r300EmitAtoms(r300, GL_TRUE); - - assert(r300->cmdbuf.count_used < r300->cmdbuf.size); - r300->hw.is_dirty = GL_FALSE; r300->hw.all_dirty = GL_FALSE; } @@ -244,6 +231,84 @@ void r300EmitState(r300ContextPtr r300) #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) +static void emit_tex_offsets(r300ContextPtr r300) +{ + BATCH_LOCALS(r300); + int numtmus = packet0_count(r300->hw.tex.offset.cmd); + + if (numtmus) { + int i; + + for(i = 0; i < numtmus; ++i) { + BEGIN_BATCH(2); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); + r300TexObj *t = r300->hw.textures[i]; + if (t && !t->image_override) { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 0); + } else if (!t) { + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + } else { + OUT_BATCH(t->override_offset); + } + END_BATCH(); + } + } +} + +static void emit_cb_offset(r300ContextPtr r300) +{ + BATCH_LOCALS(r300); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; + + rrb = r300->radeon.state.color.rrb; + if (!rrb) { + fprintf(stderr, "no rrb\n"); + return; + } + + cbpitch = rrb->pitch; + if (rrb->cpp == 4) + cbpitch |= R300_COLOR_FORMAT_ARGB8888; + else + cbpitch |= R300_COLOR_FORMAT_RGB565; + + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) + cbpitch |= R300_COLOR_TILE_ENABLE; + + BEGIN_BATCH(4); + OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); + OUT_BATCH(cbpitch); + END_BATCH(); +} + +static void emit_zb_offset(r300ContextPtr r300) +{ + BATCH_LOCALS(r300); + struct radeon_renderbuffer *rrb; + uint32_t zbpitch; + + rrb = r300->radeon.state.depth_buffer; + if (!rrb) + return; + + zbpitch = rrb->pitch; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + zbpitch |= R300_DEPTHMACROTILE_ENABLE; + } + if (r300->radeon.glCtx->Visual.depthBits == 24) { + zbpitch |= R300_DEPTHMICROTILE_TILED; + } + + BEGIN_BATCH(4); + OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); + END_BATCH(); +} + static int check_always(r300ContextPtr r300, struct r300_state_atom *atom) { return atom->cmd_size; @@ -480,8 +545,7 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(rop, always, 2, 0); r300->hw.rop.cmd[0] = cmdpacket0(R300_RB3D_ROPCNTL, 1); ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0); - r300->hw.cb.cmd[R300_CB_CMD_0] = cmdpacket0(R300_RB3D_COLOROFFSET0, 1); - r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1); + r300->hw.cb.emit = &emit_cb_offset; ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, 9); ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); @@ -495,7 +559,7 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.zstencil_format.cmd[0] = cmdpacket0(R300_ZB_FORMAT, 4); ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0); - r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(R300_ZB_DEPTHOFFSET, 2); + r300->hw.zb.emit = emit_zb_offset; ALLOC_STATE(zb_depthclearvalue, always, 2, 0); r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(R300_ZB_DEPTHCLEARVALUE, 1); ALLOC_STATE(unk4F30, always, 3, 0); @@ -562,9 +626,10 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(tex.pitch, variable, mtu + 1, 0); r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FORMAT2_0, 0); - ALLOC_STATE(tex.offset, variable, mtu + 1, 0); + ALLOC_STATE(tex.offset, variable, 1, 0); r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_OFFSET_0, 0); + r300->hw.tex.offset.emit = &emit_tex_offsets; ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0); r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = @@ -587,6 +652,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (size > 64 * 256) size = 64 * 256; + size = 64 * 1024 / 4; if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", sizeof(drm_r300_cmd_header_t)); @@ -597,10 +663,14 @@ void r300InitCmdBuf(r300ContextPtr r300) size * 4, r300->hw.max_state_size * 4); } + r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon); + if (r300->cmdbuf.csm == NULL) { + /* FIXME: fatal error */ + return; + } + r300->cmdbuf.cs = radeon_cs_create(r300->cmdbuf.csm, size); + assert(r300->cmdbuf.cs != NULL); r300->cmdbuf.size = size; - r300->cmdbuf.cmd_buf = (uint32_t *) CALLOC(size * 4); - r300->cmdbuf.count_used = 0; - r300->cmdbuf.count_reemit = 0; } /** @@ -610,66 +680,8 @@ void r300DestroyCmdBuf(r300ContextPtr r300) { struct r300_state_atom *atom; - FREE(r300->cmdbuf.cmd_buf); - + radeon_cs_destroy(r300->cmdbuf.cs); foreach(atom, &r300->hw.atomlist) { FREE(atom->cmd); } } - -void r300EmitBlit(r300ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, GLuint w, GLuint h) -{ - drm_r300_cmd_header_t *cmd; - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, - "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n", - __FUNCTION__, src_pitch, src_offset, srcx, srcy, - dst_pitch, dst_offset, dstx, dsty, w, h); - - assert((src_pitch & 63) == 0); - assert((dst_pitch & 63) == 0); - assert((src_offset & 1023) == 0); - assert((dst_offset & 1023) == 0); - assert(w < (1 << 16)); - assert(h < (1 << 16)); - - cmd = (drm_r300_cmd_header_t *) r300AllocCmdBuf(rmesa, 8, __FUNCTION__); - - cmd[0].header.cmd_type = R300_CMD_PACKET3; - cmd[0].header.pad0 = R300_CMD_PACKET3_RAW; - cmd[1].u = R300_CP_CMD_BITBLT_MULTI | (5 << 16); - cmd[2].u = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); - - cmd[3].u = ((src_pitch / 64) << 22) | (src_offset >> 10); - cmd[4].u = ((dst_pitch / 64) << 22) | (dst_offset >> 10); - cmd[5].u = (srcx << 16) | srcy; - cmd[6].u = (dstx << 16) | dsty; /* dst */ - cmd[7].u = (w << 16) | h; -} - -void r300EmitWait(r300ContextPtr rmesa, GLuint flags) -{ - drm_r300_cmd_header_t *cmd; - - assert(!(flags & ~(R300_WAIT_2D | R300_WAIT_3D))); - - cmd = (drm_r300_cmd_header_t *) r300AllocCmdBuf(rmesa, 1, __FUNCTION__); - cmd[0].u = 0; - cmd[0].wait.cmd_type = R300_CMD_WAIT; - cmd[0].wait.flags = flags; -} diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index a8eaa580bd9..98cb1af1260 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -37,6 +37,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define __R300_CMDBUF_H__ #include "r300_context.h" +#include "radeon_cs.h" extern int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller); extern int r300FlushCmdBuf(r300ContextPtr r300, const char *caller); @@ -45,72 +46,77 @@ extern void r300EmitState(r300ContextPtr r300); extern void r300InitCmdBuf(r300ContextPtr r300); extern void r300DestroyCmdBuf(r300ContextPtr r300); +extern void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller); + +void r300BeginBatch(r300ContextPtr r300, + int n, + int dostate, + const char *file, + const char *function, + int line); /** - * Make sure that enough space is available in the command buffer - * by flushing if necessary. - * - * \param dwords The number of dwords we need to be free on the command buffer + * Every function writing to the command buffer needs to declare this + * to get the necessary local variables. + */ +#define BATCH_LOCALS(r300) \ + const r300ContextPtr b_l_r300 = r300 + +/** + * Prepare writing n dwords to the command buffer, + * including producing any necessary state emits on buffer wraparound. */ -static INLINE void r300EnsureCmdBufSpace(r300ContextPtr r300, - int dwords, const char *caller) -{ - assert(dwords < r300->cmdbuf.size); +#define BEGIN_BATCH(n) r300BeginBatch(b_l_r300, n, 1, __FILE__, __FUNCTION__, __LINE__) - if (r300->cmdbuf.count_used + dwords > r300->cmdbuf.size) - r300FlushCmdBuf(r300, caller); -} +/** + * Same as BEGIN_BATCH, but do not cause automatic state emits. + */ +#define BEGIN_BATCH_NO_AUTOSTATE(n) r300BeginBatch(b_l_r300, n, 0, __FILE__, __FUNCTION__, __LINE__) + +/** + * Write one dword to the command buffer. + */ +#define OUT_BATCH(data) \ + do { \ + radeon_cs_write_dword(b_l_r300->cmdbuf.cs, data);\ + } while(0) + +/** + * Write a relocated dword to the command buffer. + */ +#define OUT_BATCH_RELOC(data, bo, offset, flags) \ + do { \ + radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\ + radeon_cs_write_reloc(b_l_r300->cmdbuf.cs,bo,0,(bo)->size,flags);\ + } while(0) + +/** + * Write n dwords from ptr to the command buffer. + */ +#define OUT_BATCH_TABLE(ptr,n) \ + do { \ + int _i; \ + for (_i=0; _i < n; _i++) {\ + radeon_cs_write_dword(b_l_r300->cmdbuf.cs, ptr[_i]);\ + }\ + } while(0) + +/** + * Finish writing dwords to the command buffer. + * The number of (direct or indirect) OUT_BATCH calls between the previous + * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. + */ +#define END_BATCH() \ + do { \ + radeon_cs_end(b_l_r300->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ + } while(0) /** - * Allocate the given number of dwords in the command buffer and return - * a pointer to the allocated area. - * When necessary, these functions cause a flush. r300AllocCmdBuf() also - * causes state reemission after a flush. This is necessary to ensure - * correct hardware state after an unlock. + * After the last END_BATCH() of rendering, this indicates that flushing + * the command buffer now is okay. */ -static INLINE uint32_t *r300RawAllocCmdBuf(r300ContextPtr r300, - int dwords, const char *caller) -{ - uint32_t *ptr; - - r300EnsureCmdBufSpace(r300, dwords, caller); - - ptr = &r300->cmdbuf.cmd_buf[r300->cmdbuf.count_used]; - r300->cmdbuf.count_used += dwords; - return ptr; -} - -static INLINE uint32_t *r300AllocCmdBuf(r300ContextPtr r300, - int dwords, const char *caller) -{ - uint32_t *ptr; - - r300EnsureCmdBufSpace(r300, dwords, caller); - - if (!r300->cmdbuf.count_used) { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, - "Reemit state after flush (from %s)\n", caller); - r300EmitState(r300); - } - - ptr = &r300->cmdbuf.cmd_buf[r300->cmdbuf.count_used]; - r300->cmdbuf.count_used += dwords; - return ptr; -} - -extern void r300EmitBlit(r300ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, GLuint w, GLuint h); - -extern void r300EmitWait(r300ContextPtr rmesa, GLuint flags); -extern void r300EmitLOAD_VBPNTR(r300ContextPtr rmesa, int start); -extern void r300EmitVertexShader(r300ContextPtr rmesa); -extern void r300EmitPixelShader(r300ContextPtr rmesa); +#define COMMIT_BATCH() \ + do { \ + } while(0) #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 37436275e34..c1e11d5e43b 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -59,15 +59,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_span.h" #include "r300_context.h" #include "r300_cmdbuf.h" +#include "r300_mipmap_tree.h" #include "r300_state.h" #include "r300_ioctl.h" #include "r300_tex.h" #include "r300_emit.h" #include "r300_swtcl.h" -#ifdef USER_BUFFERS -#include "r300_mem.h" -#endif #include "vblank.h" #include "utils.h" @@ -189,7 +187,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, struct dd_function_table functions; r300ContextPtr r300; GLcontext *ctx; - int tcl_mode, i; + int tcl_mode; assert(glVisual); assert(driContextPriv); @@ -221,10 +219,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, r300InitTextureFuncs(&functions); r300InitShaderFuncs(&functions); -#ifdef USER_BUFFERS - r300_mem_init(r300); -#endif - if (!radeonInitContext(&r300->radeon, &functions, glVisual, driContextPriv, sharedContextPrivate)) { @@ -233,33 +227,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, } /* Init r300 context data */ - r300->dma.buf0_address = - r300->radeon.radeonScreen->buffers->list[0].address; - - (void)memset(r300->texture_heaps, 0, sizeof(r300->texture_heaps)); - make_empty_list(&r300->swapped); - - r300->nr_heaps = 1 /* screen->numTexHeaps */ ; - assert(r300->nr_heaps < RADEON_NR_TEX_HEAPS); - for (i = 0; i < r300->nr_heaps; i++) { - /* *INDENT-OFF* */ - r300->texture_heaps[i] = driCreateTextureHeap(i, r300, - screen-> - texSize[i], 12, - RADEON_NR_TEX_REGIONS, - (drmTextureRegionPtr) - r300->radeon.sarea-> - tex_list[i], - &r300->radeon.sarea-> - tex_age[i], - &r300->swapped, - sizeof - (r300TexObj), - (destroy_texture_object_t - *) - r300DestroyTexObj); - /* *INDENT-ON* */ - } r300->texture_depth = driQueryOptioni(&r300->radeon.optionCache, "texture_depth"); if (r300->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) @@ -298,12 +265,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; -#ifdef USER_BUFFERS /* Needs further modifications */ #if 0 ctx->Const.MaxArrayLockSize = ( /*512 */ RADEON_BUFFER_SIZE * 16 * 1024) / (4 * 4); -#endif #endif /* Initialize the software rasterizer and helper modules. @@ -406,72 +371,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } -static void r300FreeGartAllocations(r300ContextPtr r300) -{ - int i, ret, tries = 0, done_age, in_use = 0; - drm_radeon_mem_free_t memfree; - - memfree.region = RADEON_MEM_REGION_GART; - -#ifdef USER_BUFFERS - for (i = r300->rmm->u_last; i > 0; i--) { - if (r300->rmm->u_list[i].ptr == NULL) { - continue; - } - - /* check whether this buffer is still in use */ - if (r300->rmm->u_list[i].pending) { - in_use++; - } - } - /* Cannot flush/lock if no context exists. */ - if (in_use) - r300FlushCmdBuf(r300, __FUNCTION__); - - done_age = radeonGetAge((radeonContextPtr) r300); - - for (i = r300->rmm->u_last; i > 0; i--) { - if (r300->rmm->u_list[i].ptr == NULL) { - continue; - } - - /* check whether this buffer is still in use */ - if (!r300->rmm->u_list[i].pending) { - continue; - } - - assert(r300->rmm->u_list[i].h_pending == 0); - - tries = 0; - while (r300->rmm->u_list[i].age > done_age && tries++ < 1000) { - usleep(10); - done_age = radeonGetAge((radeonContextPtr) r300); - } - if (tries >= 1000) { - WARN_ONCE("Failed to idle region!"); - } - - memfree.region_offset = (char *)r300->rmm->u_list[i].ptr - - (char *)r300->radeon.radeonScreen->gartTextures.map; - - ret = drmCommandWrite(r300->radeon.radeonScreen->driScreen->fd, - DRM_RADEON_FREE, &memfree, - sizeof(memfree)); - if (ret) { - fprintf(stderr, "Failed to free at %p\nret = %s\n", - r300->rmm->u_list[i].ptr, strerror(-ret)); - } else { - if (i == r300->rmm->u_last) - r300->rmm->u_last--; - - r300->rmm->u_list[i].pending = 0; - r300->rmm->u_list[i].ptr = NULL; - } - } - r300->rmm->u_head = i; -#endif /* USER_BUFFERS */ -} - /* Destroy the device specific context. */ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) @@ -495,23 +394,12 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) assert(r300); /* should never be null */ if (r300) { - GLboolean release_texture_heaps; - - release_texture_heaps = - (r300->radeon.glCtx->Shared->RefCount == 1); _swsetup_DestroyContext(r300->radeon.glCtx); _tnl_DestroyContext(r300->radeon.glCtx); _vbo_DestroyContext(r300->radeon.glCtx); _swrast_DestroyContext(r300->radeon.glCtx); - if (r300->dma.current.buf) { - r300ReleaseDmaRegion(r300, &r300->dma.current, - __FUNCTION__); -#ifndef USER_BUFFERS - r300FlushCmdBuf(r300, __FUNCTION__); -#endif - } - r300FreeGartAllocations(r300); + r300FlushCmdBuf(r300, __FUNCTION__); r300DestroyCmdBuf(r300); if (radeon->state.scissor.pClipRects) { @@ -519,28 +407,11 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) radeon->state.scissor.pClipRects = NULL; } - if (release_texture_heaps) { - /* This share group is about to go away, free our private - * texture object data. - */ - int i; - - for (i = 0; i < r300->nr_heaps; i++) { - driDestroyTextureHeap(r300->texture_heaps[i]); - r300->texture_heaps[i] = NULL; - } - - assert(is_empty_list(&r300->swapped)); - } - radeonCleanupContext(&r300->radeon); -#ifdef USER_BUFFERS /* the memory manager might be accessed when Mesa frees the shared * state, so don't destroy it earlier */ - r300_mem_destroy(r300); -#endif /* free the option cache */ driDestroyOptionCache(&r300->radeon.optionCache); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index c15e9fa3009..5f8b8c1a402 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -42,13 +42,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "dri_util.h" #include "texmem.h" +#include "radeon_bo.h" #include "main/macros.h" #include "main/mtypes.h" #include "main/colormac.h" -#define USER_BUFFERS - struct r300_context; typedef struct r300_context r300ContextRec; typedef struct r300_context *r300ContextPtr; @@ -122,68 +121,50 @@ static INLINE uint32_t r300PackFloat24(float f) /************ DMA BUFFERS **************/ -/* Need refcounting on dma buffers: - */ -struct r300_dma_buffer { - int refcount; /**< the number of retained regions in buf */ - drmBufPtr buf; - int id; -}; -#undef GET_START -#ifdef USER_BUFFERS -#define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start)) -#else -#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ - (rvb)->address - rmesa->dma.buf0_address + \ - (rvb)->start) -#endif -/* A retained region, eg vertices for indexed vertices. - */ -struct r300_dma_region { - struct r300_dma_buffer *buf; - char *address; /* == buf->address */ - int start, end, ptr; /* offsets from start of buf */ - - int aos_offset; /* address in GART memory */ - int aos_stride; /* distance between elements, in dwords */ - int aos_size; /* number of components (1-4) */ -}; -struct r300_dma { - /* Active dma region. Allocations for vertices and retained - * regions come from here. Also used for emitting random vertices, - * these may be flushed by calling flush_current(); - */ - struct r300_dma_region current; +/* Texture related */ +typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr; +typedef struct _r300_texture_image r300_texture_image; - void (*flush) (r300ContextPtr); - char *buf0_address; /* start of buf[0], for index calcs */ +struct _r300_texture_image { + struct gl_texture_image base; - /* Number of "in-flight" DMA buffers, i.e. the number of buffers - * for which a DISCARD command is currently queued in the command buffer. + /** + * If mt != 0, the image is stored in hardware format in the + * given mipmap tree. In this case, base.Data may point into the + * mapping of the buffer object that contains the mipmap tree. + * + * If mt == 0, the image is stored in normal memory pointed to + * by base.Data. */ - GLuint nr_released_bufs; + struct _r300_mipmap_tree *mt; + + int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ + int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ }; - /* Texture related */ +static INLINE r300_texture_image *get_r300_texture_image(struct gl_texture_image *image) +{ + return (r300_texture_image*)image; +} -typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr; /* Texture object in locally shared texture space. */ struct r300_tex_obj { - driTextureObject base; + struct gl_texture_object base; + struct _r300_mipmap_tree *mt; - GLuint bufAddr; /* Offset to start of locally - shared texture block */ - - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; - /* Six, for the cube faces */ + /** + * This is true if we've verified that the mipmap tree above is complete + * and so on. + */ + GLboolean validated; GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + GLuint override_offset; - GLuint pitch; /* this isn't sent to hardware just used in calculations */ /* hardware register values */ /* Note that R200 has 8 registers per texture and R300 only 7 */ GLuint filter; @@ -191,30 +172,16 @@ struct r300_tex_obj { GLuint pitch_reg; GLuint size; /* npot only */ GLuint format; - GLuint offset; /* Image location in the card's address space. - All cube faces follow. */ - GLuint unknown4; - GLuint unknown5; - /* end hardware registers */ - - /* registers computed by r200 code - keep them here to - compare against what is actually written. - - to be removed later.. */ GLuint pp_border_color; - GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ - GLuint format_x; - - GLboolean border_fallback; + /* end hardware registers */ GLuint tile_bits; /* hw texture tile bits used on this texture */ }; -struct r300_texture_env_state { - r300TexObjPtr texobj; - GLenum format; - GLenum envMode; -}; +static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj) +{ + return (r300TexObj*)texObj; +} /* The blit width for texture uploads */ @@ -222,7 +189,6 @@ struct r300_texture_env_state { #define R300_MAX_TEXTURE_UNITS 8 struct r300_texture_state { - struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS]; int tc_count; /* number of incoming texture coordinates from VAP */ }; @@ -242,6 +208,7 @@ struct r300_state_atom { GLboolean dirty; int (*check) (r300ContextPtr, struct r300_state_atom * atom); + void (*emit) (r300ContextPtr); }; #define R300_VPT_CMD_0 0 @@ -549,6 +516,8 @@ struct r300_hw_state { struct r300_state_atom border_color; } tex; struct r300_state_atom txe; /* tex enable (4104) */ + + r300TexObj *textures[R300_MAX_TEXTURE_UNITS]; }; /** @@ -559,10 +528,10 @@ struct r300_hw_state { * otherwise. */ struct r300_cmdbuf { - int size; /* DWORDs allocated for buffer */ - uint32_t *cmd_buf; - int count_used; /* DWORDs filled so far */ - int count_reemit; /* size of re-emission batch */ + struct radeon_cs_manager *csm; + struct radeon_cs *cs; + int size; /** # of dwords total */ + unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ }; /** @@ -811,18 +780,25 @@ struct r500_fragment_program { #define REG_COLOR0 1 #define REG_TEX0 2 +struct r300_aos { + struct radeon_bo *bo; /** Buffer object where vertex data is stored */ + int offset; /** Offset into buffer object, in bytes */ + int components; /** Number of components per vertex */ + int stride; /** Stride in dwords (may be 0 for repeating) */ + int count; /** Number of vertices */ +}; + struct r300_state { struct r300_depthbuffer_state depth; struct r300_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; struct r300_vertex_shader_state vertex_shader; - struct r300_dma_region aos[R300_MAX_AOS_ARRAYS]; + struct r300_aos aos[R300_MAX_AOS_ARRAYS]; int aos_count; - GLuint *Elts; - struct r300_dma_region elt_dma; + struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ + int elt_dma_offset; /** Offset into this buffer object, in bytes */ - struct r300_dma_region swtcl_dma; DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. They are the same as tnl->render_inputs for fixed pipeline */ @@ -881,12 +857,8 @@ struct r300_swtcl_info { */ GLuint specoffset; - /** - * Should Mesa project vertex data or will the hardware do it? - */ - GLboolean needproj; - - struct r300_dma_region indexed_verts; + struct radeon_bo *bo; + void (*flush) (r300ContextPtr); }; @@ -904,26 +876,11 @@ struct r300_context { /* Vertex buffers */ - struct r300_dma dma; - GLboolean save_on_next_unlock; GLuint NewGLState; - /* Texture object bookkeeping - */ - unsigned nr_heaps; - driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS]; - driTextureObject swapped; int texture_depth; float initialMaxAnisotropy; - /* Clientdata textures; - */ - GLuint prefer_gart_client_texturing; - -#ifdef USER_BUFFERS - struct r300_memory_manager *rmm; -#endif - GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 80bd3389aef..d07e7baf6b5 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -51,9 +51,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_emit.h" #include "r300_ioctl.h" -#ifdef USER_BUFFERS -#include "r300_mem.h" -#endif #if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \ SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \ @@ -86,11 +83,9 @@ do { \ } while (0) #endif -static void r300EmitVec4(GLcontext * ctx, struct r300_dma_region *rvb, - GLvoid * data, int stride, int count) +static void r300EmitVec4(uint32_t *out, GLvoid * data, int stride, int count) { int i; - int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d out %p data %p\n", @@ -106,11 +101,9 @@ static void r300EmitVec4(GLcontext * ctx, struct r300_dma_region *rvb, } } -static void r300EmitVec8(GLcontext * ctx, struct r300_dma_region *rvb, - GLvoid * data, int stride, int count) +static void r300EmitVec8(uint32_t *out, GLvoid * data, int stride, int count) { int i; - int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d out %p data %p\n", @@ -127,18 +120,17 @@ static void r300EmitVec8(GLcontext * ctx, struct r300_dma_region *rvb, } } -static void r300EmitVec12(GLcontext * ctx, struct r300_dma_region *rvb, - GLvoid * data, int stride, int count) +static void r300EmitVec12(uint32_t *out, GLvoid * data, int stride, int count) { int i; - int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d out %p data %p\n", __FUNCTION__, count, stride, (void *)out, (void *)data); - if (stride == 12) + if (stride == 12) { COPY_DWORDS(out, data, count * 3); + } else for (i = 0; i < count; i++) { out[0] = *(int *)data; @@ -149,11 +141,9 @@ static void r300EmitVec12(GLcontext * ctx, struct r300_dma_region *rvb, } } -static void r300EmitVec16(GLcontext * ctx, struct r300_dma_region *rvb, - GLvoid * data, int stride, int count) +static void r300EmitVec16(uint32_t *out, GLvoid * data, int stride, int count) { int i; - int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d out %p data %p\n", @@ -172,39 +162,39 @@ static void r300EmitVec16(GLcontext * ctx, struct r300_dma_region *rvb, } } -static void r300EmitVec(GLcontext * ctx, struct r300_dma_region *rvb, +static void r300EmitVec(GLcontext * ctx, struct r300_aos *aos, GLvoid * data, int size, int stride, int count) { r300ContextPtr rmesa = R300_CONTEXT(ctx); + uint32_t *out; + uint32_t bo_size; if (stride == 0) { - r300AllocDmaRegion(rmesa, rvb, size * 4, 4); + bo_size = size * 4; count = 1; - rvb->aos_offset = GET_START(rvb); - rvb->aos_stride = 0; + aos->stride = 0; } else { - r300AllocDmaRegion(rmesa, rvb, size * count * 4, 4); - rvb->aos_offset = GET_START(rvb); - rvb->aos_stride = size; + bo_size = size * count * 4; + aos->stride = size; } - + aos->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT); + aos->offset = 0; + aos->components = size; + aos->count = count; + + radeon_bo_map(aos->bo, 1); + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { - case 1: - r300EmitVec4(ctx, rvb, data, stride, count); - break; - case 2: - r300EmitVec8(ctx, rvb, data, stride, count); - break; - case 3: - r300EmitVec12(ctx, rvb, data, stride, count); - break; - case 4: - r300EmitVec16(ctx, rvb, data, stride, count); - break; + case 1: r300EmitVec4(out, data, stride, count); break; + case 2: r300EmitVec8(out, data, stride, count); break; + case 3: r300EmitVec12(out, data, stride, count); break; + case 4: r300EmitVec16(out, data, stride, count); break; default: assert(0); break; } + radeon_bo_unmap(aos->bo); } #define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \ @@ -314,10 +304,6 @@ GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten) R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; -#if 0 - if (OutputsWritten & (1 << VERT_RESULT_FOGC)) ; -#endif - if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; @@ -371,7 +357,6 @@ int r300EmitArrays(GLcontext * ctx) assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)); assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_NORMAL) == 0); - //assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR0)); if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)) { InputsRead |= 1 << VERT_ATTRIB_POS; @@ -433,7 +418,7 @@ int r300EmitArrays(GLcontext * ctx) } for (i = 0; i < nr; i++) { - int ci, fix, found = 0; + int ci; swizzle[i][0] = SWIZZLE_ZERO; swizzle[i][1] = SWIZZLE_ZERO; @@ -444,48 +429,10 @@ int r300EmitArrays(GLcontext * ctx) swizzle[i][ci] = ci; } - if (r300IsGartMemory(rmesa, vb->AttribPtr[tab[i]]->data, 4)) { - if (vb->AttribPtr[tab[i]]->stride % 4) { - return R300_FALLBACK_TCL; - } - rmesa->state.aos[i].address = (void *)(vb->AttribPtr[tab[i]]->data); - rmesa->state.aos[i].start = 0; - rmesa->state.aos[i].aos_offset = r300GartOffsetFromVirtual(rmesa, vb->AttribPtr[tab[i]]->data); - rmesa->state.aos[i].aos_stride = vb->AttribPtr[tab[i]]->stride / 4; - rmesa->state.aos[i].aos_size = vb->AttribPtr[tab[i]]->size; - } else { - r300EmitVec(ctx, &rmesa->state.aos[i], - vb->AttribPtr[tab[i]]->data, - vb->AttribPtr[tab[i]]->size, - vb->AttribPtr[tab[i]]->stride, count); - } - - rmesa->state.aos[i].aos_size = vb->AttribPtr[tab[i]]->size; - - for (fix = 0; fix <= 4 - vb->AttribPtr[tab[i]]->size; fix++) { - if ((rmesa->state.aos[i].aos_offset - _mesa_sizeof_type(GL_FLOAT) * fix) % 4) { - continue; - } - found = 1; - break; - } - - if (found) { - if (fix > 0) { - WARN_ONCE("Feeling lucky?\n"); - } - rmesa->state.aos[i].aos_offset -= _mesa_sizeof_type(GL_FLOAT) * fix; - for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { - swizzle[i][ci] += fix; - } - } else { - WARN_ONCE - ("Cannot handle offset %x with stride %d, comp %d\n", - rmesa->state.aos[i].aos_offset, - rmesa->state.aos[i].aos_stride, - vb->AttribPtr[tab[i]]->size); - return R300_FALLBACK_TCL; - } + r300EmitVec(ctx, &rmesa->state.aos[i], + vb->AttribPtr[tab[i]]->data, + vb->AttribPtr[tab[i]]->size, + vb->AttribPtr[tab[i]]->stride, count); } /* Setup INPUT_ROUTE. */ @@ -515,45 +462,34 @@ int r300EmitArrays(GLcontext * ctx) return R300_FALLBACK_NONE; } -#ifdef USER_BUFFERS -void r300UseArrays(GLcontext * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - int i; - - if (rmesa->state.elt_dma.buf) - r300_mem_use(rmesa, rmesa->state.elt_dma.buf->id); - - for (i = 0; i < rmesa->state.aos_count; i++) { - if (rmesa->state.aos[i].buf) - r300_mem_use(rmesa, rmesa->state.aos[i].buf->id); - } -} -#endif - void r300ReleaseArrays(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); int i; - r300ReleaseDmaRegion(rmesa, &rmesa->state.elt_dma, __FUNCTION__); + if (rmesa->state.elt_dma_bo) { + radeon_bo_unref(rmesa->state.elt_dma_bo); + rmesa->state.elt_dma_bo = 0; + } for (i = 0; i < rmesa->state.aos_count; i++) { - r300ReleaseDmaRegion(rmesa, &rmesa->state.aos[i], __FUNCTION__); + if (rmesa->state.aos[i].bo) { + radeon_bo_unref(rmesa->state.aos[i].bo); + rmesa->state.aos[i].bo = 0; + } } } void r300EmitCacheFlush(r300ContextPtr rmesa) { - int cmd_reserved = 0; - int cmd_written = 0; - - drm_radeon_cmd_header_t *cmd = NULL; - - reg_start(R300_RB3D_DSTCACHE_CTLSTAT, 0); - e32(R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | - R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - - reg_start(R300_ZB_ZCACHE_CTLSTAT, 0); - e32(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | - R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); + BATCH_LOCALS(rmesa); + + BEGIN_BATCH(4); + OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, + R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | + R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT, + R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | + R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); + END_BATCH(); + COMMIT_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 89d738339f8..c596e895ce3 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -127,130 +127,62 @@ static INLINE uint32_t cmdpacify(void) return cmd.u; } -/** - * Prepare to write a register value to register at address reg. - * If num_extra > 0 then the following extra values are written - * to registers with address +4, +8 and so on.. - */ -#define reg_start(reg, num_extra) \ - do { \ - int _n; \ - _n=(num_extra); \ - cmd = (drm_radeon_cmd_header_t*) \ - r300AllocCmdBuf(rmesa, \ - (_n+2), \ - __FUNCTION__); \ - cmd_reserved=_n+2; \ - cmd_written=1; \ - cmd[0].i=cmdpacket0((reg), _n+1); \ - } while (0); + +/** Single register write to command buffer; requires 2 dwords. */ +#define OUT_BATCH_REGVAL(reg, val) \ + OUT_BATCH(cmdpacket0((reg), 1)); \ + OUT_BATCH((val)) + +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define OUT_BATCH_REGSEQ(reg, count) \ + OUT_BATCH(cmdpacket0((reg), (count))); + +/** Write a 32 bit float to the ring; requires 1 dword. */ +#define OUT_BATCH_FLOAT32(f) \ + OUT_BATCH(r300PackFloat32((f))); /** - * Emit GLuint freestyle + * Write the header of a packet3 to the command buffer. + * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ -#define e32(dword) \ - do { \ - if(cmd_written 0x3fff) { \ - fprintf(stderr,"Too big packet3 %08x: cannot " \ - "store %d dwords\n", \ - _p, _n); \ - _mesa_exit(-1); \ - } \ - cmd[0].i = cmdpacket3(R300_CMD_PACKET3_RAW); \ - cmd[1].i = _p | ((_n & 0x3fff)<<16); \ - } - /** * Must be sent to switch to 2d commands */ void static INLINE end_3d(r300ContextPtr rmesa) { - drm_radeon_cmd_header_t *cmd = NULL; + BATCH_LOCALS(rmesa); - cmd = - (drm_radeon_cmd_header_t *) r300AllocCmdBuf(rmesa, 1, __FUNCTION__); - cmd[0].header.cmd_type = R300_CMD_END3D; + BEGIN_BATCH(1); + OUT_BATCH(cmdpacify()); + END_BATCH(); } void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { - drm_radeon_cmd_header_t *cmd = NULL; + BATCH_LOCALS(rmesa); - cmd = - (drm_radeon_cmd_header_t *) r300AllocCmdBuf(rmesa, 1, __FUNCTION__); - cmd[0].i = cmdcpdelay(count); + BEGIN_BATCH(1); + OUT_BATCH(cmdcpdelay(count)); + END_BATCH(); } void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) { - drm_radeon_cmd_header_t *cmd = NULL; + BATCH_LOCALS(rmesa); - cmd = - (drm_radeon_cmd_header_t *) r300AllocCmdBuf(rmesa, 1, __FUNCTION__); - cmd[0].i = cmdwait(flags); + BEGIN_BATCH(1); + OUT_BATCH(cmdwait(flags)); + END_BATCH(); } extern int r300EmitArrays(GLcontext * ctx); -#ifdef USER_BUFFERS -void r300UseArrays(GLcontext * ctx); -#endif - extern void r300ReleaseArrays(GLcontext * ctx); extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index ee85e229f0b..a3085736498 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" +#include "radeon_buffer.h" #include "r300_context.h" #include "radeon_ioctl.h" #include "r300_ioctl.h" @@ -62,64 +63,74 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define CLEARBUFFER_DEPTH 0x2 #define CLEARBUFFER_STENCIL 0x4 -static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer) +static void r300ClearBuffer(r300ContextPtr r300, int flags, + struct radeon_renderbuffer *rrb, + struct radeon_renderbuffer *rrbd) { + BATCH_LOCALS(r300); GLcontext *ctx = r300->radeon.glCtx; __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; - GLuint cboffset, cbpitch; - drm_r300_cmd_header_t *cmd2; - int cmd_reserved = 0; - int cmd_written = 0; - drm_radeon_cmd_header_t *cmd = NULL; + GLuint cbpitch = 0; r300ContextPtr rmesa = r300; if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s: %s buffer (%i,%i %ix%i)\n", - __FUNCTION__, buffer ? "back" : "front", - dPriv->x, dPriv->y, dPriv->w, dPriv->h); - - if (buffer) { - cboffset = r300->radeon.radeonScreen->backOffset; - cbpitch = r300->radeon.radeonScreen->backPitch; - } else { - cboffset = r300->radeon.radeonScreen->frontOffset; - cbpitch = r300->radeon.radeonScreen->frontPitch; + fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n", + __FUNCTION__, rrb, dPriv->x, dPriv->y, + dPriv->w, dPriv->h); + + if (rrb) { + cbpitch = rrb->pitch; + if (rrb->cpp == 4) + cbpitch |= R300_COLOR_FORMAT_ARGB8888; + else + cbpitch |= R300_COLOR_FORMAT_RGB565; + + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ + cbpitch |= R300_COLOR_TILE_ENABLE; + } } - cboffset += r300->radeon.radeonScreen->fbLocation; - + /* TODO in bufmgr */ cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); end_3d(rmesa); - R300_STATECHANGE(r300, cb); - reg_start(R300_RB3D_COLOROFFSET0, 0); - e32(cboffset); - - if (r300->radeon.radeonScreen->cpp == 4) - cbpitch |= R300_COLOR_FORMAT_ARGB8888; - else - cbpitch |= R300_COLOR_FORMAT_RGB565; - - if (r300->radeon.sarea->tiling_enabled) - cbpitch |= R300_COLOR_TILE_ENABLE; - - reg_start(R300_RB3D_COLORPITCH0, 0); - e32(cbpitch); - - R300_STATECHANGE(r300, cmk); - reg_start(RB3D_COLOR_CHANNEL_MASK, 0); - if (flags & CLEARBUFFER_COLOR) { - e32((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) | - (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) | - (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) | - (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0)); + assert(rrb != 0); + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); + END_BATCH(); + } +#if 1 + if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) { + assert(rrbd != 0); + cbpitch = rrbd->pitch; + if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ + cbpitch |= R300_DEPTHMACROTILE_ENABLE; + } + if (r300->radeon.glCtx->Visual.depthBits == 24) { + cbpitch |= R300_DEPTHMICROTILE_TILED; + } + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); + OUT_BATCH_RELOC(0, rrbd->bo, 0, 0); + OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); + END_BATCH(); + } +#endif + BEGIN_BATCH_NO_AUTOSTATE(15); + OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1); + if (flags & CLEARBUFFER_COLOR) { + OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) | + (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) | + (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) | + (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0)); } else { - e32(0x0); + OUT_BATCH(0); } - R300_STATECHANGE(r300, zs); - reg_start(R300_ZB_CNTL, 2); + OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); { uint32_t t1, t2; @@ -146,37 +157,37 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer) R300_S_FRONT_ZFAIL_OP_SHIFT); } - e32(t1); - e32(t2); - e32(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << R300_STENCILWRITEMASK_SHIFT) | - (ctx->Stencil.Clear & R300_STENCILREF_MASK)); + OUT_BATCH(t1); + OUT_BATCH(t2); + OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << R300_STENCILWRITEMASK_SHIFT) | + (ctx->Stencil.Clear & R300_STENCILREF_MASK)); } - cmd2 = (drm_r300_cmd_header_t *) r300AllocCmdBuf(r300, 9, __FUNCTION__); - cmd2[0].packet3.cmd_type = R300_CMD_PACKET3; - cmd2[0].packet3.packet = R300_CMD_PACKET3_CLEAR; - cmd2[1].u = r300PackFloat32(dPriv->w / 2.0); - cmd2[2].u = r300PackFloat32(dPriv->h / 2.0); - cmd2[3].u = r300PackFloat32(ctx->Depth.Clear); - cmd2[4].u = r300PackFloat32(1.0); - cmd2[5].u = r300PackFloat32(ctx->Color.ClearColor[0]); - cmd2[6].u = r300PackFloat32(ctx->Color.ClearColor[1]); - cmd2[7].u = r300PackFloat32(ctx->Color.ClearColor[2]); - cmd2[8].u = r300PackFloat32(ctx->Color.ClearColor[3]); + OUT_BATCH(cmdpacket3(R300_CMD_PACKET3_CLEAR)); + OUT_BATCH_FLOAT32(dPriv->w / 2.0); + OUT_BATCH_FLOAT32(dPriv->h / 2.0); + OUT_BATCH_FLOAT32(ctx->Depth.Clear); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); + END_BATCH(); r300EmitCacheFlush(rmesa); cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + + R300_STATECHANGE(r300, cb); + R300_STATECHANGE(r300, cmk); + R300_STATECHANGE(r300, zs); } static void r300EmitClearState(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); - r300ContextPtr rmesa = r300; + BATCH_LOCALS(r300); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; int i; - int cmd_reserved = 0; - int cmd_written = 0; - drm_radeon_cmd_header_t *cmd = NULL; int has_tcl = 1; int is_r500 = 0; GLuint vap_cntl; @@ -184,35 +195,37 @@ static void r300EmitClearState(GLcontext * ctx) if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) has_tcl = 0; - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - is_r500 = 1; - + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + is_r500 = 1; - /* FIXME: the values written to R300_VAP_INPUT_ROUTE_0_0 and - * R300_VAP_INPUT_ROUTE_0_1 are in fact known, however, the values are - * quite complex; see the functions in r300_emit.c. + /* State atom dirty tracking is a little subtle here. * - * I believe it would be a good idea to extend the functions in - * r300_emit.c so that they can be used to setup the default values for - * these registers, as well as the actual values used for rendering. + * On the one hand, we need to make sure base state is emitted + * here if we start with an empty batch buffer, otherwise clear + * works incorrectly with multiple processes. Therefore, the first + * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE. + * + * On the other hand, implicit state emission clears the state atom + * dirty bits, so we have to call R300_STATECHANGE later than the + * first BEGIN_BATCH. + * + * The final trickiness is that, because we change state, we need + * to ensure that any stored swtcl primitives are flushed properly + * before we start changing state. See the R300_NEWPRIM in r300Clear + * for this. */ - R300_STATECHANGE(r300, vir[0]); - reg_start(R300_VAP_PROG_STREAM_CNTL_0, 0); + BEGIN_BATCH(31); + OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1); if (!has_tcl) - e32(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) | + OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) | ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT))); else - e32(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) | + OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) | ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT))); - /* disable fog */ - R300_STATECHANGE(r300, fogs); - reg_start(R300_FG_FOG_BLEND, 0); - e32(0x0); - - R300_STATECHANGE(r300, vir[1]); - reg_start(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0); - e32(((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | + OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0); + OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0, + ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | @@ -226,238 +239,246 @@ static void r300EmitClearState(GLcontext * ctx) << R300_SWIZZLE1_SHIFT))); /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */ - R300_STATECHANGE(r300, vic); - reg_start(R300_VAP_VTX_STATE_CNTL, 1); - e32((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT)); - e32(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0); + OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2); + OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT)); + OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0); - R300_STATECHANGE(r300, vte); /* comes from fglrx startup of clear */ - reg_start(R300_SE_VTE_CNTL, 1); - e32(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | - R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | - R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | - R300_VPORT_Z_OFFSET_ENA); - e32(0x8); + OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2); + OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | + R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | + R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | + R300_VPORT_Z_OFFSET_ENA); + OUT_BATCH(0x8); - reg_start(R300_VAP_PSC_SGN_NORM_CNTL, 0); - e32(0xaaaaaaaa); + OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); - R300_STATECHANGE(r300, vof); - reg_start(R300_VAP_OUTPUT_VTX_FMT_0, 1); - e32(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); - e32(0x0); /* no textures */ + OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); + OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | + R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); + OUT_BATCH(0); /* no textures */ - R300_STATECHANGE(r300, txe); - reg_start(R300_TX_ENABLE, 0); - e32(0x0); + OUT_BATCH_REGVAL(R300_TX_ENABLE, 0); - R300_STATECHANGE(r300, vpt); - reg_start(R300_SE_VPORT_XSCALE, 5); - efloat(1.0); - efloat(dPriv->x); - efloat(1.0); - efloat(dPriv->y); - efloat(1.0); - efloat(0.0); + OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(dPriv->x); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(dPriv->y); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(0.0); - R300_STATECHANGE(r300, at); - reg_start(R300_FG_ALPHA_FUNC, 0); - e32(0x0); + OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0); + + OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + END_BATCH(); + R300_STATECHANGE(r300, vir[0]); + R300_STATECHANGE(r300, fogs); + R300_STATECHANGE(r300, vir[1]); + R300_STATECHANGE(r300, vic); + R300_STATECHANGE(r300, vte); + R300_STATECHANGE(r300, vof); + R300_STATECHANGE(r300, txe); + R300_STATECHANGE(r300, vpt); + R300_STATECHANGE(r300, at); R300_STATECHANGE(r300, bld); - reg_start(R300_RB3D_CBLEND, 1); - e32(0x0); - e32(0x0); + R300_STATECHANGE(r300, ps); if (has_tcl) { - R300_STATECHANGE(r300, vap_clip_cntl); - reg_start(R300_VAP_CLIP_CNTL, 0); - e32(R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE); + R300_STATECHANGE(r300, vap_clip_cntl); + + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE); + END_BATCH(); } - R300_STATECHANGE(r300, ps); - reg_start(R300_GA_POINT_SIZE, 0); - e32(((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) | - ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT)); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGVAL(R300_GA_POINT_SIZE, + ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) | + ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT)); + END_BATCH(); if (!is_r500) { R300_STATECHANGE(r300, ri); - reg_start(R300_RS_IP_0, 7); - for (i = 0; i < 8; ++i) { - e32(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); - } - R300_STATECHANGE(r300, rc); - /* The second constant is needed to get glxgears display anything .. */ - reg_start(R300_RS_COUNT, 1); - e32((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); - e32(0x0); - R300_STATECHANGE(r300, rr); - reg_start(R300_RS_INST_0, 0); - e32(R300_RS_INST_COL_CN_WRITE); + + BEGIN_BATCH(14); + OUT_BATCH_REGSEQ(R300_RS_IP_0, 8); + for (i = 0; i < 8; ++i) + OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); + + OUT_BATCH_REGSEQ(R300_RS_COUNT, 2); + OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_BATCH(0x0); + + OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE); + END_BATCH(); } else { R300_STATECHANGE(r300, ri); - reg_start(R500_RS_IP_0, 7); + R300_STATECHANGE(r300, rc); + R300_STATECHANGE(r300, rr); + + BEGIN_BATCH(14); + OUT_BATCH_REGSEQ(R500_RS_IP_0, 8); for (i = 0; i < 8; ++i) { - e32((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); + OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); } - R300_STATECHANGE(r300, rc); - /* The second constant is needed to get glxgears display anything .. */ - reg_start(R300_RS_COUNT, 1); - e32((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); - e32(0x0); - - R300_STATECHANGE(r300, rr); - reg_start(R500_RS_INST_0, 0); - e32(R500_RS_INST_COL_CN_WRITE); + OUT_BATCH_REGSEQ(R300_RS_COUNT, 2); + OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_BATCH(0x0); + OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); + END_BATCH(); } if (!is_r500) { R300_STATECHANGE(r300, fp); - reg_start(R300_US_CONFIG, 2); - e32(0x0); - e32(0x0); - e32(0x0); - reg_start(R300_US_CODE_ADDR_0, 3); - e32(0x0); - e32(0x0); - e32(0x0); - e32(R300_RGBA_OUT); - R300_STATECHANGE(r300, fpi[0]); R300_STATECHANGE(r300, fpi[1]); R300_STATECHANGE(r300, fpi[2]); R300_STATECHANGE(r300, fpi[3]); - reg_start(R300_US_ALU_RGB_INST_0, 0); - e32(FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); - - reg_start(R300_US_ALU_RGB_ADDR_0, 0); - e32(FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); - - reg_start(R300_US_ALU_ALPHA_INST_0, 0); - e32(FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); - - reg_start(R300_US_ALU_ALPHA_ADDR_0, 0); - e32(FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); + BEGIN_BATCH(17); + OUT_BATCH_REGSEQ(R300_US_CONFIG, 3); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(R300_RGBA_OUT); + + OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0, + FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); + OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0, + FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); + OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0, + FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); + OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0, + FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); + END_BATCH(); } else { - R300_STATECHANGE(r300, fp); - reg_start(R500_US_CONFIG, 1); - e32(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); - e32(0x0); - reg_start(R500_US_CODE_ADDR, 2); - e32(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); - e32(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); - e32(R500_US_CODE_OFFSET_ADDR(0)); - + R300_STATECHANGE(r300, fp); R300_STATECHANGE(r300, r500fp); - r500fp_start_fragment(0, 6); - - e32(R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK | - R500_INST_RGB_CLAMP | - R500_INST_ALPHA_CLAMP); - - e32(R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST); - - e32(R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST); - - e32(R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_R | - R500_ALU_RGB_B_SWIZ_B_G | - R500_ALU_RGB_G_SWIZ_B_B); - - e32(R500_ALPHA_OP_CMP | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_A); - - e32(R500_ALU_RGBA_OP_CMP | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0); + + BEGIN_BATCH(14); + OUT_BATCH_REGSEQ(R500_US_CONFIG, 2); + OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); + OUT_BATCH(0x0); + OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3); + OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); + OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); + OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0)); + + OUT_BATCH(cmdr500fp(0, 1, 0, 0)); + OUT_BATCH(R500_INST_TYPE_OUT | + R500_INST_TEX_SEM_WAIT | + R500_INST_LAST | + R500_INST_RGB_OMASK_R | + R500_INST_RGB_OMASK_G | + R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK | + R500_INST_RGB_CLAMP | + R500_INST_ALPHA_CLAMP); + OUT_BATCH(R500_RGB_ADDR0(0) | + R500_RGB_ADDR1(0) | + R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | + R500_RGB_ADDR2_CONST); + OUT_BATCH(R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR1(0) | + R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | + R500_ALPHA_ADDR2_CONST); + OUT_BATCH(R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_B); + OUT_BATCH(R500_ALPHA_OP_CMP | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_A); + OUT_BATCH(R500_ALU_RGBA_OP_CMP | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0); + END_BATCH(); } - reg_start(R300_VAP_PVS_STATE_FLUSH_REG, 0); - e32(0x00000000); + BEGIN_BATCH(2); + OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); + END_BATCH(); + if (has_tcl) { - vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | (12 << R300_VF_MAX_VTX_NUM_SHIFT)); - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - vap_cntl |= R500_TCL_STATE_OPTIMIZATION; - } else - vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + vap_cntl |= R500_TCL_STATE_OPTIMIZATION; + } else { + vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); + } if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) - vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) - vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) - vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580)) - vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); else - vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); + + R300_STATECHANGE(r300, vap_cntl); - R300_STATECHANGE(rmesa, vap_cntl); - reg_start(R300_VAP_CNTL, 0); - e32(vap_cntl); + BEGIN_BATCH(2); + OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl); + END_BATCH(); if (has_tcl) { R300_STATECHANGE(r300, pvs); - reg_start(R300_VAP_PVS_CODE_CNTL_0, 2); - - e32((0 << R300_PVS_FIRST_INST_SHIFT) | - (0 << R300_PVS_XYZW_VALID_INST_SHIFT) | - (1 << R300_PVS_LAST_INST_SHIFT)); - e32((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (0 << R300_PVS_MAX_CONST_ADDR_SHIFT)); - e32(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); - R300_STATECHANGE(r300, vpi); - vsf_start_fragment(0x0, 8); - - e32(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT)); - e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(0x0); - e32(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, PVS_DST_REG_OUT)); - e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(0x0); + BEGIN_BATCH(13); + OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3); + OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) | + (0 << R300_PVS_XYZW_VALID_INST_SHIFT) | + (1 << R300_PVS_LAST_INST_SHIFT)); + OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | + (0 << R300_PVS_MAX_CONST_ADDR_SHIFT)); + OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); + + OUT_BATCH(cmdvpu(0, 2)); + OUT_BATCH(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT)); + OUT_BATCH(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_BATCH(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_BATCH(0x0); + + OUT_BATCH(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, PVS_DST_REG_OUT)); + OUT_BATCH(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_BATCH(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_BATCH(0x0); + END_BATCH(); } } @@ -468,9 +489,11 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) { r300ContextPtr r300 = R300_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + GLframebuffer *fb = dPriv->driverPrivate; + struct radeon_renderbuffer *rrb; + struct radeon_renderbuffer *rrbd; int flags = 0; int bits = 0; - int swapped; if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r300Clear\n"); @@ -482,6 +505,12 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) return; } + /* Flush swtcl vertices if necessary, because we will change hardware + * state during clear. See also the state-related comment in + * r300EmitClearState. + */ + R300_NEWPRIM(r300); + if (mask & BUFFER_BIT_FRONT_LEFT) { flags |= BUFFER_BIT_FRONT_LEFT; mask &= ~BUFFER_BIT_FRONT_LEFT; @@ -509,26 +538,28 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) _swrast_Clear(ctx, mask); } - swapped = r300->radeon.sarea->pfCurrentPage == 1; - /* Make sure it fits there. */ r300EnsureCmdBufSpace(r300, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); + rrbd = (void *)r300->radeon.state.depth_buffer; if (flags & BUFFER_BIT_FRONT_LEFT) { - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped); + rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (flags & BUFFER_BIT_BACK_LEFT) { - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped ^ 1); + rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (bits) - r300ClearBuffer(r300, bits, 0); + r300ClearBuffer(r300, bits, NULL, rrbd); + COMMIT_BATCH(); } void r300Flush(GLcontext * ctx) @@ -538,302 +569,13 @@ void r300Flush(GLcontext * ctx) if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + if (rmesa->swtcl.flush) { + rmesa->swtcl.flush(rmesa); + } - if (rmesa->cmdbuf.count_used > rmesa->cmdbuf.count_reemit) + if (rmesa->cmdbuf.cs->cdw) { r300FlushCmdBuf(rmesa, __FUNCTION__); -} - -#ifdef USER_BUFFERS -#include "r300_mem.h" - -void r300RefillCurrentDmaRegion(r300ContextPtr rmesa, int size) -{ - struct r300_dma_buffer *dmabuf; - size = MAX2(size, RADEON_BUFFER_SIZE * 16); - - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) { - rmesa->dma.flush(rmesa); } - - if (rmesa->dma.current.buf) { -#ifdef USER_BUFFERS - r300_mem_use(rmesa, rmesa->dma.current.buf->id); -#endif - r300ReleaseDmaRegion(rmesa, &rmesa->dma.current, __FUNCTION__); - } - if (rmesa->dma.nr_released_bufs > 4) - r300FlushCmdBuf(rmesa, __FUNCTION__); - - dmabuf = CALLOC_STRUCT(r300_dma_buffer); - dmabuf->buf = (void *)1; /* hack */ - dmabuf->refcount = 1; - - dmabuf->id = r300_mem_alloc(rmesa, 4, size); - if (dmabuf->id == 0) { - LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ - - r300FlushCmdBufLocked(rmesa, __FUNCTION__); - radeonWaitForIdleLocked(&rmesa->radeon); - - dmabuf->id = r300_mem_alloc(rmesa, 4, size); - - UNLOCK_HARDWARE(&rmesa->radeon); - - if (dmabuf->id == 0) { - fprintf(stderr, - "Error: Could not get dma buffer... exiting\n"); - _mesa_exit(-1); - } - } - - rmesa->dma.current.buf = dmabuf; - rmesa->dma.current.address = r300_mem_ptr(rmesa, dmabuf->id); - rmesa->dma.current.end = size; - rmesa->dma.current.start = 0; - rmesa->dma.current.ptr = 0; -} - -void r300ReleaseDmaRegion(r300ContextPtr rmesa, - struct r300_dma_region *region, const char *caller) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (!region->buf) - return; - - if (rmesa->dma.flush) - rmesa->dma.flush(rmesa); - - if (--region->buf->refcount == 0) { - r300_mem_free(rmesa, region->buf->id); - FREE(region->buf); - rmesa->dma.nr_released_bufs++; - } - - region->buf = 0; - region->start = 0; -} - -/* Allocates a region from rmesa->dma.current. If there isn't enough - * space in current, grab a new buffer (and discard what was left of current) - */ -void r300AllocDmaRegion(r300ContextPtr rmesa, - struct r300_dma_region *region, - int bytes, int alignment) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush(rmesa); - - if (region->buf) - r300ReleaseDmaRegion(rmesa, region, __FUNCTION__); - - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; - - if (rmesa->dma.current.ptr + bytes > rmesa->dma.current.end) - r300RefillCurrentDmaRegion(rmesa, (bytes + 0x7) & ~0x7); - - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; - region->address = rmesa->dma.current.address; - region->buf = rmesa->dma.current.buf; - region->buf->refcount++; - - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; - - assert(rmesa->dma.current.ptr <= rmesa->dma.current.end); -} - -#else -static void r300RefillCurrentDmaRegion(r300ContextPtr rmesa) -{ - struct r300_dma_buffer *dmabuf; - int fd = rmesa->radeon.dri.fd; - int index = 0; - int size = 0; - drmDMAReq dma; - int ret; - - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) { - rmesa->dma.flush(rmesa); - } - - if (rmesa->dma.current.buf) - r300ReleaseDmaRegion(rmesa, &rmesa->dma.current, __FUNCTION__); - - if (rmesa->dma.nr_released_bufs > 4) - r300FlushCmdBuf(rmesa, __FUNCTION__); - - dma.context = rmesa->radeon.dri.hwContext; - dma.send_count = 0; - dma.send_list = NULL; - dma.send_sizes = NULL; - dma.flags = 0; - dma.request_count = 1; - dma.request_size = RADEON_BUFFER_SIZE; - dma.request_list = &index; - dma.request_sizes = &size; - dma.granted_count = 0; - - LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ - - ret = drmDMA(fd, &dma); - - if (ret != 0) { - /* Try to release some buffers and wait until we can't get any more */ - if (rmesa->dma.nr_released_bufs) { - r300FlushCmdBufLocked(rmesa, __FUNCTION__); - } - - if (RADEON_DEBUG & DEBUG_DMA) - fprintf(stderr, "Waiting for buffers\n"); - - radeonWaitForIdleLocked(&rmesa->radeon); - ret = drmDMA(fd, &dma); - - if (ret != 0) { - UNLOCK_HARDWARE(&rmesa->radeon); - fprintf(stderr, - "Error: Could not get dma buffer... exiting\n"); - _mesa_exit(-1); - } - } - - UNLOCK_HARDWARE(&rmesa->radeon); - - if (RADEON_DEBUG & DEBUG_DMA) - fprintf(stderr, "Allocated buffer %d\n", index); - - dmabuf = CALLOC_STRUCT(r300_dma_buffer); - dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index]; - dmabuf->refcount = 1; - - rmesa->dma.current.buf = dmabuf; - rmesa->dma.current.address = dmabuf->buf->address; - rmesa->dma.current.end = dmabuf->buf->total; - rmesa->dma.current.start = 0; - rmesa->dma.current.ptr = 0; -} - -void r300ReleaseDmaRegion(r300ContextPtr rmesa, - struct r300_dma_region *region, const char *caller) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (!region->buf) - return; - - if (rmesa->dma.flush) - rmesa->dma.flush(rmesa); - - if (--region->buf->refcount == 0) { - drm_radeon_cmd_header_t *cmd; - - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", - __FUNCTION__, region->buf->buf->idx); - cmd = - (drm_radeon_cmd_header_t *) r300AllocCmdBuf(rmesa, - sizeof - (*cmd) / 4, - __FUNCTION__); - cmd->dma.cmd_type = R300_CMD_DMA_DISCARD; - cmd->dma.buf_idx = region->buf->buf->idx; - - FREE(region->buf); - rmesa->dma.nr_released_bufs++; - } - - region->buf = 0; - region->start = 0; -} - -/* Allocates a region from rmesa->dma.current. If there isn't enough - * space in current, grab a new buffer (and discard what was left of current) - */ -void r300AllocDmaRegion(r300ContextPtr rmesa, - struct r300_dma_region *region, - int bytes, int alignment) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush(rmesa); - - if (region->buf) - r300ReleaseDmaRegion(rmesa, region, __FUNCTION__); - - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; - - if (rmesa->dma.current.ptr + bytes > rmesa->dma.current.end) - r300RefillCurrentDmaRegion(rmesa); - - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; - region->address = rmesa->dma.current.address; - region->buf = rmesa->dma.current.buf; - region->buf->refcount++; - - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; - - assert(rmesa->dma.current.ptr <= rmesa->dma.current.end); -} - -#endif - -GLboolean r300IsGartMemory(r300ContextPtr rmesa, const GLvoid * pointer, - GLint size) -{ - int offset = - (char *)pointer - - (char *)rmesa->radeon.radeonScreen->gartTextures.map; - int valid = (size >= 0 && offset >= 0 - && offset + size < - rmesa->radeon.radeonScreen->gartTextures.size); - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "r300IsGartMemory( %p ) : %d\n", pointer, - valid); - - return valid; -} - -GLuint r300GartOffsetFromVirtual(r300ContextPtr rmesa, const GLvoid * pointer) -{ - int offset = - (char *)pointer - - (char *)rmesa->radeon.radeonScreen->gartTextures.map; - - //fprintf(stderr, "offset=%08x\n", offset); - - if (offset < 0 - || offset > rmesa->radeon.radeonScreen->gartTextures.size) - return ~0; - else - return rmesa->radeon.radeonScreen->gart_texture_offset + offset; } void r300InitIoctlFuncs(struct dd_function_table *functions) diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.h b/src/mesa/drivers/dri/r300/r300_ioctl.h index e1143fb6c34..5f00264f112 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.h +++ b/src/mesa/drivers/dri/r300/r300_ioctl.h @@ -39,20 +39,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "radeon_drm.h" -extern GLboolean r300IsGartMemory(r300ContextPtr rmesa, - const GLvoid * pointer, GLint size); - -extern GLuint r300GartOffsetFromVirtual(r300ContextPtr rmesa, - const GLvoid * pointer); - extern void r300Flush(GLcontext * ctx); -extern void r300ReleaseDmaRegion(r300ContextPtr rmesa, - struct r300_dma_region *region, - const char *caller); extern void r300AllocDmaRegion(r300ContextPtr rmesa, - struct r300_dma_region *region, int bytes, - int alignment); + struct radeon_bo **pbo, int *poffset, + int bytes, int alignment); extern void r300InitIoctlFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/r300/r300_mem.c b/src/mesa/drivers/dri/r300/r300_mem.c deleted file mode 100644 index f8f9d4fcdf1..00000000000 --- a/src/mesa/drivers/dri/r300/r300_mem.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * Copyright (C) 2005 Aapo Tahkola. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/** - * \file - * - * \author Aapo Tahkola - */ - -#include - -#include "r300_context.h" -#include "r300_cmdbuf.h" -#include "r300_ioctl.h" -#include "r300_mem.h" -#include "radeon_ioctl.h" - -#ifdef USER_BUFFERS - -static void resize_u_list(r300ContextPtr rmesa) -{ - void *temp; - int nsize; - - temp = rmesa->rmm->u_list; - nsize = rmesa->rmm->u_size * 2; - - rmesa->rmm->u_list = _mesa_malloc(nsize * sizeof(*rmesa->rmm->u_list)); - _mesa_memset(rmesa->rmm->u_list, 0, - nsize * sizeof(*rmesa->rmm->u_list)); - - if (temp) { - r300FlushCmdBuf(rmesa, __FUNCTION__); - - _mesa_memcpy(rmesa->rmm->u_list, temp, - rmesa->rmm->u_size * sizeof(*rmesa->rmm->u_list)); - _mesa_free(temp); - } - - rmesa->rmm->u_size = nsize; -} - -void r300_mem_init(r300ContextPtr rmesa) -{ - rmesa->rmm = malloc(sizeof(struct r300_memory_manager)); - memset(rmesa->rmm, 0, sizeof(struct r300_memory_manager)); - - rmesa->rmm->u_size = 128; - resize_u_list(rmesa); -} - -void r300_mem_destroy(r300ContextPtr rmesa) -{ - _mesa_free(rmesa->rmm->u_list); - rmesa->rmm->u_list = NULL; - - _mesa_free(rmesa->rmm); - rmesa->rmm = NULL; -} - -void *r300_mem_ptr(r300ContextPtr rmesa, int id) -{ - assert(id <= rmesa->rmm->u_last); - return rmesa->rmm->u_list[id].ptr; -} - -int r300_mem_find(r300ContextPtr rmesa, void *ptr) -{ - int i; - - for (i = 1; i < rmesa->rmm->u_size + 1; i++) - if (rmesa->rmm->u_list[i].ptr && - ptr >= rmesa->rmm->u_list[i].ptr && - ptr < - rmesa->rmm->u_list[i].ptr + rmesa->rmm->u_list[i].size) - break; - - if (i < rmesa->rmm->u_size + 1) - return i; - - fprintf(stderr, "%p failed\n", ptr); - return 0; -} - -//#define MM_DEBUG -int r300_mem_alloc(r300ContextPtr rmesa, int alignment, int size) -{ - drm_radeon_mem_alloc_t alloc; - int offset = 0, ret; - int i, free = -1; - int done_age; - drm_radeon_mem_free_t memfree; - int tries = 0; - static int bytes_wasted = 0, allocated = 0; - - if (size < 4096) - bytes_wasted += 4096 - size; - - allocated += size; - -#if 0 - static int t = 0; - if (t != time(NULL)) { - t = time(NULL); - fprintf(stderr, "slots used %d, wasted %d kb, allocated %d\n", - rmesa->rmm->u_last, bytes_wasted / 1024, - allocated / 1024); - } -#endif - - memfree.region = RADEON_MEM_REGION_GART; - - again: - - done_age = radeonGetAge((radeonContextPtr) rmesa); - - if (rmesa->rmm->u_last + 1 >= rmesa->rmm->u_size) - resize_u_list(rmesa); - - for (i = rmesa->rmm->u_last + 1; i > 0; i--) { - if (rmesa->rmm->u_list[i].ptr == NULL) { - free = i; - continue; - } - - if (rmesa->rmm->u_list[i].h_pending == 0 && - rmesa->rmm->u_list[i].pending - && rmesa->rmm->u_list[i].age <= done_age) { - memfree.region_offset = - (char *)rmesa->rmm->u_list[i].ptr - - (char *)rmesa->radeon.radeonScreen->gartTextures. - map; - - ret = - drmCommandWrite(rmesa->radeon.radeonScreen-> - driScreen->fd, DRM_RADEON_FREE, - &memfree, sizeof(memfree)); - - if (ret) { - fprintf(stderr, "Failed to free at %p\n", - rmesa->rmm->u_list[i].ptr); - fprintf(stderr, "ret = %s\n", strerror(-ret)); - exit(1); - } else { -#ifdef MM_DEBUG - fprintf(stderr, "really freed %d at age %x\n", - i, - radeonGetAge((radeonContextPtr) rmesa)); -#endif - if (i == rmesa->rmm->u_last) - rmesa->rmm->u_last--; - - if (rmesa->rmm->u_list[i].size < 4096) - bytes_wasted -= - 4096 - rmesa->rmm->u_list[i].size; - - allocated -= rmesa->rmm->u_list[i].size; - rmesa->rmm->u_list[i].pending = 0; - rmesa->rmm->u_list[i].ptr = NULL; - free = i; - } - } - } - rmesa->rmm->u_head = i; - - if (free == -1) { - WARN_ONCE("Ran out of slots!\n"); - //usleep(100); - r300FlushCmdBuf(rmesa, __FUNCTION__); - tries++; - if (tries > 100) { - WARN_ONCE("Ran out of slots!\n"); - exit(1); - } - goto again; - } - - alloc.region = RADEON_MEM_REGION_GART; - alloc.alignment = alignment; - alloc.size = size; - alloc.region_offset = &offset; - - ret = - drmCommandWriteRead(rmesa->radeon.dri.fd, DRM_RADEON_ALLOC, &alloc, - sizeof(alloc)); - if (ret) { -#if 0 - WARN_ONCE("Ran out of mem!\n"); - r300FlushCmdBuf(rmesa, __FUNCTION__); - //usleep(100); - tries2++; - tries = 0; - if (tries2 > 100) { - WARN_ONCE("Ran out of GART memory!\n"); - exit(1); - } - goto again; -#else - WARN_ONCE - ("Ran out of GART memory (for %d)!\nPlease consider adjusting GARTSize option.\n", - size); - return 0; -#endif - } - - i = free; - - if (i > rmesa->rmm->u_last) - rmesa->rmm->u_last = i; - - rmesa->rmm->u_list[i].ptr = - ((GLubyte *) rmesa->radeon.radeonScreen->gartTextures.map) + offset; - rmesa->rmm->u_list[i].size = size; - rmesa->rmm->u_list[i].age = 0; - //fprintf(stderr, "alloc %p at id %d\n", rmesa->rmm->u_list[i].ptr, i); - -#ifdef MM_DEBUG - fprintf(stderr, "allocated %d at age %x\n", i, - radeonGetAge((radeonContextPtr) rmesa)); -#endif - - return i; -} - -void r300_mem_use(r300ContextPtr rmesa, int id) -{ - uint64_t ull; -#ifdef MM_DEBUG - fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, - radeonGetAge((radeonContextPtr) rmesa)); -#endif - drm_r300_cmd_header_t *cmd; - - assert(id <= rmesa->rmm->u_last); - - if (id == 0) - return; - - cmd = - (drm_r300_cmd_header_t *) r300AllocCmdBuf(rmesa, - 2 + sizeof(ull) / 4, - __FUNCTION__); - cmd[0].scratch.cmd_type = R300_CMD_SCRATCH; - cmd[0].scratch.reg = R300_MEM_SCRATCH; - cmd[0].scratch.n_bufs = 1; - cmd[0].scratch.flags = 0; - cmd++; - - ull = (uint64_t) (intptr_t) & rmesa->rmm->u_list[id].age; - _mesa_memcpy(cmd, &ull, sizeof(ull)); - cmd += sizeof(ull) / 4; - - cmd[0].u = /*id */ 0; - - LOCK_HARDWARE(&rmesa->radeon); /* Protect from DRM. */ - rmesa->rmm->u_list[id].h_pending++; - UNLOCK_HARDWARE(&rmesa->radeon); -} - -unsigned long r300_mem_offset(r300ContextPtr rmesa, int id) -{ - unsigned long offset; - - assert(id <= rmesa->rmm->u_last); - - offset = (char *)rmesa->rmm->u_list[id].ptr - - (char *)rmesa->radeon.radeonScreen->gartTextures.map; - offset += rmesa->radeon.radeonScreen->gart_texture_offset; - - return offset; -} - -void *r300_mem_map(r300ContextPtr rmesa, int id, int access) -{ -#ifdef MM_DEBUG - fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, - radeonGetAge((radeonContextPtr) rmesa)); -#endif - void *ptr; - int tries = 0; - - assert(id <= rmesa->rmm->u_last); - - if (access == R300_MEM_R) { - - if (rmesa->rmm->u_list[id].mapped == 1) - WARN_ONCE("buffer %d already mapped\n", id); - - rmesa->rmm->u_list[id].mapped = 1; - ptr = r300_mem_ptr(rmesa, id); - - return ptr; - } - - if (rmesa->rmm->u_list[id].h_pending) - r300FlushCmdBuf(rmesa, __FUNCTION__); - - if (rmesa->rmm->u_list[id].h_pending) { - return NULL; - } - - while (rmesa->rmm->u_list[id].age > - radeonGetAge((radeonContextPtr) rmesa) && tries++ < 1000) - usleep(10); - - if (tries >= 1000) { - fprintf(stderr, "Idling failed (%x vs %x)\n", - rmesa->rmm->u_list[id].age, - radeonGetAge((radeonContextPtr) rmesa)); - return NULL; - } - - if (rmesa->rmm->u_list[id].mapped == 1) - WARN_ONCE("buffer %d already mapped\n", id); - - rmesa->rmm->u_list[id].mapped = 1; - ptr = r300_mem_ptr(rmesa, id); - - return ptr; -} - -void r300_mem_unmap(r300ContextPtr rmesa, int id) -{ -#ifdef MM_DEBUG - fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, - radeonGetAge((radeonContextPtr) rmesa)); -#endif - - assert(id <= rmesa->rmm->u_last); - - if (rmesa->rmm->u_list[id].mapped == 0) - WARN_ONCE("buffer %d not mapped\n", id); - - rmesa->rmm->u_list[id].mapped = 0; -} - -void r300_mem_free(r300ContextPtr rmesa, int id) -{ -#ifdef MM_DEBUG - fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, - radeonGetAge((radeonContextPtr) rmesa)); -#endif - - assert(id <= rmesa->rmm->u_last); - - if (id == 0) - return; - - if (rmesa->rmm->u_list[id].ptr == NULL) { - WARN_ONCE("Not allocated!\n"); - return; - } - - if (rmesa->rmm->u_list[id].pending) { - WARN_ONCE("%p already pended!\n", rmesa->rmm->u_list[id].ptr); - return; - } - - rmesa->rmm->u_list[id].pending = 1; -} -#endif diff --git a/src/mesa/drivers/dri/r300/r300_mem.h b/src/mesa/drivers/dri/r300/r300_mem.h deleted file mode 100644 index 625a7f6d8d5..00000000000 --- a/src/mesa/drivers/dri/r300/r300_mem.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __R300_MEM_H__ -#define __R300_MEM_H__ - -//#define R300_MEM_PDL 0 -#define R300_MEM_UL 1 - -#define R300_MEM_R 1 -#define R300_MEM_W 2 -#define R300_MEM_RW (R300_MEM_R | R300_MEM_W) - -#define R300_MEM_SCRATCH 2 - -struct r300_memory_manager { - struct { - void *ptr; - uint32_t size; - uint32_t age; - uint32_t h_pending; - int pending; - int mapped; - } *u_list; - int u_head, u_size, u_last; - -}; - -extern void r300_mem_init(r300ContextPtr rmesa); -extern void r300_mem_destroy(r300ContextPtr rmesa); -extern void *r300_mem_ptr(r300ContextPtr rmesa, int id); -extern int r300_mem_find(r300ContextPtr rmesa, void *ptr); -extern int r300_mem_alloc(r300ContextPtr rmesa, int alignment, int size); -extern void r300_mem_use(r300ContextPtr rmesa, int id); -extern unsigned long r300_mem_offset(r300ContextPtr rmesa, int id); -extern void *r300_mem_map(r300ContextPtr rmesa, int id, int access); -extern void r300_mem_unmap(r300ContextPtr rmesa, int id); -extern void r300_mem_free(r300ContextPtr rmesa, int id); - -#endif diff --git a/src/mesa/drivers/dri/r300/r300_mipmap_tree.c b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c new file mode 100644 index 00000000000..81ad7ea3280 --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "r300_mipmap_tree.h" + +#include +#include + +#include "main/simple_list.h" +#include "main/texcompress.h" +#include "main/texformat.h" + +#include "radeon_buffer.h" + +static GLuint r300_compressed_texture_size(GLcontext *ctx, + GLsizei width, GLsizei height, GLsizei depth, + GLuint mesaFormat) +{ + GLuint size = _mesa_compressed_texture_size(ctx, width, height, depth, mesaFormat); + + if (mesaFormat == MESA_FORMAT_RGB_DXT1 || + mesaFormat == MESA_FORMAT_RGBA_DXT1) { + if (width + 3 < 8) /* width one block */ + size = size * 4; + else if (width + 3 < 16) + size = size * 2; + } else { + /* DXT3/5, 16 bytes per block */ + WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n"); + if (width + 3 < 8) + size = size * 2; + } + + return size; +} + +/** + * Compute sizes and fill in offset and blit information for the given + * image (determined by \p face and \p level). + * + * \param curOffset points to the offset at which the image is to be stored + * and is updated by this function according to the size of the image. + */ +static void compute_tex_image_offset(r300_mipmap_tree *mt, + GLuint face, GLuint level, GLuint* curOffset) +{ + r300_mipmap_level *lvl = &mt->levels[level]; + + /* Find image size in bytes */ + if (mt->compressed) { + /* TODO: Is this correct? Need test cases for compressed textures! */ + GLuint align; + + if (mt->target == GL_TEXTURE_RECTANGLE_NV) + align = 64 / mt->bpp; + else + align = 32 / mt->bpp; + lvl->rowstride = (lvl->width + align - 1) & ~(align - 1); + lvl->size = r300_compressed_texture_size(mt->r300->radeon.glCtx, + lvl->width, lvl->height, lvl->depth, mt->compressed); + } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { + lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; + lvl->size = lvl->rowstride * lvl->height; + } else if (mt->tilebits & R300_TXO_MICRO_TILE) { + /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, + * though the actual offset may be different (if texture is less than + * 32 bytes width) to the untiled case */ + lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; + lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; + } else { + lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; + lvl->size = lvl->rowstride * lvl->height * lvl->depth; + } + assert(lvl->size > 0); + + /* All images are aligned to a 32-byte offset */ + *curOffset = (*curOffset + 0x1f) & ~0x1f; + lvl->faces[face].offset = *curOffset; + *curOffset += lvl->size; +} + +static GLuint minify(GLuint size, GLuint levels) +{ + size = size >> levels; + if (size < 1) + size = 1; + return size; +} + +static void calculate_miptree_layout(r300_mipmap_tree *mt) +{ + GLuint curOffset; + GLuint numLevels; + GLuint i; + + numLevels = mt->lastLevel - mt->firstLevel + 1; + assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + + curOffset = 0; + for(i = 0; i < numLevels; i++) { + GLuint face; + + mt->levels[i].width = minify(mt->width0, i); + mt->levels[i].height = minify(mt->height0, i); + mt->levels[i].depth = minify(mt->depth0, i); + + for(face = 0; face < mt->faces; face++) + compute_tex_image_offset(mt, face, i, &curOffset); + } + + /* Note the required size in memory */ + mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; +} + + +/** + * Create a new mipmap tree, calculate its layout and allocate memory. + */ +r300_mipmap_tree* r300_miptree_create(r300ContextPtr rmesa, r300TexObj *t, + GLenum target, GLuint firstLevel, GLuint lastLevel, + GLuint width0, GLuint height0, GLuint depth0, + GLuint bpp, GLuint tilebits, GLuint compressed) +{ + r300_mipmap_tree *mt = CALLOC_STRUCT(_r300_mipmap_tree); + + mt->r300 = rmesa; + mt->refcount = 1; + mt->t = t; + mt->target = target; + mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; + mt->firstLevel = firstLevel; + mt->lastLevel = lastLevel; + mt->width0 = width0; + mt->height0 = height0; + mt->depth0 = depth0; + mt->bpp = bpp; + mt->tilebits = tilebits; + mt->compressed = compressed; + + calculate_miptree_layout(mt); + + mt->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, mt->totalsize, 1024, 0); + + return mt; +} + +void r300_miptree_reference(r300_mipmap_tree *mt) +{ + mt->refcount++; + assert(mt->refcount > 0); +} + +void r300_miptree_unreference(r300_mipmap_tree *mt) +{ + if (!mt) + return; + + assert(mt->refcount > 0); + mt->refcount--; + if (!mt->refcount) { + radeon_bo_unref(mt->bo); + free(mt); + } +} + + +static void calculate_first_last_level(struct gl_texture_object *tObj, + GLuint *pfirstLevel, GLuint *plastLevel) +{ + const struct gl_texture_image * const baseImage = + tObj->Image[0][tObj->BaseLevel]; + + /* These must be signed values. MinLod and MaxLod can be negative numbers, + * and having firstLevel and lastLevel as signed prevents the need for + * extra sign checks. + */ + int firstLevel; + int lastLevel; + + /* Yes, this looks overly complicated, but it's all needed. + */ + switch (tObj->Target) { + case GL_TEXTURE_1D: + case GL_TEXTURE_2D: + case GL_TEXTURE_3D: + case GL_TEXTURE_CUBE_MAP: + if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) { + /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL. + */ + firstLevel = lastLevel = tObj->BaseLevel; + } else { + firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5); + firstLevel = MAX2(firstLevel, tObj->BaseLevel); + firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); + lastLevel = MAX2(lastLevel, tObj->BaseLevel); + lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = MIN2(lastLevel, tObj->MaxLevel); + lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ + } + break; + case GL_TEXTURE_RECTANGLE_NV: + case GL_TEXTURE_4D_SGIS: + firstLevel = lastLevel = 0; + break; + default: + return; + } + + /* save these values */ + *pfirstLevel = firstLevel; + *plastLevel = lastLevel; +} + + +/** + * Checks whether the given miptree can hold the given texture image at the + * given face and level. + */ +GLboolean r300_miptree_matches_image(r300_mipmap_tree *mt, + struct gl_texture_image *texImage, GLuint face, GLuint level) +{ + r300_mipmap_level *lvl; + + if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel) + return GL_FALSE; + + if (texImage->TexFormat->TexelBytes != mt->bpp) + return GL_FALSE; + + lvl = &mt->levels[level - mt->firstLevel]; + if (lvl->width != texImage->Width || + lvl->height != texImage->Height || + lvl->depth != texImage->Depth) + return GL_FALSE; + + return GL_TRUE; +} + + +/** + * Checks whether the given miptree has the right format to store the given texture object. + */ +GLboolean r300_miptree_matches_texture(r300_mipmap_tree *mt, struct gl_texture_object *texObj) +{ + struct gl_texture_image *firstImage; + GLuint compressed; + GLuint numfaces = 1; + GLuint firstLevel, lastLevel; + + calculate_first_last_level(texObj, &firstLevel, &lastLevel); + if (texObj->Target == GL_TEXTURE_CUBE_MAP) + numfaces = 6; + + firstImage = texObj->Image[0][firstLevel]; + compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0; + + return (mt->firstLevel == firstLevel && + mt->lastLevel == lastLevel && + mt->width0 == firstImage->Width && + mt->height0 == firstImage->Height && + mt->depth0 == firstImage->Depth && + mt->bpp == firstImage->TexFormat->TexelBytes && + mt->compressed == compressed); +} + + +/** + * Try to allocate a mipmap tree for the given texture that will fit the + * given image in the given position. + */ +void r300_try_alloc_miptree(r300ContextPtr rmesa, r300TexObj *t, + struct gl_texture_image *texImage, GLuint face, GLuint level) +{ + GLuint compressed = texImage->IsCompressed ? texImage->TexFormat->MesaFormat : 0; + GLuint numfaces = 1; + GLuint firstLevel, lastLevel; + + assert(!t->mt); + + calculate_first_last_level(&t->base, &firstLevel, &lastLevel); + if (t->base.Target == GL_TEXTURE_CUBE_MAP) + numfaces = 6; + + if (level != firstLevel || face >= numfaces) + return; + + t->mt = r300_miptree_create(rmesa, t, t->base.Target, + firstLevel, lastLevel, + texImage->Width, texImage->Height, texImage->Depth, + texImage->TexFormat->TexelBytes, t->tile_bits, compressed); +} diff --git a/src/mesa/drivers/dri/r300/r300_mipmap_tree.h b/src/mesa/drivers/dri/r300/r300_mipmap_tree.h new file mode 100644 index 00000000000..aeb52dc1353 --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_mipmap_tree.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __R300_MIPMAP_TREE_H_ +#define __R300_MIPMAP_TREE_H_ + +#include "r300_context.h" + +typedef struct _r300_mipmap_tree r300_mipmap_tree; +typedef struct _r300_mipmap_level r300_mipmap_level; +typedef struct _r300_mipmap_image r300_mipmap_image; + +struct _r300_mipmap_image { + GLuint offset; /** Offset of this image from the start of mipmap tree buffer, in bytes */ +}; + +struct _r300_mipmap_level { + GLuint width; + GLuint height; + GLuint depth; + GLuint size; /** Size of each image, in bytes */ + GLuint rowstride; /** in bytes */ + r300_mipmap_image faces[6]; +}; + + +/** + * A mipmap tree contains texture images in the layout that the hardware + * expects. + * + * The meta-data of mipmap trees is immutable, i.e. you cannot change the + * layout on-the-fly; however, the texture contents (i.e. texels) can be + * changed. + */ +struct _r300_mipmap_tree { + r300ContextPtr r300; + r300TexObj *t; + struct radeon_bo *bo; + GLuint refcount; + + GLuint totalsize; /** total size of the miptree, in bytes */ + + GLenum target; /** GL_TEXTURE_xxx */ + GLuint faces; /** # of faces: 6 for cubemaps, 1 otherwise */ + GLuint firstLevel; /** First mip level stored in this mipmap tree */ + GLuint lastLevel; /** Last mip level stored in this mipmap tree */ + + GLuint width0; /** Width of firstLevel image */ + GLuint height0; /** Height of firstLevel image */ + GLuint depth0; /** Depth of firstLevel image */ + + GLuint bpp; /** Bytes per texel */ + GLuint tilebits; /** R300_TXO_xxx_TILE */ + GLuint compressed; /** MESA_FORMAT_xxx indicating a compressed format, or 0 if uncompressed */ + + r300_mipmap_level levels[RADEON_MAX_TEXTURE_LEVELS]; +}; + +r300_mipmap_tree* r300_miptree_create(r300ContextPtr rmesa, r300TexObj *t, + GLenum target, GLuint firstLevel, GLuint lastLevel, + GLuint width0, GLuint height0, GLuint depth0, + GLuint bpp, GLuint tilebits, GLuint compressed); +void r300_miptree_reference(r300_mipmap_tree *mt); +void r300_miptree_unreference(r300_mipmap_tree *mt); + +GLboolean r300_miptree_matches_image(r300_mipmap_tree *mt, + struct gl_texture_image *texImage, GLuint face, GLuint level); +GLboolean r300_miptree_matches_texture(r300_mipmap_tree *mt, struct gl_texture_object *texObj); +void r300_try_alloc_miptree(r300ContextPtr rmesa, r300TexObj *t, + struct gl_texture_image *texImage, GLuint face, GLuint level); + + +#endif /* __R300_MIPMAP_TREE_H_ */ diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index 778db96cc1f..8b3fe431ab3 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -1525,6 +1525,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R500_SEL_FILTER4_TC3 (3 << 18) #define R300_TX_OFFSET_0 0x4540 +#define R300_TX_OFFSET_1 0x4544 +#define R300_TX_OFFSET_2 0x4548 +#define R300_TX_OFFSET_3 0x454C +#define R300_TX_OFFSET_4 0x4550 +#define R300_TX_OFFSET_5 0x4554 +#define R300_TX_OFFSET_6 0x4558 +#define R300_TX_OFFSET_7 0x455C /* BEGIN: Guess from R200 */ # define R300_TXO_ENDIAN_NO_SWAP (0 << 0) # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 292f87a2b1b..1762d4cb03b 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -175,89 +175,91 @@ int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim) static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_dma_region *rvb = &rmesa->state.elt_dma; void *out; - if (r300IsGartMemory(rmesa, elts, n_elts * 4)) { - rvb->address = rmesa->radeon.radeonScreen->gartTextures.map; - rvb->start = ((char *)elts) - rvb->address; - rvb->aos_offset = - rmesa->radeon.radeonScreen->gart_texture_offset + - rvb->start; - return; - } else if (r300IsGartMemory(rmesa, elts, 1)) { - WARN_ONCE("Pointer not within GART memory!\n"); - _mesa_exit(-1); - } - - r300AllocDmaRegion(rmesa, rvb, n_elts * 4, 4); - rvb->aos_offset = GET_START(rvb); - - out = rvb->address + rvb->start; + rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, n_elts * 4, 4, + RADEON_GEM_DOMAIN_GTT); + rmesa->state.elt_dma_offset = 0; + radeon_bo_map(rmesa->state.elt_dma_bo, 1); + out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; memcpy(out, elts, n_elts * 4); + radeon_bo_unmap(rmesa->state.elt_dma_bo); } -static void r300FireEB(r300ContextPtr rmesa, unsigned long addr, - int vertex_count, int type) +static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) { - int cmd_reserved = 0; - int cmd_written = 0; - drm_radeon_cmd_header_t *cmd = NULL; - - start_packet3(CP_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0), 0); - e32(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (vertex_count << 16) | type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - - start_packet3(CP_PACKET3(R300_PACKET3_INDX_BUFFER, 2), 2); - e32(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - e32(addr); - e32(vertex_count); + BATCH_LOCALS(rmesa); + + if (vertex_count > 0) { + BEGIN_BATCH(8); + OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | + ((vertex_count + 0) << 16) | + type | + R300_VAP_VF_CNTL__INDEX_SIZE_32bit); + + OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); + OUT_BATCH_RELOC(0, rmesa->state.elt_dma_bo, + rmesa->state.elt_dma_offset, 0); + OUT_BATCH(vertex_count); + END_BATCH(); + } } static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) { + BATCH_LOCALS(rmesa); + uint32_t voffset; int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; - int cmd_reserved = 0; - int cmd_written = 0; - drm_radeon_cmd_header_t *cmd = NULL; if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); - start_packet3(CP_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1), sz - 1); - e32(nr); + BEGIN_BATCH(sz+2); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { - e32((rmesa->state.aos[i].aos_size << 0) | - (rmesa->state.aos[i].aos_stride << 8) | - (rmesa->state.aos[i + 1].aos_size << 16) | - (rmesa->state.aos[i + 1].aos_stride << 24)); - - e32(rmesa->state.aos[i].aos_offset + offset * 4 * rmesa->state.aos[i].aos_stride); - e32(rmesa->state.aos[i + 1].aos_offset + offset * 4 * rmesa->state.aos[i + 1].aos_stride); + OUT_BATCH((rmesa->state.aos[i].components << 0) | + (rmesa->state.aos[i].stride << 8) | + (rmesa->state.aos[i + 1].components << 16) | + (rmesa->state.aos[i + 1].stride << 24)); + + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + OUT_BATCH_RELOC(0, rmesa->state.aos[i].bo, voffset, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + OUT_BATCH_RELOC(0, rmesa->state.aos[i+1].bo, voffset, 0); } if (nr & 1) { - e32((rmesa->state.aos[nr - 1].aos_size << 0) | - (rmesa->state.aos[nr - 1].aos_stride << 8)); - e32(rmesa->state.aos[nr - 1].aos_offset + offset * 4 * rmesa->state.aos[nr - 1].aos_stride); + OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | + (rmesa->state.aos[nr - 1].stride << 8)); + OUT_BATCH_RELOC(0, rmesa->state.aos[nr - 1].bo, + rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride, 0); } + END_BATCH(); } static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) { - int cmd_reserved = 0; - int cmd_written = 0; - drm_radeon_cmd_header_t *cmd = NULL; + BATCH_LOCALS(rmesa); - start_packet3(CP_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0), 0); - e32(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); + BEGIN_BATCH(3); + OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); + END_BATCH(); } static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, int start, int end, int prim) { + BATCH_LOCALS(rmesa); int type, num_verts; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; @@ -268,6 +270,12 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, if (type < 0 || num_verts <= 0) return; + /* Make space for at least 64 dwords. + * This is supposed to ensure that we can get all rendering + * commands into a single command buffer. + */ + r300EnsureCmdBufSpace(rmesa, 64, __FUNCTION__); + if (vb->Elts) { if (num_verts > 65535) { /* not implemented yet */ @@ -287,11 +295,12 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, */ r300EmitElts(ctx, vb->Elts, num_verts); r300EmitAOS(rmesa, rmesa->state.aos_count, start); - r300FireEB(rmesa, rmesa->state.elt_dma.aos_offset, num_verts, type); + r300FireEB(rmesa, num_verts, type); } else { r300EmitAOS(rmesa, rmesa->state.aos_count, start); r300FireAOS(rmesa, num_verts, type); } + COMMIT_BATCH(); } static GLboolean r300RunRender(GLcontext * ctx, @@ -302,7 +311,6 @@ static GLboolean r300RunRender(GLcontext * ctx, TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; - if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); @@ -324,10 +332,6 @@ static GLboolean r300RunRender(GLcontext * ctx, r300EmitCacheFlush(rmesa); -#ifdef USER_BUFFERS - r300UseArrays(ctx); -#endif - r300ReleaseArrays(ctx); return GL_FALSE; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 6a5c3633a23..44f9510d3ce 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -55,6 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_ioctl.h" #include "radeon_state.h" +#include "radeon_buffer.h" #include "r300_context.h" #include "r300_ioctl.h" #include "r300_state.h" @@ -1144,41 +1145,26 @@ void r300UpdateViewportOffset(GLcontext * ctx) void r300UpdateDrawBuffer(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300ContextPtr r300 = rmesa; struct gl_framebuffer *fb = ctx->DrawBuffer; - driRenderbuffer *drb; + struct radeon_renderbuffer *rrb; if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { /* draw to front */ - drb = - (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT]. - Renderbuffer; + rrb = + (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { /* draw to back */ - drb = - (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT]. - Renderbuffer; + rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; } else { /* drawing to multiple buffers, or none */ return; } - assert(drb); - assert(drb->flippedPitch); + assert(rrb); + assert(rrb->pitch); R300_STATECHANGE(rmesa, cb); - r300->hw.cb.cmd[R300_CB_OFFSET] = drb->flippedOffset + //r300->radeon.state.color.drawOffset + - r300->radeon.radeonScreen->fbLocation; - r300->hw.cb.cmd[R300_CB_PITCH] = drb->flippedPitch; //r300->radeon.state.color.drawPitch; - - if (r300->radeon.radeonScreen->cpp == 4) - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_ARGB8888; - else - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_RGB565; - - if (r300->radeon.sarea->tiling_enabled) - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_TILE_ENABLE; #if 0 R200_STATECHANGE(rmesa, ctx); @@ -1497,14 +1483,9 @@ static void r300SetupTextures(GLcontext * ctx) /* We cannot let disabled tmu offsets pass DRM */ for (i = 0; i < mtu; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { - -#if 0 /* Enables old behaviour */ - hw_tmu = i; -#endif tmu_mappings[i] = hw_tmu; - t = r300->state.texture.unit[i].texobj; - /* XXX questionable fix for bug 9170: */ + t = r300_tex_obj(ctx->Texture.Unit[i]._Current); if (!t) continue; @@ -1530,21 +1511,20 @@ static void r300SetupTextures(GLcontext * ctx) */ r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->filter_1 | - translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.tObj->LodBias); + translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.LodBias); r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->size; r300->hw.tex.format.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->format; r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->pitch_reg; - r300->hw.tex.offset.cmd[R300_TEX_VALUE_0 + - hw_tmu] = t->offset; + r300->hw.textures[hw_tmu] = t; - if (t->offset & R300_TXO_MACRO_TILE) { + if (t->tile_bits & R300_TXO_MACRO_TILE) { WARN_ONCE("macro tiling enabled!\n"); } - if (t->offset & R300_TXO_MICRO_TILE) { + if (t->tile_bits & R300_TXO_MICRO_TILE) { WARN_ONCE("micro tiling enabled!\n"); } @@ -2223,8 +2203,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300UpdateCulling(ctx); - r300UpdateTextureState(ctx); - r300SetBlendState(ctx); r300SetLogicOpState(ctx); @@ -2371,20 +2349,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300BlendColor(ctx, ctx->Color.BlendColor); - /* Again, r300ClearBuffer uses this */ - r300->hw.cb.cmd[R300_CB_OFFSET] = - r300->radeon.state.color.drawOffset + - r300->radeon.radeonScreen->fbLocation; - r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.state.color.drawPitch; - - if (r300->radeon.radeonScreen->cpp == 4) - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_ARGB8888; - else - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_RGB565; - - if (r300->radeon.sarea->tiling_enabled) - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_TILE_ENABLE; - r300->hw.rb3d_dither_ctl.cmd[1] = 0; r300->hw.rb3d_dither_ctl.cmd[2] = 0; r300->hw.rb3d_dither_ctl.cmd[3] = 0; @@ -2400,10 +2364,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - r300->hw.zb.cmd[R300_ZB_OFFSET] = - r300->radeon.radeonScreen->depthOffset + - r300->radeon.radeonScreen->fbLocation; - r300->hw.zb.cmd[R300_ZB_PITCH] = r300->radeon.radeonScreen->depthPitch; if (r300->radeon.sarea->tiling_enabled) { /* XXX: Turn off when clearing buffers ? */ @@ -2675,7 +2635,7 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) GLcontext *ctx; ctx = rmesa->radeon.glCtx; - r300UpdateTextureState(ctx); + r300ValidateTextures(ctx); r300SetEarlyZState(ctx); GLuint fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index 0589ab7cad9..4d0a25fb0e1 100644 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ b/src/mesa/drivers/dri/r300/r300_state.h @@ -39,8 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_NEWPRIM( rmesa ) \ do { \ - if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa ); \ } while (0) #define R300_STATECHANGE(r300, atom) \ @@ -57,13 +55,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. TODO: This has not been implemented yet */ #define R300_FIREVERTICES( r300 ) \ -do { \ - \ - if ( (r300)->cmdbuf.count_used || (r300)->dma.flush ) { \ - r300Flush( (r300)->radeon.glCtx ); \ - } \ - \ -} while (0) + do { \ + r300Flush( (r300)->radeon.glCtx ); \ + } while (0) // r300_state.c extern int future_hw_tcl_on; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index b6e7ce1a1a6..f21766b4d8f 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -56,12 +56,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_ioctl.h" #include "r300_emit.h" -#include "r300_mem.h" static void flush_last_swtcl_prim( r300ContextPtr rmesa ); -void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, GLuint offset); +void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset); void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr); #define EMIT_ATTR( ATTR, STYLE ) \ do { \ @@ -86,7 +85,6 @@ static void r300SetVertexFormat( GLcontext *ctx ) DECLARE_RENDERINPUTS(index_bitset); GLuint InputsRead = 0, OutputsWritten = 0; int vap_fmt_0 = 0; - int vap_vte_cntl = 0; int offset = 0; int vte = 0; GLint inputs[VERT_ATTRIB_MAX]; @@ -175,7 +173,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) inputs[i] = -1; } } - + /* Fixed, apply to vir0 only */ if (InputsRead & (1 << VERT_ATTRIB_POS)) inputs[VERT_ATTRIB_POS] = 0; @@ -186,16 +184,16 @@ static void r300SetVertexFormat( GLcontext *ctx ) for (i = VERT_ATTRIB_TEX0; i <= VERT_ATTRIB_TEX7; i++) if (InputsRead & (1 << i)) inputs[i] = 6 + (i - VERT_ATTRIB_TEX0); - + for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { if (InputsRead & (1 << i)) { tab[nr++] = i; } } - + for (i = 0; i < nr; i++) { int ci; - + swizzle[i][0] = SWIZZLE_ZERO; swizzle[i][1] = SWIZZLE_ZERO; swizzle[i][2] = SWIZZLE_ZERO; @@ -215,21 +213,21 @@ static void r300SetVertexFormat( GLcontext *ctx ) ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, nr); - + R300_STATECHANGE(rmesa, vic); rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - + R300_STATECHANGE(rmesa, vof); rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_fmt_1; - + rmesa->swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->swtcl.vertex_attrs, + rmesa->swtcl.vertex_attrs, rmesa->swtcl.vertex_attr_count, NULL, 0 ); - + rmesa->swtcl.vertex_size /= 4; RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset ); @@ -247,37 +245,22 @@ static void flush_last_swtcl_prim( r300ContextPtr rmesa ) { if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->dma.flush = NULL; - - if (rmesa->dma.current.buf) { - struct r300_dma_region *current = &rmesa->dma.current; - GLuint current_offset = GET_START(current); - - assert (current->start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - current->ptr); - - if (rmesa->dma.current.start != rmesa->dma.current.ptr) { - - r300EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - - r300EmitState(rmesa); - - r300EmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - current_offset); - - r300EmitVbufPrim( rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - - r300EmitCacheFlush(rmesa); - } - - rmesa->swtcl.numverts = 0; - current->start = current->ptr; - } + rmesa->swtcl.flush = NULL; + radeon_bo_unmap(rmesa->swtcl.bo); + r300EnsureCmdBufSpace(rmesa, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); + r300EmitState(rmesa); + r300EmitVertexAOS(rmesa, + rmesa->swtcl.vertex_size, + rmesa->swtcl.bo, + 0); + r300EmitVbufPrim(rmesa, + rmesa->swtcl.hw_primitive, + rmesa->swtcl.numverts); + r300EmitCacheFlush(rmesa); + COMMIT_BATCH(); + rmesa->swtcl.numverts = 0; } /* Alloc space in the current dma region. @@ -287,26 +270,14 @@ r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - r300RefillCurrentDmaRegion( rmesa, bytes); - - if (!rmesa->dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->dma.current.start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current.ptr ); - - { - GLubyte *head = (GLubyte *) (rmesa->dma.current.address + rmesa->dma.current.ptr); - rmesa->dma.current.ptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; - } + rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT); + radeon_bo_map(rmesa->swtcl.bo, 1); + if (rmesa->swtcl.flush == NULL) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->swtcl.flush = flush_last_swtcl_prim; + } + return rmesa->swtcl.bo->ptr; } static GLuint reduced_prim[] = { @@ -352,7 +323,7 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); r300ContextPtr rmesa = R300_CONTEXT(ctx); \ const char *r300verts = (char *)rmesa->swtcl.verts; #define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int))) -#define VERTEX r300Vertex +#define VERTEX r300Vertex #define DO_DEBUG_VERTS (1 && (RADEON_DEBUG & DEBUG_VERTS)) #define PRINT_VERTEX(x) #undef TAG @@ -572,18 +543,16 @@ static void r300RenderStart(GLcontext *ctx) r300ContextPtr rmesa = R300_CONTEXT( ctx ); // fprintf(stderr, "%s\n", __FUNCTION__); - r300ChooseRenderState(ctx); + r300ChooseRenderState(ctx); r300SetVertexFormat(ctx); r300UpdateShaders(rmesa); r300UpdateShaderStates(rmesa); r300EmitCacheFlush(rmesa); - - if (rmesa->dma.flush != 0 && - rmesa->dma.flush != flush_last_swtcl_prim) - rmesa->dma.flush( rmesa ); - + if (rmesa->swtcl.flush != NULL) { + rmesa->swtcl.flush(rmesa); + } } static void r300RenderFinish(GLcontext *ctx) @@ -593,7 +562,7 @@ static void r300RenderFinish(GLcontext *ctx) static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - + if (rmesa->swtcl.hw_primitive != hwprim) { R300_NEWPRIM( rmesa ); rmesa->swtcl.hw_primitive = hwprim; @@ -611,7 +580,7 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) r300RasterPrimitive( ctx, reduced_prim[prim] ); // fprintf(stderr, "%s\n", __FUNCTION__); - + } static void r300ResetLineStipple(GLcontext *ctx) @@ -625,12 +594,12 @@ void r300InitSwtcl(GLcontext *ctx) TNLcontext *tnl = TNL_CONTEXT(ctx); r300ContextPtr rmesa = R300_CONTEXT(ctx); static int firsttime = 1; - + if (firsttime) { init_rast_tab(); firsttime = 0; } - + tnl->Driver.Render.Start = r300RenderStart; tnl->Driver.Render.Finish = r300RenderFinish; tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive; @@ -638,15 +607,15 @@ void r300InitSwtcl(GLcontext *ctx) tnl->Driver.Render.BuildVertices = _tnl_build_vertices; tnl->Driver.Render.CopyPV = _tnl_copy_pv; tnl->Driver.Render.Interp = _tnl_interp; - + /* FIXME: what are these numbers? */ - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, + _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 48 * sizeof(GLfloat) ); - + rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; rmesa->swtcl.RenderIndex = ~0; rmesa->swtcl.render_primitive = GL_TRIANGLES; - rmesa->swtcl.hw_primitive = 0; + rmesa->swtcl.hw_primitive = 0; _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); @@ -655,9 +624,9 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_need_projected_coords( ctx, GL_FALSE ); r300ChooseRenderState(ctx); - _mesa_validate_all_lighting_tables( ctx ); + _mesa_validate_all_lighting_tables( ctx ); - tnl->Driver.NotifyMaterialChange = + tnl->Driver.NotifyMaterialChange = _mesa_validate_all_lighting_tables; } @@ -665,33 +634,32 @@ void r300DestroySwtcl(GLcontext *ctx) { } -void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, GLuint offset) +void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { - int cmd_reserved = 0; - int cmd_written = 0; + BATCH_LOCALS(rmesa); - drm_radeon_cmd_header_t *cmd = NULL; if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", - __FUNCTION__, vertex_size, offset); - - start_packet3(CP_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2), 2); - e32(1); - e32(vertex_size | (vertex_size << 8)); - e32(offset); + fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", + __FUNCTION__, vertex_size, offset); + + BEGIN_BATCH(5); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); + OUT_BATCH(1); + OUT_BATCH(vertex_size | (vertex_size << 8)); + OUT_BATCH_RELOC(0, bo, offset, 0); + END_BATCH(); } void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) { - - int cmd_reserved = 0; - int cmd_written = 0; + BATCH_LOCALS(rmesa); int type, num_verts; - drm_radeon_cmd_header_t *cmd = NULL; type = r300PrimitiveType(rmesa, primitive); num_verts = r300NumVerts(rmesa, vertex_nr, primitive); - - start_packet3(CP_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0), 0); - e32(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); + + BEGIN_BATCH(3); + OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); + END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 8ab382c83cc..fa96cdf3774 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/enums.h" #include "main/image.h" +#include "main/mipmap.h" #include "main/simple_list.h" #include "main/texformat.h" #include "main/texstore.h" @@ -49,6 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "r300_state.h" #include "r300_ioctl.h" +#include "r300_mipmap_tree.h" #include "r300_tex.h" #include "xmlpool.h" @@ -79,7 +81,7 @@ static unsigned int translate_wrap_mode(GLenum wrapmode) */ static void r300UpdateTexWrap(r300TexObjPtr t) { - struct gl_texture_object *tObj = t->base.tObj; + struct gl_texture_object *tObj = &t->base; t->filter &= ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK); @@ -119,6 +121,9 @@ static GLuint aniso_filter(GLfloat anisotropy) */ static void r300SetTexFilter(r300TexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) { + /* Force revalidation to account for switches from/to mipmapping. */ + t->validated = GL_FALSE; + t->filter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK); t->filter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY; @@ -176,39 +181,6 @@ static void r300SetTexBorderColor(r300TexObjPtr t, GLubyte c[4]) t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); } -/** - * Allocate space for and load the mesa images into the texture memory block. - * This will happen before drawing with a new texture, or drawing with a - * texture after it was swapped out or teximaged again. - */ - -static r300TexObjPtr r300AllocTexObj(struct gl_texture_object *texObj) -{ - r300TexObjPtr t; - - t = CALLOC_STRUCT(r300_tex_obj); - texObj->DriverData = t; - if (t != NULL) { - if (RADEON_DEBUG & DEBUG_TEXTURE) { - fprintf(stderr, "%s( %p, %p )\n", __FUNCTION__, - (void *)texObj, (void *)t); - } - - /* Initialize non-image-dependent parts of the state: - */ - t->base.tObj = texObj; - t->border_fallback = GL_FALSE; - - make_empty_list(&t->base); - - r300UpdateTexWrap(t); - r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); - r300SetTexBorderColor(t, texObj->_BorderChan); - } - - return t; -} - /* try to find a format which will only need a memcopy */ static const struct gl_texture_format *r300Choose8888TexFormat(GLenum srcFormat, GLenum srcType) @@ -434,277 +406,204 @@ static const struct gl_texture_format *r300ChooseTextureFormat(GLcontext * ctx, return NULL; /* never get here */ } -static GLboolean -r300ValidateClientStorage(GLcontext * ctx, GLenum target, - GLint internalFormat, - GLint srcWidth, GLint srcHeight, - GLenum format, GLenum type, const void *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) + +/** + * Allocate an empty texture image object. + */ +static struct gl_texture_image *r300NewTextureImage(GLcontext *ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + return CALLOC(sizeof(r300_texture_image)); +} - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "intformat %s format %s type %s\n", - _mesa_lookup_enum_by_nr(internalFormat), - _mesa_lookup_enum_by_nr(format), - _mesa_lookup_enum_by_nr(type)); +/** + * Free memory associated with this texture image. + */ +static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) +{ + r300_texture_image* image = get_r300_texture_image(timage); - if (!ctx->Unpack.ClientStorage) - return 0; + if (image->mt) { + r300_miptree_unreference(image->mt); + image->mt = 0; + assert(!image->base.Data); + } else { + _mesa_free_texture_image_data(ctx, timage); + } +} - if (ctx->_ImageTransferState || - texImage->IsCompressed || texObj->GenerateMipmap) - return 0; - /* This list is incomplete, may be different on ppc??? - */ - switch (internalFormat) { - case GL_RGBA: - if (format == GL_BGRA && type == GL_UNSIGNED_INT_8_8_8_8_REV) { - texImage->TexFormat = _dri_texformat_argb8888; - } else - return 0; - break; +/* Set Data pointer and additional data for mapped texture image */ +static void teximage_set_map_data(r300_texture_image *image) +{ + r300_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; + image->base.RowStride = lvl->rowstride / image->mt->bpp; +} - case GL_RGB: - if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { - texImage->TexFormat = _dri_texformat_rgb565; - } else - return 0; - break; - case GL_YCBCR_MESA: - if (format == GL_YCBCR_MESA && - type == GL_UNSIGNED_SHORT_8_8_REV_APPLE) { - texImage->TexFormat = &_mesa_texformat_ycbcr_rev; - } else if (format == GL_YCBCR_MESA && - (type == GL_UNSIGNED_SHORT_8_8_APPLE || - type == GL_UNSIGNED_BYTE)) { - texImage->TexFormat = &_mesa_texformat_ycbcr; - } else - return 0; - break; +/** + * Map a single texture image for glTexImage and friends. + */ +static void r300_teximage_map(r300_texture_image *image, GLboolean write_enable) +{ + if (image->mt) { + assert(!image->base.Data); - default: - return 0; + radeon_bo_map(image->mt->bo, write_enable); + teximage_set_map_data(image); } +} - /* Could deal with these packing issues, but currently don't: - */ - if (packing->SkipPixels || - packing->SkipRows || packing->SwapBytes || packing->LsbFirst) { - return 0; - } - GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, - format, type); +static void r300_teximage_unmap(r300_texture_image *image) +{ + if (image->mt) { + assert(image->base.Data); - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: srcRowStride %d/%x\n", - __FUNCTION__, srcRowStride, srcRowStride); + image->base.Data = 0; + radeon_bo_unmap(image->mt->bo); + } +} - /* Could check this later in upload, pitch restrictions could be - * relaxed, but would need to store the image pitch somewhere, - * as packing details might change before image is uploaded: - */ - if (!r300IsGartMemory(rmesa, pixels, srcHeight * srcRowStride) - || (srcRowStride & 63)) - return 0; +/** + * Map a validated texture for reading during software rendering. + */ +static void r300MapTexture(GLcontext *ctx, struct gl_texture_object *texObj) +{ + r300TexObj* t = r300_tex_obj(texObj); + int face, level; - /* Have validated that _mesa_transfer_teximage would be a straight - * memcpy at this point. NOTE: future calls to TexSubImage will - * overwrite the client data. This is explicitly mentioned in the - * extension spec. - */ - texImage->Data = (void *)pixels; - texImage->IsClientData = GL_TRUE; - texImage->RowStride = srcRowStride / texImage->TexFormat->TexelBytes; + assert(texObj->_Complete); + assert(t->mt); - return 1; + radeon_bo_map(t->mt->bo, GL_FALSE); + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + teximage_set_map_data(get_r300_texture_image(texObj->Image[face][level])); + } } -static void r300TexImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) +static void r300UnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) { - driTextureObject *t = (driTextureObject *) texObj->DriverData; + r300TexObj* t = r300_tex_obj(texObj); + int face, level; - if (t) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D"); - return; - } - } + assert(texObj->_Complete); + assert(t->mt); - /* Note, this will call ChooseTextureFormat */ - _mesa_store_teximage1d(ctx, target, level, internalFormat, - width, border, format, type, pixels, - &ctx->Unpack, texObj, texImage); - - t->dirty_images[0] |= (1 << level); + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + texObj->Image[face][level]->Data = 0; + } + radeon_bo_unmap(t->mt->bo); } -static void r300TexSubImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) +/** + * All glTexImage calls go through this function. + */ +static void r300_teximage( + GLcontext *ctx, int dims, + GLint face, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLsizei imageSize, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) { - driTextureObject *t = (driTextureObject *) texObj->DriverData; + r300ContextPtr rmesa = R300_CONTEXT(ctx); + r300TexObj* t = r300_tex_obj(texObj); + r300_texture_image* image = get_r300_texture_image(texImage); - assert(t); /* this _should_ be true */ - if (t) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage1D"); - return; - } - } + R300_FIREVERTICES(rmesa); - _mesa_store_texsubimage1d(ctx, target, level, xoffset, width, - format, type, pixels, packing, texObj, - texImage); + t->validated = GL_FALSE; - t->dirty_images[0] |= (1 << level); -} + /* Choose and fill in the texture format for this image */ + texImage->TexFormat = r300ChooseTextureFormat(ctx, internalFormat, format, type); + _mesa_set_fetch_functions(texImage, dims); -static void r300TexImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - driTextureObject *t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = - (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; + if (texImage->TexFormat->TexelBytes == 0) { + texImage->IsCompressed = GL_TRUE; + texImage->CompressedSize = + ctx->Driver.CompressedTextureSize(ctx, texImage->Width, + texImage->Height, texImage->Depth, + texImage->TexFormat->MesaFormat); + } else { + texImage->IsCompressed = GL_FALSE; + texImage->CompressedSize = 0; } - if (t != NULL) { - driSwapOutTextureObject(t); + /* Allocate memory for image */ + r300FreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ + + if (!t->mt) + r300_try_alloc_miptree(rmesa, t, texImage, face, level); + if (t->mt && r300_miptree_matches_image(t->mt, texImage, face, level)) { + image->mt = t->mt; + image->mtlevel = level - t->mt->firstLevel; + image->mtface = face; + r300_miptree_reference(t->mt); } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D"); - return; + int size; + if (texImage->IsCompressed) { + size = texImage->CompressedSize; + } else { + size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; } + texImage->Data = _mesa_alloc_texmemory(size); } - texImage->IsClientData = GL_FALSE; - - if (r300ValidateClientStorage(ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using client storage\n", - __FUNCTION__); + /* Upload texture image; note that the spec allows pixels to be NULL */ + if (compressed) { + pixels = _mesa_validate_pbo_compressed_teximage( + ctx, imageSize, pixels, packing, "glCompressedTexImage"); } else { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using normal storage\n", - __FUNCTION__); - - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r300ChooseTextureFormat. - */ - _mesa_store_teximage2d(ctx, target, level, internalFormat, - width, height, border, format, type, - pixels, &ctx->Unpack, texObj, texImage); - - t->dirty_images[face] |= (1 << level); + pixels = _mesa_validate_pbo_teximage( + ctx, dims, width, height, depth, + format, type, pixels, packing, "glTexImage"); } -} -static void r300TexSubImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - driTextureObject *t = (driTextureObject *) texObj->DriverData; - GLuint face; + if (pixels) { + r300_teximage_map(image, GL_TRUE); - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = - (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - assert(t); /* this _should_ be true */ - if (t) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage2D"); - return; + if (compressed) { + memcpy(texImage->Data, pixels, imageSize); + } else { + GLuint dstRowStride; + if (image->mt) { + r300_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; + } + if (!texImage->TexFormat->StoreImage(ctx, dims, + texImage->_BaseFormat, + texImage->TexFormat, + texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */ + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); } + + r300_teximage_unmap(image); } - _mesa_store_texsubimage2d(ctx, target, level, xoffset, yoffset, width, - height, format, type, pixels, packing, texObj, - texImage); + _mesa_unmap_teximage_pbo(ctx, packing); - t->dirty_images[face] |= (1 << level); + /* SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); + } } -static void r300CompressedTexImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - driTextureObject *t = (driTextureObject *) texObj->DriverData; - GLuint face; - /* which cube face or ordinary 2D image */ +static GLuint face_for_target(GLenum target) +{ switch (target) { case GL_TEXTURE_CUBE_MAP_POSITIVE_X: case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: @@ -712,103 +611,50 @@ static void r300CompressedTexImage2D(GLcontext * ctx, GLenum target, case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = - (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; + return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; default: - face = 0; - } - - if (t != NULL) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, - "glCompressedTexImage2D"); - return; - } + return 0; } +} - texImage->IsClientData = GL_FALSE; - /* can't call this, different parameters. Would never evaluate to true anyway currently */ -#if 0 - if (r300ValidateClientStorage(ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using client storage\n", - __FUNCTION__); - } else -#endif - { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using normal storage\n", - __FUNCTION__); - - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r300ChooseTextureFormat. - */ - _mesa_store_compressed_teximage2d(ctx, target, level, - internalFormat, width, height, - border, imageSize, data, - texObj, texImage); - - t->dirty_images[face] |= (1 << level); - } +static void r300TexImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + r300_teximage(ctx, 1, 0, level, internalFormat, width, 1, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); } -static void r300CompressedTexSubImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint xoffset, - GLint yoffset, GLsizei width, - GLsizei height, GLenum format, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) +static void r300TexImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) { - driTextureObject *t = (driTextureObject *) texObj->DriverData; - GLuint face; + GLuint face = face_for_target(target); - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = - (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - assert(t); /* this _should_ be true */ - if (t) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, - "glCompressedTexSubImage3D"); - return; - } - } + r300_teximage(ctx, 2, face, level, internalFormat, width, height, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); +} - _mesa_store_compressed_texsubimage2d(ctx, target, level, xoffset, - yoffset, width, height, format, - imageSize, data, texObj, texImage); +static void r300CompressedTexImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint internalFormat, + GLint width, GLint height, GLint border, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + GLuint face = face_for_target(target); - t->dirty_images[face] |= (1 << level); + r300_teximage(ctx, 2, face, level, internalFormat, width, height, 1, + imageSize, 0, 0, data, 0, texObj, texImage, 1); } static void r300TexImage3D(GLcontext * ctx, GLenum target, GLint level, @@ -820,51 +666,100 @@ static void r300TexImage3D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - driTextureObject *t = (driTextureObject *) texObj->DriverData; + r300_teximage(ctx, 3, 0, level, internalFormat, width, height, depth, + 0, format, type, pixels, packing, texObj, texImage, 0); +} - if (t) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage3D"); - return; +/** + * Update a subregion of the given texture image. + */ +static void r300_texsubimage(GLcontext* ctx, int dims, int level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) +{ + r300ContextPtr rmesa = R300_CONTEXT(ctx); + r300_texture_image* image = get_r300_texture_image(texImage); + + R300_FIREVERTICES(rmesa); + + pixels = _mesa_validate_pbo_teximage(ctx, dims, + width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); + + if (pixels) { + GLint dstRowStride; + r300_teximage_map(image, GL_TRUE); + + if (image->mt) { + r300_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; } - } - texImage->IsClientData = GL_FALSE; + if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, + texImage->TexFormat, texImage->Data, + xoffset, yoffset, zoffset, + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); -#if 0 - if (r300ValidateClientStorage(ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using client storage\n", - __FUNCTION__); - } else -#endif - { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using normal storage\n", - __FUNCTION__); - - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r300ChooseTextureFormat. - */ - _mesa_store_teximage3d(ctx, target, level, internalFormat, - width, height, depth, border, - format, type, pixels, - &ctx->Unpack, texObj, texImage); + r300_teximage_unmap(image); + } - t->dirty_images[0] |= (1 << level); + _mesa_unmap_teximage_pbo(ctx, packing); + + /* GL_SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); } } +static void r300TexSubImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, + GLsizei width, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + r300_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, + format, type, pixels, packing, texObj, texImage, 0); +} + +static void r300TexSubImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + r300_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, + format, type, pixels, packing, texObj, texImage, 0); +} + +static void r300CompressedTexSubImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint xoffset, + GLint yoffset, GLsizei width, + GLsizei height, GLenum format, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + r300_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, + format, 0, data, 0, texObj, texImage, 1); +} + static void r300TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, @@ -875,30 +770,29 @@ r300TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - driTextureObject *t = (driTextureObject *) texObj->DriverData; - -/* fprintf(stderr, "%s\n", __FUNCTION__); */ + r300_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, + format, type, pixels, packing, texObj, texImage, 0); +} - assert(t); /* this _should_ be true */ - if (t) { - driSwapOutTextureObject(t); - } else { - t = (driTextureObject *) r300AllocTexObj(texObj); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage3D"); - return; - } - texObj->DriverData = t; - } - _mesa_store_texsubimage3d(ctx, target, level, xoffset, yoffset, zoffset, - width, height, depth, - format, type, pixels, packing, texObj, - texImage); +/** + * Wraps Mesa's implementation to ensure that the base level image is mapped. + * + * This relies on internal details of _mesa_generate_mipmap, in particular + * the fact that the memory for recreated texture images is always freed. + */ +static void r300_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) +{ + GLuint face = face_for_target(target); + r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[face][texObj->BaseLevel]); - t->dirty_images[0] |= (1 << level); + r300_teximage_map(baseimage, GL_FALSE); + _mesa_generate_mipmap(ctx, target, texObj); + r300_teximage_unmap(baseimage); } + + /** * Changes variables and flags for a state update, which will happen at the * next UpdateTextureState @@ -908,7 +802,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, struct gl_texture_object *texObj, GLenum pname, const GLfloat * params) { - r300TexObjPtr t = (r300TexObjPtr) texObj->DriverData; + r300TexObj* t = r300_tex_obj(texObj); if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { fprintf(stderr, "%s( %s )\n", __FUNCTION__, @@ -941,7 +835,11 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, * we just have to rely on loading the right subset of mipmap levels * to simulate a clamped LOD. */ - driSwapOutTextureObject((driTextureObject *) t); + if (t->mt) { + r300_miptree_unreference(t->mt); + t->mt = 0; + t->validated = GL_FALSE; + } break; case GL_DEPTH_TEXTURE_MODE: @@ -964,27 +862,10 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, } } -static void r300BindTexture(GLcontext * ctx, GLenum target, - struct gl_texture_object *texObj) -{ - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %p ) unit=%d\n", __FUNCTION__, - (void *)texObj, ctx->Texture.CurrentUnit); - } - - if ((target == GL_TEXTURE_1D) - || (target == GL_TEXTURE_2D) - || (target == GL_TEXTURE_3D) - || (target == GL_TEXTURE_CUBE_MAP) - || (target == GL_TEXTURE_RECTANGLE_NV)) { - assert(texObj->DriverData != NULL); - } -} - static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - driTextureObject *t = (driTextureObject *) texObj->DriverData; + r300TexObj* t = r300_tex_obj(texObj); if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, @@ -992,14 +873,19 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) _mesa_lookup_enum_by_nr(texObj->Target)); } - if (t != NULL) { - if (rmesa) { - R300_FIREVERTICES(rmesa); - } + if (rmesa) { + int i; + R300_FIREVERTICES(rmesa); + + for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i) + if (rmesa->hw.textures[i] == t) + rmesa->hw.textures[i] = 0; + } - driDestroyTextureObject(t); + if (t->mt) { + r300_miptree_unreference(t->mt); + t->mt = 0; } - /* Free mipmap images and the texture object itself */ _mesa_delete_texture_object(ctx, texObj); } @@ -1008,8 +894,6 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) * Called via ctx->Driver.NewTextureObject. * Note: this function will be called during context creation to * allocate the default texture objects. - * Note: we could use containment here to 'derive' the driver-specific - * texture object from the core mesa gl_texture_object. Not done at this time. * Fixup MaxAnisotropy according to user preference. */ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, @@ -1017,14 +901,23 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, GLenum target) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_texture_object *obj; - obj = _mesa_new_texture_object(ctx, name, target); - if (!obj) - return NULL; - obj->MaxAnisotropy = rmesa->initialMaxAnisotropy; + r300TexObj* t = CALLOC_STRUCT(r300_tex_obj); - r300AllocTexObj(obj); - return obj; + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + t, _mesa_lookup_enum_by_nr(target)); + } + + _mesa_initialize_texture_object(&t->base, name, target); + t->base.MaxAnisotropy = rmesa->initialMaxAnisotropy; + + /* Initialize hardware state */ + r300UpdateTexWrap(t); + r300SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); + r300SetTexBorderColor(t, t->base._BorderChan); + + return &t->base; } void r300InitTextureFuncs(struct dd_function_table *functions) @@ -1032,6 +925,11 @@ void r300InitTextureFuncs(struct dd_function_table *functions) /* Note: we only plug in the functions we implement in the driver * since _mesa_init_driver_functions() was already called. */ + functions->NewTextureImage = r300NewTextureImage; + functions->FreeTexImageData = r300FreeTexImageData; + functions->MapTexture = r300MapTexture; + functions->UnmapTexture = r300UnmapTexture; + functions->ChooseTextureFormat = r300ChooseTextureFormat; functions->TexImage1D = r300TexImage1D; functions->TexImage2D = r300TexImage2D; @@ -1040,7 +938,6 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->TexSubImage2D = r300TexSubImage2D; functions->TexSubImage3D = r300TexSubImage3D; functions->NewTextureObject = r300NewTextureObject; - functions->BindTexture = r300BindTexture; functions->DeleteTexture = r300DeleteTexture; functions->IsTextureResident = driIsTextureResident; @@ -1049,5 +946,7 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->CompressedTexImage2D = r300CompressedTexImage2D; functions->CompressedTexSubImage2D = r300CompressedTexSubImage2D; + functions->GenerateMipmap = r300_generate_mipmap; + driInitTextureFormats(); } diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h index b86d45bfe05..358b927828c 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ b/src/mesa/drivers/dri/r300/r300_tex.h @@ -41,12 +41,7 @@ extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); -extern void r300UpdateTextureState(GLcontext * ctx); - -extern int r300UploadTexImages(r300ContextPtr rmesa, r300TexObjPtr t, - GLuint face); - -extern void r300DestroyTexObj(r300ContextPtr rmesa, r300TexObjPtr t); +extern void r300ValidateTextures(GLcontext * ctx); extern void r300InitTextureFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/r300/r300_texmem.c b/src/mesa/drivers/dri/r300/r300_texmem.c index b03eefaa7c5..53eeca13866 100644 --- a/src/mesa/drivers/dri/r300/r300_texmem.c +++ b/src/mesa/drivers/dri/r300/r300_texmem.c @@ -48,520 +48,11 @@ SOFTWARE. #include "r300_context.h" #include "r300_state.h" #include "r300_cmdbuf.h" +#include "r300_emit.h" +#include "r300_mipmap_tree.h" #include "radeon_ioctl.h" #include "r300_tex.h" #include "r300_ioctl.h" #include /* for usleep() */ -#ifdef USER_BUFFERS -#include "r300_mem.h" -#endif -/** - * Destroy any device-dependent state associated with the texture. This may - * include NULLing out hardware state that points to the texture. - */ -void r300DestroyTexObj(r300ContextPtr rmesa, r300TexObjPtr t) -{ - int i; - - if (RADEON_DEBUG & DEBUG_TEXTURE) { - fprintf(stderr, "%s( %p, %p )\n", __FUNCTION__, - (void *)t, (void *)t->base.tObj); - } - - for (i = 0; i < rmesa->radeon.glCtx->Const.MaxTextureUnits; i++) { - if (rmesa->state.texture.unit[i].texobj == t) { - rmesa->state.texture.unit[i].texobj = NULL; - } - } -} - -/* ------------------------------------------------------------ - * Texture image conversions - */ - -static void r300UploadGARTClientSubImage(r300ContextPtr rmesa, - r300TexObjPtr t, - struct gl_texture_image *texImage, - GLint hwlevel, - GLint x, GLint y, - GLint width, GLint height) -{ - const struct gl_texture_format *texFormat = texImage->TexFormat; - GLuint srcPitch, dstPitch; - int blit_format; - int srcOffset; - - /* - * XXX it appears that we always upload the full image, not a subimage. - * I.e. x==0, y==0, width=texWidth, height=texWidth. If this is ever - * changed, the src pitch will have to change. - */ - switch (texFormat->TexelBytes) { - case 1: - blit_format = R300_CP_COLOR_FORMAT_CI8; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - case 2: - blit_format = R300_CP_COLOR_FORMAT_RGB565; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - case 4: - blit_format = R300_CP_COLOR_FORMAT_ARGB8888; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - case 8: - case 16: - blit_format = R300_CP_COLOR_FORMAT_CI8; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - default: - return; - } - - t->image[0][hwlevel].data = texImage->Data; - srcOffset = r300GartOffsetFromVirtual(rmesa, texImage->Data); - - assert(srcOffset != ~0); - - /* Don't currently need to cope with small pitches? - */ - width = texImage->Width; - height = texImage->Height; - - if (texFormat->TexelBytes > 4) { - width *= texFormat->TexelBytes; - } - - r300EmitWait(rmesa, R300_WAIT_3D); - - r300EmitBlit(rmesa, blit_format, - srcPitch, - srcOffset, - dstPitch, - t->bufAddr, - x, - y, - t->image[0][hwlevel].x + x, - t->image[0][hwlevel].y + y, width, height); - - r300EmitWait(rmesa, R300_WAIT_2D); -} - -static void r300UploadRectSubImage(r300ContextPtr rmesa, - r300TexObjPtr t, - struct gl_texture_image *texImage, - GLint x, GLint y, GLint width, GLint height) -{ - const struct gl_texture_format *texFormat = texImage->TexFormat; - int blit_format, dstPitch, done; - - switch (texFormat->TexelBytes) { - case 1: - blit_format = R300_CP_COLOR_FORMAT_CI8; - break; - case 2: - blit_format = R300_CP_COLOR_FORMAT_RGB565; - break; - case 4: - blit_format = R300_CP_COLOR_FORMAT_ARGB8888; - break; - case 8: - case 16: - blit_format = R300_CP_COLOR_FORMAT_CI8; - break; - default: - return; - } - - t->image[0][0].data = texImage->Data; - - /* Currently don't need to cope with small pitches. - */ - width = texImage->Width; - height = texImage->Height; - dstPitch = t->pitch; - - if (texFormat->TexelBytes > 4) { - width *= texFormat->TexelBytes; - } - - if (rmesa->prefer_gart_client_texturing && texImage->IsClientData) { - /* In this case, could also use GART texturing. This is - * currently disabled, but has been tested & works. - */ - t->offset = r300GartOffsetFromVirtual(rmesa, texImage->Data); - t->pitch = texImage->RowStride * texFormat->TexelBytes - 32; - - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, - "Using GART texturing for rectangular client texture\n"); - - /* Release FB memory allocated for this image: - */ - /* FIXME This may not be correct as driSwapOutTextureObject sets - * FIXME dirty_images. It may be fine, though. - */ - if (t->base.memBlock) { - driSwapOutTextureObject((driTextureObject *) t); - } - } else if (texImage->IsClientData) { - /* Data already in GART memory, with usable pitch. - */ - GLuint srcPitch; - srcPitch = texImage->RowStride * texFormat->TexelBytes; - r300EmitBlit(rmesa, - blit_format, - srcPitch, - r300GartOffsetFromVirtual(rmesa, texImage->Data), - dstPitch, t->bufAddr, 0, 0, 0, 0, width, height); - } else { - /* Data not in GART memory, or bad pitch. - */ - for (done = 0; done < height;) { - struct r300_dma_region region; - int lines = - MIN2(height - done, RADEON_BUFFER_SIZE / dstPitch); - int src_pitch; - char *tex; - - src_pitch = texImage->RowStride * texFormat->TexelBytes; - - tex = (char *)texImage->Data + done * src_pitch; - - memset(®ion, 0, sizeof(region)); - r300AllocDmaRegion(rmesa, ®ion, lines * dstPitch, - 1024); - - /* Copy texdata to dma: - */ - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, - "%s: src_pitch %d dst_pitch %d\n", - __FUNCTION__, src_pitch, dstPitch); - - if (src_pitch == dstPitch) { - memcpy(region.address + region.start, tex, - lines * src_pitch); - } else { - char *buf = region.address + region.start; - int i; - for (i = 0; i < lines; i++) { - memcpy(buf, tex, src_pitch); - buf += dstPitch; - tex += src_pitch; - } - } - - r300EmitWait(rmesa, R300_WAIT_3D); - - /* Blit to framebuffer - */ - r300EmitBlit(rmesa, - blit_format, - dstPitch, GET_START(®ion), - dstPitch | (t->tile_bits >> 16), - t->bufAddr, 0, 0, 0, done, width, lines); - - r300EmitWait(rmesa, R300_WAIT_2D); -#ifdef USER_BUFFERS - r300_mem_use(rmesa, region.buf->id); -#endif - - r300ReleaseDmaRegion(rmesa, ®ion, __FUNCTION__); - done += lines; - } - } -} - -/** - * Upload the texture image associated with texture \a t at the specified - * level at the address relative to \a start. - */ -static void r300UploadSubImage(r300ContextPtr rmesa, r300TexObjPtr t, - GLint hwlevel, - GLint x, GLint y, GLint width, GLint height, - GLuint face) -{ - struct gl_texture_image *texImage = NULL; - GLuint offset; - GLint imageWidth, imageHeight; - GLint ret; - drm_radeon_texture_t tex; - drm_radeon_tex_image_t tmp; - const int level = hwlevel + t->base.firstLevel; - - if (RADEON_DEBUG & DEBUG_TEXTURE) { - fprintf(stderr, - "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n", - __FUNCTION__, (void *)t, (void *)t->base.tObj, level, - width, height, face); - } - - ASSERT(face < 6); - - /* Ensure we have a valid texture to upload */ - if ((hwlevel < 0) || (hwlevel >= RADEON_MAX_TEXTURE_LEVELS)) { - _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); - return; - } - - texImage = t->base.tObj->Image[face][level]; - - if (!texImage) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: texImage %d is NULL!\n", - __FUNCTION__, level); - return; - } - if (!texImage->Data) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: image data is NULL!\n", - __FUNCTION__); - return; - } - - if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - assert(level == 0); - assert(hwlevel == 0); - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: image data is rectangular\n", - __FUNCTION__); - r300UploadRectSubImage(rmesa, t, texImage, x, y, width, height); - return; - } else if (texImage->IsClientData) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, - "%s: image data is in GART client storage\n", - __FUNCTION__); - r300UploadGARTClientSubImage(rmesa, t, texImage, hwlevel, x, y, - width, height); - return; - } else if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: image data is in normal memory\n", - __FUNCTION__); - - imageWidth = texImage->Width; - imageHeight = texImage->Height; - - offset = t->bufAddr; - - if (RADEON_DEBUG & (DEBUG_TEXTURE | DEBUG_IOCTL)) { - GLint imageX = 0; - GLint imageY = 0; - GLint blitX = t->image[face][hwlevel].x; - GLint blitY = t->image[face][hwlevel].y; - GLint blitWidth = t->image[face][hwlevel].width; - GLint blitHeight = t->image[face][hwlevel].height; - fprintf(stderr, " upload image: %d,%d at %d,%d\n", - imageWidth, imageHeight, imageX, imageY); - fprintf(stderr, " upload blit: %d,%d at %d,%d\n", - blitWidth, blitHeight, blitX, blitY); - fprintf(stderr, " blit ofs: 0x%07x level: %d/%d\n", - (GLuint) offset, hwlevel, level); - } - - t->image[face][hwlevel].data = texImage->Data; - - /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct. - * NOTE: we're always use a 1KB-wide blit and I8 texture format. - * We used to use 1, 2 and 4-byte texels and used to use the texture - * width to dictate the blit width - but that won't work for compressed - * textures. (Brian) - * NOTE: can't do that with texture tiling. (sroland) - */ - tex.offset = offset; - tex.image = &tmp; - /* copy (x,y,width,height,data) */ - memcpy(&tmp, &t->image[face][hwlevel], sizeof(tmp)); - - if (texImage->TexFormat->TexelBytes > 4) { - const int log2TexelBytes = - (3 + (texImage->TexFormat->TexelBytes >> 4)); - tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */ - tex.pitch = - MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / - 64, 1); - tex.height = imageHeight; - tex.width = imageWidth << log2TexelBytes; - tex.offset += (tmp.x << log2TexelBytes) & ~1023; - tmp.x = tmp.x % (1024 >> log2TexelBytes); - tmp.width = tmp.width << log2TexelBytes; - } else if (texImage->TexFormat->TexelBytes) { - /* use multi-byte upload scheme */ - tex.height = imageHeight; - tex.width = imageWidth; - switch (texImage->TexFormat->TexelBytes) { - case 1: - tex.format = RADEON_TXFORMAT_I8; - break; - case 2: - tex.format = RADEON_TXFORMAT_AI88; - break; - case 4: - tex.format = RADEON_TXFORMAT_ARGB8888; - break; - } - tex.pitch = - MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / - 64, 1); - tex.offset += tmp.x & ~1023; - tmp.x = tmp.x % 1024; - - if (t->tile_bits & R300_TXO_MICRO_TILE) { - /* need something like "tiled coordinates" ? */ - tmp.y = tmp.x / (tex.pitch * 128) * 2; - tmp.x = - tmp.x % (tex.pitch * 128) / 2 / - texImage->TexFormat->TexelBytes; - tex.pitch |= RADEON_DST_TILE_MICRO >> 22; - } else { - tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1); - } -#if 1 - if ((t->tile_bits & R300_TXO_MACRO_TILE) && - (texImage->Width * texImage->TexFormat->TexelBytes >= 256) - && ((!(t->tile_bits & R300_TXO_MICRO_TILE) - && (texImage->Height >= 8)) - || (texImage->Height >= 16))) { - /* weird: R200 disables macro tiling if mip width is smaller than 256 bytes, - OR if height is smaller than 8 automatically, but if micro tiling is active - the limit is height 16 instead ? */ - tex.pitch |= RADEON_DST_TILE_MACRO >> 22; - } -#endif - } else { - /* In case of for instance 8x8 texture (2x2 dxt blocks), - padding after the first two blocks is needed (only - with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */ - /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) - has 4 real pixels. Needed so the kernel module reads - the right amount of data. */ - tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */ - tex.pitch = (R300_BLIT_WIDTH_BYTES / 64); - tex.height = (imageHeight + 3) / 4; - tex.width = (imageWidth + 3) / 4; - if ((t->format & R300_TX_FORMAT_DXT1) == R300_TX_FORMAT_DXT1) { - tex.width *= 8; - } else { - tex.width *= 16; - } - } - - LOCK_HARDWARE(&rmesa->radeon); - do { - ret = - drmCommandWriteRead(rmesa->radeon.dri.fd, - DRM_RADEON_TEXTURE, &tex, - sizeof(drm_radeon_texture_t)); - if (ret) { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, - "DRM_RADEON_TEXTURE: again!\n"); - usleep(1); - } - } while (ret == -EAGAIN); - - UNLOCK_HARDWARE(&rmesa->radeon); - - if (ret) { - fprintf(stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret); - fprintf(stderr, " offset=0x%08x\n", offset); - fprintf(stderr, " image width=%d height=%d\n", - imageWidth, imageHeight); - fprintf(stderr, " blit width=%d height=%d data=%p\n", - t->image[face][hwlevel].width, - t->image[face][hwlevel].height, - t->image[face][hwlevel].data); - _mesa_exit(-1); - } -} - -/** - * Upload the texture images associated with texture \a t. This might - * require the allocation of texture memory. - * - * \param rmesa Context pointer - * \param t Texture to be uploaded - * \param face Cube map face to be uploaded. Zero for non-cube maps. - */ - -int r300UploadTexImages(r300ContextPtr rmesa, r300TexObjPtr t, GLuint face) -{ - const int numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - if (t->image_override) - return 0; - - if (RADEON_DEBUG & (DEBUG_TEXTURE | DEBUG_IOCTL)) { - fprintf(stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__, - (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, - t->base.totalSize, t->base.firstLevel, - t->base.lastLevel); - } - - if (t->base.totalSize == 0) - return 0; - - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "%s: Syncing\n", __FUNCTION__); - radeonFinish(rmesa->radeon.glCtx); - } - - LOCK_HARDWARE(&rmesa->radeon); - - if (t->base.memBlock == NULL) { - int heap; - - heap = driAllocateTexture(rmesa->texture_heaps, rmesa->nr_heaps, - (driTextureObject *) t); - if (heap == -1) { - UNLOCK_HARDWARE(&rmesa->radeon); - return -1; - } - - /* Set the base offset of the texture image */ - t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] - + t->base.memBlock->ofs; - t->offset = t->bufAddr; - - if (!(t->base.tObj->Image[0][0]->IsClientData)) { - /* hope it's safe to add that here... */ - t->offset |= t->tile_bits; - } - } - - /* Let the world know we've used this memory recently. - */ - driUpdateTextureLRU((driTextureObject *) t); - UNLOCK_HARDWARE(&rmesa->radeon); - - /* Upload any images that are new */ - if (t->base.dirty_images[face]) { - int i; - for (i = 0; i < numLevels; i++) { - if ((t->base. - dirty_images[face] & (1 << - (i + t->base.firstLevel))) != - 0) { - r300UploadSubImage(rmesa, t, i, 0, 0, - t->image[face][i].width, - t->image[face][i].height, - face); - } - } - t->base.dirty_images[face] = 0; - } - - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "%s: Syncing\n", __FUNCTION__); - radeonFinish(rmesa->radeon.glCtx); - } - - return 0; -} diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index e2329f04ec7..33673fa0b9c 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -48,6 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_ioctl.h" #include "radeon_ioctl.h" +#include "r300_mipmap_tree.h" #include "r300_tex.h" #include "r300_reg.h" @@ -148,8 +149,7 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) if (!tObj) return; - t = (r300TexObjPtr) tObj->DriverData; - + t = r300_tex_obj(tObj); switch (tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat) { case MESA_FORMAT_Z16: @@ -190,399 +190,228 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) /** - * Compute sizes and fill in offset and blit information for the given - * image (determined by \p face and \p level). - * - * \param curOffset points to the offset at which the image is to be stored - * and is updated by this function according to the size of the image. - */ -static void compute_tex_image_offset( - struct gl_texture_object *tObj, - GLuint face, - GLint level, - GLint* curOffset) -{ - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; - const struct gl_texture_image* texImage; - GLuint blitWidth = R300_BLIT_WIDTH_BYTES; - GLuint texelBytes; - GLuint size; - - texImage = tObj->Image[0][level + t->base.firstLevel]; - if (!texImage) - return; - - texelBytes = texImage->TexFormat->TexelBytes; - - /* find image size in bytes */ - if (texImage->IsCompressed) { - if ((t->format & R300_TX_FORMAT_DXT1) == - R300_TX_FORMAT_DXT1) { - // fprintf(stderr,"DXT 1 %d %08X\n", texImage->Width, t->format); - if ((texImage->Width + 3) < 8) /* width one block */ - size = texImage->CompressedSize * 4; - else if ((texImage->Width + 3) < 16) - size = texImage->CompressedSize * 2; - else - size = texImage->CompressedSize; - } else { - /* DXT3/5, 16 bytes per block */ - WARN_ONCE - ("DXT 3/5 suffers from multitexturing problems!\n"); - // fprintf(stderr,"DXT 3/5 %d\n", texImage->Width); - if ((texImage->Width + 3) < 8) - size = texImage->CompressedSize * 2; - else - size = texImage->CompressedSize; - } - } else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - size = - ((texImage->Width * texelBytes + - 63) & ~63) * texImage->Height; - blitWidth = 64 / texelBytes; - } else if (t->tile_bits & R300_TXO_MICRO_TILE) { - /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, - though the actual offset may be different (if texture is less than - 32 bytes width) to the untiled case */ - int w = (texImage->Width * texelBytes * 2 + 31) & ~31; - size = - (w * ((texImage->Height + 1) / 2)) * - texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - } else { - int w = (texImage->Width * texelBytes + 31) & ~31; - size = w * texImage->Height * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - } - assert(size > 0); - - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "w=%d h=%d d=%d tb=%d intFormat=%d\n", - texImage->Width, texImage->Height, - texImage->Depth, - texImage->TexFormat->TexelBytes, - texImage->InternalFormat); - - /* All images are aligned to a 32-byte offset */ - *curOffset = (*curOffset + 0x1f) & ~0x1f; - - if (texelBytes) { - /* fix x and y coords up later together with offset */ - t->image[face][level].x = *curOffset; - t->image[face][level].y = 0; - t->image[face][level].width = - MIN2(size / texelBytes, blitWidth); - t->image[face][level].height = - (size / texelBytes) / t->image[face][level].width; - } else { - t->image[face][level].x = *curOffset % R300_BLIT_WIDTH_BYTES; - t->image[face][level].y = *curOffset / R300_BLIT_WIDTH_BYTES; - t->image[face][level].width = - MIN2(size, R300_BLIT_WIDTH_BYTES); - t->image[face][level].height = size / t->image[face][level].width; - } - - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, - "level %d, face %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n", - level, face, texImage->Width, texImage->Height, - t->image[face][level].x, t->image[face][level].y, - t->image[face][level].width, t->image[face][level].height, - size, *curOffset); - - *curOffset += size; -} - - - -/** - * This function computes the number of bytes of storage needed for - * the given texture object (all mipmap levels, all cube faces). - * The \c image[face][level].x/y/width/height parameters for upload/blitting - * are computed here. \c filter, \c format, etc. will be set here - * too. + * Compute the cached hardware register values for the given texture object. * * \param rmesa Context pointer - * \param tObj GL texture object whose images are to be posted to - * hardware state. + * \param t the r300 texture object */ -static void r300SetTexImages(r300ContextPtr rmesa, - struct gl_texture_object *tObj) +static void setup_hardware_state(r300ContextPtr rmesa, r300TexObj *t) { - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; - const struct gl_texture_image *baseImage = - tObj->Image[0][tObj->BaseLevel]; - GLint curOffset; - GLint i, texelBytes; - GLint numLevels; - GLint log2Width, log2Height, log2Depth; - - /* Set the hardware texture format - */ + const struct gl_texture_image *firstImage = + t->base.Image[0][t->mt->firstLevel]; + if (!t->image_override - && VALID_FORMAT(baseImage->TexFormat->MesaFormat)) { - if (baseImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) { - r300SetDepthTexMode(tObj); + && VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + if (firstImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) { + r300SetDepthTexMode(&t->base); } else { - t->format = tx_table[baseImage->TexFormat->MesaFormat].format; + t->format = tx_table[firstImage->TexFormat->MesaFormat].format; } - t->filter |= tx_table[baseImage->TexFormat->MesaFormat].filter; + t->filter |= tx_table[firstImage->TexFormat->MesaFormat].filter; } else if (!t->image_override) { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); return; } - texelBytes = baseImage->TexFormat->TexelBytes; - - /* Compute which mipmap levels we really want to send to the hardware. - */ - driCalculateTextureFirstLastLevel((driTextureObject *) t); - log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2; - log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2; - log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2; - - numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); - - /* Calculate mipmap offsets and dimensions for blitting (uploading) - * The idea is that we lay out the mipmap levels within a block of - * memory organized as a rectangle of width BLIT_WIDTH_BYTES. - */ t->tile_bits = 0; - /* figure out if this texture is suitable for tiling. */ -#if 0 /* Disabled for now */ - if (texelBytes) { - if ((tObj->Target != GL_TEXTURE_RECTANGLE_NV) && - /* texrect might be able to use micro tiling too in theory? */ - (baseImage->Height > 1)) { - - /* allow 32 (bytes) x 1 mip (which will use two times the space - the non-tiled version would use) max if base texture is large enough */ - if ((numLevels == 1) || - (((baseImage->Width * texelBytes / - baseImage->Height) <= 32) - && (baseImage->Width * texelBytes > 64)) - || - ((baseImage->Width * texelBytes / - baseImage->Height) <= 16)) { - t->tile_bits |= R300_TXO_MICRO_TILE; - } - } - - if (tObj->Target != GL_TEXTURE_RECTANGLE_NV) { - /* we can set macro tiling even for small textures, they will be untiled anyway */ - t->tile_bits |= R300_TXO_MACRO_TILE; - } - } -#endif - - curOffset = 0; - - if (tObj->Target == GL_TEXTURE_CUBE_MAP) { - ASSERT(log2Width == log2Height); + if (t->base.Target == GL_TEXTURE_CUBE_MAP) t->format |= R300_TX_FORMAT_CUBIC_MAP; + if (t->base.Target == GL_TEXTURE_3D) + t->format |= R300_TX_FORMAT_3D; - for(i = 0; i < numLevels; i++) { - GLuint face; - for(face = 0; face < 6; face++) - compute_tex_image_offset(tObj, face, i, &curOffset); - } - } else { - if (tObj->Target == GL_TEXTURE_3D) - t->format |= R300_TX_FORMAT_3D; + t->size = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) + | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)) + | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT); - for (i = 0; i < numLevels; i++) - compute_tex_image_offset(tObj, 0, i, &curOffset); - } - - /* Align the total size of texture memory block. - */ - t->base.totalSize = - (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; - - t->size = - (((tObj->Image[0][t->base.firstLevel]->Width - - 1) << R300_TX_WIDTHMASK_SHIFT) - | ((tObj->Image[0][t->base.firstLevel]->Height - 1) << - R300_TX_HEIGHTMASK_SHIFT) - | ((tObj->Image[0][t->base.firstLevel]->DepthLog2) << - R300_TX_DEPTHMASK_SHIFT)) - | ((numLevels - 1) << R300_TX_MAX_MIP_LEVEL_SHIFT); - - t->pitch = 0; - - /* Only need to round to nearest 32 for textures, but the blitter - * requires 64-byte aligned pitches, and we may/may not need the - * blitter. NPOT only! - */ - if (baseImage->IsCompressed) { - t->pitch |= - (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); - } else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - unsigned int align = (64 / texelBytes) - 1; - t->pitch |= ((tObj->Image[0][t->base.firstLevel]->Width * - texelBytes) + 63) & ~(63); + if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { + unsigned int align = (64 / t->mt->bpp) - 1; t->size |= R300_TX_SIZE_TXPITCH_EN; if (!t->image_override) - t->pitch_reg = - (((tObj->Image[0][t->base.firstLevel]->Width) + - align) & ~align) - 1; - } else { - t->pitch |= - ((tObj->Image[0][t->base.firstLevel]->Width * - texelBytes) + 63) & ~(63); + t->pitch_reg = ((firstImage->Width + align) & ~align) - 1; } if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - if (tObj->Image[0][t->base.firstLevel]->Width > 2048) + if (firstImage->Width > 2048) t->pitch_reg |= R500_TXWIDTH_BIT11; - if (tObj->Image[0][t->base.firstLevel]->Height > 2048) + if (firstImage->Height > 2048) t->pitch_reg |= R500_TXHEIGHT_BIT11; } } -/* ================================================================ - * Texture unit state management - */ -static GLboolean r300EnableTexture2D(GLcontext * ctx, int unit) +static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, + GLuint numrows, GLuint rowsize) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; + assert(rowsize <= dststride); + assert(rowsize <= srcstride); - ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); - - if (t->base.dirty_images[0]) { - R300_FIREVERTICES(rmesa); - - r300SetTexImages(rmesa, tObj); - r300UploadTexImages(rmesa, (r300TexObjPtr) tObj->DriverData, 0); - if (!t->base.memBlock && !t->image_override) - return GL_FALSE; + if (rowsize == srcstride && rowsize == dststride) { + memcpy(dst, src, numrows*rowsize); + } else { + GLuint i; + for(i = 0; i < numrows; ++i) { + memcpy(dst, src, rowsize); + dst += dststride; + src += srcstride; + } } - - return GL_TRUE; } -static GLboolean r300EnableTexture3D(GLcontext * ctx, int unit) + +/** + * Ensure that the given image is stored in the given miptree from now on. + */ +static void migrate_image_to_miptree(r300_mipmap_tree *mt, r300_texture_image *image, int face, int level) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; + r300_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; + unsigned char *dest; - ASSERT(tObj->Target == GL_TEXTURE_3D); + assert(image->mt != mt); + assert(dstlvl->width == image->base.Width); + assert(dstlvl->height == image->base.Height); + assert(dstlvl->depth == image->base.Depth); - /* r300 does not support mipmaps for 3D textures. */ - if ((tObj->MinFilter != GL_NEAREST) && (tObj->MinFilter != GL_LINEAR)) { - return GL_FALSE; - } + radeon_bo_map(mt->bo, GL_TRUE); + dest = mt->bo->ptr + dstlvl->faces[face].offset; - if (t->base.dirty_images[0]) { - R300_FIREVERTICES(rmesa); - r300SetTexImages(rmesa, tObj); - r300UploadTexImages(rmesa, (r300TexObjPtr) tObj->DriverData, 0); - if (!t->base.memBlock) - return GL_FALSE; - } + if (image->mt) { + /* Format etc. should match, so we really just need a memcpy(). + * In fact, that memcpy() could be done by the hardware in many + * cases, provided that we have a proper memory manager. + */ + r300_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; - return GL_TRUE; -} + assert(srclvl->size == dstlvl->size); + assert(srclvl->rowstride == dstlvl->rowstride); -static GLboolean r300EnableTextureCube(GLcontext * ctx, int unit) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; - GLuint face; - - ASSERT(tObj->Target == GL_TEXTURE_CUBE_MAP); - - if (t->base.dirty_images[0] || t->base.dirty_images[1] || - t->base.dirty_images[2] || t->base.dirty_images[3] || - t->base.dirty_images[4] || t->base.dirty_images[5]) { - /* flush */ - R300_FIREVERTICES(rmesa); - /* layout memory space, once for all faces */ - r300SetTexImages(rmesa, tObj); - } + radeon_bo_map(image->mt->bo, GL_FALSE); + memcpy(dest, + image->mt->bo->ptr + srclvl->faces[face].offset, + dstlvl->size); + radeon_bo_unmap(image->mt->bo); - /* upload (per face) */ - for (face = 0; face < 6; face++) { - if (t->base.dirty_images[face]) { - r300UploadTexImages(rmesa, - (r300TexObjPtr) tObj->DriverData, - face); - } - } + r300_miptree_unreference(image->mt); + } else { + uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; - if (!t->base.memBlock) { - /* texmem alloc failed, use s/w fallback */ - return GL_FALSE; + if (mt->tilebits) + WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); + + copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, + image->base.Height * image->base.Depth, srcrowstride); + + _mesa_free_texmemory(image->base.Data); + image->base.Data = 0; } - return GL_TRUE; + radeon_bo_unmap(mt->bo); + + image->mt = mt; + image->mtface = face; + image->mtlevel = level; + r300_miptree_reference(image->mt); } -static GLboolean r300EnableTextureRect(GLcontext * ctx, int unit) + +/** + * Ensure the given texture is ready for rendering. + * + * Mostly this means populating the texture object's mipmap tree. + */ +static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; + r300TexObj *t = r300_tex_obj(texObj); + r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[0][texObj->BaseLevel]); + int face, level; + + if (t->validated) + return GL_TRUE; - ASSERT(tObj->Target == GL_TEXTURE_RECTANGLE_NV); + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj); - if (t->base.dirty_images[0]) { - R300_FIREVERTICES(rmesa); + if (baseimage->base.Border > 0) + return GL_FALSE; - r300SetTexImages(rmesa, tObj); - r300UploadTexImages(rmesa, (r300TexObjPtr) tObj->DriverData, 0); - if (!t->base.memBlock && !t->image_override && - !rmesa->prefer_gart_client_texturing) + /* Ensure a matching miptree exists. + * + * Differing mipmap trees can result when the app uses TexImage to + * change texture dimensions. + * + * Prefer to use base image's miptree if it + * exists, since that most likely contains more valid data (remember + * that the base level is usually significantly larger than the rest + * of the miptree, so cubemaps are the only possible exception). + */ + if (baseimage->mt && + baseimage->mt != t->mt && + r300_miptree_matches_texture(baseimage->mt, &t->base)) { + r300_miptree_unreference(t->mt); + t->mt = baseimage->mt; + r300_miptree_reference(t->mt); + } else if (t->mt && !r300_miptree_matches_texture(t->mt, &t->base)) { + r300_miptree_unreference(t->mt); + t->mt = 0; + } + + if (!t->mt) { + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, " Allocate new miptree\n"); + r300_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel); + if (!t->mt) { + _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree"); return GL_FALSE; + } + } + + /* Ensure all images are stored in the single main miptree */ + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { + r300_texture_image *image = get_r300_texture_image(texObj->Image[face][level]); + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, " face %i, level %i... ", face, level); + if (t->mt == image->mt) { + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "OK\n"); + continue; + } + + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "migrating\n"); + migrate_image_to_miptree(t->mt, image, face, level); + } } + /* Configure the hardware registers (more precisely, the cached version + * of the hardware registers). */ + setup_hardware_state(rmesa, t); + + t->validated = GL_TRUE; return GL_TRUE; } -static GLboolean r300UpdateTexture(GLcontext * ctx, int unit) + +/** + * Ensure all enabled and complete textures are uploaded. + */ +void r300ValidateTextures(GLcontext * ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData; + int i; - /* Fallback if there's a texture border */ - if (tObj->Image[0][tObj->BaseLevel]->Border > 0) - return GL_FALSE; + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + if (!ctx->Texture.Unit[i]._ReallyEnabled) + continue; - /* Update state if this is a different texture object to last - * time. - */ - if (rmesa->state.texture.unit[unit].texobj != t) { - if (rmesa->state.texture.unit[unit].texobj != NULL) { - /* The old texture is no longer bound to this texture unit. - * Mark it as such. - */ - - rmesa->state.texture.unit[unit].texobj->base.bound &= - ~(1 << unit); + if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { + _mesa_warning(ctx, + "failed to validate texture for unit %d.\n", + i); } - - rmesa->state.texture.unit[unit].texobj = t; - t->base.bound |= (1 << unit); - driUpdateTextureLRU((driTextureObject *) t); /* XXX: should be locked! */ } - - return !t->border_fallback; } void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, @@ -591,20 +420,18 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, r300ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); - r300TexObjPtr t; + r300TexObjPtr t = r300_tex_obj(tObj); uint32_t pitch_val; if (!tObj) return; - t = (r300TexObjPtr) tObj->DriverData; - t->image_override = GL_TRUE; if (!offset) return; - t->offset = offset; + t->override_offset = offset; t->pitch_reg &= (1 << 13) -1; pitch_val = pitch; @@ -630,39 +457,3 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, t->pitch_reg |= pitch_val; } - -static GLboolean r300UpdateTextureUnit(GLcontext * ctx, int unit) -{ - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - - if (texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT)) { - return (r300EnableTextureRect(ctx, unit) && - r300UpdateTexture(ctx, unit)); - } else if (texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT)) { - return (r300EnableTexture2D(ctx, unit) && - r300UpdateTexture(ctx, unit)); - } else if (texUnit->_ReallyEnabled & (TEXTURE_3D_BIT)) { - return (r300EnableTexture3D(ctx, unit) && - r300UpdateTexture(ctx, unit)); - } else if (texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT)) { - return (r300EnableTextureCube(ctx, unit) && - r300UpdateTexture(ctx, unit)); - } else if (texUnit->_ReallyEnabled) { - return GL_FALSE; - } else { - return GL_TRUE; - } -} - -void r300UpdateTextureState(GLcontext * ctx) -{ - int i; - - for (i = 0; i < 8; i++) { - if (!r300UpdateTextureUnit(ctx, i)) { - _mesa_warning(ctx, - "failed to update texture state for unit %d.\n", - i); - } - } -} diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 5267fe9a774..e62cf46d1e4 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" #include "swrast/swrast.h" +#include "radeon_buffer.h" #include "radeon_screen.h" #include "radeon_ioctl.h" #include "radeon_macros.h" @@ -57,6 +58,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "vblank.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ +#include "drirenderbuffer.h" #define DRIVER_DATE "20060815" @@ -258,6 +260,54 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, } } +static void +radeon_make_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + int size = 4096*4096*4; + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch; + } +} + + /* Force the context `c' to be the current context and associate with it * buffer `b'. */ @@ -265,51 +315,57 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv) { - if (driContextPriv) { - radeonContextPtr radeon = - (radeonContextPtr) driContextPriv->driverPrivate; + radeonContextPtr radeon; + GLframebuffer *dfb, *rfb; + if (!driContextPriv) { if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, - radeon->glCtx); - - if (radeon->dri.drawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = - (radeon->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&radeon-> - optionCache) - : VBLANK_FLAG_NO_IRQ; + fprintf(stderr, "%s ctx is null\n", __FUNCTION__); + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; + } - driDrawableInitVBlank(driDrawPriv); - } - } + radeon = (radeonContextPtr) driContextPriv->driverPrivate; + dfb = driDrawPriv->driverPrivate; + rfb = driReadPriv->driverPrivate; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); - radeon->dri.readable = driReadPriv; + driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); + if (driReadPriv != driDrawPriv) + driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - if (radeon->dri.drawable != driDrawPriv || - radeon->lastStamp != driDrawPriv->lastStamp) { - radeon->dri.drawable = driDrawPriv; + radeon_make_renderbuffer_current(radeon, dfb); + + _mesa_make_current(radeon->glCtx, dfb, rfb); + + if (radeon->dri.drawable != driDrawPriv) { + if (driDrawPriv->swap_interval == (unsigned)-1) { + driDrawPriv->vblFlags = + (radeon->radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; - radeonSetCliprects(radeon); - r300UpdateViewportOffset(radeon->glCtx); + driDrawableInitVBlank(driDrawPriv); } + } - _mesa_make_current(radeon->glCtx, - (GLframebuffer *) driDrawPriv-> - driverPrivate, - (GLframebuffer *) driReadPriv-> - driverPrivate); + radeon->dri.readable = driReadPriv; - _mesa_update_state(radeon->glCtx); + if (radeon->dri.drawable != driDrawPriv || + radeon->lastStamp != driDrawPriv->lastStamp) { + radeon->dri.drawable = driDrawPriv; - radeonUpdatePageFlipping(radeon); - } else { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current(0, 0, 0); + radeonSetCliprects(radeon); + r300UpdateViewportOffset(radeon->glCtx); } + _mesa_update_state(radeon->glCtx); + + radeonUpdatePageFlipping(radeon); + if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "End %s\n", __FUNCTION__); return GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index 47cbc22a725..5658df7d1b3 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -132,12 +132,13 @@ struct radeon_scissor_state { struct radeon_colorbuffer_state { GLuint clear; - GLint drawOffset, drawPitch; + struct radeon_renderbuffer *rrb; }; struct radeon_state { struct radeon_colorbuffer_state color; struct radeon_scissor_state scissor; + struct radeon_renderbuffer *depth_buffer; }; /** diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.c b/src/mesa/drivers/dri/r300/radeon_ioctl.c index 36502eb42de..c8d6bf99bc7 100644 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.c +++ b/src/mesa/drivers/dri/r300/radeon_ioctl.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r300_context.h" #include "radeon_ioctl.h" +#include "radeon_buffer.h" #include "r300_ioctl.h" #include "r300_state.h" #include "radeon_reg.h" @@ -171,7 +172,7 @@ void radeonCopyBuffer(__DRIdrawablePrivate * dPriv, assert(dPriv->driContextPriv->driverPrivate); radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - + if (RADEON_DEBUG & DEBUG_IOCTL) { fprintf(stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)radeon->glCtx); @@ -261,6 +262,8 @@ void radeonPageFlip(__DRIdrawablePrivate * dPriv) GLint ret; GLboolean missed_target; __DRIscreenPrivate *psp = dPriv->driScreenPriv; + GLframebuffer *fb = dPriv->driverPrivate; + struct radeon_renderbuffer *rrb; assert(dPriv); assert(dPriv->driContextPriv); @@ -268,6 +271,8 @@ void radeonPageFlip(__DRIdrawablePrivate * dPriv) radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (RADEON_DEBUG & DEBUG_IOCTL) { fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, radeon->sarea->pfCurrentPage); @@ -315,32 +320,10 @@ void radeonPageFlip(__DRIdrawablePrivate * dPriv) radeon->swap_count++; (void)(*psp->systemTime->getUST) (&radeon->swap_ust); - driFlipRenderbuffers(radeon->glCtx->WinSysDrawBuffer, + driFlipRenderbuffers(radeon->glCtx->WinSysDrawBuffer, radeon->sarea->pfCurrentPage); - if (radeon->sarea->pfCurrentPage == 1) { - radeon->state.color.drawOffset = radeon->radeonScreen->frontOffset; - radeon->state.color.drawPitch = radeon->radeonScreen->frontPitch; - } else { - radeon->state.color.drawOffset = radeon->radeonScreen->backOffset; - radeon->state.color.drawPitch = radeon->radeonScreen->backPitch; - } - - if (IS_R300_CLASS(radeon->radeonScreen)) { - r300ContextPtr r300 = (r300ContextPtr)radeon; - R300_STATECHANGE(r300, cb); - r300->hw.cb.cmd[R300_CB_OFFSET] = r300->radeon.state.color.drawOffset + - r300->radeon.radeonScreen->fbLocation; - r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.state.color.drawPitch; - - if (r300->radeon.radeonScreen->cpp == 4) - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_ARGB8888; - else - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_FORMAT_RGB565; - - if (r300->radeon.sarea->tiling_enabled) - r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_TILE_ENABLE; - } + radeon->state.color.rrb = rrb; } void radeonWaitForIdleLocked(radeonContextPtr radeon) @@ -391,6 +374,7 @@ void radeonFinish(GLcontext * ctx) radeonEmitIrqLocked(radeon); UNLOCK_HARDWARE(radeon); radeonWaitIrq(radeon); - } else + } else { radeonWaitForIdle(radeon); + } } diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c index 4f47afd5dc6..bef8db1d0f4 100644 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ b/src/mesa/drivers/dri/r300/radeon_lock.c @@ -59,11 +59,11 @@ int prevLockLine = 0; void radeonUpdatePageFlipping(radeonContextPtr rmesa) { int use_back; + __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; + GLframebuffer *fb = drawable->driverPrivate; rmesa->doPageFlip = rmesa->sarea->pfState; if (rmesa->glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); r300UpdateDrawBuffer(rmesa->glCtx); } @@ -72,16 +72,12 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) BUFFER_BACK_LEFT) : 1; use_back ^= (rmesa->sarea->pfCurrentPage == 1); - if (use_back) { - rmesa->state.color.drawOffset = - rmesa->radeonScreen->backOffset; - rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch; - } else { - rmesa->state.color.drawOffset = - rmesa->radeonScreen->frontOffset; - rmesa->state.color.drawPitch = - rmesa->radeonScreen->frontPitch; - } + if (use_back) + rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + else + rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + + rmesa->state.depth_buffer = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; } /* Update the hardware state. This is called if another context has @@ -98,7 +94,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) __DRIdrawablePrivate *const readable = rmesa->dri.readable; __DRIscreenPrivate *sPriv = rmesa->dri.screen; drm_radeon_sarea_t *sarea = rmesa->sarea; - r300ContextPtr r300 = (r300ContextPtr) rmesa; assert(drawable != NULL); @@ -125,12 +120,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) } if (sarea->ctx_owner != rmesa->dri.hwContext) { - int i; - sarea->ctx_owner = rmesa->dri.hwContext; - for (i = 0; i < r300->nr_heaps; i++) { - DRI_AGE_TEXTURES(r300->texture_heaps[i]); - } + radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); } rmesa->lost_context = GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c index 16f9fb99e67..b12b19f24e1 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -48,7 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "radeon_span.h" -#include "drirenderbuffer.h" +#include "radeon_buffer.h" #define DBG 0 @@ -58,21 +58,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * information. */ #define LOCAL_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ + const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ - GLubyte *buf = (GLubyte *) drb->flippedData \ - + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \ - GLuint p; \ - (void) p; + GLubyte *buf = (GLubyte *) ((char*)rrb->bo->ptr) \ + + (dPriv->y * rrb->pitch + dPriv->x) * rrb->cpp; \ + GLuint p; \ + (void)p; #define LOCAL_DEPTH_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ + const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ GLuint xo = dPriv->x; \ GLuint yo = dPriv->y; \ - GLubyte *buf = (GLubyte *) drb->Base.Data; + GLubyte *buf = (GLubyte *) rrb->bo->ptr; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -93,7 +93,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) +#define GET_PTR(X,Y) (buf + ((Y) * rrb->pitch + (X)) * 2) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -103,7 +103,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) +#define GET_PTR(X,Y) (buf + ((Y) * rrb->pitch + (X)) * 4) #include "spantmp2.h" /* ================================================================ @@ -120,10 +120,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * too... */ -static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y) +static GLuint radeon_mba_z32(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) { - GLuint pitch = drb->pitch; - if (drb->depthHasSurface) { + GLuint pitch = rrb->pitch; + if (rrb->depthHasSurface) { return 4 * (x + y * pitch); } else { GLuint ba, address = 0; /* a[0..1] = 0 */ @@ -148,10 +149,10 @@ static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y) } static INLINE GLuint -radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) +radeon_mba_z16(const struct radeon_renderbuffer *rrb, GLint x, GLint y) { - GLuint pitch = drb->pitch; - if (drb->depthHasSurface) { + GLuint pitch = rrb->pitch; + if (rrb->depthHasSurface) { return 2 * (x + y * pitch); } else { GLuint ba, address = 0; /* a[0] = 0 */ @@ -175,10 +176,10 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d; + *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo )) = d; #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )); + d = *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo )); #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -193,7 +194,7 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ @@ -202,7 +203,7 @@ do { \ #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ @@ -213,12 +214,12 @@ do { \ #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ + d = (*(GLuint *)(buf + radeon_mba_z32( rrb, _x + xo, \ _y + yo )) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ + d = *(GLuint *)(buf + radeon_mba_z32( rrb, _x + xo, \ _y + yo )) & 0x00ffffff; #endif @@ -234,7 +235,7 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ @@ -243,7 +244,7 @@ do { \ #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ @@ -254,14 +255,14 @@ do { \ #ifdef COMPILE_R300 #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ GLuint tmp = *(GLuint *)(buf + offset); \ d = tmp & 0x000000ff; \ } while (0) #else #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ GLuint tmp = *(GLuint *)(buf + offset); \ d = (tmp & 0xff000000) >> 24; \ } while (0) @@ -270,6 +271,24 @@ do { \ #define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" +static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) +{ + struct radeon_renderbuffer *rrb = (void*)rb; + + if (rrb->bo) { + radeon_bo_map(rrb->bo, write); + } +} + +static void unmap_buffer(struct gl_renderbuffer *rb) +{ + struct radeon_renderbuffer *rrb = (void*)rb; + + if (rrb->bo) { + radeon_bo_unmap(rrb->bo); + } +} + /* Move locking out to get reasonable span performance (10x better * than doing this in HW_LOCK above). WaitForIdle() is the main * culprit. @@ -278,45 +297,63 @@ do { \ static void radeonSpanRenderStart(GLcontext * ctx) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + int i; #ifdef COMPILE_R300 r300ContextPtr r300 = (r300ContextPtr) rmesa; R300_FIREVERTICES(r300); #else RADEON_FIREVERTICES(rmesa); #endif - LOCK_HARDWARE(rmesa); - radeonWaitForIdleLocked(rmesa); - /* Read the first pixel in the frame buffer. This should - * be a noop, right? In fact without this conform fails as reading - * from the framebuffer sometimes produces old results -- the - * on-card read cache gets mixed up and doesn't notice that the - * framebuffer has been updated. - * - * Note that we should probably be reading some otherwise unused - * region of VRAM, otherwise we might get incorrect results when - * reading pixels from the top left of the screen. - * - * I found this problem on an R420 with glean's texCube test. - * Note that the R200 span code also *writes* the first pixel in the - * framebuffer, but I've found this to be unnecessary. - * -- Nicolai Hähnle, June 2008 - */ - { - int p; - driRenderbuffer *drb = - (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0]; - volatile int *buf = - (volatile int *)(rmesa->dri.screen->pFB + drb->offset); - p = *buf; + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); } + + /* color draw buffers */ + for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { + map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); + } + + map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); + + if (ctx->DrawBuffer->_DepthBuffer) { + map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); + } + if (ctx->DrawBuffer->_StencilBuffer) + map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); + + /* The locking and wait for idle should really only be needed in classic mode. + * In a future memory manager based implementation, this should become + * unnecessary due to the fact that mapping our buffers, textures, etc. + * should implicitly wait for any previous rendering commands that must + * be waited on. */ + LOCK_HARDWARE(rmesa); + radeonWaitForIdleLocked(rmesa); } static void radeonSpanRenderFinish(GLcontext * ctx) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + int i; _swrast_flush(ctx); UNLOCK_HARDWARE(rmesa); + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + + /* color draw buffers */ + for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) + unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); + + unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); + + if (ctx->DrawBuffer->_DepthBuffer) + unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); + if (ctx->DrawBuffer->_StencilBuffer) + unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); } void radeonInitSpanFuncs(GLcontext * ctx) @@ -330,20 +367,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis) +void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 - && vis->blueBits == 5) { - radeonInitPointers_RGB565(&drb->Base); - } else { - radeonInitPointers_ARGB8888(&drb->Base); - } - } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) { - radeonInitDepthPointers_z16(&drb->Base); - } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) { - radeonInitDepthPointers_z24_s8(&drb->Base); - } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&drb->Base); + if (rrb->base.InternalFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); + } else if (rrb->base.InternalFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); } } diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c index c401da6c544..024190317b8 100644 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ b/src/mesa/drivers/dri/r300/radeon_state.c @@ -223,14 +223,6 @@ void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state) void radeonInitState(radeonContextPtr radeon) { radeon->Fallback = 0; - - if (radeon->glCtx->Visual.doubleBufferMode && radeon->sarea->pfCurrentPage == 0) { - radeon->state.color.drawOffset = radeon->radeonScreen->backOffset; - radeon->state.color.drawPitch = radeon->radeonScreen->backPitch; - } else { - radeon->state.color.drawOffset = radeon->radeonScreen->frontOffset; - radeon->state.color.drawPitch = radeon->radeonScreen->frontPitch; - } } diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c new file mode 100644 index 00000000000..580ff374c77 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -0,0 +1,718 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Dave Airlie + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Dave Airlie + * Jérôme Glisse + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "xf86drm.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_bo.h" +#include "radeon_bo_legacy.h" +#include "radeon_ioctl.h" +#include "texmem.h" + +struct bo_legacy { + struct radeon_bo base; + driTextureObject tobj_base; + int map_count; + uint32_t pending; + int is_pending; + int validated; + int static_bo; + int got_dri_texture_obj; + int dirty; + uint32_t offset; + driTextureObject dri_texture_obj; + void *ptr; + struct bo_legacy *next, *prev; + struct bo_legacy *pnext, *pprev; +}; + +struct bo_manager_legacy { + struct radeon_bo_manager base; + unsigned nhandle; + unsigned nfree_handles; + unsigned cfree_handles; + uint32_t current_age; + struct bo_legacy bos; + struct bo_legacy pending_bos; + uint32_t fb_location; + uint32_t texture_offset; + unsigned dma_alloc_size; + unsigned cpendings; + driTextureObject texture_swapped; + driTexHeap *texture_heap; + struct radeon_screen *screen; + unsigned *free_handles; +}; + +static void bo_legacy_tobj_destroy(void *data, driTextureObject *t) +{ + struct bo_legacy *bo_legacy; + + bo_legacy = (struct bo_legacy*)((char*)t)-sizeof(struct radeon_bo); + bo_legacy->got_dri_texture_obj = 0; + bo_legacy->validated = 0; +} + +static int legacy_new_handle(struct bo_manager_legacy *bom, uint32_t *handle) +{ + uint32_t tmp; + + *handle = 0; + if (bom->nhandle == 0xFFFFFFFF) { + return -EINVAL; + } + if (bom->cfree_handles > 0) { + tmp = bom->free_handles[--bom->cfree_handles]; + while (!bom->free_handles[bom->cfree_handles - 1]) { + bom->cfree_handles--; + if (bom->cfree_handles <= 0) { + bom->cfree_handles = 0; + } + } + } else { + bom->cfree_handles = 0; + tmp = bom->nhandle++; + } + assert(tmp); + *handle = tmp; + return 0; +} + +static int legacy_free_handle(struct bo_manager_legacy *bom, uint32_t handle) +{ + uint32_t *handles; + + if (!handle) { + return 0; + } + if (handle == (bom->nhandle - 1)) { + int i; + + bom->nhandle--; + for (i = bom->cfree_handles - 1; i >= 0; i--) { + if (bom->free_handles[i] == (bom->nhandle - 1)) { + bom->nhandle--; + bom->free_handles[i] = 0; + } + } + while (!bom->free_handles[bom->cfree_handles - 1]) { + bom->cfree_handles--; + if (bom->cfree_handles <= 0) { + bom->cfree_handles = 0; + } + } + return 0; + } + if (bom->cfree_handles < bom->nfree_handles) { + bom->free_handles[bom->cfree_handles++] = handle; + return 0; + } + bom->nfree_handles += 0x100; + handles = (uint32_t*)realloc(bom->free_handles, bom->nfree_handles * 4); + if (handles == NULL) { + bom->nfree_handles -= 0x100; + return -ENOMEM; + } + bom->free_handles = handles; + bom->free_handles[bom->cfree_handles++] = handle; + return 0; +} + +static void legacy_get_current_age(struct bo_manager_legacy *boml) +{ + drm_radeon_getparam_t gp; + int r; + + gp.param = RADEON_PARAM_LAST_CLEAR; + gp.value = (int *)&boml->current_age; + r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (r) { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); + exit(1); + } +} + +static int legacy_is_pending(struct radeon_bo *bo) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + if (bo_legacy->is_pending <= 0) { + bo_legacy->is_pending = 0; + return 0; + } + if (boml->current_age >= bo_legacy->pending) { + if (boml->pending_bos.pprev == bo_legacy) { + boml->pending_bos.pprev = bo_legacy->pprev; + } + bo_legacy->pprev->pnext = bo_legacy->pnext; + if (bo_legacy->pnext) { + bo_legacy->pnext->pprev = bo_legacy->pprev; + } + while (bo_legacy->is_pending--) { + radeon_bo_unref(bo); + } + bo_legacy->is_pending = 0; + boml->cpendings--; + return 0; + } + return 1; +} + +static int legacy_wait_pending(struct radeon_bo *bo) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + if (!bo_legacy->is_pending) { + return 0; + } + /* FIXME: lockup and userspace busy looping that's all the folks */ + legacy_get_current_age(boml); + while (legacy_is_pending(bo)) { + usleep(10); + legacy_get_current_age(boml); + } + return 0; +} + +static void legacy_track_pending(struct bo_manager_legacy *boml) +{ + struct bo_legacy *bo_legacy; + struct bo_legacy *next; + + legacy_get_current_age(boml); + bo_legacy = boml->pending_bos.pnext; + while (bo_legacy) { + next = bo_legacy->pnext; + if (legacy_is_pending(&(bo_legacy->base))) { + } + bo_legacy = next; + } +} + +static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, + uint32_t size, + uint32_t alignment, + uint32_t flags) +{ + struct bo_legacy *bo_legacy; + + bo_legacy = (struct bo_legacy*)calloc(1, sizeof(struct bo_legacy)); + if (bo_legacy == NULL) { + return NULL; + } + bo_legacy->base.bom = (struct radeon_bo_manager*)boml; + bo_legacy->base.handle = 0; + bo_legacy->base.size = size; + bo_legacy->base.alignment = alignment; + bo_legacy->base.flags = flags; + bo_legacy->base.ptr = NULL; + bo_legacy->map_count = 0; + bo_legacy->next = NULL; + bo_legacy->prev = NULL; + bo_legacy->got_dri_texture_obj = 0; + bo_legacy->pnext = NULL; + bo_legacy->pprev = NULL; + bo_legacy->next = boml->bos.next; + bo_legacy->prev = &boml->bos; + boml->bos.next = bo_legacy; + if (bo_legacy->next) { + bo_legacy->next->prev = bo_legacy; + } + return bo_legacy; +} + +static int bo_dma_alloc(struct radeon_bo *bo) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + drm_radeon_mem_alloc_t alloc; + unsigned size; + int base_offset; + int r; + + /* align size on 4Kb */ + size = (((4 * 1024) - 1) + bo->size) & ~((4 * 1024) - 1); + alloc.region = RADEON_MEM_REGION_GART; + alloc.alignment = bo_legacy->base.alignment; + alloc.size = size; + alloc.region_offset = &base_offset; + r = drmCommandWriteRead(bo->bom->fd, + DRM_RADEON_ALLOC, + &alloc, + sizeof(alloc)); + if (r) { + /* ptr is set to NULL if dma allocation failed */ + bo_legacy->ptr = NULL; + exit(0); + return r; + } + bo_legacy->ptr = boml->screen->gartTextures.map + base_offset; + bo_legacy->offset = boml->screen->gart_texture_offset + base_offset; + bo->size = size; + boml->dma_alloc_size += size; + return 0; +} + +static int bo_dma_free(struct radeon_bo *bo) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + drm_radeon_mem_free_t memfree; + int r; + + if (bo_legacy->ptr == NULL) { + /* ptr is set to NULL if dma allocation failed */ + return 0; + } + legacy_get_current_age(boml); + memfree.region = RADEON_MEM_REGION_GART; + memfree.region_offset = bo_legacy->offset; + memfree.region_offset -= boml->screen->gart_texture_offset; + r = drmCommandWrite(boml->base.fd, + DRM_RADEON_FREE, + &memfree, + sizeof(memfree)); + if (r) { + fprintf(stderr, "Failed to free bo[%p] at %08x\n", + &bo_legacy->base, memfree.region_offset); + fprintf(stderr, "ret = %s\n", strerror(-r)); + return r; + } + boml->dma_alloc_size -= bo_legacy->base.size; + return 0; +} + +static void bo_free(struct bo_legacy *bo_legacy) +{ + struct bo_manager_legacy *boml; + + if (bo_legacy == NULL) { + return; + } + boml = (struct bo_manager_legacy *)bo_legacy->base.bom; + bo_legacy->prev->next = bo_legacy->next; + if (bo_legacy->next) { + bo_legacy->next->prev = bo_legacy->prev; + } + if (!bo_legacy->static_bo) { + legacy_free_handle(boml, bo_legacy->base.handle); + if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) { + /* dma buffers */ + bo_dma_free(&bo_legacy->base); + } else { + /* free backing store */ + free(bo_legacy->ptr); + } + } + memset(bo_legacy, 0 , sizeof(struct bo_legacy)); + free(bo_legacy); +} + +static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t flags) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom; + struct bo_legacy *bo_legacy; + int r; + + if (handle) { + bo_legacy = boml->bos.next; + while (bo_legacy) { + if (bo_legacy->base.handle == handle) { + radeon_bo_ref(&(bo_legacy->base)); + return (struct radeon_bo*)bo_legacy; + } + bo_legacy = bo_legacy->next; + } + return NULL; + } + + bo_legacy = bo_allocate(boml, size, alignment, flags); + bo_legacy->static_bo = 0; + r = legacy_new_handle(boml, &bo_legacy->base.handle); + if (r) { + bo_free(bo_legacy); + return NULL; + } + if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) { + legacy_track_pending(boml); + /* dma buffers */ + r = bo_dma_alloc(&(bo_legacy->base)); + if (r) { + fprintf(stderr, "Ran out of GART memory (for %d)!\n", size); + fprintf(stderr, "Please consider adjusting GARTSize option.\n"); + bo_free(bo_legacy); + exit(-1); + return NULL; + } + } else { + bo_legacy->ptr = malloc(bo_legacy->base.size); + if (bo_legacy->ptr == NULL) { + bo_free(bo_legacy); + return NULL; + } + } + radeon_bo_ref(&(bo_legacy->base)); + return (struct radeon_bo*)bo_legacy; +} + +static void bo_ref(struct radeon_bo *bo) +{ +} + +static void bo_unref(struct radeon_bo *bo) +{ + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + if (bo->cref <= 0) { + bo_legacy->prev->next = bo_legacy->next; + if (bo_legacy->next) { + bo_legacy->next->prev = bo_legacy->prev; + } + if (!bo_legacy->is_pending) { + bo_free(bo_legacy); + } + } +} + +static int bo_map(struct radeon_bo *bo, int write) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + legacy_wait_pending(bo); + bo_legacy->validated = 0; + bo_legacy->dirty = 1; + bo_legacy->map_count++; + bo->ptr = bo_legacy->ptr; + /* Read the first pixel in the frame buffer. This should + * be a noop, right? In fact without this conform fails as reading + * from the framebuffer sometimes produces old results -- the + * on-card read cache gets mixed up and doesn't notice that the + * framebuffer has been updated. + * + * Note that we should probably be reading some otherwise unused + * region of VRAM, otherwise we might get incorrect results when + * reading pixels from the top left of the screen. + * + * I found this problem on an R420 with glean's texCube test. + * Note that the R200 span code also *writes* the first pixel in the + * framebuffer, but I've found this to be unnecessary. + * -- Nicolai Hähnle, June 2008 + */ + { + int p; + volatile int *buf = (int*)boml->screen->driScreen->pFB; + p = *buf; + } + + return 0; +} + +static int bo_unmap(struct radeon_bo *bo) +{ + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + if (--bo_legacy->map_count > 0) { + return 0; + } + bo->ptr = NULL; + return 0; +} + +static struct radeon_bo_funcs bo_legacy_funcs = { + bo_open, + bo_ref, + bo_unref, + bo_map, + bo_unmap +}; + +static int bo_vram_validate(struct radeon_bo *bo, + uint32_t *soffset, + uint32_t *eoffset) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + int r; + + if (!bo_legacy->got_dri_texture_obj) { + make_empty_list(&bo_legacy->dri_texture_obj); + bo_legacy->dri_texture_obj.totalSize = bo->size; + r = driAllocateTexture(&boml->texture_heap, 1, + &bo_legacy->dri_texture_obj); + if (r) { + uint8_t *segfault=NULL; + fprintf(stderr, "Ouch! vram_validate failed %d\n", r); + *segfault=1; + return -1; + } + bo_legacy->offset = boml->texture_offset + + bo_legacy->dri_texture_obj.memBlock->ofs; + bo_legacy->got_dri_texture_obj = 1; + bo_legacy->dirty = 1; + } + if (bo_legacy->dirty) { + /* Copy to VRAM using a blit. + * All memory is 4K aligned. We're using 1024 pixels wide blits. + */ + drm_radeon_texture_t tex; + drm_radeon_tex_image_t tmp; + int ret; + + tex.offset = bo_legacy->offset; + tex.image = &tmp; + assert(!(tex.offset & 1023)); + + tmp.x = 0; + tmp.y = 0; + if (bo->size < 4096) { + tmp.width = (bo->size + 3) / 4; + tmp.height = 1; + } else { + tmp.width = 1024; + tmp.height = (bo->size + 4095) / 4096; + } + tmp.data = bo_legacy->ptr; + tex.format = RADEON_TXFORMAT_ARGB8888; + tex.width = tmp.width; + tex.height = tmp.height; + tex.pitch = MAX2(tmp.width / 16, 1); + do { + ret = drmCommandWriteRead(bo->bom->fd, + DRM_RADEON_TEXTURE, + &tex, + sizeof(drm_radeon_texture_t)); + if (ret) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n"); + usleep(1); + } + } while (ret == -EAGAIN); + bo_legacy->dirty = 0; + } + return 0; +} + +int radeon_bo_legacy_validate(struct radeon_bo *bo, + uint32_t *soffset, + uint32_t *eoffset) +{ + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + int r; + + if (bo_legacy->map_count) { + fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n", + bo, bo->size, bo_legacy->map_count); + return -EINVAL; + } + if (bo_legacy->static_bo || bo_legacy->validated) { + *soffset = bo_legacy->offset; + *eoffset = bo_legacy->offset + bo->size; + return 0; + } + if (!(bo->flags & RADEON_GEM_DOMAIN_GTT)) { + r = bo_vram_validate(bo, soffset, eoffset); + if (r) { + return r; + } + } + *soffset = bo_legacy->offset; + *eoffset = bo_legacy->offset + bo->size; + bo_legacy->validated = 1; + return 0; +} + +void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + bo_legacy->pending = pending; + bo_legacy->is_pending += 1; + /* add to pending list */ + radeon_bo_ref(bo); + if (bo_legacy->is_pending > 1) { + return; + } + bo_legacy->pprev = boml->pending_bos.pprev; + bo_legacy->pnext = NULL; + bo_legacy->pprev->pnext = bo_legacy; + boml->pending_bos.pprev = bo_legacy; + boml->cpendings++; +} + +void radeon_bo_manager_legacy_shutdown(struct radeon_bo_manager *bom) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom; + struct bo_legacy *bo_legacy; + + if (bom == NULL) { + return; + } + bo_legacy = boml->bos.next; + while (bo_legacy) { + struct bo_legacy *next; + + next = bo_legacy->next; + bo_free(bo_legacy); + bo_legacy = next; + } + free(boml->free_handles); + free(boml); +} + +struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) +{ + struct bo_manager_legacy *bom; + struct bo_legacy *bo; + unsigned size; + + bom = (struct bo_manager_legacy*) + calloc(1, sizeof(struct bo_manager_legacy)); + if (bom == NULL) { + return NULL; + } + + bom->texture_heap = driCreateTextureHeap(0, + bom, + scrn->texSize[0], + 12, + RADEON_NR_TEX_REGIONS, + (drmTextureRegionPtr)scrn->sarea->tex_list[0], + &scrn->sarea->tex_age[0], + &bom->texture_swapped, + sizeof(struct bo_legacy), + &bo_legacy_tobj_destroy); + bom->texture_offset = scrn->texOffset[0]; + + bom->base.funcs = &bo_legacy_funcs; + bom->base.fd = scrn->driScreen->fd; + bom->bos.next = NULL; + bom->bos.prev = NULL; + bom->pending_bos.pprev = &bom->pending_bos; + bom->pending_bos.pnext = NULL; + bom->screen = scrn; + bom->fb_location = scrn->fbLocation; + bom->nhandle = 1; + bom->cfree_handles = 0; + bom->nfree_handles = 0x400; + bom->free_handles = (uint32_t*)malloc(bom->nfree_handles * 4); + if (bom->free_handles == NULL) { + radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + return NULL; + } + + /* biggest framebuffer size */ + size = 4096*4096*4; + /* allocate front */ + bo = bo_allocate(bom, size, 0, 0); + if (bo == NULL) { + radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + return NULL; + } + if (scrn->sarea->tiling_enabled) { + bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; + } + bo->static_bo = 1; + bo->offset = bom->screen->frontOffset + bom->fb_location; + bo->base.handle = bo->offset; + bo->ptr = scrn->driScreen->pFB + bom->screen->frontOffset; + if (bo->base.handle > bom->nhandle) { + bom->nhandle = bo->base.handle + 1; + } + /* allocate back */ + bo = bo_allocate(bom, size, 0, 0); + if (bo == NULL) { + radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + return NULL; + } + if (scrn->sarea->tiling_enabled) { + bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; + } + bo->static_bo = 1; + bo->offset = bom->screen->backOffset + bom->fb_location; + bo->base.handle = bo->offset; + bo->ptr = scrn->driScreen->pFB + bom->screen->backOffset; + if (bo->base.handle > bom->nhandle) { + bom->nhandle = bo->base.handle + 1; + } + /* allocate depth */ + bo = bo_allocate(bom, size, 0, 0); + if (bo == NULL) { + radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + return NULL; + } + bo->base.flags = 0; + if (scrn->sarea->tiling_enabled) { + bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; + } + bo->static_bo = 1; + bo->offset = bom->screen->depthOffset + bom->fb_location; + bo->base.handle = bo->offset; + bo->ptr = scrn->driScreen->pFB + bom->screen->depthOffset; + if (bo->base.handle > bom->nhandle) { + bom->nhandle = bo->base.handle + 1; + } + return (struct radeon_bo_manager*)bom; +} + +void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom) +{ + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom; + DRI_AGE_TEXTURES(boml->texture_heap); +} + +unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo) +{ + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + + if (bo_legacy->static_bo || (bo->flags & RADEON_GEM_DOMAIN_GTT)) { + return 0; + } + return bo->size; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h new file mode 100644 index 00000000000..316b023fb0f --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h @@ -0,0 +1,47 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#ifndef RADEON_BO_LEGACY_H +#define RADEON_BO_LEGACY_H + +#include "radeon_bo.h" +#include "radeon_screen.h" + +void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending); +int radeon_bo_legacy_validate(struct radeon_bo *bo, + uint32_t *soffset, + uint32_t *eoffset); +struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn); +void radeon_bo_manager_legacy_shutdown(struct radeon_bo_manager *bom); +void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom); +unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo); + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h new file mode 100644 index 00000000000..d41558f2e0e --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_buffer.h @@ -0,0 +1,47 @@ +/* + * Copyright 2008 Red Hat, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software") + * to deal in the software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * them Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTIBILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES, OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Adam Jackson + */ + +#ifndef RADEON_BUFFER_H +#define RADEON_BUFFER_H + +#include "radeon_bo.h" +#include "dri_util.h" + +struct radeon_renderbuffer +{ + struct gl_renderbuffer base; + struct radeon_bo *bo; + unsigned int cpp; + /* unsigned int offset; */ + unsigned int pitch; + unsigned int height; + + /* boo Xorg 6.8.2 compat */ + int depthHasSurface; + + __DRIdrawablePrivate *dPriv; +}; + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c new file mode 100644 index 00000000000..a2a8423e6a7 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -0,0 +1,376 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#include +#include "r300_reg.h" +#include "r300_emit.h" +#include "r300_cmdbuf.h" +#include "radeon_cs.h" +#include "radeon_cs_legacy.h" +#include "radeon_bo_legacy.h" +#include "radeon_context.h" + +struct cs_manager_legacy { + struct radeon_cs_manager base; + struct radeon_context *ctx; + /* hack for scratch stuff */ + uint32_t pending_age; + uint32_t pending_count; +}; + +struct cs_reloc_legacy { + struct radeon_cs_reloc base; + uint32_t cindices; + uint32_t *indices; +}; + + +static struct radeon_cs *cs_create(struct radeon_cs_manager *csm, + uint32_t ndw) +{ + struct radeon_cs *cs; + + cs = (struct radeon_cs*)calloc(1, sizeof(struct radeon_cs)); + if (cs == NULL) { + return NULL; + } + cs->csm = csm; + cs->ndw = (ndw + 0x3FF) & (~0x3FF); + cs->packets = (uint32_t*)malloc(4*cs->ndw); + if (cs->packets == NULL) { + free(cs); + return NULL; + } + cs->relocs_total_size = 0; + return cs; +} + +static int cs_write_dword(struct radeon_cs *cs, uint32_t dword) +{ + if (cs->cdw >= cs->ndw) { + uint32_t tmp, *ptr; + tmp = (cs->cdw + 1 + 0x3FF) & (~0x3FF); + ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); + if (ptr == NULL) { + return -ENOMEM; + } + cs->packets = ptr; + cs->ndw = tmp; + } + cs->packets[cs->cdw++] = dword; + if (cs->section) { + cs->section_cdw++; + } + return 0; +} + +static int cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t soffset, + uint32_t eoffset, + uint32_t domains) +{ + struct cs_reloc_legacy *relocs; + int i; + + relocs = (struct cs_reloc_legacy *)cs->relocs; + /* check reloc window */ + if (eoffset > bo->size) { + return -EINVAL; + } + if (soffset > eoffset) { + return -EINVAL; + } + /* check if bo is already referenced */ + for(i = 0; i < cs->crelocs; i++) { + uint32_t *indices; + + if (relocs[i].base.bo->handle == bo->handle) { + /* update start offset and size */ + if (eoffset > relocs[i].base.eoffset) { + relocs[i].base.eoffset = eoffset; + } + if (soffset < relocs[i].base.soffset) { + relocs[i].base.soffset = soffset; + } + relocs[i].base.size = relocs[i].base.eoffset - + relocs[i].base.soffset; + relocs[i].base.domains |= domains; + relocs[i].cindices += 1; + indices = (uint32_t*)realloc(relocs[i].indices, + relocs[i].cindices * 4); + if (indices == NULL) { + relocs[i].cindices -= 1; + return -ENOMEM; + } + relocs[i].indices = indices; + relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1; + return 0; + } + } + /* add bo to reloc */ + relocs = (struct cs_reloc_legacy*) + realloc(cs->relocs, + sizeof(struct cs_reloc_legacy) * (cs->crelocs + 1)); + if (relocs == NULL) { + return -ENOMEM; + } + cs->relocs = relocs; + relocs[cs->crelocs].base.bo = bo; + relocs[cs->crelocs].base.soffset = soffset; + relocs[cs->crelocs].base.eoffset = eoffset; + relocs[cs->crelocs].base.size = eoffset - soffset; + relocs[cs->crelocs].base.domains = domains; + relocs[cs->crelocs].indices = (uint32_t*)malloc(4); + if (relocs[cs->crelocs].indices == NULL) { + return -ENOMEM; + } + relocs[cs->crelocs].indices[0] = cs->cdw - 1; + relocs[cs->crelocs].cindices = 1; + cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo); + cs->crelocs++; + radeon_bo_ref(bo); + return 0; +} + +static int cs_begin(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, + int line) +{ + if (cs->section) { + fprintf(stderr, "CS already in a section(%s,%s,%d)\n", + cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS can't start section(%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + cs->section = 1; + cs->section_ndw = ndw; + cs->section_cdw = 0; + cs->section_file = file; + cs->section_func = func; + cs->section_line = line; + return 0; +} + +static int cs_end(struct radeon_cs *cs, + const char *file, + const char *func, + int line) + +{ + if (!cs->section) { + fprintf(stderr, "CS no section to end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + cs->section = 0; + if (cs->section_ndw != cs->section_cdw) { + fprintf(stderr, "CS section size missmatch start at (%s,%s,%d)\n", + cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS section end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + return 0; +} + +static int cs_process_relocs(struct radeon_cs *cs) +{ + struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm; + struct cs_reloc_legacy *relocs; + int i, j, r; + + if (!IS_R300_CLASS(csm->ctx->radeonScreen)) { + /* FIXME: r300 only right now */ + return -EINVAL; + } + csm = (struct cs_manager_legacy*)cs->csm; + relocs = (struct cs_reloc_legacy *)cs->relocs; + for (i = 0; i < cs->crelocs; i++) { + for (j = 0; j < relocs[i].cindices; j++) { + uint32_t soffset, eoffset; + + soffset = relocs[i].base.soffset; + eoffset = relocs[i].base.eoffset; + r = radeon_bo_legacy_validate(relocs[i].base.bo, + &soffset, &eoffset); + if (r) { + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + return r; + } + cs->packets[relocs[i].indices[j]] += soffset; + if (cs->packets[relocs[i].indices[j]] >= eoffset) { + radeon_bo_debug(relocs[i].base.bo, 12); + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", + relocs[i].base.bo, + cs->packets[relocs[i].indices[j]], + eoffset); + exit(0); + return -EINVAL; + } + } + } + return 0; +} + +static int cs_set_age(struct radeon_cs *cs) +{ + struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm; + struct cs_reloc_legacy *relocs; + int i; + + relocs = (struct cs_reloc_legacy *)cs->relocs; + for (i = 0; i < cs->crelocs; i++) { + radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age); + radeon_bo_unref(relocs[i].base.bo); + } + return 0; +} + +static int cs_emit(struct radeon_cs *cs) +{ + struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm; + drm_radeon_cmd_buffer_t cmd; + drm_r300_cmd_header_t age; + uint64_t ull; + int r; + + /* please flush pipe do all pending work */ + cs_write_dword(cs, cmdpacket0(R300_SC_SCREENDOOR, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdpacket0(R300_SC_SCREENDOOR, 1)); + cs_write_dword(cs, 0x00FFFFFF); + cs_write_dword(cs, cmdpacket0(R300_SC_HYPERZ, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdpacket0(R300_US_CONFIG, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdpacket0(R300_ZB_CNTL, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdwait(R300_WAIT_3D)); + cs_write_dword(cs, cmdpacket0(R300_RB3D_DSTCACHE_CTLSTAT, 1)); + cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + cs_write_dword(cs, cmdpacket0(R300_ZB_ZCACHE_CTLSTAT, 1)); + cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); + cs_write_dword(cs, cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN)); + + /* append buffer age */ + age.scratch.cmd_type = R300_CMD_SCRATCH; + /* Scratch register 2 corresponds to what radeonGetAge polls */ + csm->pending_age = 0; + csm->pending_count = 1; + ull = (uint64_t) (intptr_t) &csm->pending_age; + age.scratch.reg = 2; + age.scratch.n_bufs = 1; + age.scratch.flags = 0; + radeon_cs_write_dword(cs, age.u); + radeon_cs_write_dword(cs, ull & 0xffffffff); + radeon_cs_write_dword(cs, ull >> 32); + radeon_cs_write_dword(cs, 0); + + + r = cs_process_relocs(cs); + if (r) { + return 0; + } + + cmd.buf = (char *)cs->packets; + cmd.bufsz = cs->cdw * 4; + if (csm->ctx->state.scissor.enabled) { + cmd.nbox = csm->ctx->state.scissor.numClipRects; + cmd.boxes = (drm_clip_rect_t *) csm->ctx->state.scissor.pClipRects; + } else { + cmd.nbox = csm->ctx->numClipRects; + cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; + } + + r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); + cs_set_age(cs); + return r; +} + +static int cs_destroy(struct radeon_cs *cs) +{ + free(cs->relocs); + free(cs->packets); + free(cs); + return 0; +} + +static int cs_erase(struct radeon_cs *cs) +{ + free(cs->relocs); + cs->relocs_total_size = 0; + cs->relocs = NULL; + cs->crelocs = 0; + cs->cdw = 0; + cs->section = 0; + return 0; +} + +static int cs_need_flush(struct radeon_cs *cs) +{ + /* FIXME: we should get the texture heap size */ + return (cs->relocs_total_size > (7*1024*1024)); +} + +struct radeon_cs_funcs radeon_cs_funcs = { + cs_create, + cs_write_dword, + cs_write_reloc, + cs_begin, + cs_end, + cs_emit, + cs_destroy, + cs_erase, + cs_need_flush +}; + +struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx) +{ + struct cs_manager_legacy *csm; + + csm = (struct cs_manager_legacy*) + calloc(1, sizeof(struct cs_manager_legacy)); + if (csm == NULL) { + return NULL; + } + csm->base.funcs = &radeon_cs_funcs; + csm->base.fd = ctx->dri.fd; + csm->ctx = ctx; + csm->pending_age = 1; + return (struct radeon_cs_manager*)csm; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h new file mode 100644 index 00000000000..6ab384e9789 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h @@ -0,0 +1,40 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#ifndef RADEON_CS_LEGACY_H +#define RADEON_CS_LEGACY_H + +#include "radeon_cs.h" +#include "radeon_context.h" + +struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx); + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 5f32dd575e3..861310de659 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -45,6 +45,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_chipset.h" #include "radeon_macros.h" #include "radeon_screen.h" +#include "radeon_buffer.h" #if !RADEON_COMMON #include "radeon_context.h" #include "radeon_span.h" @@ -70,6 +71,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Radeon configuration */ #include "xmlpool.h" +#include "radeon_bo_legacy.h" #if !RADEON_COMMON /* R100 */ PUBLIC const char __driConfigOptions[] = @@ -960,6 +962,13 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->driScreen = sPriv; screen->sarea_priv_offset = dri_priv->sarea_priv_offset; + screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + + screen->sarea_priv_offset); + screen->bom = radeon_bo_manager_legacy(screen); + if (screen->bom == NULL) { + free(screen); + return NULL; + } return screen; } @@ -973,6 +982,8 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) if (!screen) return; + radeon_bo_manager_legacy_shutdown(screen->bom); + if ( screen->gartTextures.map ) { drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); } @@ -1002,6 +1013,160 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) return GL_TRUE; } +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +static GLboolean +radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, + GLenum intFormat, GLuint w, GLuint h) +{ + rb->Width = w; + rb->Height = h; + rb->_ActualFormat = intFormat; + + return GL_TRUE; +} + + +static struct radeon_renderbuffer * +radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) +{ + struct radeon_renderbuffer *ret; + + ret = CALLOC_STRUCT(radeon_renderbuffer); + if (!ret) + return NULL; + + _mesa_init_renderbuffer(&ret->base, 0); + + /* XXX format junk */ + switch (format) { + case GL_RGB5: + ret->base._ActualFormat = GL_RGB5; + ret->base._BaseFormat = GL_RGBA; + ret->base.RedBits = 5; + ret->base.GreenBits = 6; + ret->base.BlueBits = 5; + ret->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_RGBA8: + ret->base._ActualFormat = GL_RGBA8; + ret->base._BaseFormat = GL_RGBA; + ret->base.RedBits = 8; + ret->base.GreenBits = 8; + ret->base.BlueBits = 8; + ret->base.AlphaBits = 8; + ret->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_STENCIL_INDEX8_EXT: + ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; + ret->base._BaseFormat = GL_STENCIL_INDEX; + ret->base.StencilBits = 8; + ret->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_DEPTH_COMPONENT16: + ret->base._ActualFormat = GL_DEPTH_COMPONENT16; + ret->base._BaseFormat = GL_DEPTH_COMPONENT; + ret->base.DepthBits = 16; + ret->base.DataType = GL_UNSIGNED_SHORT; + break; + case GL_DEPTH_COMPONENT24: + ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; + ret->base._BaseFormat = GL_DEPTH_COMPONENT; + ret->base.DepthBits = 24; + ret->base.DataType = GL_UNSIGNED_INT; + break; + case GL_DEPTH24_STENCIL8_EXT: + ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; + ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; + ret->base.DepthBits = 24; + ret->base.StencilBits = 8; + ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; + break; + default: + fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); + _mesa_delete_renderbuffer(&ret->base); + return NULL; + } + + ret->dPriv = driDrawPriv; + ret->base.InternalFormat = format; + + ret->base.AllocStorage = radeon_alloc_window_storage; + + radeonSetSpanFunctions(ret); + + return ret; +} + +/** + * Create the Mesa framebuffer and renderbuffers for a given window/drawable. + * + * \todo This function (and its interface) will need to be updated to support + * pbuffers. + */ +static GLboolean +radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, + __DRIdrawablePrivate *driDrawPriv, + const __GLcontextModes *mesaVis, + GLboolean isPixmap ) +{ + radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; + + const GLboolean swDepth = GL_FALSE; + const GLboolean swAlpha = GL_FALSE; + const GLboolean swAccum = mesaVis->accumRedBits > 0; + const GLboolean swStencil = mesaVis->stencilBits > 0 && + mesaVis->depthBits != 24; + GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); + GLenum depthFormat = GL_NONE; + struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); + + if (mesaVis->depthBits == 16) + depthFormat = GL_DEPTH_COMPONENT16; + else if (mesaVis->depthBits == 24) + depthFormat = GL_DEPTH_COMPONENT24; + + /* front color renderbuffer */ + { + struct radeon_renderbuffer *front = + radeon_create_renderbuffer(rgbFormat, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); + } + + /* back color renderbuffer */ + if (mesaVis->doubleBufferMode) { + struct radeon_renderbuffer *back = + radeon_create_renderbuffer(rgbFormat, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); + } + + /* depth renderbuffer */ + if (depthFormat != GL_NONE) { + struct radeon_renderbuffer *depth = + radeon_create_renderbuffer(depthFormat, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); + depth->depthHasSurface = screen->depthHasSurface; + } + + /* stencil renderbuffer */ + if (mesaVis->stencilBits > 0 && !swStencil) { + struct radeon_renderbuffer *stencil = + radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); + stencil->depthHasSurface = screen->depthHasSurface; + } + + _mesa_add_soft_renderbuffers(fb, + GL_FALSE, /* color */ + swDepth, + swStencil, + swAccum, + swAlpha, + GL_FALSE /* aux */); + driDrawPriv->driverPrivate = (void *) fb; + + return (driDrawPriv->driverPrivate != NULL); +} +#else /** * Create the Mesa framebuffer and renderbuffers for a given window/drawable. @@ -1101,7 +1266,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, return (driDrawPriv->driverPrivate != NULL); } } - +#endif static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) @@ -1197,11 +1362,11 @@ radeonInitScreen(__DRIscreenPrivate *psp) if (!radeonInitDriver(psp)) return NULL; + /* for now fill in all modes */ return radeonFillInModes( psp, dri_priv->bpp, (dri_priv->bpp == 16) ? 16 : 24, - (dri_priv->bpp == 16) ? 0 : 8, - (dri_priv->backOffset != dri_priv->depthOffset) ); + (dri_priv->bpp == 16) ? 0 : 8, 1); } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index b84c70bfae9..7b9d036148e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_reg.h" #include "drm_sarea.h" #include "xmlconfig.h" +#include "radeon_bo.h" typedef struct { @@ -54,7 +55,7 @@ typedef struct { drmAddress map; /* Mapping of the DRM region */ } radeonRegionRec, *radeonRegionPtr; -typedef struct { +typedef struct radeon_screen { int chip_family; int chip_flags; int cpp; @@ -106,6 +107,8 @@ typedef struct { const __DRIextension *extensions[8]; int num_gb_pipes; + drm_radeon_sarea_t *sarea; /* Private SAREA data */ + struct radeon_bo_manager *bom; } radeonScreenRec, *radeonScreenPtr; #define IS_R100_CLASS(screen) \ diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h index 9abe0864b17..1650a9bea98 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h @@ -44,7 +44,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" +#include "radeon_buffer.h" + extern void radeonInitSpanFuncs(GLcontext * ctx); -extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis); +#if COMPILE_R300 +extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); +#else +extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis); +#endif #endif -- cgit v1.2.3 From 3b43c28195ffce79822728b546a707ee14a03320 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 9 Nov 2008 19:00:28 +0100 Subject: r300: cs + DRI2 support If DRI2 is enabled then switch cmd assembly to directly build hw packet. --- src/mesa/drivers/dri/r300/Makefile | 4 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 311 ++++++++++++++++--------- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 7 + src/mesa/drivers/dri/r300/r300_context.h | 2 +- src/mesa/drivers/dri/r300/r300_emit.c | 15 +- src/mesa/drivers/dri/r300/r300_emit.h | 105 ++++++--- src/mesa/drivers/dri/r300/r300_ioctl.c | 101 +++++--- src/mesa/drivers/dri/r300/r300_mipmap_tree.c | 5 +- src/mesa/drivers/dri/r300/r300_render.c | 62 ++++- src/mesa/drivers/dri/r300/r300_state.c | 65 +++--- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/r300/radeon_context.c | 139 ++++++++++- src/mesa/drivers/dri/r300/radeon_context.h | 1 + src/mesa/drivers/dri/r300/radeon_lock.h | 4 + src/mesa/drivers/dri/r300/radeon_span.c | 241 ++++++++++++------- src/mesa/drivers/dri/r300/radeon_state.c | 2 + src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 22 +- src/mesa/drivers/dri/radeon/radeon_buffer.h | 3 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 40 +++- src/mesa/drivers/dri/radeon/radeon_cs_legacy.h | 1 + src/mesa/drivers/dri/radeon/radeon_screen.c | 174 +++++++++++--- 21 files changed, 958 insertions(+), 348 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index f1141523c07..c041bc6ad01 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -57,8 +57,8 @@ C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) DRIVER_DEFINES = -DCOMPILE_R300 -DR200_MERGED=0 \ -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300 \ -# -DRADEON_BO_TRACK_OPEN \ # -DRADEON_BO_TRACK_REF \ +# -DRADEON_BO_TRACK_OPEN \ -Wall SYMLINKS = \ @@ -80,6 +80,8 @@ COMMON_SYMLINKS = \ radeon_bo_legacy.h \ radeon_cs_legacy.h +DRI_LIB_DEPS += -ldrm_radeon + ##### TARGETS ##### include ../Makefile.template diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 7d7fed4e5d6..dbb7761b3b5 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -55,6 +55,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_mipmap_tree.h" #include "r300_state.h" #include "radeon_cs_legacy.h" +#include "radeon_cs_gem.h" +#include "radeon_reg.h" + +#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 +# define RADEON_ONE_REG_WR (1 << 15) // Set this to 1 for extremely verbose debugging of command buffers #define DEBUG_CMDBUF 0 @@ -106,8 +111,6 @@ int r300FlushCmdBuf(r300ContextPtr r300, const char *caller) */ void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller) { - assert(dwords < r300->cmdbuf.size); - if ((r300->cmdbuf.cs->cdw + dwords + 128) > r300->cmdbuf.size || radeon_cs_need_flush(r300->cmdbuf.cs)) { r300FlushCmdBuf(r300, caller); @@ -157,12 +160,12 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) struct r300_state_atom *atom; int dwords; - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH(cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN)); - OUT_BATCH(cmdpacket0(R300_TX_INVALTAGS, 1)); + cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1)); OUT_BATCH(R300_TX_FLUSH); - OUT_BATCH(cmdpacify()); END_BATCH(); + end_3d(r300); /* Emit actual atoms */ foreach(atom, &r300->hw.atomlist) { @@ -173,7 +176,7 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) r300PrintStateAtom(r300, atom); } if (atom->emit) { - (*atom->emit)(r300); + (*atom->emit)(r300, atom); } else { BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); @@ -227,14 +230,62 @@ void r300EmitState(r300ContextPtr r300) r300->hw.all_dirty = GL_FALSE; } -#define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count) +static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) +{ + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + return ((((*pkt) >> 16) & 0x3FFF) + 1); + } else { + drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; + return t->packet0.count; + } + return 0; +} + #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) -static void emit_tex_offsets(r300ContextPtr r300) +void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) +{ + BATCH_LOCALS(r300); + drm_r300_cmd_header_t cmd; + uint32_t addr, ndw, i; + + if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { + uint32_t dwords; + dwords = (*atom->check) (r300, atom); + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + return; + } + + cmd.u = atom->cmd[0]; + addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; + ndw = cmd.vpu.count * 4; + if (ndw) { + /* flush processing vertices */ + OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); + OUT_BATCH(0x0); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH((1 << 15) | (1 << 28)); + OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); + OUT_BATCH(0x00FFFFFF); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); + OUT_BATCH(1); + /* write vpu */ + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0)); + OUT_BATCH(addr); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); + for (i = 0; i < ndw; i++) { + OUT_BATCH(atom->cmd[i+1]); + } + } +} + +static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) { BATCH_LOCALS(r300); - int numtmus = packet0_count(r300->hw.tex.offset.cmd); + int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); if (numtmus) { int i; @@ -255,19 +306,23 @@ static void emit_tex_offsets(r300ContextPtr r300) } } -static void emit_cb_offset(r300ContextPtr r300) +static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) { BATCH_LOCALS(r300); struct radeon_renderbuffer *rrb; uint32_t cbpitch; + GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate; rrb = r300->radeon.state.color.rrb; + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } if (!rrb) { fprintf(stderr, "no rrb\n"); return; } - cbpitch = rrb->pitch; + cbpitch = (rrb->pitch / rrb->cpp); if (rrb->cpp == 4) cbpitch |= R300_COLOR_FORMAT_ARGB8888; else @@ -284,7 +339,7 @@ static void emit_cb_offset(r300ContextPtr r300) END_BATCH(); } -static void emit_zb_offset(r300ContextPtr r300) +static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) { BATCH_LOCALS(r300); struct radeon_renderbuffer *rrb; @@ -294,11 +349,11 @@ static void emit_zb_offset(r300ContextPtr r300) if (!rrb) return; - zbpitch = rrb->pitch; + zbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { zbpitch |= R300_DEPTHMACROTILE_ENABLE; } - if (r300->radeon.glCtx->Visual.depthBits == 24) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ zbpitch |= R300_DEPTHMICROTILE_TILED; } @@ -317,13 +372,17 @@ static int check_always(r300ContextPtr r300, struct r300_state_atom *atom) static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom) { int cnt; - cnt = packet0_count(atom->cmd); + if (atom->cmd[0] == CP_PACKET2) { + return 0; + } + cnt = packet0_count(r300, atom->cmd); return cnt ? cnt + 1 : 0; } -static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) +int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) { int cnt; + cnt = vpu_count(atom->cmd); return cnt ? (cnt * 4) + 1 : 0; } @@ -331,6 +390,7 @@ static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) { int cnt; + cnt = r500fp_count(atom->cmd); return cnt ? (cnt * 6) + 1 : 0; } @@ -338,7 +398,8 @@ static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) { int cnt; - cnt = r500fp_count(atom->cmd); + + cnt = r500fp_count(atom->cmd); return cnt ? (cnt * 4) + 1 : 0; } @@ -383,92 +444,92 @@ void r300InitCmdBuf(r300ContextPtr r300) /* Initialize state atoms */ ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0); - r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(R300_SE_VPORT_XSCALE, 6); + r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6); ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0); - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(R300_VAP_PVS_STATE_FLUSH_REG, 1); + r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1); r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0; - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(R300_VAP_CNTL, 1); + r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1); if (is_r500) { ALLOC_STATE(vap_index_offset, always, 2, 0); - r300->hw.vap_index_offset.cmd[0] = cmdpacket0(R500_VAP_INDEX_OFFSET, 1); + r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1); r300->hw.vap_index_offset.cmd[1] = 0; } ALLOC_STATE(vte, always, 3, 0); - r300->hw.vte.cmd[0] = cmdpacket0(R300_SE_VTE_CNTL, 2); + r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2); ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0); - r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(R300_VAP_VF_MAX_VTX_INDX, 2); + r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2); ALLOC_STATE(vap_cntl_status, always, 2, 0); - r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1); + r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1); ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0); r300->hw.vir[0].cmd[R300_VIR_CMD_0] = - cmdpacket0(R300_VAP_PROG_STREAM_CNTL_0, 1); + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1); ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1); r300->hw.vir[1].cmd[R300_VIR_CMD_0] = - cmdpacket0(R300_VAP_PROG_STREAM_CNTL_EXT_0, 1); + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1); ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0); - r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_VTX_STATE_CNTL, 2); + r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2); ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0); - r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); + r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); if (has_tcl) { ALLOC_STATE(vap_clip_cntl, always, 2, 0); - r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(R300_VAP_CLIP_CNTL, 1); + r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1); ALLOC_STATE(vap_clip, always, 5, 0); - r300->hw.vap_clip.cmd[0] = cmdpacket0(R300_VAP_GB_VERT_CLIP_ADJ, 4); + r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4); ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); - r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(VAP_PVS_VTX_TIMEOUT_REG, 1); + r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); } ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0); r300->hw.vof.cmd[R300_VOF_CMD_0] = - cmdpacket0(R300_VAP_OUTPUT_VTX_FMT_0, 2); + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2); if (has_tcl) { ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0); r300->hw.pvs.cmd[R300_PVS_CMD_0] = - cmdpacket0(R300_VAP_PVS_CODE_CNTL_0, 3); + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3); } ALLOC_STATE(gb_enable, always, 2, 0); - r300->hw.gb_enable.cmd[0] = cmdpacket0(R300_GB_ENABLE, 1); + r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1); ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0); - r300->hw.gb_misc.cmd[0] = cmdpacket0(R300_GB_MSPOS0, 5); + r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5); ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0); - r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(R300_TX_ENABLE, 1); + r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1); ALLOC_STATE(ga_point_s0, always, 5, 0); - r300->hw.ga_point_s0.cmd[0] = cmdpacket0(R300_GA_POINT_S0, 4); + r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4); ALLOC_STATE(ga_triangle_stipple, always, 2, 0); - r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(R300_GA_TRIANGLE_STIPPLE, 1); + r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1); ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0); - r300->hw.ps.cmd[0] = cmdpacket0(R300_GA_POINT_SIZE, 1); + r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1); ALLOC_STATE(ga_point_minmax, always, 4, 0); - r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(R300_GA_POINT_MINMAX, 3); + r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3); ALLOC_STATE(lcntl, always, 2, 0); - r300->hw.lcntl.cmd[0] = cmdpacket0(R300_GA_LINE_CNTL, 1); + r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1); ALLOC_STATE(ga_line_stipple, always, 4, 0); - r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(R300_GA_LINE_STIPPLE_VALUE, 3); + r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3); ALLOC_STATE(shade, always, 5, 0); - r300->hw.shade.cmd[0] = cmdpacket0(R300_GA_ENHANCE, 4); + r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4); ALLOC_STATE(polygon_mode, always, 4, 0); - r300->hw.polygon_mode.cmd[0] = cmdpacket0(R300_GA_POLY_MODE, 3); + r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3); ALLOC_STATE(fogp, always, 3, 0); - r300->hw.fogp.cmd[0] = cmdpacket0(R300_GA_FOG_SCALE, 2); + r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2); ALLOC_STATE(zbias_cntl, always, 2, 0); - r300->hw.zbias_cntl.cmd[0] = cmdpacket0(R300_SU_TEX_WRAP, 1); + r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1); ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0); r300->hw.zbs.cmd[R300_ZBS_CMD_0] = - cmdpacket0(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); + cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4); ALLOC_STATE(occlusion_cntl, always, 2, 0); - r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(R300_SU_POLY_OFFSET_ENABLE, 1); + r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1); ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0); - r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(R300_SU_CULL_MODE, 1); + r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1); ALLOC_STATE(su_depth_scale, always, 3, 0); - r300->hw.su_depth_scale.cmd[0] = cmdpacket0(R300_SU_DEPTH_SCALE, 2); + r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2); ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0); - r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(R300_RS_COUNT, 2); + r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2); if (is_r500) { ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R500_RS_IP_0, 16); + r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16); for (i = 0; i < 8; i++) { r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | @@ -477,132 +538,144 @@ void r300InitCmdBuf(r300ContextPtr r300) (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); } ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R500_RS_INST_0, 1); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1); } else { ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_IP_0, 8); + r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8); ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, 1); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1); } ALLOC_STATE(sc_hyperz, always, 3, 0); - r300->hw.sc_hyperz.cmd[0] = cmdpacket0(R300_SC_HYPERZ, 2); + r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2); ALLOC_STATE(sc_screendoor, always, 2, 0); - r300->hw.sc_screendoor.cmd[0] = cmdpacket0(R300_SC_SCREENDOOR, 1); + r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1); ALLOC_STATE(us_out_fmt, always, 6, 0); - r300->hw.us_out_fmt.cmd[0] = cmdpacket0(R300_US_OUT_FMT, 5); + r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5); if (is_r500) { ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0); - r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(R500_US_CONFIG, 2); + r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2); r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO; - r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(R500_US_CODE_ADDR, 3); - r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(R500_US_FC_CTRL, 1); + r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3); + r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1); r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */ ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0); - r300->hw.r500fp.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 0, 0); + r300->hw.r500fp.cmd[R300_FPI_CMD_0] = + cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0); ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0); - r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 1, 0); + r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = + cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0); } else { ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0); - r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_US_CONFIG, 3); - r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_US_CODE_ADDR_0, 4); + r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3); + r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4); + ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0); - r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_US_TEX_INST_0, 0); + r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0); ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0); - r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, 1); + r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1); ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1); - r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, 1); + r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1); ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2); - r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, 1); + r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1); ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3); - r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, 1); + r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1); ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0); - r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0); + r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0); } ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0); - r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(R300_FG_FOG_BLEND, 1); + r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1); ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0); - r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(R300_FG_FOG_COLOR_R, 3); + r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3); ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0); - r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(R300_FG_ALPHA_FUNC, 2); + r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2); ALLOC_STATE(fg_depth_src, always, 2, 0); - r300->hw.fg_depth_src.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, 1); + r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1); ALLOC_STATE(rb3d_cctl, always, 2, 0); - r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1); + r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1); ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0); - r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2); + r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2); ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0); - r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(RB3D_COLOR_CHANNEL_MASK, 1); + r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); if (is_r500) { ALLOC_STATE(blend_color, always, 3, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(R500_RB3D_CONSTANT_COLOR_AR, 2); + r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2); } else { ALLOC_STATE(blend_color, always, 2, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 1); + r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1); } ALLOC_STATE(rop, always, 2, 0); - r300->hw.rop.cmd[0] = cmdpacket0(R300_RB3D_ROPCNTL, 1); + r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1); ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0); r300->hw.cb.emit = &emit_cb_offset; ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); - r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, 9); + r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9); ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); - r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(R300_RB3D_AARESOLVE_CTL, 1); + r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1); ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); r300->hw.zs.cmd[R300_ZS_CMD_0] = - cmdpacket0(R300_ZB_CNTL, 3); + cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); ALLOC_STATE(zstencil_format, always, 5, 0); r300->hw.zstencil_format.cmd[0] = - cmdpacket0(R300_ZB_FORMAT, 4); + cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4); ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0); r300->hw.zb.emit = emit_zb_offset; ALLOC_STATE(zb_depthclearvalue, always, 2, 0); - r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(R300_ZB_DEPTHCLEARVALUE, 1); + r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1); ALLOC_STATE(unk4F30, always, 3, 0); - r300->hw.unk4F30.cmd[0] = cmdpacket0(0x4F30, 2); + r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2); ALLOC_STATE(zb_hiz_offset, always, 2, 0); - r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(R300_ZB_HIZ_OFFSET, 1); + r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1); ALLOC_STATE(zb_hiz_pitch, always, 2, 0); - r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(R300_ZB_HIZ_PITCH, 1); + r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1); /* VPU only on TCL */ if (has_tcl) { int i; ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0); - r300->hw.vpi.cmd[R300_VPI_CMD_0] = - cmdvpu(R300_PVS_CODE_START, 0); + r300->hw.vpi.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0); + r300->hw.vpi.emit = emit_vpu; if (is_r500) { ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); - r300->hw.vpp.cmd[R300_VPP_CMD_0] = - cmdvpu(R500_PVS_CONST_START, 0); + r300->hw.vpp.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0); + r300->hw.vpp.emit = emit_vpu; ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); - r300->hw.vps.cmd[R300_VPS_CMD_0] = - cmdvpu(R500_POINT_VPORT_SCALE_OFFSET, 1); + r300->hw.vps.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); + r300->hw.vps.emit = emit_vpu; for (i = 0; i < 6; i++) { ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] = - cmdvpu(R500_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].cmd[0] = + cmdvpu(r300->radeon.radeonScreen, + R500_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].emit = emit_vpu; } } else { ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); - r300->hw.vpp.cmd[R300_VPP_CMD_0] = - cmdvpu(R300_PVS_CONST_START, 0); + r300->hw.vpp.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0); + r300->hw.vpp.emit = emit_vpu; ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); - r300->hw.vps.cmd[R300_VPS_CMD_0] = - cmdvpu(R300_POINT_VPORT_SCALE_OFFSET, 1); + r300->hw.vps.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1); + r300->hw.vps.emit = emit_vpu; for (i = 0; i < 6; i++) { ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] = - cmdvpu(R300_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].cmd[0] = + cmdvpu(r300->radeon.radeonScreen, + R300_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].emit = emit_vpu; } } } @@ -610,34 +683,34 @@ void r300InitCmdBuf(r300ContextPtr r300) /* Textures */ ALLOC_STATE(tex.filter, variable, mtu + 1, 0); r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FILTER0_0, 0); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0); ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0); r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FILTER1_0, 0); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0); ALLOC_STATE(tex.size, variable, mtu + 1, 0); - r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_SIZE_0, 0); + r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0); ALLOC_STATE(tex.format, variable, mtu + 1, 0); r300->hw.tex.format.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FORMAT_0, 0); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0); ALLOC_STATE(tex.pitch, variable, mtu + 1, 0); - r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FORMAT2_0, 0); + r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0); ALLOC_STATE(tex.offset, variable, 1, 0); r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_OFFSET_0, 0); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0); r300->hw.tex.offset.emit = &emit_tex_offsets; ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0); r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_CHROMA_KEY_0, 0); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0); ALLOC_STATE(tex.border_color, variable, mtu + 1, 0); r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_BORDER_COLOR_0, 0); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0); r300->hw.is_dirty = GL_TRUE; r300->hw.all_dirty = GL_TRUE; @@ -663,7 +736,12 @@ void r300InitCmdBuf(r300ContextPtr r300) size * 4, r300->hw.max_state_size * 4); } - r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon); + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + int fd = r300->radeon.radeonScreen->driScreen->fd; + r300->cmdbuf.csm = radeon_cs_manager_gem(fd); + } else { + r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon); + } if (r300->cmdbuf.csm == NULL) { /* FIXME: fatal error */ return; @@ -684,4 +762,9 @@ void r300DestroyCmdBuf(r300ContextPtr r300) foreach(atom, &r300->hw.atomlist) { FREE(atom->cmd); } + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + radeon_cs_manager_gem_shutdown(r300->cmdbuf.csm); + } else { + radeon_cs_manager_legacy_shutdown(r300->cmdbuf.csm); + } } diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index 98cb1af1260..b21619fd181 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -86,6 +86,10 @@ void r300BeginBatch(r300ContextPtr r300, */ #define OUT_BATCH_RELOC(data, bo, offset, flags) \ do { \ + if (offset) {\ + fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ + __FILE__, __FUNCTION__, __LINE__, offset);\ + }\ radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\ radeon_cs_write_reloc(b_l_r300->cmdbuf.cs,bo,0,(bo)->size,flags);\ } while(0) @@ -119,4 +123,7 @@ void r300BeginBatch(r300ContextPtr r300, do { \ } while(0) +void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom); +int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom); + #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 5f8b8c1a402..63bf67e76e8 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -208,7 +208,7 @@ struct r300_state_atom { GLboolean dirty; int (*check) (r300ContextPtr, struct r300_state_atom * atom); - void (*emit) (r300ContextPtr); + void (*emit) (r300ContextPtr, struct r300_state_atom * atom); }; #define R300_VPT_CMD_0 0 diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index d07e7baf6b5..d2628633d48 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -178,7 +178,7 @@ static void r300EmitVec(GLcontext * ctx, struct r300_aos *aos, aos->stride = size; } aos->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT); + 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); aos->offset = 0; aos->components = size; aos->count = count; @@ -436,6 +436,18 @@ int r300EmitArrays(GLcontext * ctx) } /* Setup INPUT_ROUTE. */ + if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + R300_STATECHANGE(rmesa, vir[0]); + rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[0].cmd[0] |= + (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; + R300_STATECHANGE(rmesa, vir[1]); + rmesa->hw.vir[1].cmd[0] |= + (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + nr) & 0x3FFF) << 16; + } else { R300_STATECHANGE(rmesa, vir[0]); ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], @@ -444,6 +456,7 @@ int r300EmitArrays(GLcontext * ctx) ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, nr); + } /* Setup INPUT_CNTL. */ R300_STATECHANGE(rmesa, vic); diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index c596e895ce3..bf34ced86e6 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -46,23 +46,31 @@ /* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up * with DRM */ +#define CP_PACKET2 (2 << 30) #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) #define CP_PACKET3( pkt, n ) \ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) -static INLINE uint32_t cmdpacket0(int reg, int count) +static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, + int reg, int count) { - drm_r300_cmd_header_t cmd; - - cmd.packet0.cmd_type = R300_CMD_PACKET0; - cmd.packet0.count = count; - cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8; - cmd.packet0.reglo = ((unsigned int)reg & 0x00FF); - - return cmd.u; + if (!rscrn->driScreen->dri2.enabled) { + drm_r300_cmd_header_t cmd; + + cmd.packet0.cmd_type = R300_CMD_PACKET0; + cmd.packet0.count = count; + cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8; + cmd.packet0.reglo = ((unsigned int)reg & 0x00FF); + + return cmd.u; + } + if (count) { + return CP_PACKET0(reg, count - 1); + } + return CP_PACKET2; } -static INLINE uint32_t cmdvpu(int addr, int count) +static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) { drm_r300_cmd_header_t cmd; @@ -74,7 +82,8 @@ static INLINE uint32_t cmdvpu(int addr, int count) return cmd.u; } -static INLINE uint32_t cmdr500fp(int addr, int count, int type, int clamp) +static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn, + int addr, int count, int type, int clamp) { drm_r300_cmd_header_t cmd; @@ -88,7 +97,7 @@ static INLINE uint32_t cmdr500fp(int addr, int count, int type, int clamp) return cmd.u; } -static INLINE uint32_t cmdpacket3(int packet) +static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet) { drm_r300_cmd_header_t cmd; @@ -98,7 +107,8 @@ static INLINE uint32_t cmdpacket3(int packet) return cmd.u; } -static INLINE uint32_t cmdcpdelay(unsigned short count) +static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, + unsigned short count) { drm_r300_cmd_header_t cmd; @@ -108,7 +118,8 @@ static INLINE uint32_t cmdcpdelay(unsigned short count) return cmd.u; } -static INLINE uint32_t cmdwait(unsigned char flags) +static INLINE uint32_t cmdwait(struct radeon_screen *rscrn, + unsigned char flags) { drm_r300_cmd_header_t cmd; @@ -118,7 +129,7 @@ static INLINE uint32_t cmdwait(unsigned char flags) return cmd.u; } -static INLINE uint32_t cmdpacify(void) +static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) { drm_r300_cmd_header_t cmd; @@ -130,13 +141,13 @@ static INLINE uint32_t cmdpacify(void) /** Single register write to command buffer; requires 2 dwords. */ #define OUT_BATCH_REGVAL(reg, val) \ - OUT_BATCH(cmdpacket0((reg), 1)); \ + OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), 1)); \ OUT_BATCH((val)) /** Continuous register range write to command buffer; requires 1 dword, * expects count dwords afterwards for register contents. */ #define OUT_BATCH_REGSEQ(reg, count) \ - OUT_BATCH(cmdpacket0((reg), (count))); + OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), (count))); /** Write a 32 bit float to the ring; requires 1 dword. */ #define OUT_BATCH_FLOAT32(f) \ @@ -147,7 +158,10 @@ static INLINE uint32_t cmdpacify(void) * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - OUT_BATCH(cmdpacket3(R300_CMD_PACKET3_RAW)); \ + if (!b_l_r300->radeon.radeonScreen->driScreen->dri2.enabled) { \ + OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\ + R300_CMD_PACKET3_RAW)); \ + }\ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } while(0) @@ -158,27 +172,62 @@ void static INLINE end_3d(r300ContextPtr rmesa) { BATCH_LOCALS(rmesa); - BEGIN_BATCH(1); - OUT_BATCH(cmdpacify()); - END_BATCH(); + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + BEGIN_BATCH(1); + OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); + END_BATCH(); + } } void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { BATCH_LOCALS(rmesa); - BEGIN_BATCH(1); - OUT_BATCH(cmdcpdelay(count)); - END_BATCH(); + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + BEGIN_BATCH(1); + OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); + END_BATCH(); + } } void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) { BATCH_LOCALS(rmesa); - - BEGIN_BATCH(1); - OUT_BATCH(cmdwait(flags)); - END_BATCH(); + uint32_t wait_until; + + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); + END_BATCH(); + } else { + switch(flags) { + case R300_WAIT_2D: + wait_until = (1 << 14); + break; + case R300_WAIT_3D: + wait_until = (1 << 15); + break; + case R300_NEW_WAIT_2D_3D: + wait_until = (1 << 14) | (1 << 15); + break; + case R300_NEW_WAIT_2D_2D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + break; + case R300_NEW_WAIT_3D_3D_CLEAN: + wait_until = (1 << 15) | (1 << 17) | (1 << 18); + break; + case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + wait_until |= (1 << 15) | (1 << 17) | (1 << 18); + break; + default: + return; + } + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH(wait_until); + END_BATCH(); + } } extern int r300EmitArrays(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index a3085736498..a3353db520a 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -56,9 +56,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_reg.h" #include "r300_emit.h" #include "r300_fragprog.h" +#include "r300_context.h" #include "vblank.h" +#define R200_3D_DRAW_IMMD_2 0xC0003500 + #define CLEARBUFFER_COLOR 0x1 #define CLEARBUFFER_DEPTH 0x2 #define CLEARBUFFER_STENCIL 0x4 @@ -79,7 +82,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, dPriv->w, dPriv->h); if (rrb) { - cbpitch = rrb->pitch; + cbpitch = (rrb->pitch / rrb->cpp); if (rrb->cpp == 4) cbpitch |= R300_COLOR_FORMAT_ARGB8888; else @@ -105,11 +108,11 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, #if 1 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) { assert(rrbd != 0); - cbpitch = rrbd->pitch; + cbpitch = (rrbd->pitch / rrbd->cpp); if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ cbpitch |= R300_DEPTHMACROTILE_ENABLE; } - if (r300->radeon.glCtx->Visual.depthBits == 24) { + if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ cbpitch |= R300_DEPTHMICROTILE_TILED; } BEGIN_BATCH_NO_AUTOSTATE(4); @@ -119,7 +122,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, END_BATCH(); } #endif - BEGIN_BATCH_NO_AUTOSTATE(15); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1); if (flags & CLEARBUFFER_COLOR) { OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) | @@ -130,7 +133,6 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, OUT_BATCH(0); } - OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); { uint32_t t1, t2; @@ -157,22 +159,40 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, R300_S_FRONT_ZFAIL_OP_SHIFT); } + OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); OUT_BATCH(t1); OUT_BATCH(t2); - OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << R300_STENCILWRITEMASK_SHIFT) | + OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << + R300_STENCILWRITEMASK_SHIFT) | (ctx->Stencil.Clear & R300_STENCILREF_MASK)); + END_BATCH(); } - OUT_BATCH(cmdpacket3(R300_CMD_PACKET3_CLEAR)); - OUT_BATCH_FLOAT32(dPriv->w / 2.0); - OUT_BATCH_FLOAT32(dPriv->h / 2.0); - OUT_BATCH_FLOAT32(ctx->Depth.Clear); - OUT_BATCH_FLOAT32(1.0); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); - END_BATCH(); + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + BEGIN_BATCH_NO_AUTOSTATE(9); + OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR)); + OUT_BATCH_FLOAT32(dPriv->w / 2.0); + OUT_BATCH_FLOAT32(dPriv->h / 2.0); + OUT_BATCH_FLOAT32(ctx->Depth.Clear); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); + END_BATCH(); + } else { + OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); + OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | + (1 << R300_PRIM_NUM_VERTICES_SHIFT)); + OUT_BATCH_FLOAT32(dPriv->w / 2.0); + OUT_BATCH_FLOAT32(dPriv->h / 2.0); + OUT_BATCH_FLOAT32(ctx->Depth.Clear); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); + } r300EmitCacheFlush(rmesa); cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); @@ -379,7 +399,7 @@ static void r300EmitClearState(GLcontext * ctx) OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0)); - OUT_BATCH(cmdr500fp(0, 1, 0, 0)); + OUT_BATCH(cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0)); OUT_BATCH(R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | @@ -456,10 +476,12 @@ static void r300EmitClearState(GLcontext * ctx) END_BATCH(); if (has_tcl) { + struct r300_state_atom vpu; + uint32_t _cmd[10]; R300_STATECHANGE(r300, pvs); R300_STATECHANGE(r300, vpi); - BEGIN_BATCH(13); + BEGIN_BATCH(4); OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3); OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) | (0 << R300_PVS_XYZW_VALID_INST_SHIFT) | @@ -467,18 +489,37 @@ static void r300EmitClearState(GLcontext * ctx) OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | (0 << R300_PVS_MAX_CONST_ADDR_SHIFT)); OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); - - OUT_BATCH(cmdvpu(0, 2)); - OUT_BATCH(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT)); - OUT_BATCH(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_BATCH(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_BATCH(0x0); - - OUT_BATCH(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, PVS_DST_REG_OUT)); - OUT_BATCH(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_BATCH(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_BATCH(0x0); END_BATCH(); + + vpu.check = check_vpu; + vpu.cmd = _cmd; + vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2); + + vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, + 0, 0xf, PVS_DST_REG_OUT); + vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, + PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, + PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + vpu.cmd[4] = 0x0; + + vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, + PVS_DST_REG_OUT); + vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, + PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, + PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, + VSF_FLAG_NONE); + vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + vpu.cmd[8] = 0x0; + emit_vpu(r300, &vpu); } } @@ -542,7 +583,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) r300EnsureCmdBufSpace(r300, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); - rrbd = (void *)r300->radeon.state.depth_buffer; + rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; diff --git a/src/mesa/drivers/dri/r300/r300_mipmap_tree.c b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c index 81ad7ea3280..097f9cdfece 100644 --- a/src/mesa/drivers/dri/r300/r300_mipmap_tree.c +++ b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c @@ -163,7 +163,10 @@ r300_mipmap_tree* r300_miptree_create(r300ContextPtr rmesa, r300TexObj *t, calculate_miptree_layout(mt); - mt->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, mt->totalsize, 1024, 0); + mt->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, mt->totalsize, 1024, + RADEON_GEM_DOMAIN_VRAM, + 0); return mt; } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 1762d4cb03b..f281e28e427 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -179,7 +179,7 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, n_elts * 4, 4, - RADEON_GEM_DOMAIN_GTT); + RADEON_GEM_DOMAIN_GTT, 0); rmesa->state.elt_dma_offset = 0; radeon_bo_map(rmesa->state.elt_dma_bo, 1); out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; @@ -199,11 +199,23 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit); + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); OUT_BATCH_RELOC(0, rmesa->state.elt_dma_bo, rmesa->state.elt_dma_offset, 0); OUT_BATCH(vertex_count); + } else { + OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); + OUT_BATCH(rmesa->state.elt_dma_offset); + OUT_BATCH(vertex_count); + radeon_cs_write_reloc(rmesa->cmdbuf.cs, + rmesa->state.elt_dma_bo, + 0, + rmesa->state.elt_dma_bo->size, + 0); + } END_BATCH(); } } @@ -223,6 +235,8 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); + + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->state.aos[i].components << 0) | (rmesa->state.aos[i].stride << 8) | @@ -243,6 +257,52 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH_RELOC(0, rmesa->state.aos[nr - 1].bo, rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride, 0); } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->state.aos[i].components << 0) | + (rmesa->state.aos[i].stride << 8) | + (rmesa->state.aos[i + 1].components << 16) | + (rmesa->state.aos[i + 1].stride << 24)); + + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | + (rmesa->state.aos[nr - 1].stride << 8)); + OUT_BATCH(rmesa->state.aos[nr - 1].offset + offset * 4 * + rmesa->state.aos[nr - 1].stride); + } + for (i = 0; i + 1 < nr; i += 2) { + #if 0 + fprintf(stderr, "3D_LOAD_VBPNTR 0x%08X & 0x%08X\n", + rmesa->state.aos[i+0].bo->handle, + rmesa->state.aos[i+1].bo->handle); + #endif + radeon_cs_write_reloc(rmesa->cmdbuf.cs, + rmesa->state.aos[i+0].bo, + 0, + rmesa->state.aos[i+0].bo->size, + 0); + radeon_cs_write_reloc(rmesa->cmdbuf.cs, + rmesa->state.aos[i+1].bo, + 0, + rmesa->state.aos[i+1].bo->size, + 0); + } + if (nr & 1) { + radeon_cs_write_reloc(rmesa->cmdbuf.cs, + rmesa->state.aos[nr-1].bo, + 0, + rmesa->state.aos[nr-1].bo->size, + 0); + } + } END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 44f9510d3ce..c79e69ae04c 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1101,10 +1101,19 @@ static void r300UpdateWindow(GLcontext * ctx) static void r300Viewport(GLcontext * ctx, GLint x, GLint y, GLsizei width, GLsizei height) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); + __DRIcontext *driContext = rmesa->radeon.dri.context; /* Don't pipeline viewport changes, conflict with window offset * setting below. Could apply deltas to rescue pipelined viewport * values, or keep the originals hanging around. */ + if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + radeon_update_renderbuffers(driContext, driContext->driDrawablePriv); + if (driContext->driDrawablePriv != driContext->driReadablePriv) { + radeon_update_renderbuffers(driContext, + driContext->driReadablePriv); + } + } r300UpdateWindow(ctx); } @@ -1164,21 +1173,6 @@ void r300UpdateDrawBuffer(GLcontext * ctx) assert(rrb->pitch); R300_STATECHANGE(rmesa, cb); - -#if 0 - R200_STATECHANGE(rmesa, ctx); - - /* Note: we used the (possibly) page-flipped values */ - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->r200Screen->fbLocation) - & R200_COLOROFFSET_MASK); - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; - - if (rmesa->sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= - R200_COLOR_TILE_ENABLE; - } -#endif } static void @@ -1398,7 +1392,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) } r300->hw.fpt.cmd[R300_FPT_CMD_0] = - cmdpacket0(R300_US_TEX_INST_0, code->tex.length); + cmdpacket0(r300->radeon.radeonScreen, + R300_US_TEX_INST_0, code->tex.length); } static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) @@ -1541,21 +1536,21 @@ static void r300SetupTextures(GLcontext * ctx) } r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FILTER0_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1); r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FILTER1_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1); r300->hw.tex.size.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_SIZE_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1); r300->hw.tex.format.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FORMAT_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1); r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FORMAT2_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1); r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_OFFSET_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1); r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_CHROMA_KEY_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1); r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_BORDER_COLOR_0, last_hw_tmu + 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1); if (!fp) /* should only happenen once, just after context is created */ return; @@ -1567,7 +1562,7 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1; r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0; r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(R300_TX_FILTER0_0, 1); + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1); } r300SetupFragmentShaderTextures(ctx, tmu_mappings); } else @@ -1729,7 +1724,7 @@ static void r300SetupRSUnit(GLcontext * ctx) | R300_HIRES_EN; assert(high_rr >= 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr + 1); r300->hw.rc.cmd[2] = high_rr; if (InputsRead) @@ -1889,7 +1884,7 @@ static void r500SetupRSUnit(GLcontext * ctx) | R300_HIRES_EN; assert(high_rr >= 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R500_RS_INST_0, high_rr + 1); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr + 1); r300->hw.rc.cmd[2] = 0xC0 | high_rr; if (InputsRead) @@ -2087,6 +2082,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa) (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); } + static void r300SetupVertexProgram(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; @@ -2173,6 +2169,7 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) static void r300ResetHwState(r300ContextPtr r300) { GLcontext *ctx = r300->radeon.glCtx; + struct radeon_renderbuffer *rrb; int has_tcl = 1; if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) @@ -2364,8 +2361,8 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - - if (r300->radeon.sarea->tiling_enabled) { + rrb = r300->radeon.state.depth_buffer; + if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { /* XXX: Turn off when clearing buffers ? */ r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; @@ -2499,10 +2496,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) R300_STATECHANGE(rmesa, fpi[1]); R300_STATECHANGE(rmesa, fpi[2]); R300_STATECHANGE(rmesa, fpi[3]); - rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, code->alu.length); - rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, code->alu.length); - rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, code->alu.length); - rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, code->alu.length); + rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length); + rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length); + rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length); + rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length); for (i = 0; i < code->alu.length; i++) { rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; @@ -2533,7 +2530,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) } R300_STATECHANGE(rmesa, fpp); - rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, code->const_nr * 4); + rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, code->const_nr * 4); for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, &fp->mesa_program.Base, code->constant[i]); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index f21766b4d8f..43a2599dfec 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -271,7 +271,7 @@ r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) GLuint bytes = vsize * nverts; rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bytes, 4, RADEON_GEM_DOMAIN_GTT); + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); radeon_bo_map(rmesa->swtcl.bo, 1); if (rmesa->swtcl.flush == NULL) { rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index e62cf46d1e4..e65b8c1cc47 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -220,7 +220,7 @@ void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) ctx = radeon->glCtx; if (ctx->Visual.doubleBufferMode) { - _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ + _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ if (radeon->doPageFlip) { radeonPageFlip(dPriv); } else { @@ -276,10 +276,11 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, radeon->radeonScreen->fbLocation, size, 4096, + RADEON_GEM_DOMAIN_VRAM, 0); } rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; } if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { if (!rb->bo) { @@ -288,10 +289,11 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, radeon->radeonScreen->fbLocation, size, 4096, + RADEON_GEM_DOMAIN_VRAM, 0); } rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; } if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { if (!rb->bo) { @@ -300,13 +302,122 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, radeon->radeonScreen->fbLocation, size, 4096, + RADEON_GEM_DOMAIN_VRAM, 0); } rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; } } +void +radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) +{ + unsigned int attachments[10]; + __DRIbuffer *buffers; + __DRIscreen *screen; + struct radeon_renderbuffer *rb; + int i, count; + GLframebuffer *draw; + radeonContextPtr radeon; + + draw = drawable->driverPrivate; + screen = context->driScreenPriv; + radeon = (radeonContextPtr) context->driverPrivate; + i = 0; + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_DEPTH; + } + + buffers = (*screen->dri2.loader->getBuffers)(drawable, + &drawable->w, + &drawable->h, + attachments, i, + &count, + drawable->loaderPrivate); + if (buffers == NULL) + return; + + /* set one cliprect to cover the whole drawable */ + drawable->x = 0; + drawable->y = 0; + drawable->backX = 0; + drawable->backY = 0; + drawable->numClipRects = 1; + drawable->pClipRects[0].x1 = 0; + drawable->pClipRects[0].y1 = 0; + drawable->pClipRects[0].x2 = drawable->w; + drawable->pClipRects[0].y2 = drawable->h; + drawable->numBackClipRects = 1; + drawable->pBackClipRects[0].x1 = 0; + drawable->pBackClipRects[0].y1 = 0; + drawable->pBackClipRects[0].x2 = drawable->w; + drawable->pBackClipRects[0].y2 = drawable->h; + for (i = 0; i < count; i++) { + switch (buffers[i].attachment) { + case __DRI_BUFFER_FRONT_LEFT: + rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + if (rb->bo == NULL) { + fprintf(stderr, "failled to attach front %d\n", + buffers[i].name); + } + break; + case __DRI_BUFFER_BACK_LEFT: + rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_DEPTH: + rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_STENCIL: + break; + case __DRI_BUFFER_ACCUM: + default: + fprintf(stderr, + "unhandled buffer attach event, attacment type %d\n", + buffers[i].attachment); + return; + } + } + radeon = (radeonContextPtr) context->driverPrivate; + driUpdateFramebufferSize(radeon->glCtx, drawable); +} + /* Force the context `c' to be the current context and associate with it * buffer `b'. @@ -324,11 +435,21 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, _mesa_make_current(NULL, NULL, NULL); return GL_TRUE; } - radeon = (radeonContextPtr) driContextPriv->driverPrivate; dfb = driDrawPriv->driverPrivate; rfb = driReadPriv->driverPrivate; + if (driContextPriv->driScreenPriv->dri2.enabled) { + radeon_update_renderbuffers(driContextPriv, driDrawPriv); + if (driDrawPriv != driReadPriv) + radeon_update_renderbuffers(driContextPriv, driReadPriv); + radeon->state.color.rrb = + (void *)dfb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + radeon->state.depth_buffer = + (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + } + + if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); @@ -336,7 +457,9 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (driReadPriv != driDrawPriv) driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - radeon_make_renderbuffer_current(radeon, dfb); + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeon_make_renderbuffer_current(radeon, dfb); + } _mesa_make_current(radeon->glCtx, dfb, rfb); @@ -364,7 +487,9 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, _mesa_update_state(radeon->glCtx); - radeonUpdatePageFlipping(radeon); + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeonUpdatePageFlipping(radeon); + } if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "End %s\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index 5658df7d1b3..d5bbf2928df 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -203,6 +203,7 @@ extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv); extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); +void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); /* ================================================================ * Debugging: diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h index a344837f475..eaef49c3253 100644 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ b/src/mesa/drivers/dri/r300/radeon_lock.h @@ -97,19 +97,23 @@ extern int prevLockLine; do { \ char __ret = 0; \ DEBUG_CHECK_LOCK(); \ + if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ DRM_CAS((rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret); \ if (__ret) \ radeonGetLock((rmesa), 0); \ + }\ DEBUG_LOCK(); \ } while (0) #define UNLOCK_HARDWARE( rmesa ) \ do { \ + if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ DRM_UNLOCK((rmesa)->dri.fd, \ (rmesa)->dri.hwLock, \ (rmesa)->dri.hwContext); \ DEBUG_RESET(); \ + }\ } while (0) #endif /* __RADEON_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c index b12b19f24e1..30dde809948 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -61,8 +61,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct radeon_renderbuffer *rrb = (void *) rb; \ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ - GLubyte *buf = (GLubyte *) ((char*)rrb->bo->ptr) \ - + (dPriv->y * rrb->pitch + dPriv->x) * rrb->cpp; \ GLuint p; \ (void)p; @@ -71,8 +69,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; \ - GLubyte *buf = (GLubyte *) rrb->bo->ptr; + GLuint yo = dPriv->y; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -82,6 +79,133 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define HW_UNLOCK() +static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + nmacroblkpl = rrb->pitch >> 5; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x >> 5) << 11; + offset += ((x & 31) >> 2) << 5; + offset += (x & 3) << 2; + } else { + nmacroblkpl = rrb->pitch >> 6; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x >> 6) << 11; + offset += ((x & 63) >> 3) << 5; + offset += (x & 7) << 2; + } + } else { + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x >> 3) << 5; + offset += (x & 7) << 2; + } + } + return &ptr[offset]; +} + +static GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + nmacroblkpl = rrb->pitch >> 6; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x >> 6) << 11; + offset += ((x & 63) >> 3) << 5; + offset += (x & 7) << 1; + } else { + nmacroblkpl = rrb->pitch >> 7; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x >> 7) << 11; + offset += ((x & 127) >> 4) << 5; + offset += (x & 15) << 2; + } + } else { + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x >> 4) << 5; + offset += (x & 15) << 2; + } + } + return &ptr[offset]; +} + +static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint microblkxs; + GLint macroblkxs; + GLint nmacroblkpl; + GLint nmicroblkpl; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + microblkxs = 16 / rrb->cpp; + macroblkxs = 128 / rrb->cpp; + nmacroblkpl = rrb->pitch / macroblkxs; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x / macroblkxs) << 11; + offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } else { + microblkxs = 32 / rrb->cpp; + macroblkxs = 256 / rrb->cpp; + nmacroblkpl = rrb->pitch / macroblkxs; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x / macroblkxs) << 11; + offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } + } else { + microblkxs = 32 / rrb->cpp; + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } + } + return &ptr[offset]; +} + /* ================================================================ * Color buffer */ @@ -93,7 +217,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) (buf + ((Y) * rrb->pitch + (X)) * 2) +#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -103,7 +227,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) (buf + ((Y) * rrb->pitch + (X)) * 4) +#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) #include "spantmp2.h" /* ================================================================ @@ -120,66 +244,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * too... */ -static GLuint radeon_mba_z32(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLuint pitch = rrb->pitch; - if (rrb->depthHasSurface) { - return 4 * (x + y * pitch); - } else { - GLuint ba, address = 0; /* a[0..1] = 0 */ - -#ifdef COMPILE_R300 - ba = (y / 8) * (pitch / 8) + (x / 8); -#else - ba = (y / 16) * (pitch / 16) + (x / 16); -#endif - - address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */ - address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */ - address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */ - address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ - - return address; - } -} - -static INLINE GLuint -radeon_mba_z16(const struct radeon_renderbuffer *rrb, GLint x, GLint y) -{ - GLuint pitch = rrb->pitch; - if (rrb->depthHasSurface) { - return 2 * (x + y * pitch); - } else { - GLuint ba, address = 0; /* a[0] = 0 */ - - ba = (y / 16) * (pitch / 32) + (x / 32); - - address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */ - address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */ - address |= (x & 0x8) << 4; /* a[7] = x[3] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */ - address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ - - return address; - } -} - /* 16-bit depth buffer functions */ #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo )) = d; + *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo )); + d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -194,35 +267,36 @@ radeon_mba_z16(const struct radeon_renderbuffer *rrb, GLint x, GLint y) #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ + GLuint tmp = *_ptr; \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ + GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #endif #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint *)(buf + radeon_mba_z32( rrb, _x + xo, \ - _y + yo )) & 0xffffff00) >> 8; \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + radeon_mba_z32( rrb, _x + xo, \ - _y + yo )) & 0x00ffffff; + d = *(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo )) & 0x00ffffff; #endif - +/* + fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\ + d = *(GLuint*)(radeon_ptr(rrb, _x + xo, _y + yo )) & 0x00ffffff; +*/ #define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" @@ -235,35 +309,35 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #endif #ifdef COMPILE_R300 #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ + GLuint tmp = *_ptr; \ d = tmp & 0x000000ff; \ } while (0) #else #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ + GLuint tmp = *_ptr; \ d = (tmp & 0xff000000) >> 24; \ } while (0) #endif @@ -274,9 +348,14 @@ do { \ static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) { struct radeon_renderbuffer *rrb = (void*)rb; + int r; if (rrb->bo) { - radeon_bo_map(rrb->bo, write); + r = radeon_bo_map(rrb->bo, write); + if (r) { + fprintf(stderr, "(%s) error(%d) mapping buffer.\n", + __FUNCTION__, r); + } } } diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c index 024190317b8..9cce179308b 100644 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ b/src/mesa/drivers/dri/r300/radeon_state.c @@ -153,6 +153,7 @@ void radeonSetCliprects(radeonContextPtr radeon) GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; + if (!radeon->radeonScreen->driScreen->dri2.enabled) { if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { /* Can't ignore 2d windows if we are page flipping. */ if (drawable->numBackClipRects == 0 || radeon->doPageFlip || @@ -168,6 +169,7 @@ void radeonSetCliprects(radeonContextPtr radeon) radeon->numClipRects = drawable->numClipRects; radeon->pClipRects = drawable->pClipRects; } + } if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) { diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 580ff374c77..d57b19de8dd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -233,6 +233,7 @@ static void legacy_track_pending(struct bo_manager_legacy *boml) static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, uint32_t size, uint32_t alignment, + uint32_t domains, uint32_t flags) { struct bo_legacy *bo_legacy; @@ -245,6 +246,7 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, bo_legacy->base.handle = 0; bo_legacy->base.size = size; bo_legacy->base.alignment = alignment; + bo_legacy->base.domains = domains; bo_legacy->base.flags = flags; bo_legacy->base.ptr = NULL; bo_legacy->map_count = 0; @@ -337,7 +339,7 @@ static void bo_free(struct bo_legacy *bo_legacy) } if (!bo_legacy->static_bo) { legacy_free_handle(boml, bo_legacy->base.handle); - if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) { + if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) { /* dma buffers */ bo_dma_free(&bo_legacy->base); } else { @@ -353,6 +355,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, uint32_t handle, uint32_t size, uint32_t alignment, + uint32_t domains, uint32_t flags) { struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom; @@ -371,14 +374,14 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, return NULL; } - bo_legacy = bo_allocate(boml, size, alignment, flags); + bo_legacy = bo_allocate(boml, size, alignment, domains, flags); bo_legacy->static_bo = 0; r = legacy_new_handle(boml, &bo_legacy->base.handle); if (r) { bo_free(bo_legacy); return NULL; } - if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) { + if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) { legacy_track_pending(boml); /* dma buffers */ r = bo_dma_alloc(&(bo_legacy->base)); @@ -555,7 +558,7 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo, *eoffset = bo_legacy->offset + bo->size; return 0; } - if (!(bo->flags & RADEON_GEM_DOMAIN_GTT)) { + if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) { r = bo_vram_validate(bo, soffset, eoffset); if (r) { return r; @@ -650,7 +653,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) /* biggest framebuffer size */ size = 4096*4096*4; /* allocate front */ - bo = bo_allocate(bom, size, 0, 0); + bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (bo == NULL) { radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); return NULL; @@ -666,7 +669,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) bom->nhandle = bo->base.handle + 1; } /* allocate back */ - bo = bo_allocate(bom, size, 0, 0); + bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (bo == NULL) { radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); return NULL; @@ -682,14 +685,15 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) bom->nhandle = bo->base.handle + 1; } /* allocate depth */ - bo = bo_allocate(bom, size, 0, 0); + bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (bo == NULL) { radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); return NULL; } bo->base.flags = 0; if (scrn->sarea->tiling_enabled) { - bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; + bo->base.flags |= RADEON_BO_FLAGS_MACRO_TILE; + bo->base.flags |= RADEON_BO_FLAGS_MICRO_TILE; } bo->static_bo = 1; bo->offset = bom->screen->depthOffset + bom->fb_location; @@ -711,7 +715,7 @@ unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo) { struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; - if (bo_legacy->static_bo || (bo->flags & RADEON_GEM_DOMAIN_GTT)) { + if (bo_legacy->static_bo || (bo->domains & RADEON_GEM_DOMAIN_GTT)) { return 0; } return bo->size; diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h index d41558f2e0e..d32809ef1a6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_buffer.h +++ b/src/mesa/drivers/dri/radeon/radeon_buffer.h @@ -39,7 +39,8 @@ struct radeon_renderbuffer unsigned int height; /* boo Xorg 6.8.2 compat */ - int depthHasSurface; + int has_surface; + __DRIdrawablePrivate *dPriv; }; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index a2a8423e6a7..8de928692a0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -270,22 +270,30 @@ static int cs_emit(struct radeon_cs *cs) int r; /* please flush pipe do all pending work */ - cs_write_dword(cs, cmdpacket0(R300_SC_SCREENDOOR, 1)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_SC_SCREENDOOR, 1)); cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(R300_SC_SCREENDOOR, 1)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_SC_SCREENDOOR, 1)); cs_write_dword(cs, 0x00FFFFFF); - cs_write_dword(cs, cmdpacket0(R300_SC_HYPERZ, 1)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_SC_HYPERZ, 1)); cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(R300_US_CONFIG, 1)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_US_CONFIG, 1)); cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(R300_ZB_CNTL, 1)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_ZB_CNTL, 1)); cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdwait(R300_WAIT_3D)); - cs_write_dword(cs, cmdpacket0(R300_RB3D_DSTCACHE_CTLSTAT, 1)); + cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, R300_WAIT_3D)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_RB3D_DSTCACHE_CTLSTAT, 1)); cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - cs_write_dword(cs, cmdpacket0(R300_ZB_ZCACHE_CTLSTAT, 1)); + cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, + R300_ZB_ZCACHE_CTLSTAT, 1)); cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); - cs_write_dword(cs, cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN)); + cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, + R300_WAIT_3D | R300_WAIT_3D_CLEAN)); /* append buffer age */ age.scratch.cmd_type = R300_CMD_SCRATCH; @@ -318,8 +326,15 @@ static int cs_emit(struct radeon_cs *cs) } r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); + if (r) { + return r; + } cs_set_age(cs); - return r; + for (int i = 0; i < cs->cdw; i++) { + fprintf(stderr, "pkt[%04d]=0x%08X\n", i, cs->packets[i]); + } + exit(0); + return 0; } static int cs_destroy(struct radeon_cs *cs) @@ -374,3 +389,8 @@ struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx) csm->pending_age = 1; return (struct radeon_cs_manager*)csm; } + +void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm) +{ + free(csm); +} diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h index 6ab384e9789..cf0f20ec309 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h @@ -36,5 +36,6 @@ #include "radeon_context.h" struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx); +void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 861310de659..4f76fcf4109 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -72,6 +72,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "xmlpool.h" #include "radeon_bo_legacy.h" +#include "radeon_bo_gem.h" #if !RADEON_COMMON /* R100 */ PUBLIC const char __driConfigOptions[] = @@ -972,30 +973,100 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return screen; } -/* Destroy the device specific screen private data struct. - */ -static void -radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +static radeonScreenPtr +radeonCreateScreen2(__DRIscreenPrivate *sPriv) { - radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; + radeonScreenPtr screen; + int i; + + /* Allocate the private area */ + screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); + if ( !screen ) { + __driUtilMessage("%s: Could not allocate memory for screen structure", + __FUNCTION__); + fprintf(stderr, "leaving here\n"); + return NULL; + } + +#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); +#endif + + /* parse information in __driConfigOptions */ + driParseOptionInfo (&screen->optionCache, + __driConfigOptions, __driNConfigOptions); + + screen->chip_flags = 0; + /* FIXME: do either an ioctl (bad) or a sysfs file for driver to + * information about which chipset is their */ + screen->chip_family = CHIP_FAMILY_RV350; + screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CLASS_R300; - if (!screen) - return; + i = 0; + screen->extensions[i++] = &driCopySubBufferExtension.base; + screen->extensions[i++] = &driFrameTrackingExtension.base; + screen->extensions[i++] = &driReadDrawableExtension; + + if ( screen->irq != 0 ) { + screen->extensions[i++] = &driSwapControlExtension.base; + screen->extensions[i++] = &driMediaStreamCounterExtension.base; + } + +#if !RADEON_COMMON + screen->extensions[i++] = &radeonTexOffsetExtension.base; +#endif - radeon_bo_manager_legacy_shutdown(screen->bom); +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) + screen->extensions[i++] = &r200AllocateExtension.base; + + screen->extensions[i++] = &r200texOffsetExtension.base; +#endif + +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + //screen->extensions[i++] = &r300texOffsetExtension.base; +#endif + + screen->extensions[i++] = NULL; + sPriv->extensions = screen->extensions; - if ( screen->gartTextures.map ) { - drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); + screen->driScreen = sPriv; + screen->bom = radeon_bo_manager_gem(sPriv->fd); + if (screen->bom == NULL) { + free(screen); + return NULL; } - drmUnmapBufs( screen->buffers ); - drmUnmap( screen->status.map, screen->status.size ); - drmUnmap( screen->mmio.map, screen->mmio.size ); + return screen; +} - /* free all option information */ - driDestroyOptionInfo (&screen->optionCache); +/* Destroy the device specific screen private data struct. + */ +static void +radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +{ + radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; + + if (!screen) + return; + + if (sPriv->dri2.enabled) { + radeon_bo_manager_gem_shutdown(screen->bom); + } else { + radeon_bo_manager_legacy_shutdown(screen->bom); + + if ( screen->gartTextures.map ) { + drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); + } + drmUnmapBufs( screen->buffers ); + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + } + + /* free all option information */ + driDestroyOptionInfo (&screen->optionCache); - FREE( screen ); - sPriv->private = NULL; + FREE( screen ); + sPriv->private = NULL; } @@ -1004,13 +1075,17 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) static GLboolean radeonInitDriver( __DRIscreenPrivate *sPriv ) { - sPriv->private = (void *) radeonCreateScreen( sPriv ); - if ( !sPriv->private ) { - radeonDestroyScreen( sPriv ); - return GL_FALSE; - } + if (sPriv->dri2.enabled) { + sPriv->private = (void *) radeonCreateScreen2( sPriv ); + } else { + sPriv->private = (void *) radeonCreateScreen( sPriv ); + } + if ( !sPriv->private ) { + radeonDestroyScreen( sPriv ); + return GL_FALSE; + } - return GL_TRUE; + return GL_TRUE; } #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) @@ -1130,6 +1205,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, struct radeon_renderbuffer *front = radeon_create_renderbuffer(rgbFormat, driDrawPriv); _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); + front->has_surface = 1; } /* back color renderbuffer */ @@ -1137,6 +1213,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, struct radeon_renderbuffer *back = radeon_create_renderbuffer(rgbFormat, driDrawPriv); _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); + back->has_surface = 1; } /* depth renderbuffer */ @@ -1144,7 +1221,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, struct radeon_renderbuffer *depth = radeon_create_renderbuffer(depthFormat, driDrawPriv); _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); - depth->depthHasSurface = screen->depthHasSurface; + depth->has_surface = screen->depthHasSurface; } /* stencil renderbuffer */ @@ -1152,7 +1229,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, struct radeon_renderbuffer *stencil = radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); - stencil->depthHasSurface = screen->depthHasSurface; + stencil->has_surface = screen->depthHasSurface; } _mesa_add_soft_renderbuffers(fb, @@ -1227,7 +1304,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, driDrawPriv); radeonSetSpanFunctions(depthRb, mesaVis); _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - depthRb->depthHasSurface = screen->depthHasSurface; + depthRb->has_surface = screen->depthHasSurface; } else if (mesaVis->depthBits == 24) { driRenderbuffer *depthRb @@ -1238,7 +1315,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, driDrawPriv); radeonSetSpanFunctions(depthRb, mesaVis); _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - depthRb->depthHasSurface = screen->depthHasSurface; + depthRb->has_surface = screen->depthHasSurface; } /* stencil renderbuffer */ @@ -1251,7 +1328,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, driDrawPriv); radeonSetSpanFunctions(stencilRb, mesaVis); _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); - stencilRb->depthHasSurface = screen->depthHasSurface; + stencilRb->has_surface = screen->depthHasSurface; } _mesa_add_soft_renderbuffers(fb, @@ -1369,6 +1446,45 @@ radeonInitScreen(__DRIscreenPrivate *psp) (dri_priv->bpp == 16) ? 0 : 8, 1); } +/** + * This is the driver specific part of the createNewScreen entry point. + * Called when using DRI2. + * + * \return the __GLcontextModes supported by this driver + */ +static const +__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) +{ + fprintf(stderr, "DRI2 initialization\n"); + + /* Calling driInitExtensions here, with a NULL context pointer, + * does not actually enable the extensions. It just makes sure + * that all the dispatch offsets for all the extensions that + * *might* be enables are known. This is needed because the + * dispatch offsets need to be known when _mesa_context_create + * is called, but we can't enable the extensions until we have a + * context pointer. + * + * Hello chicken. Hello egg. How are you two today? + */ + driInitExtensions( NULL, card_extensions, GL_FALSE ); +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + driInitExtensions( NULL, blend_extensions, GL_FALSE ); + driInitSingleExtension( NULL, ARB_vp_extension ); + driInitSingleExtension( NULL, NV_vp_extension ); + driInitSingleExtension( NULL, ATI_fs_extension ); + driInitExtensions( NULL, point_extensions, GL_FALSE ); +#endif + + if (!radeonInitDriver(psp)) { + return NULL; + } + + fprintf(stderr, "DRI2 initialized\n"); + + /* for now fill in all modes */ + return radeonFillInModes( psp, 24, 24, 8, 1); +} /** * Get information about previous buffer swaps. @@ -1417,6 +1533,8 @@ const struct __DriverAPIRec driDriverAPI = { .WaitForSBC = NULL, .SwapBuffersMSC = NULL, .CopySubBuffer = radeonCopySubBuffer, + /* DRI2 */ + .InitScreen2 = radeonInitScreen2, }; #else const struct __DriverAPIRec driDriverAPI = { -- cgit v1.2.3 From d07d1379314c9222ccb955244fa7e56bd4d03d6d Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 12 Nov 2008 14:02:57 +0100 Subject: r300: SetTex extension support --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 12 +++-- src/mesa/drivers/dri/r300/r300_context.c | 13 ++++- src/mesa/drivers/dri/r300/r300_context.h | 1 + src/mesa/drivers/dri/r300/r300_texstate.c | 75 +++++++++++++++++++++++++- src/mesa/drivers/dri/r300/radeon_context.c | 3 ++ src/mesa/drivers/dri/radeon/radeon_buffer.h | 1 + src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 9 +--- src/mesa/drivers/dri/radeon/radeon_screen.c | 16 ++++-- src/mesa/drivers/dri/radeon/radeon_screen.h | 2 +- 9 files changed, 113 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index dbb7761b3b5..9552778f541 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -74,14 +74,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller) { - int ret; + int ret = 0; if (r300->cmdbuf.flushing) { fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n"); exit(-1); } r300->cmdbuf.flushing = 1; - ret = radeon_cs_emit(r300->cmdbuf.cs); + if (r300->cmdbuf.cs->cdw) { + ret = radeon_cs_emit(r300->cmdbuf.cs); + } radeon_cs_erase(r300->cmdbuf.cs); r300->cmdbuf.flushing = 0; return ret; @@ -299,7 +301,11 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) } else if (!t) { OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); } else { - OUT_BATCH(t->override_offset); + if (t->bo) { + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 0); + } else { + OUT_BATCH(t->override_offset); + } } END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index c1e11d5e43b..5fce8413bbd 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -176,6 +176,17 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { 0, }; +static void r300RunPipeline(GLcontext * ctx) +{ + _mesa_lock_context_textures(ctx); + + if (ctx->NewState) + _mesa_update_state_locked(ctx); + + _tnl_run_pipeline(ctx); + _mesa_unlock_context_textures(ctx); +} + /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, @@ -348,7 +359,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) r300InitSwtcl(ctx); - TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline; + TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline; tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode"); if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) { diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 63bf67e76e8..aec03a81e04 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -176,6 +176,7 @@ struct r300_tex_obj { /* end hardware registers */ GLuint tile_bits; /* hw texture tile bits used on this texture */ + struct radeon_bo *bo; }; static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj) diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 33673fa0b9c..9153646aa73 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -51,6 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_mipmap_tree.h" #include "r300_tex.h" #include "r300_reg.h" +#include "radeon_buffer.h" #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5 \ || ((f) >= MESA_FORMAT_RGBA_FLOAT32 && \ @@ -328,7 +329,7 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[0][texObj->BaseLevel]); int face, level; - if (t->validated) + if (t->validated || t->image_override) return GL_TRUE; if (RADEON_DEBUG & DEBUG_TEXTURE) @@ -430,7 +431,7 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - + t->bo = NULL; t->override_offset = offset; t->pitch_reg &= (1 << 13) -1; pitch_val = pitch; @@ -457,3 +458,73 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, t->pitch_reg |= pitch_val; } + +void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + struct gl_texture_unit *texUnit; + struct gl_texture_object *texObj; + struct gl_texture_image *texImage; + struct radeon_renderbuffer *rb; + radeonContextPtr radeon; + r300ContextPtr rmesa; + GLframebuffer *fb; + r300TexObjPtr t; + uint32_t pitch_val; + + target = GL_TEXTURE_RECTANGLE_ARB; + radeon = pDRICtx->driverPrivate; + rmesa = pDRICtx->driverPrivate; + fb = dPriv->driverPrivate; + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + + radeon_update_renderbuffers(pDRICtx, dPriv); + rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; + } + + _mesa_lock_texture(radeon->glCtx, texObj); + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->width, rb->height, rb->cpp, 0, rb->cpp); + texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + + t = r300_tex_obj(texObj); + if (t == NULL) { + return; + } + t->bo = rb->bo; + t->tile_bits = 0; + t->image_override = GL_TRUE; + t->override_offset = 0; + t->pitch_reg &= (1 << 13) -1; + pitch_val = rb->pitch; + switch (rb->cpp) { + case 4: + t->format = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + t->filter |= tx_table[2].filter; + pitch_val /= 4; + break; + case 3: + default: + t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + t->filter |= tx_table[4].filter; + pitch_val /= 4; + break; + case 2: + t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); + t->filter |= tx_table[5].filter; + pitch_val /= 2; + break; + } + pitch_val--; + t->size = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) | + ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT); + t->size |= R300_TX_SIZE_TXPITCH_EN; + t->pitch_reg |= pitch_val; + t->validated = GL_TRUE; + _mesa_unlock_texture(radeon->glCtx, texObj); + return; +} diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index e65b8c1cc47..9bb95a5a325 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -365,6 +365,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; + rb->width = drawable->w; rb->height = drawable->h; rb->has_surface = 0; rb->bo = radeon_bo_open(radeon->radeonScreen->bom, @@ -382,6 +383,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; + rb->width = drawable->w; rb->height = drawable->h; rb->has_surface = 0; rb->bo = radeon_bo_open(radeon->radeonScreen->bom, @@ -395,6 +397,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; + rb->width = drawable->w; rb->height = drawable->h; rb->has_surface = 0; rb->bo = radeon_bo_open(radeon->radeonScreen->bom, diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h index d32809ef1a6..62cdfad4a0c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_buffer.h +++ b/src/mesa/drivers/dri/radeon/radeon_buffer.h @@ -36,6 +36,7 @@ struct radeon_renderbuffer unsigned int cpp; /* unsigned int offset; */ unsigned int pitch; + unsigned int width; unsigned int height; /* boo Xorg 6.8.2 compat */ diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 8de928692a0..ec3919ced69 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -309,7 +309,6 @@ static int cs_emit(struct radeon_cs *cs) radeon_cs_write_dword(cs, ull >> 32); radeon_cs_write_dword(cs, 0); - r = cs_process_relocs(cs); if (r) { return 0; @@ -330,10 +329,6 @@ static int cs_emit(struct radeon_cs *cs) return r; } cs_set_age(cs); - for (int i = 0; i < cs->cdw; i++) { - fprintf(stderr, "pkt[%04d]=0x%08X\n", i, cs->packets[i]); - } - exit(0); return 0; } @@ -362,7 +357,7 @@ static int cs_need_flush(struct radeon_cs *cs) return (cs->relocs_total_size > (7*1024*1024)); } -struct radeon_cs_funcs radeon_cs_funcs = { +static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_create, cs_write_dword, cs_write_reloc, @@ -383,7 +378,7 @@ struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx) if (csm == NULL) { return NULL; } - csm->base.funcs = &radeon_cs_funcs; + csm->base.funcs = &radeon_cs_legacy_funcs; csm->base.fd = ctx->dri.fd; csm->ctx = ctx; csm->pending_age = 1; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 4f76fcf4109..9cc91ac197f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -349,6 +349,14 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, r300SetTexOffset, }; + +void r300SetTexBuffer(__DRIcontext *pDRICtx, + GLint target, + __DRIdrawable *dPriv); +static const __DRItexBufferExtension r300TexBufferExtension = { + { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, + r300SetTexBuffer, +}; #endif /* Create the device specific screen private data struct. @@ -1024,7 +1032,8 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - //screen->extensions[i++] = &r300texOffsetExtension.base; + screen->extensions[i++] = &r300texOffsetExtension.base; + screen->extensions[i++] = &r300TexBufferExtension.base; #endif screen->extensions[i++] = NULL; @@ -1455,8 +1464,6 @@ radeonInitScreen(__DRIscreenPrivate *psp) static const __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) { - fprintf(stderr, "DRI2 initialization\n"); - /* Calling driInitExtensions here, with a NULL context pointer, * does not actually enable the extensions. It just makes sure * that all the dispatch offsets for all the extensions that @@ -1480,8 +1487,6 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) return NULL; } - fprintf(stderr, "DRI2 initialized\n"); - /* for now fill in all modes */ return radeonFillInModes( psp, 24, 24, 8, 1); } @@ -1555,3 +1560,4 @@ const struct __DriverAPIRec driDriverAPI = { .CopySubBuffer = r200CopySubBuffer, }; #endif + diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 7b9d036148e..ccddbb8ae02 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -104,7 +104,7 @@ typedef struct radeon_screen { /* Configuration cache with default values for all contexts */ driOptionCache optionCache; - const __DRIextension *extensions[8]; + const __DRIextension *extensions[16]; int num_gb_pipes; drm_radeon_sarea_t *sarea; /* Private SAREA data */ -- cgit v1.2.3 From c26ec97b1390deb7c2ae586450e621a7095dac87 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 12 Nov 2008 17:00:28 +0100 Subject: r300: convert to new relocations format (see libdrm-radeon) --- src/mesa/drivers/dri/r300/Makefile | 2 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 10 ++-- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 10 +++- src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_render.c | 60 +++++++++++++++-------- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 66 ++++++++++++++++++-------- 7 files changed, 105 insertions(+), 49 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index c041bc6ad01..d0616aaca6e 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -80,7 +80,7 @@ COMMON_SYMLINKS = \ radeon_bo_legacy.h \ radeon_cs_legacy.h -DRI_LIB_DEPS += -ldrm_radeon +DRI_LIB_DEPS += -ldrm-radeon ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 9552778f541..517860da435 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -297,12 +297,14 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); r300TexObj *t = r300->hw.textures[i]; if (t && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 0); + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); } else { if (t->bo) { - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 0); + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { OUT_BATCH(t->override_offset); } @@ -339,7 +341,7 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) BEGIN_BATCH(4); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); OUT_BATCH(cbpitch); END_BATCH(); @@ -365,7 +367,7 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) BEGIN_BATCH(4); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index b21619fd181..1a249c8d52c 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -84,14 +84,20 @@ void r300BeginBatch(r300ContextPtr r300, /** * Write a relocated dword to the command buffer. */ -#define OUT_BATCH_RELOC(data, bo, offset, flags) \ +#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ do { \ if (offset) {\ fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ __FILE__, __FUNCTION__, __LINE__, offset);\ }\ radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\ - radeon_cs_write_reloc(b_l_r300->cmdbuf.cs,bo,0,(bo)->size,flags);\ + radeon_cs_write_reloc(b_l_r300->cmdbuf.cs, \ + bo, \ + offset, \ + (bo)->size, \ + rd, \ + wd, \ + flags);\ } while(0) /** diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index a3353db520a..5202248ab77 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -101,7 +101,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, assert(rrb != 0); BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); END_BATCH(); } @@ -117,7 +117,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, } BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrbd->bo, 0, 0); + OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index f281e28e427..a8d42a2391e 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -202,8 +202,10 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - OUT_BATCH_RELOC(0, rmesa->state.elt_dma_bo, - rmesa->state.elt_dma_offset, 0); + OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, + rmesa->state.elt_dma_bo, + rmesa->state.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count); } else { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); @@ -214,7 +216,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) rmesa->state.elt_dma_bo, 0, rmesa->state.elt_dma_bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); } @@ -245,17 +247,30 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) voffset = rmesa->state.aos[i + 0].offset + offset * 4 * rmesa->state.aos[i + 0].stride; - OUT_BATCH_RELOC(0, rmesa->state.aos[i].bo, voffset, 0); + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); voffset = rmesa->state.aos[i + 1].offset + offset * 4 * rmesa->state.aos[i + 1].stride; - OUT_BATCH_RELOC(0, rmesa->state.aos[i+1].bo, voffset, 0); + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); } if (nr & 1) { OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | (rmesa->state.aos[nr - 1].stride << 8)); - OUT_BATCH_RELOC(0, rmesa->state.aos[nr - 1].bo, - rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride, 0); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { @@ -275,32 +290,37 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) if (nr & 1) { OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | (rmesa->state.aos[nr - 1].stride << 8)); - OUT_BATCH(rmesa->state.aos[nr - 1].offset + offset * 4 * - rmesa->state.aos[nr - 1].stride); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - #if 0 - fprintf(stderr, "3D_LOAD_VBPNTR 0x%08X & 0x%08X\n", - rmesa->state.aos[i+0].bo->handle, - rmesa->state.aos[i+1].bo->handle); - #endif + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[i+0].bo, - 0, + voffset, rmesa->state.aos[i+0].bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[i+1].bo, - 0, + voffset, rmesa->state.aos[i+1].bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, + 0, 0); } if (nr & 1) { + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[nr-1].bo, - 0, + voffset, rmesa->state.aos[nr-1].bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, + 0, 0); } } END_BATCH(); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 43a2599dfec..fbfa8f452b0 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -646,7 +646,7 @@ void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_b OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(0, bo, offset, 0); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index ec3919ced69..b69537bc656 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -94,19 +94,34 @@ static int cs_write_dword(struct radeon_cs *cs, uint32_t dword) static int cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, - uint32_t soffset, - uint32_t eoffset, - uint32_t domains) + uint32_t start_offset, + uint32_t end_offset, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags) { struct cs_reloc_legacy *relocs; int i; relocs = (struct cs_reloc_legacy *)cs->relocs; + /* check domains */ + if ((read_domain && write_domain) || (!read_domain && !write_domain)) { + /* in one CS a bo can only be in read or write domain but not + * in read & write domain at the same sime + */ + return -EINVAL; + } + if (read_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + if (write_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } /* check reloc window */ - if (eoffset > bo->size) { + if (end_offset > bo->size) { return -EINVAL; } - if (soffset > eoffset) { + if (start_offset > end_offset) { return -EINVAL; } /* check if bo is already referenced */ @@ -114,16 +129,28 @@ static int cs_write_reloc(struct radeon_cs *cs, uint32_t *indices; if (relocs[i].base.bo->handle == bo->handle) { - /* update start offset and size */ - if (eoffset > relocs[i].base.eoffset) { - relocs[i].base.eoffset = eoffset; + /* update start and end offset */ + if (start_offset < relocs[i].base.start_offset) { + relocs[i].base.start_offset = start_offset; + } + if (end_offset > relocs[i].base.end_offset) { + relocs[i].base.end_offset = end_offset; } - if (soffset < relocs[i].base.soffset) { - relocs[i].base.soffset = soffset; + /* Check domains must be in read or write. As we check already + * checked that in argument one of the read or write domain was + * set we only need to check that if previous reloc as the read + * domain set then the read_domain should also be set for this + * new relocation. + */ + if (relocs[i].base.read_domain && !read_domain) { + return -EINVAL; + } + if (relocs[i].base.write_domain && !write_domain) { + return -EINVAL; } - relocs[i].base.size = relocs[i].base.eoffset - - relocs[i].base.soffset; - relocs[i].base.domains |= domains; + relocs[i].base.read_domain |= read_domain; + relocs[i].base.write_domain |= write_domain; + /* save indice */ relocs[i].cindices += 1; indices = (uint32_t*)realloc(relocs[i].indices, relocs[i].cindices * 4); @@ -145,10 +172,11 @@ static int cs_write_reloc(struct radeon_cs *cs, } cs->relocs = relocs; relocs[cs->crelocs].base.bo = bo; - relocs[cs->crelocs].base.soffset = soffset; - relocs[cs->crelocs].base.eoffset = eoffset; - relocs[cs->crelocs].base.size = eoffset - soffset; - relocs[cs->crelocs].base.domains = domains; + relocs[cs->crelocs].base.start_offset = start_offset; + relocs[cs->crelocs].base.end_offset = end_offset; + relocs[cs->crelocs].base.read_domain = read_domain; + relocs[cs->crelocs].base.write_domain = write_domain; + relocs[cs->crelocs].base.flags = flags; relocs[cs->crelocs].indices = (uint32_t*)malloc(4); if (relocs[cs->crelocs].indices == NULL) { return -ENOMEM; @@ -221,8 +249,8 @@ static int cs_process_relocs(struct radeon_cs *cs) for (j = 0; j < relocs[i].cindices; j++) { uint32_t soffset, eoffset; - soffset = relocs[i].base.soffset; - eoffset = relocs[i].base.eoffset; + soffset = relocs[i].base.start_offset; + eoffset = relocs[i].base.end_offset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); if (r) { -- cgit v1.2.3 From 93a9d2f18de8517af92eba787a4eee34765481ab Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 13 Nov 2008 20:04:50 +0100 Subject: r300: release bo from pixmap --- src/mesa/drivers/dri/r300/r300_context.h | 1 + src/mesa/drivers/dri/r300/r300_tex.c | 4 ++++ src/mesa/drivers/dri/r300/r300_texstate.c | 25 +++++++++++++++++++++---- 3 files changed, 26 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index aec03a81e04..30229ed4fbc 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -139,6 +139,7 @@ struct _r300_texture_image { * by base.Data. */ struct _r300_mipmap_tree *mt; + struct radeon_bo *bo; int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index fa96cdf3774..9ceac70f5e3 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -429,6 +429,10 @@ static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage } else { _mesa_free_texture_image_data(ctx, timage); } + if (image->bo) { + radeon_bo_unref(image->bo); + image->bo = NULL; + } } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 9153646aa73..bb2f0937c13 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -465,6 +465,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) struct gl_texture_object *texObj; struct gl_texture_image *texImage; struct radeon_renderbuffer *rb; + r300_texture_image *rImage; radeonContextPtr radeon; r300ContextPtr rmesa; GLframebuffer *fb; @@ -478,6 +479,11 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + rImage = get_r300_texture_image(texImage); + t = r300_tex_obj(texObj); + if (t == NULL) { + return; + } radeon_update_renderbuffers(pDRICtx, dPriv); rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; @@ -487,14 +493,25 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) } _mesa_lock_texture(radeon->glCtx, texObj); + if (t->bo) { + t->bo = NULL; + } + if (t->mt) { + t->mt = NULL; + } + if (rImage->bo) { + radeon_bo_unref(rImage->bo); + rImage->bo = NULL; + } + if (rImage->mt) { + r300_miptree_unreference(rImage->mt); + rImage->mt = NULL; + } _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, rb->cpp, 0, rb->cpp); texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + rImage->bo = rb->bo; - t = r300_tex_obj(texObj); - if (t == NULL) { - return; - } t->bo = rb->bo; t->tile_bits = 0; t->image_override = GL_TRUE; -- cgit v1.2.3 From 5b79c18c83288eaaa6af25fdf3fe71b8347b5c1d Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 14 Nov 2008 11:25:28 +0100 Subject: radeon: dri2 don't forget to free buffer --- src/mesa/drivers/dri/r300/r300_texstate.c | 11 +++++++ src/mesa/drivers/dri/r300/radeon_context.c | 50 ++++++++++++++++++++++++++++- src/mesa/drivers/dri/radeon/radeon_screen.c | 17 ++++++++++ 3 files changed, 77 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index bb2f0937c13..30efc0b6dbc 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -486,6 +486,17 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) } radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ + rb = (void*)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb->bo == NULL) { /* Failed to BO for the buffer */ diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 9bb95a5a325..3a1ab8d96ed 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -191,6 +191,37 @@ GLboolean radeonInitContext(radeonContextPtr radeon, */ void radeonCleanupContext(radeonContextPtr radeon) { + FILE *track; + struct radeon_renderbuffer *rb; + GLframebuffer *fb; + + fb = (void*)radeon->dri.drawable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + fb = (void*)radeon->dri.readable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + /* _mesa_destroy_context() might result in calls to functions that * depend on the DriverCtx, so don't set it to NULL before. * @@ -204,6 +235,11 @@ void radeonCleanupContext(radeonContextPtr radeon) FREE(radeon->state.scissor.pClipRects); radeon->state.scissor.pClipRects = 0; } + track = fopen("/tmp/tracklog", "w"); + if (track) { + radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); + fclose(track); + } } @@ -363,6 +399,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) switch (buffers[i].attachment) { case __DRI_BUFFER_FRONT_LEFT: rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; rb->width = drawable->w; @@ -381,6 +421,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) break; case __DRI_BUFFER_BACK_LEFT: rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; rb->width = drawable->w; @@ -395,6 +439,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) break; case __DRI_BUFFER_DEPTH: rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; rb->width = drawable->w; @@ -447,7 +495,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (driDrawPriv != driReadPriv) radeon_update_renderbuffers(driContextPriv, driReadPriv); radeon->state.color.rrb = - (void *)dfb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; radeon->state.depth_buffer = (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 9cc91ac197f..93131d269cd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1059,6 +1059,7 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) return; if (sPriv->dri2.enabled) { + radeon_tracker_print(&screen->bom->tracker, stderr); radeon_bo_manager_gem_shutdown(screen->bom); } else { radeon_bo_manager_legacy_shutdown(screen->bom); @@ -1357,6 +1358,22 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) { + struct radeon_renderbuffer *rb; + GLframebuffer *fb; + + fb = (void*)driDrawPriv->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + } _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); } -- cgit v1.2.3 From 56c458e0f2027bc19b45ed3112e84b6ace67920f Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sat, 15 Nov 2008 10:40:32 +0100 Subject: radeon: update to libdrm-radeon API changes --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 8 ++++---- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 16 +++++++++------- src/mesa/drivers/dri/radeon/radeon_bo_legacy.h | 4 ++-- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 4 ++-- src/mesa/drivers/dri/radeon/radeon_cs_legacy.h | 4 ++-- src/mesa/drivers/dri/radeon/radeon_screen.c | 8 ++++---- 6 files changed, 23 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 517860da435..b8740e298ba 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -746,9 +746,9 @@ void r300InitCmdBuf(r300ContextPtr r300) if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { int fd = r300->radeon.radeonScreen->driScreen->fd; - r300->cmdbuf.csm = radeon_cs_manager_gem(fd); + r300->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); } else { - r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon); + r300->cmdbuf.csm = radeon_cs_manager_legacy_ctor(&r300->radeon); } if (r300->cmdbuf.csm == NULL) { /* FIXME: fatal error */ @@ -771,8 +771,8 @@ void r300DestroyCmdBuf(r300ContextPtr r300) FREE(atom->cmd); } if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - radeon_cs_manager_gem_shutdown(r300->cmdbuf.csm); + radeon_cs_manager_gem_dtor(r300->cmdbuf.csm); } else { - radeon_cs_manager_legacy_shutdown(r300->cmdbuf.csm); + radeon_cs_manager_legacy_dtor(r300->cmdbuf.csm); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index d57b19de8dd..3aa1d869f10 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -407,7 +407,7 @@ static void bo_ref(struct radeon_bo *bo) { } -static void bo_unref(struct radeon_bo *bo) +static struct radeon_bo *bo_unref(struct radeon_bo *bo) { struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; @@ -419,7 +419,9 @@ static void bo_unref(struct radeon_bo *bo) if (!bo_legacy->is_pending) { bo_free(bo_legacy); } + return NULL; } + return bo; } static int bo_map(struct radeon_bo *bo, int write) @@ -589,7 +591,7 @@ void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending) boml->cpendings++; } -void radeon_bo_manager_legacy_shutdown(struct radeon_bo_manager *bom) +void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom) { struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom; struct bo_legacy *bo_legacy; @@ -609,7 +611,7 @@ void radeon_bo_manager_legacy_shutdown(struct radeon_bo_manager *bom) free(boml); } -struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) +struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *scrn) { struct bo_manager_legacy *bom; struct bo_legacy *bo; @@ -646,7 +648,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) bom->nfree_handles = 0x400; bom->free_handles = (uint32_t*)malloc(bom->nfree_handles * 4); if (bom->free_handles == NULL) { - radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } @@ -655,7 +657,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) /* allocate front */ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (bo == NULL) { - radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } if (scrn->sarea->tiling_enabled) { @@ -671,7 +673,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) /* allocate back */ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (bo == NULL) { - radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } if (scrn->sarea->tiling_enabled) { @@ -687,7 +689,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn) /* allocate depth */ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (bo == NULL) { - radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom); + radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } bo->base.flags = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h index 316b023fb0f..208171e3720 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h @@ -39,8 +39,8 @@ void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending); int radeon_bo_legacy_validate(struct radeon_bo *bo, uint32_t *soffset, uint32_t *eoffset); -struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn); -void radeon_bo_manager_legacy_shutdown(struct radeon_bo_manager *bom); +struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *scrn); +void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom); void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom); unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo); diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index b69537bc656..6bc41bca3bf 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -397,7 +397,7 @@ static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_need_flush }; -struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx) +struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) { struct cs_manager_legacy *csm; @@ -413,7 +413,7 @@ struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx) return (struct radeon_cs_manager*)csm; } -void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm) +void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm) { free(csm); } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h index cf0f20ec309..71a4dad58d4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h @@ -35,7 +35,7 @@ #include "radeon_cs.h" #include "radeon_context.h" -struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx); -void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm); +struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); +void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 93131d269cd..79cc4c8c8ef 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -973,7 +973,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->sarea_priv_offset = dri_priv->sarea_priv_offset; screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + screen->sarea_priv_offset); - screen->bom = radeon_bo_manager_legacy(screen); + screen->bom = radeon_bo_manager_legacy_ctor(screen); if (screen->bom == NULL) { free(screen); return NULL; @@ -1040,7 +1040,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) sPriv->extensions = screen->extensions; screen->driScreen = sPriv; - screen->bom = radeon_bo_manager_gem(sPriv->fd); + screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); if (screen->bom == NULL) { free(screen); return NULL; @@ -1060,9 +1060,9 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) if (sPriv->dri2.enabled) { radeon_tracker_print(&screen->bom->tracker, stderr); - radeon_bo_manager_gem_shutdown(screen->bom); + radeon_bo_manager_gem_dtor(screen->bom); } else { - radeon_bo_manager_legacy_shutdown(screen->bom); + radeon_bo_manager_legacy_dtor(screen->bom); if ( screen->gartTextures.map ) { drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); -- cgit v1.2.3 From f1d98e51275eaa440e1c6b9c61e5e014faaad45a Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 16 Nov 2008 17:58:43 +0100 Subject: radeon: fix pointer dangling --- src/mesa/drivers/dri/r300/Makefile | 3 +-- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 6 +++--- src/mesa/drivers/dri/r300/r300_emit.c | 5 ++--- src/mesa/drivers/dri/r300/r300_texstate.c | 4 ---- src/mesa/drivers/dri/r300/radeon_context.c | 6 ++++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 4 ++++ 6 files changed, 16 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index d0616aaca6e..cbb09e6ce59 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -57,8 +57,7 @@ C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) DRIVER_DEFINES = -DCOMPILE_R300 -DR200_MERGED=0 \ -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300 \ -# -DRADEON_BO_TRACK_REF \ -# -DRADEON_BO_TRACK_OPEN \ +# -DRADEON_BO_TRACK \ -Wall SYMLINKS = \ diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index b8740e298ba..9d0ed698e16 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -83,6 +83,7 @@ int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller) r300->cmdbuf.flushing = 1; if (r300->cmdbuf.cs->cdw) { ret = radeon_cs_emit(r300->cmdbuf.cs); + r300->hw.all_dirty = 1; } radeon_cs_erase(r300->cmdbuf.cs); r300->cmdbuf.flushing = 0; @@ -208,8 +209,7 @@ void r300EmitState(r300ContextPtr r300) if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); - if (r300->cmdbuf.cs->cdw && !r300->hw.is_dirty - && !r300->hw.all_dirty) + if (r300->cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty) return; /* To avoid going across the entire set of states multiple times, just check @@ -325,7 +325,7 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; } - if (!rrb) { + if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; } diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index d2628633d48..4405b7a3f50 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -169,6 +169,7 @@ static void r300EmitVec(GLcontext * ctx, struct r300_aos *aos, uint32_t *out; uint32_t bo_size; + memset(aos, 0, sizeof(struct r300_aos)); if (stride == 0) { bo_size = size * 4; count = 1; @@ -428,7 +429,6 @@ int r300EmitArrays(GLcontext * ctx) for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] = ci; } - r300EmitVec(ctx, &rmesa->state.aos[i], vb->AttribPtr[tab[i]]->data, vb->AttribPtr[tab[i]]->size, @@ -486,8 +486,7 @@ void r300ReleaseArrays(GLcontext * ctx) } for (i = 0; i < rmesa->state.aos_count; i++) { if (rmesa->state.aos[i].bo) { - radeon_bo_unref(rmesa->state.aos[i].bo); - rmesa->state.aos[i].bo = 0; + rmesa->state.aos[i].bo = radeon_bo_unref(rmesa->state.aos[i].bo); } } } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 30efc0b6dbc..4fea8228910 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -510,10 +510,6 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) if (t->mt) { t->mt = NULL; } - if (rImage->bo) { - radeon_bo_unref(rImage->bo); - rImage->bo = NULL; - } if (rImage->mt) { r300_miptree_unreference(rImage->mt); rImage->mt = NULL; diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 3a1ab8d96ed..2f4d06110f9 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -199,27 +199,33 @@ void radeonCleanupContext(radeonContextPtr radeon) rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } fb = (void*)radeon->dri.readable->driverPrivate; rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } /* _mesa_destroy_context() might result in calls to functions that diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 79cc4c8c8ef..9b5f2201b29 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1179,6 +1179,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) radeonSetSpanFunctions(ret); + ret->bo = NULL; return ret; } @@ -1365,14 +1366,17 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); + rb->bo = NULL; } _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); } -- cgit v1.2.3 From 9770bb32f50659ef749751780e00d8c88e16126c Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 16 Nov 2008 17:59:46 +0100 Subject: radeon: cs add print cs callback --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 6bc41bca3bf..20956ff5c7b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -385,6 +385,10 @@ static int cs_need_flush(struct radeon_cs *cs) return (cs->relocs_total_size > (7*1024*1024)); } +static void cs_print(struct radeon_cs *cs, FILE *file) +{ +} + static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_create, cs_write_dword, @@ -394,7 +398,8 @@ static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_emit, cs_destroy, cs_erase, - cs_need_flush + cs_need_flush, + cs_print }; struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) -- cgit v1.2.3 From 72cd2c8c0c863873d280a0e49dfa381e5c3236c8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 1 Dec 2008 16:24:50 +1000 Subject: radeon: make DRI1 one work with new CS mechanism --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 8 +- src/mesa/drivers/dri/r300/r300_emit.c | 8 +- src/mesa/drivers/dri/r300/r300_emit.h | 10 +-- src/mesa/drivers/dri/r300/r300_ioctl.c | 2 +- src/mesa/drivers/dri/r300/r300_render.c | 4 +- src/mesa/drivers/dri/r300/radeon_context.c | 130 +++++++++++++++++++--------- src/mesa/drivers/dri/r300/radeon_lock.c | 3 +- src/mesa/drivers/dri/r300/radeon_state.c | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 127 ++++++++++++++++----------- src/mesa/drivers/dri/radeon/radeon_screen.h | 3 +- 10 files changed, 187 insertions(+), 110 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 9d0ed698e16..ca9d36a8b66 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -234,7 +234,7 @@ void r300EmitState(r300ContextPtr r300) static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) { - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + if (r300->radeon.radeonScreen->kernel_mm) { return ((((*pkt) >> 16) & 0x3FFF) + 1); } else { drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; @@ -252,7 +252,7 @@ void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i; - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!r300->radeon.radeonScreen->kernel_mm) { uint32_t dwords; dwords = (*atom->check) (r300, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -744,7 +744,7 @@ void r300InitCmdBuf(r300ContextPtr r300) size * 4, r300->hw.max_state_size * 4); } - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + if (r300->radeon.radeonScreen->kernel_mm) { int fd = r300->radeon.radeonScreen->driScreen->fd; r300->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); } else { @@ -770,7 +770,7 @@ void r300DestroyCmdBuf(r300ContextPtr r300) foreach(atom, &r300->hw.atomlist) { FREE(atom->cmd); } - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + if (r300->radeon.radeonScreen->driScreen->dri2.enabled || r300->radeon.radeonScreen->kernel_mm) { radeon_cs_manager_gem_dtor(r300->cmdbuf.csm); } else { radeon_cs_manager_legacy_dtor(r300->cmdbuf.csm); diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4405b7a3f50..a984f552bdf 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -436,10 +436,10 @@ int r300EmitArrays(GLcontext * ctx) } /* Setup INPUT_ROUTE. */ - if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { - R300_STATECHANGE(rmesa, vir[0]); - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; + if (rmesa->radeon.radeonScreen->kernel_mm) { + R300_STATECHANGE(rmesa, vir[0]); + rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; rmesa->hw.vir[0].cmd[0] |= (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index bf34ced86e6..db43cc3beed 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -54,7 +54,7 @@ static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, int reg, int count) { - if (!rscrn->driScreen->dri2.enabled) { + if (!rscrn->kernel_mm) { drm_r300_cmd_header_t cmd; cmd.packet0.cmd_type = R300_CMD_PACKET0; @@ -158,7 +158,7 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_r300->radeon.radeonScreen->driScreen->dri2.enabled) { \ + if (!b_l_r300->radeon.radeonScreen->kernel_mm) { \ OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\ R300_CMD_PACKET3_RAW)); \ }\ @@ -172,7 +172,7 @@ void static INLINE end_3d(r300ContextPtr rmesa) { BATCH_LOCALS(rmesa); - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(1); OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); END_BATCH(); @@ -183,7 +183,7 @@ void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { BATCH_LOCALS(rmesa); - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(1); OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); END_BATCH(); @@ -195,7 +195,7 @@ void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) BATCH_LOCALS(rmesa); uint32_t wait_until; - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH_NO_AUTOSTATE(1); OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); END_BATCH(); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 5202248ab77..a86841cea41 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -168,7 +168,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, END_BATCH(); } - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH_NO_AUTOSTATE(9); OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR)); OUT_BATCH_FLOAT32(dPriv->w / 2.0); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index a8d42a2391e..dd9da80fd01 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -199,7 +199,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, @@ -238,7 +238,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { + if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->state.aos[i].components << 0) | (rmesa->state.aos[i].stride << 8) | diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 2f4d06110f9..2bb679b4793 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -302,56 +302,108 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, } } +static void +radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + static void radeon_make_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) + GLframebuffer *draw) { int size = 4096*4096*4; /* if radeon->fake */ struct radeon_renderbuffer *rb; - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (radeon->radeonScreen->kernel_mm) { + radeon_make_kernel_renderbuffer_current(radeon, draw); + return; + } + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; } if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; } if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; } } + void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) { @@ -496,15 +548,15 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, dfb = driDrawPriv->driverPrivate; rfb = driReadPriv->driverPrivate; - if (driContextPriv->driScreenPriv->dri2.enabled) { - radeon_update_renderbuffers(driContextPriv, driDrawPriv); - if (driDrawPriv != driReadPriv) - radeon_update_renderbuffers(driContextPriv, driReadPriv); - radeon->state.color.rrb = - (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - radeon->state.depth_buffer = - (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; - } + if (driContextPriv->driScreenPriv->dri2.enabled) { + radeon_update_renderbuffers(driContextPriv, driDrawPriv); + if (driDrawPriv != driReadPriv) + radeon_update_renderbuffers(driContextPriv, driReadPriv); + radeon->state.color.rrb = + (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon->state.depth_buffer = + (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + } if (RADEON_DEBUG & DEBUG_DRI) @@ -514,10 +566,10 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (driReadPriv != driDrawPriv) driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeon_make_renderbuffer_current(radeon, dfb); - } - + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeon_make_renderbuffer_current(radeon, dfb); + } + _mesa_make_current(radeon->glCtx, dfb, rfb); if (radeon->dri.drawable != driDrawPriv) { diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c index bef8db1d0f4..a1b21634410 100644 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ b/src/mesa/drivers/dri/r300/radeon_lock.c @@ -121,7 +121,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) if (sarea->ctx_owner != rmesa->dri.hwContext) { sarea->ctx_owner = rmesa->dri.hwContext; - radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); + if (!rmesa->radeonScreen->kernel_mm) + radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); } rmesa->lost_context = GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c index 9cce179308b..14d489bf1aa 100644 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ b/src/mesa/drivers/dri/r300/radeon_state.c @@ -153,7 +153,7 @@ void radeonSetCliprects(radeonContextPtr radeon) GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; - if (!radeon->radeonScreen->driScreen->dri2.enabled) { + if (!radeon->radeonScreen->driScreen->dri2.enabled) { if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { /* Can't ignore 2d windows if we are page flipping. */ if (drawable->numBackClipRects == 0 || radeon->doPageFlip || diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 9b5f2201b29..0dda28edc38 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -35,6 +35,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * \author Gareth Hughes */ +#include #include "main/glheader.h" #include "main/imports.h" #include "main/mtypes.h" @@ -366,7 +367,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) { radeonScreenPtr screen; RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; - unsigned char *RADEONMMIO; + unsigned char *RADEONMMIO = NULL; int i; int ret; uint32_t temp; @@ -398,6 +399,21 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); { int ret; + +#ifdef RADEON_PARAM_KERNEL_MM + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, + &screen->kernel_mm); + + if (ret && ret != -EINVAL) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); + return NULL; + } + + if (ret == -EINVAL) + screen->kernel_mm = 0; +#endif + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, &screen->gart_buffer_offset); @@ -431,58 +447,60 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); } - screen->mmio.handle = dri_priv->registerHandle; - screen->mmio.size = dri_priv->registerSize; - if ( drmMap( sPriv->fd, - screen->mmio.handle, - screen->mmio.size, - &screen->mmio.map ) ) { - FREE( screen ); - __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); - return NULL; - } - - RADEONMMIO = screen->mmio.map; - - screen->status.handle = dri_priv->statusHandle; - screen->status.size = dri_priv->statusSize; - if ( drmMap( sPriv->fd, - screen->status.handle, - screen->status.size, - &screen->status.map ) ) { - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); - return NULL; - } - screen->scratch = (__volatile__ uint32_t *) - ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); - - screen->buffers = drmMapBufs( sPriv->fd ); - if ( !screen->buffers ) { - drmUnmap( screen->status.map, screen->status.size ); - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); - return NULL; - } - - if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { - screen->gartTextures.handle = dri_priv->gartTexHandle; - screen->gartTextures.size = dri_priv->gartTexMapSize; - if ( drmMap( sPriv->fd, - screen->gartTextures.handle, - screen->gartTextures.size, - (drmAddressPtr)&screen->gartTextures.map ) ) { + if (!screen->kernel_mm) { + screen->mmio.handle = dri_priv->registerHandle; + screen->mmio.size = dri_priv->registerSize; + if ( drmMap( sPriv->fd, + screen->mmio.handle, + screen->mmio.size, + &screen->mmio.map ) ) { + FREE( screen ); + __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); + return NULL; + } + + RADEONMMIO = screen->mmio.map; + + screen->status.handle = dri_priv->statusHandle; + screen->status.size = dri_priv->statusSize; + if ( drmMap( sPriv->fd, + screen->status.handle, + screen->status.size, + &screen->status.map ) ) { + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); + return NULL; + } + screen->scratch = (__volatile__ uint32_t *) + ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); + + screen->buffers = drmMapBufs( sPriv->fd ); + if ( !screen->buffers ) { + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); + return NULL; + } + + if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { + screen->gartTextures.handle = dri_priv->gartTexHandle; + screen->gartTextures.size = dri_priv->gartTexMapSize; + if ( drmMap( sPriv->fd, + screen->gartTextures.handle, + screen->gartTextures.size, + (drmAddressPtr)&screen->gartTextures.map ) ) { drmUnmapBufs( screen->buffers ); drmUnmap( screen->status.map, screen->status.size ); drmUnmap( screen->mmio.map, screen->mmio.size ); FREE( screen ); __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); return NULL; - } - - screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; + } + + screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; + } } screen->chip_flags = 0; @@ -849,7 +867,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { - if (screen->chip_family < CHIP_FAMILY_RS690) + if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; else { FREE( screen ); @@ -973,10 +991,14 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->sarea_priv_offset = dri_priv->sarea_priv_offset; screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + screen->sarea_priv_offset); - screen->bom = radeon_bo_manager_legacy_ctor(screen); + + if (screen->kernel_mm) + screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); + else + screen->bom = radeon_bo_manager_legacy_ctor(screen); if (screen->bom == NULL) { - free(screen); - return NULL; + free(screen); + return NULL; } return screen; } @@ -1004,6 +1026,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) driParseOptionInfo (&screen->optionCache, __driConfigOptions, __driNConfigOptions); + screen->kernel_mm = 1; screen->chip_flags = 0; /* FIXME: do either an ioctl (bad) or a sysfs file for driver to * information about which chipset is their */ @@ -1058,7 +1081,7 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) if (!screen) return; - if (sPriv->dri2.enabled) { + if (screen->kernel_mm) { radeon_tracker_print(&screen->bom->tracker, stderr); radeon_bo_manager_gem_dtor(screen->bom); } else { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index ccddbb8ae02..3287e125f45 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -107,7 +107,8 @@ typedef struct radeon_screen { const __DRIextension *extensions[16]; int num_gb_pipes; - drm_radeon_sarea_t *sarea; /* Private SAREA data */ + int kernel_mm; + drm_radeon_sarea_t *sarea; /* Private SAREA data */ struct radeon_bo_manager *bom; } radeonScreenRec, *radeonScreenPtr; -- cgit v1.2.3 From 9f2732d3128a1482d4d7feacd98efaf7bdcc4eef Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 21 Dec 2008 09:54:35 +1000 Subject: radeno: hopefully make r200/radeon build --- src/mesa/drivers/dri/r200/Makefile | 4 +++- src/mesa/drivers/dri/radeon/radeon_screen.c | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index e9144ac75ce..7064f423dc9 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -48,7 +48,9 @@ SYMLINKS = \ COMMON_SYMLINKS = \ radeon_chipset.h \ radeon_screen.c \ - radeon_screen.h + radeon_screen.h \ + radeon_bo_legacy.h \ + radeon_buffer.h ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 0dda28edc38..d5795095070 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1338,7 +1338,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, driDrawPriv); radeonSetSpanFunctions(depthRb, mesaVis); _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - depthRb->has_surface = screen->depthHasSurface; + // depthRb->has_surface = screen->depthHasSurface; } else if (mesaVis->depthBits == 24) { driRenderbuffer *depthRb @@ -1349,7 +1349,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, driDrawPriv); radeonSetSpanFunctions(depthRb, mesaVis); _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - depthRb->has_surface = screen->depthHasSurface; + // depthRb->has_surface = screen->depthHasSurface; } /* stencil renderbuffer */ @@ -1362,7 +1362,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, driDrawPriv); radeonSetSpanFunctions(stencilRb, mesaVis); _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); - stencilRb->has_surface = screen->depthHasSurface; + //stencilRb->has_surface = screen->depthHasSurface; } _mesa_add_soft_renderbuffers(fb, -- cgit v1.2.3 From a42000bd6b799da4160d20f74422449415d1e370 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 22 Dec 2008 11:41:23 +1000 Subject: radeon: fixup r500 FP emission for new CS --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 51 ++++++++++++++++++-- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 4 ++ src/mesa/drivers/dri/r300/r300_ioctl.c | 82 ++++++++++++++++++--------------- 3 files changed, 95 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index ca9d36a8b66..ed94520aba2 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -284,6 +284,45 @@ void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) } } +void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) +{ + BATCH_LOCALS(r300); + drm_r300_cmd_header_t cmd; + uint32_t addr, ndw, i, sz; + int type, clamp, stride; + + if (!r300->radeon.radeonScreen->kernel_mm) { + uint32_t dwords; + dwords = (*atom->check) (r300, atom); + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + return; + } + + cmd.u = atom->cmd[0]; + sz = cmd.r500fp.count; + addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo; + type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); + clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); + + addr |= (type << 16); + addr |= (clamp << 17); + + stride = type ? 4 : 6; + + ndw = sz * stride; + if (ndw) { + + OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0)); + OUT_BATCH(addr); + OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR); + for (i = 0; i < ndw; i++) { + OUT_BATCH(atom->cmd[i+1]); + } + } +} + static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) { BATCH_LOCALS(r300); @@ -395,7 +434,7 @@ int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) return cnt ? (cnt * 4) + 1 : 0; } -static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) +int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) { int cnt; @@ -403,11 +442,11 @@ static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) return cnt ? (cnt * 6) + 1 : 0; } -static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) { int cnt; - cnt = r500fp_count(atom->cmd); + cnt = r500fp_count(atom->cmd); return cnt ? (cnt * 4) + 1 : 0; } @@ -570,10 +609,12 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0); r300->hw.r500fp.cmd[R300_FPI_CMD_0] = - cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0); + cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0); + r300->hw.r500fp.emit = emit_r500fp; ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0); r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = - cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0); + cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0); + r300->hw.r500fp_const.emit = emit_r500fp; } else { ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0); r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3); diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index 1a249c8d52c..95701b49b43 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -132,4 +132,8 @@ void r300BeginBatch(r300ContextPtr r300, void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom); int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom); +void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom); +int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom); +int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom); + #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index a86841cea41..0cf084bde54 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -387,6 +387,9 @@ static void r300EmitClearState(GLcontext * ctx) FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); END_BATCH(); } else { + struct r300_state_atom r500fp; + uint32_t _cmd[10]; + R300_STATECHANGE(r300, fp); R300_STATECHANGE(r300, r500fp); @@ -398,44 +401,49 @@ static void r300EmitClearState(GLcontext * ctx) OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0)); - - OUT_BATCH(cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0)); - OUT_BATCH(R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK | - R500_INST_RGB_CLAMP | - R500_INST_ALPHA_CLAMP); - OUT_BATCH(R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST); - OUT_BATCH(R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST); - OUT_BATCH(R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_R | - R500_ALU_RGB_B_SWIZ_B_G | - R500_ALU_RGB_G_SWIZ_B_B); - OUT_BATCH(R500_ALPHA_OP_CMP | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_A); - OUT_BATCH(R500_ALU_RGBA_OP_CMP | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0); END_BATCH(); + + r500fp.check = check_r500fp; + r500fp.cmd = _cmd; + r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0); + r500fp.cmd[1] = R500_INST_TYPE_OUT | + R500_INST_TEX_SEM_WAIT | + R500_INST_LAST | + R500_INST_RGB_OMASK_R | + R500_INST_RGB_OMASK_G | + R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK | + R500_INST_RGB_CLAMP | + R500_INST_ALPHA_CLAMP; + r500fp.cmd[2] = R500_RGB_ADDR0(0) | + R500_RGB_ADDR1(0) | + R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | + R500_RGB_ADDR2_CONST; + r500fp.cmd[3] = R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR1(0) | + R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | + R500_ALPHA_ADDR2_CONST; + r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_B; + r500fp.cmd[5] = R500_ALPHA_OP_CMP | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_A; + r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0; + + r500fp.cmd[7] = 0; + emit_r500fp(r300, &r500fp); } BEGIN_BATCH(2); -- cgit v1.2.3 From e14ffb1fa176dbaf260a62cc5e4ddbd602ff6327 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 22 Dec 2008 11:41:32 +1000 Subject: radeon: remove start/end offset + cleanup some whitespace --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 56 +++++++++++++------------- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 2 - src/mesa/drivers/dri/r300/r300_ioctl.c | 9 +++-- src/mesa/drivers/dri/r300/r300_render.c | 8 ---- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 20 --------- 5 files changed, 33 insertions(+), 62 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index ed94520aba2..4eac5183b2f 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -341,14 +341,14 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) } else if (!t) { OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); } else { - if (t->bo) { - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - OUT_BATCH(t->override_offset); - } + if (t->bo) { + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH(t->override_offset); + } } - END_BATCH(); + END_BATCH(); } } } @@ -361,9 +361,9 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate; rrb = r300->radeon.state.color.rrb; - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; @@ -397,13 +397,13 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) return; zbpitch = (rrb->pitch / rrb->cpp); - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - zbpitch |= R300_DEPTHMACROTILE_ENABLE; - } - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ - zbpitch |= R300_DEPTHMICROTILE_TILED; - } - + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + zbpitch |= R300_DEPTHMACROTILE_ENABLE; + } + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ + zbpitch |= R300_DEPTHMICROTILE_TILED; + } + BEGIN_BATCH(4); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); @@ -688,43 +688,43 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0); r300->hw.vpi.cmd[0] = cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0); - r300->hw.vpi.emit = emit_vpu; + r300->hw.vpi.emit = emit_vpu; if (is_r500) { ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); r300->hw.vpp.cmd[0] = cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0); - r300->hw.vpp.emit = emit_vpu; + r300->hw.vpp.emit = emit_vpu; ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); r300->hw.vps.cmd[0] = cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); - r300->hw.vps.emit = emit_vpu; + r300->hw.vps.emit = emit_vpu; for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[0] = - cmdvpu(r300->radeon.radeonScreen, + ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); + r300->hw.vpucp[i].cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R500_PVS_UCP_START + i, 1); - r300->hw.vpucp[i].emit = emit_vpu; + r300->hw.vpucp[i].emit = emit_vpu; } } else { ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); r300->hw.vpp.cmd[0] = cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0); - r300->hw.vpp.emit = emit_vpu; + r300->hw.vpp.emit = emit_vpu; ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); r300->hw.vps.cmd[0] = cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1); - r300->hw.vps.emit = emit_vpu; + r300->hw.vps.emit = emit_vpu; for (i = 0; i < 6; i++) { ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); r300->hw.vpucp[i].cmd[0] = cmdvpu(r300->radeon.radeonScreen, - R300_PVS_UCP_START + i, 1); - r300->hw.vpucp[i].emit = emit_vpu; + R300_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].emit = emit_vpu; } } } diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index 95701b49b43..bb7e0bf2960 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -93,8 +93,6 @@ void r300BeginBatch(r300ContextPtr r300, radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\ radeon_cs_write_reloc(b_l_r300->cmdbuf.cs, \ bo, \ - offset, \ - (bo)->size, \ rd, \ wd, \ flags);\ diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 0cf084bde54..6d7b191b24d 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -499,9 +499,9 @@ static void r300EmitClearState(GLcontext * ctx) OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); END_BATCH(); - vpu.check = check_vpu; - vpu.cmd = _cmd; - vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2); + vpu.check = check_vpu; + vpu.cmd = _cmd; + vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2); vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT); @@ -520,6 +520,7 @@ static void r300EmitClearState(GLcontext * ctx) vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, + VSF_FLAG_NONE); vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, @@ -527,7 +528,7 @@ static void r300EmitClearState(GLcontext * ctx) PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); vpu.cmd[8] = 0x0; - emit_vpu(r300, &vpu); + emit_vpu(r300, &vpu); } } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index dd9da80fd01..ccc00b381fa 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -214,8 +214,6 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) OUT_BATCH(vertex_count); radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.elt_dma_bo, - 0, - rmesa->state.elt_dma_bo->size, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); @@ -299,16 +297,12 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) offset * 4 * rmesa->state.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[i+0].bo, - voffset, - rmesa->state.aos[i+0].bo->size, RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->state.aos[i + 1].offset + offset * 4 * rmesa->state.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[i+1].bo, - voffset, - rmesa->state.aos[i+1].bo->size, RADEON_GEM_DOMAIN_GTT, 0, 0); } @@ -317,8 +311,6 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) offset * 4 * rmesa->state.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[nr-1].bo, - voffset, - rmesa->state.aos[nr-1].bo->size, RADEON_GEM_DOMAIN_GTT, 0, 0); } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 20956ff5c7b..11b9f89ca7d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -94,8 +94,6 @@ static int cs_write_dword(struct radeon_cs *cs, uint32_t dword) static int cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, - uint32_t start_offset, - uint32_t end_offset, uint32_t read_domain, uint32_t write_domain, uint32_t flags) @@ -117,25 +115,11 @@ static int cs_write_reloc(struct radeon_cs *cs, if (write_domain == RADEON_GEM_DOMAIN_CPU) { return -EINVAL; } - /* check reloc window */ - if (end_offset > bo->size) { - return -EINVAL; - } - if (start_offset > end_offset) { - return -EINVAL; - } /* check if bo is already referenced */ for(i = 0; i < cs->crelocs; i++) { uint32_t *indices; if (relocs[i].base.bo->handle == bo->handle) { - /* update start and end offset */ - if (start_offset < relocs[i].base.start_offset) { - relocs[i].base.start_offset = start_offset; - } - if (end_offset > relocs[i].base.end_offset) { - relocs[i].base.end_offset = end_offset; - } /* Check domains must be in read or write. As we check already * checked that in argument one of the read or write domain was * set we only need to check that if previous reloc as the read @@ -172,8 +156,6 @@ static int cs_write_reloc(struct radeon_cs *cs, } cs->relocs = relocs; relocs[cs->crelocs].base.bo = bo; - relocs[cs->crelocs].base.start_offset = start_offset; - relocs[cs->crelocs].base.end_offset = end_offset; relocs[cs->crelocs].base.read_domain = read_domain; relocs[cs->crelocs].base.write_domain = write_domain; relocs[cs->crelocs].base.flags = flags; @@ -249,8 +231,6 @@ static int cs_process_relocs(struct radeon_cs *cs) for (j = 0; j < relocs[i].cindices; j++) { uint32_t soffset, eoffset; - soffset = relocs[i].base.start_offset; - eoffset = relocs[i].base.end_offset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); if (r) { -- cgit v1.2.3 From d9b325f77e9011918ad1bb59db7c58c44582fda0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 22 Dec 2008 12:28:16 +1000 Subject: radeon: fix library name for consistency --- src/mesa/drivers/dri/r300/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index cbb09e6ce59..3d7122fce2d 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -79,7 +79,7 @@ COMMON_SYMLINKS = \ radeon_bo_legacy.h \ radeon_cs_legacy.h -DRI_LIB_DEPS += -ldrm-radeon +DRI_LIB_DEPS += -ldrm_radeon ##### TARGETS ##### -- cgit v1.2.3 From 2a287ddd324cf285200aaf2eddc78da4eaaad1a1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 22 Dec 2008 17:04:39 +1000 Subject: r300: disable settexoffset extension on r300 --- src/mesa/drivers/dri/radeon/radeon_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index d5795095070..7af03f3e5b2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -981,7 +981,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - screen->extensions[i++] = &r300texOffsetExtension.base; + //screen->extensions[i++] = &r300texOffsetExtension.base; #endif screen->extensions[i++] = NULL; -- cgit v1.2.3 From efe68930dce815b3ecda7dc1164dcd9a504dc525 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 11 Jan 2009 09:47:38 +1000 Subject: radeon/r300: add code to setup r300 vs r500 using pci device from kernel --- src/mesa/drivers/dri/radeon/radeon_screen.c | 326 +++++++++++++++------------- 1 file changed, 177 insertions(+), 149 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 7af03f3e5b2..29ae17c52b8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -360,152 +360,10 @@ static const __DRItexBufferExtension r300TexBufferExtension = { }; #endif -/* Create the device specific screen private data struct. - */ -static radeonScreenPtr -radeonCreateScreen( __DRIscreenPrivate *sPriv ) +int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) { - radeonScreenPtr screen; - RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; - unsigned char *RADEONMMIO = NULL; - int i; - int ret; - uint32_t temp; - - if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { - fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); - return GL_FALSE; - } - - /* Allocate the private area */ - screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); - if ( !screen ) { - __driUtilMessage("%s: Could not allocate memory for screen structure", - __FUNCTION__); - return NULL; - } - -#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); -#endif - - /* parse information in __driConfigOptions */ - driParseOptionInfo (&screen->optionCache, - __driConfigOptions, __driNConfigOptions); - - /* This is first since which regions we map depends on whether or - * not we are using a PCI card. - */ - screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); - { - int ret; - -#ifdef RADEON_PARAM_KERNEL_MM - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, - &screen->kernel_mm); - - if (ret && ret != -EINVAL) { - FREE( screen ); - fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); - return NULL; - } - - if (ret == -EINVAL) - screen->kernel_mm = 0; -#endif - - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, - &screen->gart_buffer_offset); - - if (ret) { - FREE( screen ); - fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); - return NULL; - } - - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, - &screen->gart_base); - if (ret) { - FREE( screen ); - fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); - return NULL; - } - - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, - &screen->irq); - if (ret) { - FREE( screen ); - fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); - return NULL; - } - screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); - screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); - screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); - screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); - screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); - screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); - screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); - } - - if (!screen->kernel_mm) { - screen->mmio.handle = dri_priv->registerHandle; - screen->mmio.size = dri_priv->registerSize; - if ( drmMap( sPriv->fd, - screen->mmio.handle, - screen->mmio.size, - &screen->mmio.map ) ) { - FREE( screen ); - __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); - return NULL; - } - - RADEONMMIO = screen->mmio.map; - - screen->status.handle = dri_priv->statusHandle; - screen->status.size = dri_priv->statusSize; - if ( drmMap( sPriv->fd, - screen->status.handle, - screen->status.size, - &screen->status.map ) ) { - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); - return NULL; - } - screen->scratch = (__volatile__ uint32_t *) - ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); - - screen->buffers = drmMapBufs( sPriv->fd ); - if ( !screen->buffers ) { - drmUnmap( screen->status.map, screen->status.size ); - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); - return NULL; - } - - if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { - screen->gartTextures.handle = dri_priv->gartTexHandle; - screen->gartTextures.size = dri_priv->gartTexMapSize; - if ( drmMap( sPriv->fd, - screen->gartTextures.handle, - screen->gartTextures.size, - (drmAddressPtr)&screen->gartTextures.map ) ) { - drmUnmapBufs( screen->buffers ); - drmUnmap( screen->status.map, screen->status.size ); - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); - return NULL; - } - - screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; - } - } - screen->chip_flags = 0; - /* XXX: add more chipsets */ - switch ( dri_priv->deviceID ) { + switch ( device_id ) { case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: case PCI_CHIP_RADEON_QY: @@ -837,9 +695,162 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) default: fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", - dri_priv->deviceID); + device_id); + return -1; + } + + return 0; +} + + +/* Create the device specific screen private data struct. + */ +static radeonScreenPtr +radeonCreateScreen( __DRIscreenPrivate *sPriv ) +{ + radeonScreenPtr screen; + RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; + unsigned char *RADEONMMIO = NULL; + int i; + int ret; + uint32_t temp; + + if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { + fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); + return GL_FALSE; + } + + /* Allocate the private area */ + screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); + if ( !screen ) { + __driUtilMessage("%s: Could not allocate memory for screen structure", + __FUNCTION__); return NULL; } + +#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); +#endif + + /* parse information in __driConfigOptions */ + driParseOptionInfo (&screen->optionCache, + __driConfigOptions, __driNConfigOptions); + + /* This is first since which regions we map depends on whether or + * not we are using a PCI card. + */ + screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); + { + int ret; + +#ifdef RADEON_PARAM_KERNEL_MM + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, + &screen->kernel_mm); + + if (ret && ret != -EINVAL) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); + return NULL; + } + + if (ret == -EINVAL) + screen->kernel_mm = 0; +#endif + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, + &screen->gart_buffer_offset); + + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); + return NULL; + } + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, + &screen->gart_base); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); + return NULL; + } + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, + &screen->irq); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); + return NULL; + } + screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); + screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); + screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); + screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); + screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); + screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); + screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); + } + + if (!screen->kernel_mm) { + screen->mmio.handle = dri_priv->registerHandle; + screen->mmio.size = dri_priv->registerSize; + if ( drmMap( sPriv->fd, + screen->mmio.handle, + screen->mmio.size, + &screen->mmio.map ) ) { + FREE( screen ); + __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); + return NULL; + } + + RADEONMMIO = screen->mmio.map; + + screen->status.handle = dri_priv->statusHandle; + screen->status.size = dri_priv->statusSize; + if ( drmMap( sPriv->fd, + screen->status.handle, + screen->status.size, + &screen->status.map ) ) { + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); + return NULL; + } + screen->scratch = (__volatile__ uint32_t *) + ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); + + screen->buffers = drmMapBufs( sPriv->fd ); + if ( !screen->buffers ) { + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); + return NULL; + } + + if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { + screen->gartTextures.handle = dri_priv->gartTexHandle; + screen->gartTextures.size = dri_priv->gartTexMapSize; + if ( drmMap( sPriv->fd, + screen->gartTextures.handle, + screen->gartTextures.size, + (drmAddressPtr)&screen->gartTextures.map ) ) { + drmUnmapBufs( screen->buffers ); + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); + return NULL; + } + + screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; + } + } + + + ret = radeon_set_screen_flags(screen, dri_priv->deviceID); + if (ret == -1) + return NULL; + if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && sPriv->ddx_version.minor < 2) { fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); @@ -1008,6 +1019,8 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) { radeonScreenPtr screen; int i; + int ret; + uint32_t device_id; /* Allocate the private area */ screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); @@ -1028,10 +1041,25 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) screen->kernel_mm = 1; screen->chip_flags = 0; - /* FIXME: do either an ioctl (bad) or a sysfs file for driver to - * information about which chipset is their */ - screen->chip_family = CHIP_FAMILY_RV350; - screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CLASS_R300; + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, + &device_id); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); + return NULL; + } + + ret = radeon_set_screen_flags(screen, device_id); + if (ret == -1) + return NULL; + + if (screen->chip_family <= CHIP_FAMILY_RS200) + screen->chip_flags |= RADEON_CLASS_R100; + else if (screen->chip_family <= CHIP_FAMILY_RV280) + screen->chip_flags |= RADEON_CLASS_R200; + else + screen->chip_flags |= RADEON_CLASS_R300; i = 0; screen->extensions[i++] = &driCopySubBufferExtension.base; -- cgit v1.2.3 From d67987b0d144bb754215784cf347512806f15496 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Mon, 1 Dec 2008 21:44:03 -0500 Subject: Bump dri2proto requirement to 1.99.3, drop CopyRegion bitmask from protocol. (cherry picked from commit 154a9e5317f890618932cea0129ef887e16baf84) --- configure.ac | 2 +- src/glx/x11/dri2.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/configure.ac b/configure.ac index e48137f2abc..995d99cc17f 100644 --- a/configure.ac +++ b/configure.ac @@ -23,7 +23,7 @@ AC_CANONICAL_HOST dnl Versions for external dependencies LIBDRM_REQUIRED=2.3.1 -DRI2PROTO_REQUIRED=1.99.1 +DRI2PROTO_REQUIRED=1.99.3 dnl Check for progs AC_PROG_CPP diff --git a/src/glx/x11/dri2.c b/src/glx/x11/dri2.c index 661100a218f..3b48cd9c1ca 100644 --- a/src/glx/x11/dri2.c +++ b/src/glx/x11/dri2.c @@ -293,7 +293,6 @@ void DRI2CopyRegion(Display *dpy, XID drawable, XserverRegion region, req->region = region; req->dest = dest; req->src = src; - req->bitmask = 0; _XReply(dpy, (xReply *)&rep, 0, xFalse); -- cgit v1.2.3 From 4b9a09e9f63791787fb9a276a4efd685b399be52 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 13 Jan 2009 16:50:15 +1000 Subject: radeon: use bo_wait to wait for all buffers to be rendered to Not 100% sure this is correct, but its what Intel does and its better than CP_IDLE. --- src/mesa/drivers/dri/r300/radeon_ioctl.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.c b/src/mesa/drivers/dri/r300/radeon_ioctl.c index c8d6bf99bc7..87123170508 100644 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.c +++ b/src/mesa/drivers/dri/r300/radeon_ioctl.c @@ -366,10 +366,19 @@ void radeonFlush(GLcontext * ctx) void radeonFinish(GLcontext * ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct gl_framebuffer *fb = ctx->DrawBuffer; + int i; radeonFlush(ctx); - if (radeon->do_irqs) { + if (radeon->radeonScreen->kernel_mm) { + for (i = 0; i < fb->_NumColorDrawBuffers; i++) { + struct radeon_renderbuffer *rrb; + rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; + if (rrb->bo) + radeon_bo_wait(rrb->bo); + } + } else if (radeon->do_irqs) { LOCK_HARDWARE(radeon); radeonEmitIrqLocked(radeon); UNLOCK_HARDWARE(radeon); -- cgit v1.2.3 From 692ca82116485a9c6191e5265c5b369d5b4f82f3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 13 Jan 2009 22:55:27 +1000 Subject: radeon/r200: start splitting out commonalities into separate headers --- src/mesa/drivers/dri/r200/Makefile | 3 +- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 2 +- src/mesa/drivers/dri/r200/r200_context.c | 2 +- src/mesa/drivers/dri/r200/r200_context.h | 211 +++----------------------- src/mesa/drivers/dri/r200/r200_fragshader.c | 2 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 8 +- src/mesa/drivers/dri/r200/r200_ioctl.h | 6 +- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 20 +-- src/mesa/drivers/dri/r200/r200_state.c | 8 +- src/mesa/drivers/dri/r200/r200_swtcl.c | 16 +- src/mesa/drivers/dri/r200/r200_swtcl.h | 4 +- src/mesa/drivers/dri/r200/r200_tex.c | 22 +-- src/mesa/drivers/dri/r200/r200_tex.h | 4 +- src/mesa/drivers/dri/r200/r200_texmem.c | 14 +- src/mesa/drivers/dri/r200/r200_texstate.c | 28 ++-- src/mesa/drivers/dri/radeon/common_context.h | 178 ++++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_context.h | 167 +------------------- src/mesa/drivers/dri/radeon/radeon_screen.c | 3 + src/mesa/drivers/dri/radeon/radeon_tex.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texmem.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 2 +- 21 files changed, 279 insertions(+), 425 deletions(-) create mode 100644 src/mesa/drivers/dri/radeon/common_context.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 7064f423dc9..f4c173085b1 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -50,7 +50,8 @@ COMMON_SYMLINKS = \ radeon_screen.c \ radeon_screen.h \ radeon_bo_legacy.h \ - radeon_buffer.h + radeon_buffer.h \ + common_context.h ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index e1633772a18..b7f025ca5ff 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -321,7 +321,7 @@ void r200EmitVertexAOS( r200ContextPtr rmesa, void r200EmitAOS( r200ContextPtr rmesa, - struct r200_dma_region **component, + struct radeon_dma_region **component, GLuint nr, GLuint offset ) { diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 5531e0a7399..e8d4ca25375 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -341,7 +341,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, (drmTextureRegionPtr)rmesa->sarea->tex_list[i], & rmesa->sarea->tex_age[i], & rmesa->swapped, - sizeof( r200TexObj ), + sizeof( radeonTexObj ), (destroy_texture_object_t *) r200DestroyTexObj ); } rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache, diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 14a1dda46ac..dd9944173ae 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -53,49 +53,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #error This driver requires a newer libdrm to compile #endif +#include "common_context.h" + struct r200_context; typedef struct r200_context r200ContextRec; typedef struct r200_context *r200ContextPtr; -/* This union is used to avoid warnings/miscompilation - with float to uint32_t casts due to strict-aliasing */ -typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; - #include "r200_lock.h" #include "radeon_screen.h" #include "main/mm.h" -/* Flags for software fallback cases */ -/* See correponding strings in r200_swtcl.c */ -#define R200_FALLBACK_TEXTURE 0x01 -#define R200_FALLBACK_DRAW_BUFFER 0x02 -#define R200_FALLBACK_STENCIL 0x04 -#define R200_FALLBACK_RENDER_MODE 0x08 -#define R200_FALLBACK_DISABLE 0x10 -#define R200_FALLBACK_BORDER_MODE 0x20 - -/* The blit width for texture uploads - */ -#define BLIT_WIDTH_BYTES 1024 - -/* Use the templated vertex format: - */ -#define COLOR_IS_RGBA -#define TAG(x) r200##x -#include "tnl_dd/t_dd_vertex.h" -#undef TAG - typedef void (*r200_tri_func)( r200ContextPtr, - r200Vertex *, - r200Vertex *, - r200Vertex * ); + radeonVertex *, + radeonVertex *, + radeonVertex * ); typedef void (*r200_line_func)( r200ContextPtr, - r200Vertex *, - r200Vertex * ); + radeonVertex *, + radeonVertex * ); typedef void (*r200_point_func)( r200ContextPtr, - r200Vertex * ); + radeonVertex * ); struct r200_vertex_program { @@ -112,93 +90,11 @@ struct r200_vertex_program { int fogmode; }; -struct r200_colorbuffer_state { - GLuint clear; -#if 000 - GLint drawOffset, drawPitch; -#endif - int roundEnable; -}; - - -struct r200_depthbuffer_state { - GLuint clear; - GLfloat scale; -}; - -#if 000 -struct r200_pixel_state { - GLint readOffset, readPitch; -}; -#endif - -struct r200_scissor_state { - drm_clip_rect_t rect; - GLboolean enabled; - - GLuint numClipRects; /* Cliprects active */ - GLuint numAllocedClipRects; /* Cliprects available */ - drm_clip_rect_t *pClipRects; -}; - -struct r200_stencilbuffer_state { - GLboolean hwBuffer; - GLuint clear; /* rb3d_stencilrefmask value */ -}; - -struct r200_stipple_state { - GLuint mask[32]; -}; - - - -#define TEX_0 0x1 -#define TEX_1 0x2 -#define TEX_2 0x4 -#define TEX_3 0x8 -#define TEX_4 0x10 -#define TEX_5 0x20 -#define TEX_ALL 0x3f - -typedef struct r200_tex_obj r200TexObj, *r200TexObjPtr; - -/* Texture object in locally shared texture space. - */ -struct r200_tex_obj { - driTextureObject base; - - GLuint bufAddr; /* Offset to start of locally - shared texture block */ - - GLuint dirty_state; /* Flags (1 per texunit) for - whether or not this texobj - has dirty hardware state - (pp_*) that needs to be - brought into the - texunit. */ - - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; - /* Six, for the cube faces */ - GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ - - GLuint pp_txfilter; /* hardware register values */ - GLuint pp_txformat; - GLuint pp_txformat_x; - GLuint pp_txoffset; /* Image location in texmem. - All cube faces follow. */ - GLuint pp_txsize; /* npot only */ - GLuint pp_txpitch; /* npot only */ - GLuint pp_border_color; - GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ - - GLboolean border_fallback; - - GLuint tile_bits; /* hw texture tile bits used on this texture */ -}; +#define R200_TEX_ALL 0x3f struct r200_texture_env_state { - r200TexObjPtr texobj; + radeonTexObjPtr texobj; GLuint outputreg; GLuint unitneeded; }; @@ -214,14 +110,13 @@ struct r200_state_atom { struct r200_state_atom *next, *prev; const char *name; /* for debug */ int cmd_size; /* size in bytes */ + GLuint is_tcl; GLuint idx; int *cmd; /* one or more cmd's */ int *lastcmd; /* one or more cmd's */ GLboolean dirty; GLboolean (*check)( GLcontext *, int ); /* is this state active? */ }; - - /* Trying to keep these relatively short as the variables are becoming * extravagently long. Drop the driver name prefix off the front of @@ -648,54 +543,22 @@ struct r200_hw_state { struct r200_state { /* Derived state for internal purposes: */ - struct r200_colorbuffer_state color; - struct r200_depthbuffer_state depth; + struct radeon_colorbuffer_state color; + struct radeon_depthbuffer_state depth; #if 00 struct r200_pixel_state pixel; #endif - struct r200_scissor_state scissor; - struct r200_stencilbuffer_state stencil; - struct r200_stipple_state stipple; + struct radeon_scissor_state scissor; + struct radeon_stencilbuffer_state stencil; + struct radeon_stipple_state stipple; struct r200_texture_state texture; GLuint envneeded; }; -/* Need refcounting on dma buffers: - */ -struct r200_dma_buffer { - int refcount; /* the number of retained regions in buf */ - drmBufPtr buf; -}; - #define GET_START(rvb) (rmesa->r200Screen->gart_buffer_offset + \ (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) -/* A retained region, eg vertices for indexed vertices. - */ -struct r200_dma_region { - struct r200_dma_buffer *buf; - char *address; /* == buf->address */ - int start, end, ptr; /* offsets from start of buf */ - int aos_start; - int aos_stride; - int aos_size; -}; - - -struct r200_dma { - /* Active dma region. Allocations for vertices and retained - * regions come from here. Also used for emitting random vertices, - * these may be flushed by calling flush_current(); - */ - struct r200_dma_region current; - - void (*flush)( r200ContextPtr ); - - char *buf0_address; /* start of buf[0], for index calcs */ - GLuint nr_released_bufs; /* flush after so many buffers released */ -}; - struct r200_dri_mirror { __DRIcontextPrivate *context; /* DRI context */ __DRIscreenPrivate *screen; /* DRI screen */ @@ -726,13 +589,13 @@ struct r200_tcl_info { GLuint hw_primitive; /* hw can handle 12 components max */ - struct r200_dma_region *aos_components[12]; + struct radeon_dma_region *aos_components[12]; GLuint nr_aos_components; GLuint *Elts; - struct r200_dma_region indexed_verts; - struct r200_dma_region vertex_data[15]; + struct radeon_dma_region indexed_verts; + struct radeon_dma_region vertex_data[15]; }; @@ -788,26 +651,11 @@ struct r200_swtcl_info { */ GLboolean needproj; - struct r200_dma_region indexed_verts; -}; - - -struct r200_ioctl { - GLuint vertex_offset; - GLuint vertex_size; + struct radeon_dma_region indexed_verts; }; -#define R200_MAX_PRIMS 64 - - - -struct r200_prim { - GLuint start; - GLuint end; - GLuint prim; -}; /* A maximum total of 29 elements per vertex: 3 floats for position, 3 * floats for normal, 4 floats for color, 4 bytes for secondary color, @@ -849,8 +697,8 @@ struct r200_context { /* Vertex buffers */ - struct r200_ioctl ioctl; - struct r200_dma dma; + struct radeon_ioctl ioctl; + struct radeon_dma dma; struct r200_store store; /* A full state emit as of the first state emit in the main store, in case * the context is lost. @@ -927,21 +775,6 @@ struct r200_context { #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) -static INLINE GLuint r200PackColor( GLuint cpp, - GLubyte r, GLubyte g, - GLubyte b, GLubyte a ) -{ - switch ( cpp ) { - case 2: - return PACK_COLOR_565( r, g, b ); - case 4: - return PACK_COLOR_8888( a, r, g, b ); - default: - return 0; - } -} - - extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, __DRIcontextPrivate *driContextPriv, diff --git a/src/mesa/drivers/dri/r200/r200_fragshader.c b/src/mesa/drivers/dri/r200/r200_fragshader.c index d514b28219a..85c1b7bdd19 100644 --- a/src/mesa/drivers/dri/r200/r200_fragshader.c +++ b/src/mesa/drivers/dri/r200/r200_fragshader.c @@ -522,7 +522,7 @@ static void r200UpdateFSConstants( GLcontext *ctx ) CLAMPED_FLOAT_TO_UBYTE(con_byte[2], ctx->ATIFragmentShader.GlobalConstants[i][2]); CLAMPED_FLOAT_TO_UBYTE(con_byte[3], ctx->ATIFragmentShader.GlobalConstants[i][3]); } - rmesa->hw.atf.cmd[ATF_TFACTOR_0 + i] = r200PackColor ( + rmesa->hw.atf.cmd[ATF_TFACTOR_0 + i] = radeonPackColor ( 4, con_byte[0], con_byte[1], con_byte[2], con_byte[3] ); } } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 0741e57af71..8ad3a676738 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -194,7 +194,7 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) { - struct r200_dma_buffer *dmabuf; + struct radeon_dma_buffer *dmabuf; int fd = rmesa->dri.fd; int index = 0; int size = 0; @@ -248,7 +248,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) if (R200_DEBUG & DEBUG_DMA) fprintf(stderr, "Allocated buffer %d\n", index); - dmabuf = CALLOC_STRUCT( r200_dma_buffer ); + dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); dmabuf->buf = &rmesa->r200Screen->buffers->list[index]; dmabuf->refcount = 1; @@ -260,7 +260,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) } void r200ReleaseDmaRegion( r200ContextPtr rmesa, - struct r200_dma_region *region, + struct radeon_dma_region *region, const char *caller ) { if (R200_DEBUG & DEBUG_IOCTL) @@ -295,7 +295,7 @@ void r200ReleaseDmaRegion( r200ContextPtr rmesa, * space in current, grab a new buffer (and discard what was left of current) */ void r200AllocDmaRegion( r200ContextPtr rmesa, - struct r200_dma_region *region, + struct radeon_dma_region *region, int bytes, int alignment ) { diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index f7458e4a0ed..b760dd6eeca 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -59,7 +59,7 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint min_nr ); extern void r200EmitAOS( r200ContextPtr rmesa, - struct r200_dma_region **regions, + struct radeon_dma_region **regions, GLuint n, GLuint offset ); @@ -81,12 +81,12 @@ extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ); extern void r200AllocDmaRegion( r200ContextPtr rmesa, - struct r200_dma_region *region, + struct radeon_dma_region *region, int bytes, int alignment ); extern void r200ReleaseDmaRegion( r200ContextPtr rmesa, - struct r200_dma_region *region, + struct radeon_dma_region *region, const char *caller ); extern void r200CopyBuffer( __DRIdrawablePrivate *drawable, diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 8512b9af478..838dfe79f9d 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -61,7 +61,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ static void emit_ubyte_rgba3( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -84,7 +84,7 @@ static void emit_ubyte_rgba3( GLcontext *ctx, } static void emit_ubyte_rgba4( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -109,7 +109,7 @@ static void emit_ubyte_rgba4( GLcontext *ctx, static void emit_ubyte_rgba( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int size, int stride, @@ -176,7 +176,7 @@ do { \ static void emit_vecfog( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -219,7 +219,7 @@ static void emit_vecfog( GLcontext *ctx, static void emit_vec4( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -243,7 +243,7 @@ static void emit_vec4( GLcontext *ctx, static void emit_vec8( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -267,7 +267,7 @@ static void emit_vec8( GLcontext *ctx, } static void emit_vec12( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -292,7 +292,7 @@ static void emit_vec12( GLcontext *ctx, } static void emit_vec16( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int stride, int count ) @@ -319,7 +319,7 @@ static void emit_vec16( GLcontext *ctx, static void emit_vector( GLcontext *ctx, - struct r200_dma_region *rvb, + struct radeon_dma_region *rvb, char *data, int size, int stride, @@ -379,7 +379,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - struct r200_dma_region **component = rmesa->tcl.aos_components; + struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt0 = 0, vfmt1 = 0; GLuint count = VB->Count; diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 0eaaaf69ac7..7fd93a749e5 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -115,7 +115,7 @@ static void r200BlendColor( GLcontext *ctx, const GLfloat cf[4] ) CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); if (rmesa->r200Screen->drmSupportsBlendColor) - rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = r200PackColor( 4, color[0], color[1], color[2], color[3] ); + rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] ); } /** @@ -480,7 +480,7 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) case GL_FOG_COLOR: R200_STATECHANGE( rmesa, ctx ); UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color ); - i = r200PackColor( 4, col[0], col[1], col[2], 0 ); + i = radeonPackColor( 4, col[0], col[1], col[2], 0 ); rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_COLOR_MASK; rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= i; break; @@ -803,7 +803,7 @@ static void r200ColorMask( GLcontext *ctx, GLboolean b, GLboolean a ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint mask = r200PackColor( rmesa->r200Screen->cpp, + GLuint mask = radeonPackColor( rmesa->r200Screen->cpp, ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], @@ -1805,7 +1805,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); - rmesa->state.color.clear = r200PackColor( rmesa->r200Screen->cpp, + rmesa->state.color.clear = radeonPackColor( rmesa->r200Screen->cpp, color[0], color[1], color[2], color[3] ); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index b25f0282445..e4a5c129cec 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -284,7 +284,7 @@ static void flush_last_swtcl_prim( r200ContextPtr rmesa ) rmesa->dma.flush = NULL; if (rmesa->dma.current.buf) { - struct r200_dma_region *current = &rmesa->dma.current; + struct radeon_dma_region *current = &rmesa->dma.current; GLuint current_offset = (rmesa->r200Screen->gart_buffer_offset + current->buf->buf->idx * RADEON_BUFFER_SIZE + current->start); @@ -397,8 +397,8 @@ static void r200ResetLineStipple( GLcontext *ctx ); #define LOCAL_VARS \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ const char *r200verts = (char *)rmesa->swtcl.verts; -#define VERT(x) (r200Vertex *)(r200verts + ((x) * vertsize * sizeof(int))) -#define VERTEX r200Vertex +#define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int))) +#define VERTEX radeonVertex #define DO_DEBUG_VERTS (1 && (R200_DEBUG & DEBUG_VERTS)) #undef TAG @@ -460,7 +460,7 @@ static struct { #define VERT_SET_RGBA( v, c ) \ do { \ - r200_color_t *color = (r200_color_t *)&((v)->ui[coloroffset]); \ + radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \ UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ @@ -472,7 +472,7 @@ do { \ #define VERT_SET_SPEC( v, c ) \ do { \ if (specoffset) { \ - r200_color_t *spec = (r200_color_t *)&((v)->ui[specoffset]); \ + radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \ UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \ UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \ UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \ @@ -481,8 +481,8 @@ do { \ #define VERT_COPY_SPEC( v0, v1 ) \ do { \ if (specoffset) { \ - r200_color_t *spec0 = (r200_color_t *)&((v0)->ui[specoffset]); \ - r200_color_t *spec1 = (r200_color_t *)&((v1)->ui[specoffset]); \ + radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \ + radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \ spec0->red = spec1->red; \ spec0->green = spec1->green; \ spec0->blue = spec1->blue; \ @@ -772,7 +772,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, r200ContextPtr rmesa = R200_CONTEXT(ctx); const GLfloat *rc = ctx->Current.RasterColor; GLint row, col; - r200Vertex vert; + radeonVertex vert; GLuint orig_vte; GLuint h; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index 8c29fd0c999..0c25d8bc83d 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -57,10 +57,10 @@ extern void r200_emit_indexed_verts( GLcontext *ctx, GLuint count ); extern void r200_translate_vertex( GLcontext *ctx, - const r200Vertex *src, + const radeonVertex *src, SWvertex *dst ); -extern void r200_print_vertex( GLcontext *ctx, const r200Vertex *v ); +extern void r200_print_vertex( GLcontext *ctx, const radeonVertex *v ); extern void r200_import_float_colors( GLcontext *ctx ); extern void r200_import_float_spec_colors( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 5a4db33f441..0cd93253664 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -63,7 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * \param twrap Wrap mode for the \a t texture coordinate */ -static void r200SetTexWrap( r200TexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap ) +static void r200SetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap ) { GLboolean is_clamp = GL_FALSE; GLboolean is_clamp_to_border = GL_FALSE; @@ -180,7 +180,7 @@ static void r200SetTexWrap( r200TexObjPtr t, GLenum swrap, GLenum twrap, GLenum t->border_fallback = (is_clamp && is_clamp_to_border); } -static void r200SetTexMaxAnisotropy( r200TexObjPtr t, GLfloat max ) +static void r200SetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max ) { t->pp_txfilter &= ~R200_MAX_ANISO_MASK; @@ -205,7 +205,7 @@ static void r200SetTexMaxAnisotropy( r200TexObjPtr t, GLfloat max ) * \param magf Texture magnification mode */ -static void r200SetTexFilter( r200TexObjPtr t, GLenum minf, GLenum magf ) +static void r200SetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) { GLuint anisotropy = (t->pp_txfilter & R200_MAX_ANISO_MASK); @@ -267,9 +267,9 @@ static void r200SetTexFilter( r200TexObjPtr t, GLenum minf, GLenum magf ) } } -static void r200SetTexBorderColor( r200TexObjPtr t, GLubyte c[4] ) +static void r200SetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] ) { - t->pp_border_color = r200PackColor( 4, c[0], c[1], c[2], c[3] ); + t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); } @@ -279,11 +279,11 @@ static void r200SetTexBorderColor( r200TexObjPtr t, GLubyte c[4] ) * texture after it was swapped out or teximaged again. */ -static r200TexObjPtr r200AllocTexObj( struct gl_texture_object *texObj ) +static radeonTexObjPtr r200AllocTexObj( struct gl_texture_object *texObj ) { - r200TexObjPtr t; + radeonTexObjPtr t; - t = CALLOC_STRUCT( r200_tex_obj ); + t = CALLOC_STRUCT( radeon_tex_obj ); texObj->DriverData = t; if ( t != NULL ) { if ( R200_DEBUG & DEBUG_TEXTURE ) { @@ -978,7 +978,7 @@ static void r200TexEnv( GLcontext *ctx, GLenum target, GLubyte c[4]; GLuint envColor; UNCLAMPED_FLOAT_TO_RGBA_CHAN( c, texUnit->EnvColor ); - envColor = r200PackColor( 4, c[0], c[1], c[2], c[3] ); + envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) { R200_STATECHANGE( rmesa, tf ); rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor; @@ -1034,7 +1034,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, struct gl_texture_object *texObj, GLenum pname, const GLfloat *params ) { - r200TexObjPtr t = (r200TexObjPtr) texObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr) texObj->DriverData; if ( R200_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { fprintf( stderr, "%s( %s )\n", __FUNCTION__, @@ -1077,7 +1077,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, /* Mark this texobj as dirty (one bit per tex unit) */ - t->dirty_state = TEX_ALL; + t->dirty_state = R200_TEX_ALL; } diff --git a/src/mesa/drivers/dri/r200/r200_tex.h b/src/mesa/drivers/dri/r200/r200_tex.h index 10ff8e8a660..55592ed4f74 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.h +++ b/src/mesa/drivers/dri/r200/r200_tex.h @@ -41,9 +41,9 @@ extern void r200SetTexOffset(__DRIcontext *pDRICtx, GLint texname, extern void r200UpdateTextureState( GLcontext *ctx ); -extern int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face ); +extern int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ); -extern void r200DestroyTexObj( r200ContextPtr rmesa, r200TexObjPtr t ); +extern void r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t ); extern void r200InitTextureFuncs( struct dd_function_table *functions ); diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index 3b81ac0c802..a8ff5394bff 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -55,7 +55,7 @@ SOFTWARE. * include NULLing out hardware state that points to the texture. */ void -r200DestroyTexObj( r200ContextPtr rmesa, r200TexObjPtr t ) +r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t ) { if ( R200_DEBUG & DEBUG_TEXTURE ) { fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, @@ -83,7 +83,7 @@ r200DestroyTexObj( r200ContextPtr rmesa, r200TexObjPtr t ) static void r200UploadGARTClientSubImage( r200ContextPtr rmesa, - r200TexObjPtr t, + radeonTexObjPtr t, struct gl_texture_image *texImage, GLint hwlevel, GLint x, GLint y, @@ -147,7 +147,7 @@ static void r200UploadGARTClientSubImage( r200ContextPtr rmesa, } static void r200UploadRectSubImage( r200ContextPtr rmesa, - r200TexObjPtr t, + radeonTexObjPtr t, struct gl_texture_image *texImage, GLint x, GLint y, GLint width, GLint height ) @@ -216,7 +216,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, /* Data not in GART memory, or bad pitch. */ for (done = 0; done < height ; ) { - struct r200_dma_region region; + struct radeon_dma_region region; int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch ); int src_pitch; char *tex; @@ -273,7 +273,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, * Upload the texture image associated with texture \a t at the specified * level at the address relative to \a start. */ -static void uploadSubImage( r200ContextPtr rmesa, r200TexObjPtr t, +static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t, GLint hwlevel, GLint x, GLint y, GLint width, GLint height, GLuint face ) @@ -458,7 +458,7 @@ static void uploadSubImage( r200ContextPtr rmesa, r200TexObjPtr t, * \param face Cube map face to be uploaded. Zero for non-cube maps. */ -int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face ) +int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) { const int numLevels = t->base.lastLevel - t->base.firstLevel + 1; @@ -500,7 +500,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face ) /* Mark this texobj as dirty on all units: */ - t->dirty_state = TEX_ALL; + t->dirty_state = R200_TEX_ALL; } /* Let the world know we've used this memory recently. diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 3f9a2f4ac1b..eeccf50c449 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -153,7 +153,7 @@ static const struct tx_table tx_table_le[] = static void r200SetTexImages( r200ContextPtr rmesa, struct gl_texture_object *tObj ) { - r200TexObjPtr t = (r200TexObjPtr)tObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData; const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; GLint curOffset, blitWidth; GLint i, texelBytes; @@ -383,7 +383,7 @@ static void r200SetTexImages( r200ContextPtr rmesa, t->pp_txpitch -= 32; } - t->dirty_state = TEX_ALL; + t->dirty_state = R200_TEX_ALL; /* FYI: r200UploadTexImages( rmesa, t ) used to be called here */ } @@ -982,12 +982,12 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, r200ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->glCtx, texname); - r200TexObjPtr t; + radeonTexObjPtr t; if (!tObj) return; - t = (r200TexObjPtr) tObj->DriverData; + t = (radeonTexObjPtr) tObj->DriverData; t->image_override = GL_TRUE; @@ -1209,7 +1209,7 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx ) static void import_tex_obj_state( r200ContextPtr rmesa, int unit, - r200TexObjPtr texobj ) + radeonTexObjPtr texobj ) { /* do not use RADEON_DB_STATE to avoid stale texture caches */ int *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; @@ -1580,7 +1580,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; - r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; /* Need to load the 2d images associated with this unit. */ @@ -1594,7 +1594,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) if ( t->base.dirty_images[0] ) { R200_FIREVERTICES( rmesa ); r200SetTexImages( rmesa, tObj ); - r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); + r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); if ( !t->base.memBlock && !t->image_override ) return GL_FALSE; } @@ -1610,7 +1610,7 @@ static GLboolean enable_tex_3d( GLcontext *ctx, int unit ) r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; - r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; /* Need to load the 3d images associated with this unit. */ @@ -1630,7 +1630,7 @@ static GLboolean enable_tex_3d( GLcontext *ctx, int unit ) if ( t->base.dirty_images[0] ) { R200_FIREVERTICES( rmesa ); r200SetTexImages( rmesa, tObj ); - r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); + r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); if ( !t->base.memBlock ) return GL_FALSE; } @@ -1646,7 +1646,7 @@ static GLboolean enable_tex_cube( GLcontext *ctx, int unit ) r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; - r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; GLuint face; /* Need to load the 2d images associated with this unit. @@ -1671,7 +1671,7 @@ static GLboolean enable_tex_cube( GLcontext *ctx, int unit ) /* upload (per face) */ for (face = 0; face < 6; face++) { if (t->base.dirty_images[face]) { - r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, face ); + r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, face ); } } @@ -1690,7 +1690,7 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; - r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; if (!(t->pp_txformat & R200_TXFORMAT_NON_POWER2)) { t->pp_txformat |= R200_TXFORMAT_NON_POWER2; @@ -1702,7 +1702,7 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) if ( t->base.dirty_images[0] ) { R200_FIREVERTICES( rmesa ); r200SetTexImages( rmesa, tObj ); - r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); + r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); if ( !t->base.memBlock && !t->image_override && !rmesa->prefer_gart_client_texturing ) @@ -1720,7 +1720,7 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit ) r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; - r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; + radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; /* Fallback if there's a texture border */ if ( tObj->Image[0][tObj->BaseLevel]->Border > 0 ) diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h new file mode 100644 index 00000000000..e9bf4137864 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -0,0 +1,178 @@ +/* This union is used to avoid warnings/miscompilation + with float to uint32_t casts due to strict-aliasing */ +typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; + +#include "main/mm.h" +#include "math/m_vector.h" + + +#define TEX_0 0x1 +#define TEX_1 0x2 +#define TEX_2 0x4 +#define TEX_3 0x8 +#define TEX_4 0x10 +#define TEX_5 0x20 + +/* Rasterizing fallbacks */ +/* See correponding strings in r200_swtcl.c */ +#define RADEON_FALLBACK_TEXTURE 0x0001 +#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 +#define RADEON_FALLBACK_STENCIL 0x0004 +#define RADEON_FALLBACK_RENDER_MODE 0x0008 +#define RADEON_FALLBACK_BLEND_EQ 0x0010 +#define RADEON_FALLBACK_BLEND_FUNC 0x0020 +#define RADEON_FALLBACK_DISABLE 0x0040 +#define RADEON_FALLBACK_BORDER_MODE 0x0080 + +#define R200_FALLBACK_TEXTURE 0x01 +#define R200_FALLBACK_DRAW_BUFFER 0x02 +#define R200_FALLBACK_STENCIL 0x04 +#define R200_FALLBACK_RENDER_MODE 0x08 +#define R200_FALLBACK_DISABLE 0x10 +#define R200_FALLBACK_BORDER_MODE 0x20 + +/* The blit width for texture uploads + */ +#define BLIT_WIDTH_BYTES 1024 + +/* Use the templated vertex format: + */ +#define COLOR_IS_RGBA +#define TAG(x) radeon##x +#include "tnl_dd/t_dd_vertex.h" +#undef TAG + +struct radeon_colorbuffer_state { + GLuint clear; + int roundEnable; +}; + +struct radeon_depthbuffer_state { + GLuint clear; + GLfloat scale; +}; + +struct radeon_scissor_state { + drm_clip_rect_t rect; + GLboolean enabled; + + GLuint numClipRects; /* Cliprects active */ + GLuint numAllocedClipRects; /* Cliprects available */ + drm_clip_rect_t *pClipRects; +}; + +struct radeon_stencilbuffer_state { + GLboolean hwBuffer; + GLuint clear; /* rb3d_stencilrefmask value */ +}; + +struct radeon_stipple_state { + GLuint mask[32]; +}; + +struct radeon_state_atom { + struct radeon_state_atom *next, *prev; + const char *name; /* for debug */ + int cmd_size; /* size in bytes */ + GLuint is_tcl; + int *cmd; /* one or more cmd's */ + int *lastcmd; /* one or more cmd's */ + GLboolean dirty; /* dirty-mark in emit_state_list */ + GLboolean(*check) (GLcontext *); /* is this state active? */ +}; + +typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; + +/* Texture object in locally shared texture space. + */ +struct radeon_tex_obj { + driTextureObject base; + + GLuint bufAddr; /* Offset to start of locally + shared texture block */ + + GLuint dirty_state; /* Flags (1 per texunit) for + whether or not this texobj + has dirty hardware state + (pp_*) that needs to be + brought into the + texunit. */ + + drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; + /* Six, for the cube faces */ + + GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + + GLuint pp_txfilter; /* hardware register values */ + GLuint pp_txformat; + GLuint pp_txformat_x; + GLuint pp_txoffset; /* Image location in texmem. + All cube faces follow. */ + GLuint pp_txsize; /* npot only */ + GLuint pp_txpitch; /* npot only */ + GLuint pp_border_color; + GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ + + GLboolean border_fallback; + + GLuint tile_bits; /* hw texture tile bits used on this texture */ +}; + +/* Need refcounting on dma buffers: + */ +struct radeon_dma_buffer { + int refcount; /* the number of retained regions in buf */ + drmBufPtr buf; +}; + +/* A retained region, eg vertices for indexed vertices. + */ +struct radeon_dma_region { + struct radeon_dma_buffer *buf; + char *address; /* == buf->address */ + int start, end, ptr; /* offsets from start of buf */ + int aos_start; + int aos_stride; + int aos_size; +}; + + +struct radeon_dma { + /* Active dma region. Allocations for vertices and retained + * regions come from here. Also used for emitting random vertices, + * these may be flushed by calling flush_current(); + */ + struct radeon_dma_region current; + + void (*flush)( void * ); + + char *buf0_address; /* start of buf[0], for index calcs */ + GLuint nr_released_bufs; /* flush after so many buffers released */ +}; + +struct radeon_ioctl { + GLuint vertex_offset; + GLuint vertex_size; +}; + +#define RADEON_MAX_PRIMS 64 + +struct radeon_prim { + GLuint start; + GLuint end; + GLuint prim; +}; + +static INLINE GLuint radeonPackColor(GLuint cpp, + GLubyte r, GLubyte g, + GLubyte b, GLubyte a) +{ + switch (cpp) { + case 2: + return PACK_COLOR_565(r, g, b); + case 4: + return PACK_COLOR_8888(a, r, g, b); + default: + return 0; + } +} diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 53df766f8cb..75ec2d15dd8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -57,45 +57,12 @@ struct radeon_context; typedef struct radeon_context radeonContextRec; typedef struct radeon_context *radeonContextPtr; -/* This union is used to avoid warnings/miscompilation - with float to uint32_t casts due to strict-aliasing */ -typedef union { - GLfloat f; - uint32_t ui32; -} float_ui32_type; - #include "radeon_lock.h" #include "radeon_screen.h" -#include "main/mm.h" - -#include "math/m_vector.h" - -#define TEX_0 0x1 -#define TEX_1 0x2 -#define TEX_2 0x4 -#define TEX_ALL 0x7 - -/* Rasterizing fallbacks */ -/* See correponding strings in r200_swtcl.c */ -#define RADEON_FALLBACK_TEXTURE 0x0001 -#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 -#define RADEON_FALLBACK_STENCIL 0x0004 -#define RADEON_FALLBACK_RENDER_MODE 0x0008 -#define RADEON_FALLBACK_BLEND_EQ 0x0010 -#define RADEON_FALLBACK_BLEND_FUNC 0x0020 -#define RADEON_FALLBACK_DISABLE 0x0040 -#define RADEON_FALLBACK_BORDER_MODE 0x0080 - -/* The blit width for texture uploads - */ -#define BLIT_WIDTH_BYTES 1024 -/* Use the templated vertex format: - */ -#define COLOR_IS_RGBA -#define TAG(x) radeon##x -#include "tnl_dd/t_dd_vertex.h" -#undef TAG +#include "common_context.h" + +#define R100_TEX_ALL 0x7 typedef void (*radeon_tri_func) (radeonContextPtr, radeonVertex *, @@ -106,33 +73,7 @@ typedef void (*radeon_line_func) (radeonContextPtr, typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); -struct radeon_colorbuffer_state { - GLuint clear; - int roundEnable; -}; -struct radeon_depthbuffer_state { - GLuint clear; - GLfloat scale; -}; - -struct radeon_scissor_state { - drm_clip_rect_t rect; - GLboolean enabled; - - GLuint numClipRects; /* Cliprects active */ - GLuint numAllocedClipRects; /* Cliprects available */ - drm_clip_rect_t *pClipRects; -}; - -struct radeon_stencilbuffer_state { - GLboolean hwBuffer; - GLuint clear; /* rb3d_stencilrefmask value */ -}; - -struct radeon_stipple_state { - GLuint mask[32]; -}; /* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ #define RADEON_ST_BIT(unit) \ @@ -141,42 +82,6 @@ struct radeon_stipple_state { #define RADEON_Q_BIT(unit) \ (unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) -typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; - -/* Texture object in locally shared texture space. - */ -struct radeon_tex_obj { - driTextureObject base; - - GLuint bufAddr; /* Offset to start of locally - shared texture block */ - - GLuint dirty_state; /* Flags (1 per texunit) for - whether or not this texobj - has dirty hardware state - (pp_*) that needs to be - brought into the - texunit. */ - - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; - /* Six, for the cube faces */ - - GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ - - GLuint pp_txfilter; /* hardware register values */ - GLuint pp_txformat; - GLuint pp_txoffset; /* Image location in texmem. - All cube faces follow. */ - GLuint pp_txsize; /* npot only */ - GLuint pp_txpitch; /* npot only */ - GLuint pp_border_color; - GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ - - GLboolean border_fallback; - - GLuint tile_bits; /* hw texture tile bits used on this texture */ -}; - struct radeon_texture_env_state { radeonTexObjPtr texobj; GLenum format; @@ -187,17 +92,6 @@ struct radeon_texture_state { struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; }; -struct radeon_state_atom { - struct radeon_state_atom *next, *prev; - const char *name; /* for debug */ - int cmd_size; /* size in bytes */ - GLuint is_tcl; - int *cmd; /* one or more cmd's */ - int *lastcmd; /* one or more cmd's */ - GLboolean dirty; /* dirty-mark in emit_state_list */ - GLboolean(*check) (GLcontext *); /* is this state active? */ -}; - /* Trying to keep these relatively short as the variables are becoming * extravagently long. Drop the driver name prefix off the front of * everything - I think we know which driver we're in by now, and keep the @@ -453,41 +347,10 @@ struct radeon_state { struct radeon_texture_state texture; }; -/* Need refcounting on dma buffers: - */ -struct radeon_dma_buffer { - int refcount; /* the number of retained regions in buf */ - drmBufPtr buf; -}; - #define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) -/* A retained region, eg vertices for indexed vertices. - */ -struct radeon_dma_region { - struct radeon_dma_buffer *buf; - char *address; /* == buf->address */ - int start, end, ptr; /* offsets from start of buf */ - int aos_start; - int aos_stride; - int aos_size; -}; - -struct radeon_dma { - /* Active dma region. Allocations for vertices and retained - * regions come from here. Also used for emitting random vertices, - * these may be flushed by calling flush_current(); - */ - struct radeon_dma_region current; - - void (*flush) (radeonContextPtr); - - char *buf0_address; /* start of buf[0], for index calcs */ - GLuint nr_released_bufs; /* flush after so many buffers released */ -}; - struct radeon_dri_mirror { __DRIcontextPrivate *context; /* DRI context */ __DRIscreenPrivate *screen; /* DRI screen */ @@ -580,18 +443,7 @@ struct radeon_swtcl_info { struct radeon_dma_region indexed_verts; }; -struct radeon_ioctl { - GLuint vertex_offset; - GLuint vertex_size; -}; -#define RADEON_MAX_PRIMS 64 - -struct radeon_prim { - GLuint start; - GLuint end; - GLuint prim; -}; /* A maximum total of 20 elements per vertex: 3 floats for position, 3 * floats for normal, 4 floats for color, 4 bytes for secondary color, @@ -707,19 +559,6 @@ struct radeon_context { #define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) -static INLINE GLuint radeonPackColor(GLuint cpp, - GLubyte r, GLubyte g, - GLubyte b, GLubyte a) -{ - switch (cpp) { - case 2: - return PACK_COLOR_565(r, g, b); - case 4: - return PACK_COLOR_8888(a, r, g, b); - default: - return 0; - } -} #define RADEON_OLD_PACKETS 1 diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 29ae17c52b8..080fbfe5f41 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1042,6 +1042,9 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) screen->kernel_mm = 1; screen->chip_flags = 0; + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, + &screen->irq); + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, &device_id); if (ret) { diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index b0aec216706..35774ab8c69 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -776,7 +776,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, /* Mark this texobj as dirty (one bit per tex unit) */ - t->dirty_state = TEX_ALL; + t->dirty_state = R100_TEX_ALL; } diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c index 5f7bbe6a4cb..786373d3004 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texmem.c +++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c @@ -373,7 +373,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac /* Mark this texobj as dirty on all units: */ - t->dirty_state = TEX_ALL; + t->dirty_state = R100_TEX_ALL; } diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 1e2f654addf..54674a7fa2a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -350,7 +350,7 @@ static void radeonSetTexImages( radeonContextPtr rmesa, t->pp_txpitch -= 32; } - t->dirty_state = TEX_ALL; + t->dirty_state = R100_TEX_ALL; /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */ } -- cgit v1.2.3 From b6e486906968d82c7b8a869d7ab51697a7cce80c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 06:28:43 +1000 Subject: radeon/r200: move state atom to common header --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 6 +- src/mesa/drivers/dri/r200/r200_context.h | 118 ++++++++---------------- src/mesa/drivers/dri/r200/r200_ioctl.h | 2 +- src/mesa/drivers/dri/r200/r200_state_init.c | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 24 +++-- src/mesa/drivers/dri/radeon/common_context.h | 39 +++++++- src/mesa/drivers/dri/radeon/radeon_context.h | 33 ------- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 6 +- src/mesa/drivers/dri/radeon/radeon_state_init.c | 10 +- 9 files changed, 103 insertions(+), 137 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index b7f025ca5ff..a426e7ad3fa 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -45,7 +45,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_sanity.h" #include "radeon_reg.h" -static void print_state_atom( struct r200_state_atom *state ) +static void print_state_atom( struct radeon_state_atom *state ) { int i; @@ -118,7 +118,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) static void r200SaveHwState( r200ContextPtr rmesa ) { - struct r200_state_atom *atom; + struct radeon_state_atom *atom; char * dest = rmesa->backup_store.cmd_buf; if (R200_DEBUG & DEBUG_STATE) @@ -146,7 +146,7 @@ void r200EmitState( r200ContextPtr rmesa ) { char *dest; int mtu; - struct r200_state_atom *atom; + struct radeon_state_atom *atom; if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index dd9944173ae..4349730bfd5 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -106,18 +106,6 @@ struct r200_texture_state { }; -struct r200_state_atom { - struct r200_state_atom *next, *prev; - const char *name; /* for debug */ - int cmd_size; /* size in bytes */ - GLuint is_tcl; - GLuint idx; - int *cmd; /* one or more cmd's */ - int *lastcmd; /* one or more cmd's */ - GLboolean dirty; - GLboolean (*check)( GLcontext *, int ); /* is this state active? */ -}; - /* Trying to keep these relatively short as the variables are becoming * extravagently long. Drop the driver name prefix off the front of * everything - I think we know which driver we're in by now, and keep the @@ -493,48 +481,48 @@ struct r200_state_atom { struct r200_hw_state { /* Head of the linked list of state atoms. */ - struct r200_state_atom atomlist; + struct radeon_state_atom atomlist; /* Hardware state, stored as cmdbuf commands: * -- Need to doublebuffer for * - reviving state after loss of context * - eliding noop statechange loops? (except line stipple count) */ - struct r200_state_atom ctx; - struct r200_state_atom set; - struct r200_state_atom vte; - struct r200_state_atom lin; - struct r200_state_atom msk; - struct r200_state_atom vpt; - struct r200_state_atom vap; - struct r200_state_atom vtx; - struct r200_state_atom tcl; - struct r200_state_atom msl; - struct r200_state_atom tcg; - struct r200_state_atom msc; - struct r200_state_atom cst; - struct r200_state_atom tam; - struct r200_state_atom tf; - struct r200_state_atom tex[6]; - struct r200_state_atom cube[6]; - struct r200_state_atom zbs; - struct r200_state_atom mtl[2]; - struct r200_state_atom mat[9]; - struct r200_state_atom lit[8]; /* includes vec, scl commands */ - struct r200_state_atom ucp[6]; - struct r200_state_atom pix[6]; /* pixshader stages */ - struct r200_state_atom eye; /* eye pos */ - struct r200_state_atom grd; /* guard band clipping */ - struct r200_state_atom fog; - struct r200_state_atom glt; - struct r200_state_atom prf; - struct r200_state_atom afs[2]; - struct r200_state_atom pvs; - struct r200_state_atom vpi[2]; - struct r200_state_atom vpp[2]; - struct r200_state_atom atf; - struct r200_state_atom spr; - struct r200_state_atom ptp; + struct radeon_state_atom ctx; + struct radeon_state_atom set; + struct radeon_state_atom vte; + struct radeon_state_atom lin; + struct radeon_state_atom msk; + struct radeon_state_atom vpt; + struct radeon_state_atom vap; + struct radeon_state_atom vtx; + struct radeon_state_atom tcl; + struct radeon_state_atom msl; + struct radeon_state_atom tcg; + struct radeon_state_atom msc; + struct radeon_state_atom cst; + struct radeon_state_atom tam; + struct radeon_state_atom tf; + struct radeon_state_atom tex[6]; + struct radeon_state_atom cube[6]; + struct radeon_state_atom zbs; + struct radeon_state_atom mtl[2]; + struct radeon_state_atom mat[9]; + struct radeon_state_atom lit[8]; /* includes vec, scl commands */ + struct radeon_state_atom ucp[6]; + struct radeon_state_atom pix[6]; /* pixshader stages */ + struct radeon_state_atom eye; /* eye pos */ + struct radeon_state_atom grd; /* guard band clipping */ + struct radeon_state_atom fog; + struct radeon_state_atom glt; + struct radeon_state_atom prf; + struct radeon_state_atom afs[2]; + struct radeon_state_atom pvs; + struct radeon_state_atom vpi[2]; + struct radeon_state_atom vpp[2]; + struct radeon_state_atom atf; + struct radeon_state_atom spr; + struct radeon_state_atom ptp; int max_state_size; /* Number of bytes necessary for a full state emit. */ GLboolean is_dirty, all_dirty; @@ -545,9 +533,6 @@ struct r200_state { */ struct radeon_colorbuffer_state color; struct radeon_depthbuffer_state depth; -#if 00 - struct r200_pixel_state pixel; -#endif struct radeon_scissor_state scissor; struct radeon_stencilbuffer_state stencil; struct radeon_stipple_state stipple; @@ -559,19 +544,6 @@ struct r200_state { (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) -struct r200_dri_mirror { - __DRIcontextPrivate *context; /* DRI context */ - __DRIscreenPrivate *screen; /* DRI screen */ - __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */ - __DRIdrawablePrivate *readable; /* DRI readable bound to this ctx */ - - drm_context_t hwContext; - drm_hw_lock_t *hwLock; - int fd; - int drmMinor; -}; - - #define R200_CMD_BUF_SZ (16*1024) struct r200_store { @@ -760,7 +732,7 @@ struct r200_context { /* Mirrors of some DRI state */ - struct r200_dri_mirror dri; + struct radeon_dri_mirror dri; /* Configuration cache */ @@ -798,20 +770,6 @@ extern int R200_DEBUG; #define R200_DEBUG 0 #endif -#define DEBUG_TEXTURE 0x001 -#define DEBUG_STATE 0x002 -#define DEBUG_IOCTL 0x004 -#define DEBUG_PRIMS 0x008 -#define DEBUG_VERTS 0x010 -#define DEBUG_FALLBACKS 0x020 -#define DEBUG_VFMT 0x040 -#define DEBUG_CODEGEN 0x080 -#define DEBUG_VERBOSE 0x100 -#define DEBUG_DRI 0x200 -#define DEBUG_DMA 0x400 -#define DEBUG_SANITY 0x800 -#define DEBUG_SYNC 0x1000 -#define DEBUG_PIXEL 0x2000 -#define DEBUG_MEMORY 0x4000 + #endif /* __R200_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index b760dd6eeca..d37efddaef7 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -139,7 +139,7 @@ do { \ static INLINE int R200_DB_STATECHANGE( r200ContextPtr rmesa, - struct r200_state_atom *atom ) + struct radeon_state_atom *atom ) { if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { int *tmp; diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 9e4677eda40..21b61243fd1 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -58,7 +58,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) { - struct r200_state_atom *l; + struct radeon_state_atom *l; fprintf(stderr, msg); fprintf(stderr, ": "); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 4fea8228910..ed75bdd2c96 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -461,8 +461,8 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) { - struct gl_texture_unit *texUnit; - struct gl_texture_object *texObj; + struct gl_texture_unit *texUnit; + struct gl_texture_object *texObj; struct gl_texture_image *texImage; struct radeon_renderbuffer *rb; r300_texture_image *rImage; @@ -472,18 +472,21 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) r300TexObjPtr t; uint32_t pitch_val; - target = GL_TEXTURE_RECTANGLE_ARB; + target = GL_TEXTURE_RECTANGLE_ARB; + radeon = pDRICtx->driverPrivate; rmesa = pDRICtx->driverPrivate; + fb = dPriv->driverPrivate; - texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; - texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); - texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + rImage = get_r300_texture_image(texImage); t = r300_tex_obj(texObj); - if (t == NULL) { - return; - } + if (t == NULL) { + return; + } radeon_update_renderbuffers(pDRICtx, dPriv); /* back & depth buffer are useless free them right away */ @@ -514,8 +517,9 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) r300_miptree_unreference(rImage->mt); rImage->mt = NULL; } + fprintf(stderr,"settexbuf %dx%d@%d\n", rb->width, rb->height, rb->cpp); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, - rb->width, rb->height, rb->cpp, 0, rb->cpp); + rb->width, rb->height, 1, 0, rb->cpp); texImage->TexFormat = &_mesa_texformat_rgba8888_rev; rImage->bo = rb->bo; diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index e9bf4137864..d8539df6df0 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -74,11 +74,12 @@ struct radeon_state_atom { struct radeon_state_atom *next, *prev; const char *name; /* for debug */ int cmd_size; /* size in bytes */ + GLuint idx; GLuint is_tcl; int *cmd; /* one or more cmd's */ int *lastcmd; /* one or more cmd's */ GLboolean dirty; /* dirty-mark in emit_state_list */ - GLboolean(*check) (GLcontext *); /* is this state active? */ + GLboolean(*check) (GLcontext *, int idx); /* is this state active? */ }; typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; @@ -176,3 +177,39 @@ static INLINE GLuint radeonPackColor(GLuint cpp, return 0; } } + +struct radeon_dri_mirror { + __DRIcontextPrivate *context; /* DRI context */ + __DRIscreenPrivate *screen; /* DRI screen */ + + /** + * DRI drawable bound to this context for drawing. + */ + __DRIdrawablePrivate *drawable; + + /** + * DRI drawable bound to this context for reading. + */ + __DRIdrawablePrivate *readable; + + drm_context_t hwContext; + drm_hw_lock_t *hwLock; + int fd; + int drmMinor; +}; + +#define DEBUG_TEXTURE 0x001 +#define DEBUG_STATE 0x002 +#define DEBUG_IOCTL 0x004 +#define DEBUG_PRIMS 0x008 +#define DEBUG_VERTS 0x010 +#define DEBUG_FALLBACKS 0x020 +#define DEBUG_VFMT 0x040 +#define DEBUG_CODEGEN 0x080 +#define DEBUG_VERBOSE 0x100 +#define DEBUG_DRI 0x200 +#define DEBUG_DMA 0x400 +#define DEBUG_SANITY 0x800 +#define DEBUG_SYNC 0x1000 +#define DEBUG_PIXEL 0x2000 +#define DEBUG_MEMORY 0x4000 diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 75ec2d15dd8..bdd4a476098 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -351,25 +351,6 @@ struct radeon_state { (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) -struct radeon_dri_mirror { - __DRIcontextPrivate *context; /* DRI context */ - __DRIscreenPrivate *screen; /* DRI screen */ - - /** - * DRI drawable bound to this context for drawing. - */ - __DRIdrawablePrivate *drawable; - - /** - * DRI drawable bound to this context for reading. - */ - __DRIdrawablePrivate *readable; - - drm_context_t hwContext; - drm_hw_lock_t *hwLock; - int fd; - int drmMinor; -}; #define RADEON_CMD_BUF_SZ (8*1024) @@ -585,18 +566,4 @@ extern int RADEON_DEBUG; #define RADEON_DEBUG 0 #endif -#define DEBUG_TEXTURE 0x0001 -#define DEBUG_STATE 0x0002 -#define DEBUG_IOCTL 0x0004 -#define DEBUG_PRIMS 0x0008 -#define DEBUG_VERTS 0x0010 -#define DEBUG_FALLBACKS 0x0020 -#define DEBUG_VFMT 0x0040 -#define DEBUG_CODEGEN 0x0080 -#define DEBUG_VERBOSE 0x0100 -#define DEBUG_DRI 0x0200 -#define DEBUG_DMA 0x0400 -#define DEBUG_SANITY 0x0800 -#define DEBUG_SYNC 0x1000 - #endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 09acf6b4f85..9858dacc136 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -85,7 +85,7 @@ static void radeonSaveHwState( radeonContextPtr rmesa ) rmesa->backup_store.cmd_used = 0; foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->check( rmesa->glCtx ) ) { + if ( atom->check( rmesa->glCtx, 0 ) ) { int size = atom->cmd_size * 4; memcpy( dest, atom->cmd, size); dest += size; @@ -198,7 +198,7 @@ void radeonEmitState( radeonContextPtr rmesa ) if (RADEON_DEBUG & DEBUG_STATE) { foreach(atom, &rmesa->hw.atomlist) { if (atom->dirty || rmesa->hw.all_dirty) { - if (atom->check(rmesa->glCtx)) + if (atom->check(rmesa->glCtx, 0)) print_state_atom(atom); else fprintf(stderr, "skip state %s\n", atom->name); @@ -213,7 +213,7 @@ void radeonEmitState( radeonContextPtr rmesa ) atom->is_tcl) atom->dirty = GL_FALSE; if (atom->dirty) { - if (atom->check(rmesa->glCtx)) { + if (atom->check(rmesa->glCtx, 0)) { int size = atom->cmd_size * 4; memcpy(dest, atom->cmd, size); dest += size; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 57dc3800501..5b1e79bad24 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -96,14 +96,14 @@ static int cmdscl( int offset, int stride, int count ) return h.i; } -#define CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx ) \ -{ \ - return FLAG; \ +#define CHECK( NM, FLAG ) \ +static GLboolean check_##NM( GLcontext *ctx, int idx ) \ +{ \ + return FLAG; \ } #define TCL_CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx ) \ +static GLboolean check_##NM( GLcontext *ctx, int idx ) \ { \ radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ return !rmesa->TclFallback && (FLAG); \ -- cgit v1.2.3 From 0217ed2cf9b0a538ca03d26b302a7cd57af7dd21 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 08:40:15 +1000 Subject: radeon/r200: move more stuff closer together in context --- src/mesa/drivers/dri/r200/r200_context.c | 34 +++++++------- src/mesa/drivers/dri/r200/r200_context.h | 16 ++----- src/mesa/drivers/dri/r200/r200_ioctl.c | 44 +++++++++--------- src/mesa/drivers/dri/r200/r200_pixel.c | 24 +++++----- src/mesa/drivers/dri/r200/r200_state.c | 12 ++--- src/mesa/drivers/dri/r200/r200_state_init.c | 68 ++++++++++++++-------------- src/mesa/drivers/dri/r200/r200_swtcl.c | 2 +- src/mesa/drivers/dri/r200/r200_texmem.c | 2 +- src/mesa/drivers/dri/r200/r200_texstate.c | 6 +-- src/mesa/drivers/dri/r200/r200_vertprog.c | 2 +- src/mesa/drivers/dri/radeon/common_context.h | 11 +++++ src/mesa/drivers/dri/radeon/radeon_context.h | 8 ---- 12 files changed, 112 insertions(+), 117 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index e8d4ca25375..6a1b9fb9fdf 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -93,8 +93,8 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) r200ContextPtr rmesa = R200_CONTEXT(ctx); static char buffer[128]; unsigned offset; - GLuint agp_mode = (rmesa->r200Screen->card_type == RADEON_CARD_PCI)? 0 : - rmesa->r200Screen->AGPMode; + GLuint agp_mode = (rmesa->radeonScreen->card_type == RADEON_CARD_PCI)? 0 : + rmesa->radeonScreen->AGPMode; switch ( name ) { case GL_VENDOR: @@ -321,12 +321,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa->dri.fd = sPriv->fd; rmesa->dri.drmMinor = sPriv->drm_version.minor; - rmesa->r200Screen = screen; + rmesa->radeonScreen = screen; rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + screen->sarea_priv_offset); - rmesa->dma.buf0_address = rmesa->r200Screen->buffers->list[0].address; + rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address; (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) ); make_empty_list( & rmesa->swapped ); @@ -391,7 +391,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, ctx->Const.MinPointSizeAA = 1.0; ctx->Const.MaxPointSizeAA = 1.0; ctx->Const.PointSizeGranularity = 0.0625; - if (rmesa->r200Screen->drmSupportsPointSprites) + if (rmesa->radeonScreen->drmSupportsPointSprites) ctx->Const.MaxPointSize = 2047.0; else ctx->Const.MaxPointSize = 1.0; @@ -445,7 +445,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, _math_matrix_set_identity( &rmesa->tmpmat ); driInitExtensions( ctx, card_extensions, GL_TRUE ); - if (!(rmesa->r200Screen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { + if (!(rmesa->radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { /* yuv textures don't work with some chips - R200 / rv280 okay so far others get the bit ordering right but don't actually do YUV-RGB conversion */ _mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" ); @@ -458,19 +458,19 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); } - if (rmesa->r200Screen->drmSupportsCubeMapsR200) + if (rmesa->radeonScreen->drmSupportsCubeMapsR200) _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" ); - if (rmesa->r200Screen->drmSupportsBlendColor) { + if (rmesa->radeonScreen->drmSupportsBlendColor) { driInitExtensions( ctx, blend_extensions, GL_FALSE ); } - if(rmesa->r200Screen->drmSupportsVertexProgram) + if(rmesa->radeonScreen->drmSupportsVertexProgram) driInitSingleExtension( ctx, ARB_vp_extension ); if(driQueryOptionb(&rmesa->optionCache, "nv_vertex_program")) driInitSingleExtension( ctx, NV_vp_extension ); - if ((ctx->Const.MaxTextureUnits == 6) && rmesa->r200Screen->drmSupportsFragShader) + if ((ctx->Const.MaxTextureUnits == 6) && rmesa->radeonScreen->drmSupportsFragShader) driInitSingleExtension( ctx, ATI_fs_extension ); - if (rmesa->r200Screen->drmSupportsPointSprites) + if (rmesa->radeonScreen->drmSupportsPointSprites) driInitExtensions( ctx, point_extensions, GL_FALSE ); #if 0 r200InitDriverFuncs( ctx ); @@ -490,7 +490,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa->iw.irq_seq = -1; rmesa->irqsEmitted = 0; rmesa->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - rmesa->r200Screen->irq); + rmesa->radeonScreen->irq); rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); @@ -499,7 +499,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, "IRQ's not enabled, falling back to %s: %d %d\n", rmesa->do_usleeps ? "usleeps" : "busy waits", fthrottle_mode, - rmesa->r200Screen->irq); + rmesa->radeonScreen->irq); rmesa->prefer_gart_client_texturing = (getenv("R200_GART_CLIENT_TEXTURES") != 0); @@ -520,9 +520,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1); } else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") || - !(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) { - if (rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL) { - rmesa->r200Screen->chip_flags &= ~RADEON_CHIPSET_TCL; + !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; fprintf(stderr, "Disabling HW TCL support\n"); } TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1); @@ -670,7 +670,7 @@ r200MakeCurrent( __DRIcontextPrivate *driContextPriv, if ( newCtx->dri.drawable != driDrawPriv || newCtx->lastStamp != driDrawPriv->lastStamp ) { if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->r200Screen->irq != 0) + driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0) ? driGetDefaultVBlankFlags(&newCtx->optionCache) : VBLANK_FLAG_NO_IRQ; diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 4349730bfd5..64f773826c4 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -540,20 +540,12 @@ struct r200_state { GLuint envneeded; }; -#define GET_START(rvb) (rmesa->r200Screen->gart_buffer_offset + \ +#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) #define R200_CMD_BUF_SZ (16*1024) -struct r200_store { - GLuint statenr; - GLuint primnr; - char cmd_buf[R200_CMD_BUF_SZ]; - int cmd_used; - int elts_start; -}; - /* r200_tcl.c */ @@ -671,11 +663,11 @@ struct r200_context { */ struct radeon_ioctl ioctl; struct radeon_dma dma; - struct r200_store store; + struct radeon_store store; /* A full state emit as of the first state emit in the main store, in case * the context is lost. */ - struct r200_store backup_store; + struct radeon_store backup_store; /* Page flipping */ @@ -699,7 +691,7 @@ struct r200_context { unsigned int lastStamp; GLboolean lost_context; GLboolean save_on_next_emit; - radeonScreenPtr r200Screen; /* Screen private DRI data */ + radeonScreenPtr radeonScreen; /* Screen private DRI data */ drm_radeon_sarea_t *sarea; /* Private SAREA data */ /* TCL stuff diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 8ad3a676738..da9a293241c 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -66,7 +66,7 @@ static void r200WaitForIdle( r200ContextPtr rmesa ); static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) { GLuint nr_released_bufs; - struct r200_store saved_store; + struct radeon_store saved_store; if (rmesa->backup_store.cmd_used == 0) return; @@ -249,7 +249,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) fprintf(stderr, "Allocated buffer %d\n", index); dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); - dmabuf->buf = &rmesa->r200Screen->buffers->list[index]; + dmabuf->buf = &rmesa->radeonScreen->buffers->list[index]; dmabuf->refcount = 1; rmesa->dma.current.buf = dmabuf; @@ -578,16 +578,16 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) #if 000 if ( rmesa->sarea->pfCurrentPage == 1 ) { - rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset; - rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch; + rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset; + rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch; } else { - rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset; - rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch; + rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset; + rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch; } R200_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset - + rmesa->r200Screen->fbLocation; + + rmesa->radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; if (rmesa->sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; @@ -663,7 +663,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) if (rmesa->using_hyperz) { flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) +/* if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) flags |= RADEON_USE_HIERZ; */ if (!(rmesa->state.stencil.hwBuffer) || ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && @@ -875,7 +875,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, writefreq, priority); - if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->r200Screen->gartTextures.map) + if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeonScreen->gartTextures.map) return NULL; if (getenv("R200_NO_ALLOC")) @@ -886,7 +886,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, alloc.size = size; alloc.region_offset = ®ion_offset; - ret = drmCommandWriteRead( rmesa->r200Screen->driScreen->fd, + ret = drmCommandWriteRead( rmesa->radeonScreen->driScreen->fd, DRM_RADEON_ALLOC, &alloc, sizeof(alloc)); @@ -896,7 +896,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, } { - char *region_start = (char *)rmesa->r200Screen->gartTextures.map; + char *region_start = (char *)rmesa->radeonScreen->gartTextures.map; return (void *)(region_start + region_offset); } } @@ -914,24 +914,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %p\n", __FUNCTION__, pointer); - if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->r200Screen->gartTextures.map) { + if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeonScreen->gartTextures.map) { fprintf(stderr, "%s: no context\n", __FUNCTION__); return; } - region_offset = (char *)pointer - (char *)rmesa->r200Screen->gartTextures.map; + region_offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map; if (region_offset < 0 || - region_offset > rmesa->r200Screen->gartTextures.size) { + region_offset > rmesa->radeonScreen->gartTextures.size) { fprintf(stderr, "offset %d outside range 0..%d\n", region_offset, - rmesa->r200Screen->gartTextures.size); + rmesa->radeonScreen->gartTextures.size); return; } memfree.region = RADEON_MEM_REGION_GART; memfree.region_offset = region_offset; - ret = drmCommandWrite( rmesa->r200Screen->driScreen->fd, + ret = drmCommandWrite( rmesa->radeonScreen->driScreen->fd, DRM_RADEON_FREE, &memfree, sizeof(memfree)); @@ -956,16 +956,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer) card_offset = r200GartOffsetFromVirtual( rmesa, pointer ); - return card_offset - rmesa->r200Screen->gart_base; + return card_offset - rmesa->radeonScreen->gart_base; } GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, GLint size ) { - ptrdiff_t offset = (char *)pointer - (char *)rmesa->r200Screen->gartTextures.map; + ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map; int valid = (size >= 0 && offset >= 0 && - offset + size < rmesa->r200Screen->gartTextures.size); + offset + size < rmesa->radeonScreen->gartTextures.size); if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid ); @@ -976,12 +976,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) { - ptrdiff_t offset = (char *)pointer - (char *)rmesa->r200Screen->gartTextures.map; + ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map; - if (offset < 0 || offset > rmesa->r200Screen->gartTextures.size) + if (offset < 0 || offset > rmesa->radeonScreen->gartTextures.size) return ~0; else - return rmesa->r200Screen->gart_texture_offset + offset; + return rmesa->radeonScreen->gart_texture_offset + offset; } diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index be68821dc1d..77506c5532e 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -51,7 +51,7 @@ check_color( const GLcontext *ctx, GLenum type, GLenum format, const void *pixels, GLint sz, GLint pitch ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint cpp = rmesa->r200Screen->cpp; + GLuint cpp = rmesa->radeonScreen->cpp; if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -137,8 +137,8 @@ clip_pixelrect( const GLcontext *ctx, if (*height <= 0) return GL_FALSE; - *size = ((*y + *height - 1) * rmesa->r200Screen->frontPitch + - (*x + *width - 1) * rmesa->r200Screen->cpp); + *size = ((*y + *height - 1) * rmesa->radeonScreen->frontPitch + + (*x + *width - 1) * rmesa->radeonScreen->cpp); return GL_TRUE; } @@ -153,7 +153,7 @@ r200TryReadPixels( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT(ctx); GLint pitch = pack->RowLength ? pack->RowLength : width; GLint blit_format; - GLuint cpp = rmesa->r200Screen->cpp; + GLuint cpp = rmesa->radeonScreen->cpp; GLint size = width * height * cpp; if (R200_DEBUG & DEBUG_PIXEL) @@ -162,7 +162,7 @@ r200TryReadPixels( GLcontext *ctx, /* Only accelerate reading to GART buffers. */ if ( !r200IsGartMemory(rmesa, pixels, - pitch * height * rmesa->r200Screen->cpp ) ) { + pitch * height * rmesa->radeonScreen->cpp ) ) { if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: dest not GART\n", __FUNCTION__); return GL_FALSE; @@ -180,7 +180,7 @@ r200TryReadPixels( GLcontext *ctx, if (!check_color(ctx, type, format, pack, pixels, size, pitch)) return GL_FALSE; - switch ( rmesa->r200Screen->cpp ) { + switch ( rmesa->radeonScreen->cpp ) { case 4: blit_format = R200_CP_COLOR_FORMAT_ARGB8888; break; @@ -216,10 +216,10 @@ r200TryReadPixels( GLcontext *ctx, driRenderbuffer *drb = (driRenderbuffer *) ctx->ReadBuffer->_ColorReadBuffer; int nbox = dPriv->numClipRects; int src_offset = drb->offset - + rmesa->r200Screen->fbLocation; + + rmesa->radeonScreen->fbLocation; int src_pitch = drb->pitch * drb->cpp; int dst_offset = r200GartOffsetFromVirtual( rmesa, pixels ); - int dst_pitch = pitch * rmesa->r200Screen->cpp; + int dst_pitch = pitch * rmesa->radeonScreen->cpp; drm_clip_rect_t *box = dPriv->pClipRects; int i; @@ -301,12 +301,12 @@ static void do_draw_pix( GLcontext *ctx, int blit_format; int size; int src_offset = r200GartOffsetFromVirtual( rmesa, pixels ); - int src_pitch = pitch * rmesa->r200Screen->cpp; + int src_pitch = pitch * rmesa->radeonScreen->cpp; if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); - switch ( rmesa->r200Screen->cpp ) { + switch ( rmesa->radeonScreen->cpp ) { case 2: blit_format = R200_CP_COLOR_FORMAT_RGB565; break; @@ -357,7 +357,7 @@ static void do_draw_pix( GLcontext *ctx, blit_format, src_pitch, src_offset, drb->pitch * drb->cpp, - drb->offset + rmesa->r200Screen->fbLocation, + drb->offset + rmesa->radeonScreen->fbLocation, bx - x, by - y, bx, by, bw, bh ); @@ -381,7 +381,7 @@ r200TryDrawPixels( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT(ctx); GLint pitch = unpack->RowLength ? unpack->RowLength : width; GLuint planemask; - GLuint cpp = rmesa->r200Screen->cpp; + GLuint cpp = rmesa->radeonScreen->cpp; GLint size = height * pitch * cpp; if (R200_DEBUG & DEBUG_PIXEL) diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 7fd93a749e5..8e9f2562a18 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -114,7 +114,7 @@ static void r200BlendColor( GLcontext *ctx, const GLfloat cf[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); - if (rmesa->r200Screen->drmSupportsBlendColor) + if (rmesa->radeonScreen->drmSupportsBlendColor) rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] ); } @@ -213,7 +213,7 @@ static void r200_set_blend_state( GLcontext * ctx ) R200_STATECHANGE( rmesa, ctx ); - if (rmesa->r200Screen->drmSupportsBlendColor) { + if (rmesa->radeonScreen->drmSupportsBlendColor) { if (ctx->Color.ColorLogicOpEnabled) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func; @@ -278,7 +278,7 @@ static void r200_set_blend_state( GLcontext * ctx ) return; } - if (!rmesa->r200Screen->drmSupportsBlendColor) { + if (!rmesa->radeonScreen->drmSupportsBlendColor) { rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = eqn | func; return; } @@ -803,7 +803,7 @@ static void r200ColorMask( GLcontext *ctx, GLboolean b, GLboolean a ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint mask = radeonPackColor( rmesa->r200Screen->cpp, + GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp, ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], @@ -1805,7 +1805,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); - rmesa->state.color.clear = radeonPackColor( rmesa->r200Screen->cpp, + rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp, color[0], color[1], color[2], color[3] ); } @@ -2465,7 +2465,7 @@ r200UpdateDrawBuffer(GLcontext *ctx) /* Note: we used the (possibly) page-flipped values */ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->r200Screen->fbLocation) + = ((drb->flippedOffset + rmesa->radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; if (rmesa->sarea->tiling_enabled) { diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 21b61243fd1..724c224c5e8 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -191,7 +191,7 @@ void r200InitState( r200ContextPtr rmesa ) GLuint color_fmt, depth_fmt, i; GLint drawPitch, drawOffset; - switch ( rmesa->r200Screen->cpp ) { + switch ( rmesa->radeonScreen->cpp ) { case 2: color_fmt = R200_COLOR_FORMAT_RGB565; break; @@ -231,19 +231,19 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->Fallback = 0; if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - drawOffset = rmesa->r200Screen->backOffset; - drawPitch = rmesa->r200Screen->backPitch; + drawOffset = rmesa->radeonScreen->backOffset; + drawPitch = rmesa->radeonScreen->backPitch; } else { - drawOffset = rmesa->r200Screen->frontOffset; - drawPitch = rmesa->r200Screen->frontPitch; + drawOffset = rmesa->radeonScreen->frontOffset; + drawPitch = rmesa->radeonScreen->frontPitch; } #if 000 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset; - rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch; + rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset; + rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch; } else { - rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset; - rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch; + rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset; + rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch; } rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; @@ -267,7 +267,7 @@ void r200InitState( r200ContextPtr rmesa ) /* Allocate state buffers: */ - if (rmesa->r200Screen->drmSupportsBlendColor) + if (rmesa->radeonScreen->drmSupportsBlendColor) ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); @@ -282,8 +282,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); - if (rmesa->r200Screen->drmSupportsFragShader) { - if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) { + if (rmesa->radeonScreen->drmSupportsFragShader) { + if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) { /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); @@ -303,7 +303,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } else { - if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) { + if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) { ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); @@ -321,7 +321,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } - if (rmesa->r200Screen->drmSupportsCubeMapsR200) { + if (rmesa->radeonScreen->drmSupportsCubeMapsR200) { ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); @@ -337,7 +337,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); } - if (rmesa->r200Screen->drmSupportsVertexProgram) { + if (rmesa->radeonScreen->drmSupportsVertexProgram) { ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); @@ -390,13 +390,13 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); - if (rmesa->r200Screen->drmSupportsTriPerf) { + if (rmesa->radeonScreen->drmSupportsTriPerf) { ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); } else { ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); } - if (rmesa->r200Screen->drmSupportsPointSprites) { + if (rmesa->radeonScreen->drmSupportsPointSprites) { ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 ); } @@ -412,7 +412,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); - if (rmesa->r200Screen->drmSupportsBlendColor) + if (rmesa->radeonScreen->drmSupportsBlendColor) rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR); rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); @@ -429,7 +429,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3); rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0); - if (rmesa->r200Screen->drmSupportsFragShader) { + if (rmesa->radeonScreen->drmSupportsFragShader) { rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR); rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0); rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0); @@ -567,7 +567,7 @@ void r200InitState( r200ContextPtr rmesa ) (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - if (rmesa->r200Screen->drmSupportsBlendColor) { + if (rmesa->radeonScreen->drmSupportsBlendColor) { rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | @@ -578,10 +578,10 @@ void r200InitState( r200ContextPtr rmesa ) } rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->r200Screen->depthOffset + rmesa->r200Screen->fbLocation; + rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = - ((rmesa->r200Screen->depthPitch & + ((rmesa->radeonScreen->depthPitch & R200_DEPTHPITCH_MASK) | R200_DEPTH_ENDIAN_NO_SWAP); @@ -599,7 +599,7 @@ void r200InitState( r200ContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | R200_Z_DECOMPRESSION_ENABLE; -/* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) +/* if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ } @@ -628,7 +628,7 @@ void r200InitState( r200ContextPtr rmesa ) #if 000 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + - rmesa->r200Screen->fbLocation) + rmesa->radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & @@ -636,7 +636,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_COLOR_ENDIAN_NO_SWAP); #else rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + - rmesa->r200Screen->fbLocation) + rmesa->radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & @@ -704,7 +704,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_VC_NO_SWAP; #endif - if (!(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) { + if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { /* Bypass TCL */ rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); } @@ -743,28 +743,28 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ 0x100000); /* Small default bias */ - if (rmesa->r200Screen->drmSupportsFragShader) { + if (rmesa->radeonScreen->drmSupportsFragShader) { rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; } else { rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; } rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = - rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = (R200_TXC_ARG_A_ZERO | diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index e4a5c129cec..104c4945629 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -285,7 +285,7 @@ static void flush_last_swtcl_prim( r200ContextPtr rmesa ) if (rmesa->dma.current.buf) { struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->r200Screen->gart_buffer_offset + + GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset + current->buf->buf->idx * RADEON_BUFFER_SIZE + current->start); diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index a8ff5394bff..3a700def050 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -489,7 +489,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) } /* Set the base offset of the texture image */ - t->bufAddr = rmesa->r200Screen->texOffset[heap] + t->bufAddr = rmesa->radeonScreen->texOffset[heap] + t->base.memBlock->ofs; t->pp_txoffset = t->bufAddr; diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index eeccf50c449..b5dfe304247 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1225,7 +1225,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa, cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */ cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */ cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; - if (rmesa->r200Screen->drmSupportsFragShader) { + if (rmesa->radeonScreen->drmSupportsFragShader) { cmd[TEX_PP_TXOFFSET_NEWDRM] = texobj->pp_txoffset; } else { @@ -1239,7 +1239,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa, R200_STATECHANGE( rmesa, cube[unit] ); cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; - if (rmesa->r200Screen->drmSupportsFragShader) { + if (rmesa->radeonScreen->drmSupportsFragShader) { /* that value is submitted twice. could change cube atom to not include that command when new drm is used */ cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces; @@ -1850,7 +1850,7 @@ void r200UpdateTextureState( GLcontext *ctx ) r200ChooseVertexState( ctx ); - if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) { + if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) { /* * T0 hang workaround ------------- diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c index 562992fbb5c..4a25031e039 100644 --- a/src/mesa/drivers/dri/r200/r200_vertprog.c +++ b/src/mesa/drivers/dri/r200/r200_vertprog.c @@ -1110,7 +1110,7 @@ void r200SetupVertexProg( GLcontext *ctx ) { } /* could optimize setting up vertex progs away for non-tcl hw */ fallback = !(vp->native && r200VertexProgUpdateParams(ctx, vp) && - rmesa->r200Screen->drmSupportsVertexProgram); + rmesa->radeonScreen->drmSupportsVertexProgram); TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, fallback); if (rmesa->TclFallback) return; diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index d8539df6df0..471763d4180 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -178,6 +178,16 @@ static INLINE GLuint radeonPackColor(GLuint cpp, } } +#define MAX_CMD_BUF_SZ (16*1024) + +struct radeon_store { + GLuint statenr; + GLuint primnr; + char cmd_buf[MAX_CMD_BUF_SZ]; + int cmd_used; + int elts_start; +}; + struct radeon_dri_mirror { __DRIcontextPrivate *context; /* DRI context */ __DRIscreenPrivate *screen; /* DRI screen */ @@ -213,3 +223,4 @@ struct radeon_dri_mirror { #define DEBUG_SYNC 0x1000 #define DEBUG_PIXEL 0x2000 #define DEBUG_MEMORY 0x4000 + diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index bdd4a476098..167f7de6187 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -354,14 +354,6 @@ struct radeon_state { #define RADEON_CMD_BUF_SZ (8*1024) -struct radeon_store { - GLuint statenr; - GLuint primnr; - char cmd_buf[RADEON_CMD_BUF_SZ]; - int cmd_used; - int elts_start; -}; - /* radeon_tcl.c */ struct radeon_tcl_info { -- cgit v1.2.3 From 4637235183b80963536f2364e4d50fcb894886dd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 10:44:48 +1000 Subject: radeon/r200/r300: initial attempt to convert to common context code --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 17 ++- src/mesa/drivers/dri/r200/r200_context.c | 186 +++++++++++------------ src/mesa/drivers/dri/r200/r200_context.h | 77 +--------- src/mesa/drivers/dri/r200/r200_ioctl.c | 160 ++++++++++---------- src/mesa/drivers/dri/r200/r200_ioctl.h | 8 +- src/mesa/drivers/dri/r200/r200_lock.c | 36 ++--- src/mesa/drivers/dri/r200/r200_lock.h | 10 +- src/mesa/drivers/dri/r200/r200_pixel.c | 32 ++-- src/mesa/drivers/dri/r200/r200_span.c | 2 +- src/mesa/drivers/dri/r200/r200_state.c | 82 +++++----- src/mesa/drivers/dri/r200/r200_state.h | 2 +- src/mesa/drivers/dri/r200/r200_state_init.c | 132 ++++++++--------- src/mesa/drivers/dri/r200/r200_swtcl.c | 37 ++--- src/mesa/drivers/dri/r200/r200_tcl.c | 14 +- src/mesa/drivers/dri/r200/r200_tex.c | 8 +- src/mesa/drivers/dri/r200/r200_texmem.c | 14 +- src/mesa/drivers/dri/r200/r200_texstate.c | 20 +-- src/mesa/drivers/dri/r200/r200_vertprog.c | 4 +- src/mesa/drivers/dri/r300/Makefile | 3 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 52 ++++--- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 10 +- src/mesa/drivers/dri/r300/r300_context.h | 180 ++++++++++------------ src/mesa/drivers/dri/r300/r300_ioctl.c | 8 +- src/mesa/drivers/dri/r300/radeon_context.h | 118 +-------------- src/mesa/drivers/dri/radeon/common_context.h | 96 +++++++++++- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 3 +- src/mesa/drivers/dri/radeon/radeon_context.c | 162 ++++++++++---------- src/mesa/drivers/dri/radeon/radeon_context.h | 84 ++--------- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 189 ++++++++++++------------ src/mesa/drivers/dri/radeon/radeon_ioctl.h | 45 +++--- src/mesa/drivers/dri/radeon/radeon_lock.c | 40 ++--- src/mesa/drivers/dri/radeon/radeon_lock.h | 12 +- src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 4 +- src/mesa/drivers/dri/radeon/radeon_sanity.c | 2 +- src/mesa/drivers/dri/radeon/radeon_sanity.h | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 4 - src/mesa/drivers/dri/radeon/radeon_span.c | 9 +- src/mesa/drivers/dri/radeon/radeon_state.c | 174 +++++++++++----------- src/mesa/drivers/dri/radeon/radeon_state.h | 12 +- src/mesa/drivers/dri/radeon/radeon_state_init.c | 64 ++++---- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 67 ++++----- src/mesa/drivers/dri/radeon/radeon_tcl.c | 28 ++-- src/mesa/drivers/dri/radeon/radeon_tex.c | 18 +-- src/mesa/drivers/dri/radeon/radeon_tex.h | 4 +- src/mesa/drivers/dri/radeon/radeon_texmem.c | 22 +-- src/mesa/drivers/dri/radeon/radeon_texstate.c | 40 ++--- 46 files changed, 1067 insertions(+), 1226 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index a426e7ad3fa..4f0275cc875 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -64,7 +64,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) { int i, mtu; - mtu = rmesa->glCtx->Const.MaxTextureUnits; + mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; make_empty_list(&rmesa->hw.atomlist); rmesa->hw.atomlist.name = "atom-list"; @@ -127,7 +127,7 @@ static void r200SaveHwState( r200ContextPtr rmesa ) rmesa->backup_store.cmd_used = 0; foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->check( rmesa->glCtx, atom->idx ) ) { + if ( atom->check( rmesa->radeon.glCtx, atom ) ) { int size = atom->cmd_size * 4; memcpy( dest, atom->cmd, size); dest += size; @@ -159,7 +159,7 @@ void r200EmitState( r200ContextPtr rmesa ) if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty) return; - mtu = rmesa->glCtx->Const.MaxTextureUnits; + mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; /* To avoid going across the entire set of states multiple times, just check * for enough space for the case of emitting all state, and inline the @@ -173,7 +173,7 @@ void r200EmitState( r200ContextPtr rmesa ) if (R200_DEBUG & DEBUG_STATE) { foreach( atom, &rmesa->hw.atomlist ) { if ( atom->dirty || rmesa->hw.all_dirty ) { - if ( atom->check( rmesa->glCtx, atom->idx ) ) + if ( atom->check( rmesa->radeon.glCtx, atom ) ) print_state_atom( atom ); else fprintf(stderr, "skip state %s\n", atom->name); @@ -185,7 +185,7 @@ void r200EmitState( r200ContextPtr rmesa ) if ( rmesa->hw.all_dirty ) atom->dirty = GL_TRUE; if ( atom->dirty ) { - if ( atom->check( rmesa->glCtx, atom->idx ) ) { + if ( atom->check( rmesa->radeon.glCtx, atom ) ) { int size = atom->cmd_size * 4; memcpy( dest, atom->cmd, size); dest += size; @@ -230,8 +230,9 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, } -void r200FlushElts( r200ContextPtr rmesa ) +void r200FlushElts( GLcontext *ctx ) { + r200ContextPtr rmesa = R200_CONTEXT(ctx); int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start); int dwords; int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2; @@ -252,7 +253,7 @@ void r200FlushElts( r200ContextPtr rmesa ) if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); - r200Finish( rmesa->glCtx ); + r200Finish( rmesa->radeon.glCtx ); } } @@ -289,7 +290,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, cmd[1].i, primitive); assert(!rmesa->dma.flush); - rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->dma.flush = r200FlushElts; rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 6a1b9fb9fdf..9e89c1d7433 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -93,8 +93,8 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) r200ContextPtr rmesa = R200_CONTEXT(ctx); static char buffer[128]; unsigned offset; - GLuint agp_mode = (rmesa->radeonScreen->card_type == RADEON_CARD_PCI)? 0 : - rmesa->radeonScreen->AGPMode; + GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 : + rmesa->radeon.radeonScreen->AGPMode; switch ( name ) { case GL_VENDOR: @@ -105,7 +105,7 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) agp_mode ); sprintf( & buffer[ offset ], " %sTCL", - !(rmesa->TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) + !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) ? "" : "NO-" ); return (GLubyte *)buffer; @@ -273,12 +273,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, * Do this here so that initialMaxAnisotropy is set before we create * the default textures. */ - driParseConfigFiles (&rmesa->optionCache, &screen->optionCache, + driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r200"); - rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache, - "def_max_anisotropy"); + rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache, + "def_max_anisotropy"); - if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) { + if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) { if ( sPriv->drm_version.minor < 13 ) fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " "disabling.\n", sPriv->drm_version.minor ); @@ -301,53 +301,53 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, /* Allocate and initialize the Mesa context */ if (sharedContextPrivate) - shareCtx = ((r200ContextPtr) sharedContextPrivate)->glCtx; + shareCtx = ((r200ContextPtr) sharedContextPrivate)->radeon.glCtx; else shareCtx = NULL; - rmesa->glCtx = _mesa_create_context(glVisual, shareCtx, + rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx, &functions, (void *) rmesa); - if (!rmesa->glCtx) { + if (!rmesa->radeon.glCtx) { FREE(rmesa); return GL_FALSE; } driContextPriv->driverPrivate = rmesa; /* Init r200 context data */ - rmesa->dri.context = driContextPriv; - rmesa->dri.screen = sPriv; - rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */ - rmesa->dri.hwContext = driContextPriv->hHWContext; - rmesa->dri.hwLock = &sPriv->pSAREA->lock; - rmesa->dri.fd = sPriv->fd; - rmesa->dri.drmMinor = sPriv->drm_version.minor; - - rmesa->radeonScreen = screen; - rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + + rmesa->radeon.dri.context = driContextPriv; + rmesa->radeon.dri.screen = sPriv; + rmesa->radeon.dri.drawable = NULL; /* Set by XMesaMakeCurrent */ + rmesa->radeon.dri.hwContext = driContextPriv->hHWContext; + rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock; + rmesa->radeon.dri.fd = sPriv->fd; + rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor; + + rmesa->radeon.radeonScreen = screen; + rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + screen->sarea_priv_offset); - rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address; + rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; - (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) ); - make_empty_list( & rmesa->swapped ); + (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); + make_empty_list( & rmesa->radeon.swapped ); - rmesa->nr_heaps = 1 /* screen->numTexHeaps */ ; - assert(rmesa->nr_heaps < RADEON_NR_TEX_HEAPS); - for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { - rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa, + rmesa->radeon.nr_heaps = 1 /* screen->numTexHeaps */ ; + assert(rmesa->radeon.nr_heaps < RADEON_NR_TEX_HEAPS); + for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { + rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa, screen->texSize[i], 12, RADEON_NR_TEX_REGIONS, - (drmTextureRegionPtr)rmesa->sarea->tex_list[i], - & rmesa->sarea->tex_age[i], - & rmesa->swapped, + (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i], + & rmesa->radeon.sarea->tex_age[i], + & rmesa->radeon.swapped, sizeof( radeonTexObj ), (destroy_texture_object_t *) r200DestroyTexObj ); } - rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache, + rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, "texture_depth"); - if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - rmesa->texture_depth = ( screen->cpp == 4 ) ? + if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) + rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; rmesa->swtcl.RenderIndex = ~0; @@ -359,16 +359,16 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, * setting allow larger textures. */ - ctx = rmesa->glCtx; - ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache, + ctx = rmesa->radeon.glCtx; + ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache, "texture_units"); ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits; ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; - i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures"); + i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); - driCalculateMaxTextureLevels( rmesa->texture_heaps, - rmesa->nr_heaps, + driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps, + rmesa->radeon.nr_heaps, & ctx->Const, 4, 11, /* max 2D texture size is 2048x2048 */ @@ -391,7 +391,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, ctx->Const.MinPointSizeAA = 1.0; ctx->Const.MaxPointSizeAA = 1.0; ctx->Const.PointSizeGranularity = 0.0625; - if (rmesa->radeonScreen->drmSupportsPointSprites) + if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) ctx->Const.MaxPointSize = 2047.0; else ctx->Const.MaxPointSize = 1.0; @@ -445,32 +445,32 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, _math_matrix_set_identity( &rmesa->tmpmat ); driInitExtensions( ctx, card_extensions, GL_TRUE ); - if (!(rmesa->radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { + if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { /* yuv textures don't work with some chips - R200 / rv280 okay so far others get the bit ordering right but don't actually do YUV-RGB conversion */ _mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" ); } - if (rmesa->glCtx->Mesa_DXTn) { + if (rmesa->radeon.glCtx->Mesa_DXTn) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); _mesa_enable_extension( ctx, "GL_S3_s3tc" ); } - else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) { + else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); } - if (rmesa->radeonScreen->drmSupportsCubeMapsR200) + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" ); - if (rmesa->radeonScreen->drmSupportsBlendColor) { + if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) { driInitExtensions( ctx, blend_extensions, GL_FALSE ); } - if(rmesa->radeonScreen->drmSupportsVertexProgram) + if(rmesa->radeon.radeonScreen->drmSupportsVertexProgram) driInitSingleExtension( ctx, ARB_vp_extension ); - if(driQueryOptionb(&rmesa->optionCache, "nv_vertex_program")) + if(driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program")) driInitSingleExtension( ctx, NV_vp_extension ); - if ((ctx->Const.MaxTextureUnits == 6) && rmesa->radeonScreen->drmSupportsFragShader) + if ((ctx->Const.MaxTextureUnits == 6) && rmesa->radeon.radeonScreen->drmSupportsFragShader) driInitSingleExtension( ctx, ATI_fs_extension ); - if (rmesa->radeonScreen->drmSupportsPointSprites) + if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) driInitExtensions( ctx, point_extensions, GL_FALSE ); #if 0 r200InitDriverFuncs( ctx ); @@ -486,25 +486,25 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitState( rmesa ); r200InitSwtcl( ctx ); - fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode"); - rmesa->iw.irq_seq = -1; - rmesa->irqsEmitted = 0; - rmesa->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - rmesa->radeonScreen->irq); + fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); + rmesa->radeon.iw.irq_seq = -1; + rmesa->radeon.irqsEmitted = 0; + rmesa->radeon.do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && + rmesa->radeon.radeonScreen->irq); - rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); + rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - if (!rmesa->do_irqs) + if (!rmesa->radeon.do_irqs) fprintf(stderr, "IRQ's not enabled, falling back to %s: %d %d\n", - rmesa->do_usleeps ? "usleeps" : "busy waits", + rmesa->radeon.do_usleeps ? "usleeps" : "busy waits", fthrottle_mode, - rmesa->radeonScreen->irq); + rmesa->radeon.radeonScreen->irq); rmesa->prefer_gart_client_texturing = (getenv("R200_GART_CLIENT_TEXTURES") != 0); - (*sPriv->systemTime->getUST)( & rmesa->swap_ust ); + (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); #if DO_DEBUG @@ -514,18 +514,18 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, debug_control ); #endif - tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode"); - if (driQueryOptionb(&rmesa->optionCache, "no_rast")) { + tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode"); + if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) { fprintf(stderr, "disabling 3D acceleration\n"); FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1); } else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") || - !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { - if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; + !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; fprintf(stderr, "Disabling HW TCL support\n"); } - TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1); + TCL_FALLBACK(rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1); } return GL_TRUE; @@ -554,14 +554,14 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) GLboolean release_texture_heaps; - release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1); - _swsetup_DestroyContext( rmesa->glCtx ); - _tnl_DestroyContext( rmesa->glCtx ); - _vbo_DestroyContext( rmesa->glCtx ); - _swrast_DestroyContext( rmesa->glCtx ); + release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1); + _swsetup_DestroyContext( rmesa->radeon.glCtx ); + _tnl_DestroyContext( rmesa->radeon.glCtx ); + _vbo_DestroyContext( rmesa->radeon.glCtx ); + _swrast_DestroyContext( rmesa->radeon.glCtx ); - r200DestroySwtcl( rmesa->glCtx ); - r200ReleaseArrays( rmesa->glCtx, ~0 ); + r200DestroySwtcl( rmesa->radeon.glCtx ); + r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->dma.current.buf) { r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); @@ -579,20 +579,20 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) */ int i; - for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { - driDestroyTextureHeap( rmesa->texture_heaps[ i ] ); - rmesa->texture_heaps[ i ] = NULL; + for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { + driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] ); + rmesa->radeon.texture_heaps[ i ] = NULL; } - assert( is_empty_list( & rmesa->swapped ) ); + assert( is_empty_list( & rmesa->radeon.swapped ) ); } /* free the Mesa context */ - rmesa->glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->glCtx ); + rmesa->radeon.glCtx->DriverCtx = NULL; + _mesa_destroy_context( rmesa->radeon.glCtx ); /* free the option cache */ - driDestroyOptionCache (&rmesa->optionCache); + driDestroyOptionCache (&rmesa->radeon.optionCache); FREE( rmesa ); } @@ -608,10 +608,10 @@ r200SwapBuffers( __DRIdrawablePrivate *dPriv ) r200ContextPtr rmesa; GLcontext *ctx; rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = rmesa->glCtx; + ctx = rmesa->radeon.glCtx; if (ctx->Visual.doubleBufferMode) { _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ - if ( rmesa->doPageFlip ) { + if ( rmesa->radeon.doPageFlip ) { r200PageFlip( dPriv ); } else { @@ -633,7 +633,7 @@ r200CopySubBuffer( __DRIdrawablePrivate *dPriv, r200ContextPtr rmesa; GLcontext *ctx; rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = rmesa->glCtx; + ctx = rmesa->radeon.glCtx; if (ctx->Visual.doubleBufferMode) { drm_clip_rect_t rect; rect.x1 = x + dPriv->x; @@ -663,32 +663,32 @@ r200MakeCurrent( __DRIcontextPrivate *driContextPriv, (r200ContextPtr) driContextPriv->driverPrivate; if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->glCtx); + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->radeon.glCtx); - newCtx->dri.readable = driReadPriv; + newCtx->radeon.dri.readable = driReadPriv; - if ( newCtx->dri.drawable != driDrawPriv || - newCtx->lastStamp != driDrawPriv->lastStamp ) { + if ( newCtx->radeon.dri.drawable != driDrawPriv || + newCtx->radeon.lastStamp != driDrawPriv->lastStamp ) { if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&newCtx->optionCache) + driDrawPriv->vblFlags = (newCtx->radeon.radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&newCtx->radeon.optionCache) : VBLANK_FLAG_NO_IRQ; driDrawableInitVBlank( driDrawPriv ); } - newCtx->dri.drawable = driDrawPriv; + newCtx->radeon.dri.drawable = driDrawPriv; r200SetCliprects(newCtx); - r200UpdateViewportOffset( newCtx->glCtx ); + r200UpdateViewportOffset( newCtx->radeon.glCtx ); } - _mesa_make_current( newCtx->glCtx, + _mesa_make_current( newCtx->radeon.glCtx, (GLframebuffer *) driDrawPriv->driverPrivate, (GLframebuffer *) driReadPriv->driverPrivate ); - _mesa_update_state( newCtx->glCtx ); - r200ValidateState( newCtx->glCtx ); + _mesa_update_state( newCtx->radeon.glCtx ); + r200ValidateState( newCtx->radeon.glCtx ); } else { if (R200_DEBUG & DEBUG_DRI) @@ -709,7 +709,7 @@ r200UnbindContext( __DRIcontextPrivate *driContextPriv ) r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate; if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->glCtx); + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 64f773826c4..9ee6c15bf4e 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -53,6 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #error This driver requires a newer libdrm to compile #endif +#include "radeon_screen.h" #include "common_context.h" struct r200_context; @@ -60,21 +61,8 @@ typedef struct r200_context r200ContextRec; typedef struct r200_context *r200ContextPtr; #include "r200_lock.h" -#include "radeon_screen.h" -#include "main/mm.h" - -typedef void (*r200_tri_func)( r200ContextPtr, - radeonVertex *, - radeonVertex *, - radeonVertex * ); - -typedef void (*r200_line_func)( r200ContextPtr, - radeonVertex *, - radeonVertex * ); - -typedef void (*r200_point_func)( r200ContextPtr, - radeonVertex * ); +#include "main/mm.h" struct r200_vertex_program { struct gl_vertex_program mesa_program; /* Must be first */ @@ -540,7 +528,7 @@ struct r200_state { GLuint envneeded; }; -#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ +#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) @@ -592,9 +580,9 @@ struct r200_swtcl_info { /* Fallback rasterization functions */ - r200_point_func draw_point; - r200_line_func draw_line; - r200_tri_func draw_tri; + radeon_point_func draw_point; + radeon_line_func draw_line; + radeon_tri_func draw_tri; GLuint hw_primitive; GLenum render_primitive; @@ -636,7 +624,7 @@ struct r200_swtcl_info { struct r200_context { - GLcontext *glCtx; /* Mesa context */ + struct radeon_context radeon; /* Driver and hardware state management */ @@ -644,21 +632,6 @@ struct r200_context { struct r200_state state; struct r200_vertex_program *curr_vp_hw; - /* Texture object bookkeeping - */ - unsigned nr_heaps; - driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; - driTextureObject swapped; - int texture_depth; - float initialMaxAnisotropy; - - /* Rasterization and vertex state: - */ - GLuint TclFallback; - GLuint Fallback; - GLuint NewGLState; - DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ - /* Vertex buffers */ struct radeon_ioctl ioctl; @@ -669,30 +642,11 @@ struct r200_context { */ struct radeon_store backup_store; - /* Page flipping - */ - GLuint doPageFlip; - - /* Busy waiting - */ - GLuint do_usleeps; - GLuint do_irqs; - GLuint irqsEmitted; - drm_radeon_irq_wait_t iw; - /* Clientdata textures; */ GLuint prefer_gart_client_texturing; - /* Drawable, cliprect and scissor information - */ - GLuint numClipRects; /* Cliprects for the draw buffer */ - drm_clip_rect_t *pClipRects; - unsigned int lastStamp; - GLboolean lost_context; GLboolean save_on_next_emit; - radeonScreenPtr radeonScreen; /* Screen private DRI data */ - drm_radeon_sarea_t *sarea; /* Private SAREA data */ /* TCL stuff */ @@ -705,15 +659,6 @@ struct r200_context { GLuint TexGenCompSel; GLmatrix tmpmat; - /* buffer swap - */ - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; - - /* r200_tcl.c */ struct r200_tcl_info tcl; @@ -722,14 +667,6 @@ struct r200_context { */ struct r200_swtcl_info swtcl; - /* Mirrors of some DRI state - */ - struct radeon_dri_mirror dri; - - /* Configuration cache - */ - driOptionCache optionCache; - GLboolean using_hyperz; GLboolean texmicrotile; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index da9a293241c..16776abd027 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -74,7 +74,7 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) if (R200_DEBUG & DEBUG_STATE) fprintf(stderr, "Emitting backup state on lost context\n"); - rmesa->lost_context = GL_FALSE; + rmesa->radeon.lost_context = GL_FALSE; nr_released_bufs = rmesa->dma.nr_released_bufs; saved_store = rmesa->store; @@ -90,7 +90,7 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) int ret, i; drm_radeon_cmd_buffer_t cmd; - if (rmesa->lost_context) + if (rmesa->radeon.lost_context) r200BackUpAndEmitLostStateLocked( rmesa ); if (R200_DEBUG & DEBUG_IOCTL) { @@ -114,8 +114,8 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) rmesa->state.scissor.pClipRects); else ret = r200SanityCmdBuffer( rmesa, - rmesa->numClipRects, - rmesa->pClipRects); + rmesa->radeon.numClipRects, + rmesa->radeon.pClipRects); if (ret) { fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); goto out; @@ -124,8 +124,8 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) if (R200_DEBUG & DEBUG_MEMORY) { - if (! driValidateTextureHeaps( rmesa->texture_heaps, rmesa->nr_heaps, - & rmesa->swapped ) ) { + if (! driValidateTextureHeaps( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, + & rmesa->radeon.swapped ) ) { fprintf( stderr, "%s: texture memory is inconsistent - expect " "mangled textures\n", __FUNCTION__ ); } @@ -139,11 +139,11 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) cmd.nbox = rmesa->state.scissor.numClipRects; cmd.boxes = (drm_clip_rect_t *)rmesa->state.scissor.pClipRects; } else { - cmd.nbox = rmesa->numClipRects; - cmd.boxes = (drm_clip_rect_t *)rmesa->pClipRects; + cmd.nbox = rmesa->radeon.numClipRects; + cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects; } - ret = drmCommandWrite( rmesa->dri.fd, + ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd) ); @@ -195,7 +195,7 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) { struct radeon_dma_buffer *dmabuf; - int fd = rmesa->dri.fd; + int fd = rmesa->radeon.dri.fd; int index = 0; int size = 0; drmDMAReq dma; @@ -205,7 +205,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) fprintf(stderr, "%s\n", __FUNCTION__); if (rmesa->dma.flush) { - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); } if (rmesa->dma.current.buf) @@ -214,7 +214,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) if (rmesa->dma.nr_released_bufs > 4) r200FlushCmdBuf( rmesa, __FUNCTION__ ); - dma.context = rmesa->dri.hwContext; + dma.context = rmesa->radeon.dri.hwContext; dma.send_count = 0; dma.send_list = NULL; dma.send_sizes = NULL; @@ -236,7 +236,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); } - if (rmesa->do_usleeps) { + if (rmesa->radeon.do_usleeps) { UNLOCK_HARDWARE( rmesa ); DO_USLEEP( 1 ); LOCK_HARDWARE( rmesa ); @@ -249,7 +249,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) fprintf(stderr, "Allocated buffer %d\n", index); dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); - dmabuf->buf = &rmesa->radeonScreen->buffers->list[index]; + dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index]; dmabuf->refcount = 1; rmesa->dma.current.buf = dmabuf; @@ -270,7 +270,7 @@ void r200ReleaseDmaRegion( r200ContextPtr rmesa, return; if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); if (--region->buf->refcount == 0) { drm_radeon_cmd_header_t *cmd; @@ -303,7 +303,7 @@ void r200AllocDmaRegion( r200ContextPtr rmesa, fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); if (region->buf) r200ReleaseDmaRegion( rmesa, region, __FUNCTION__ ); @@ -341,7 +341,7 @@ static uint32_t r200GetLastFrame(r200ContextPtr rmesa) gp.param = RADEON_PARAM_LAST_FRAME; gp.value = (int *)&frame; - ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM, + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret ); @@ -356,8 +356,8 @@ static void r200EmitIrqLocked( r200ContextPtr rmesa ) drm_radeon_irq_emit_t ie; int ret; - ie.irq_seq = &rmesa->iw.irq_seq; - ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT, + ie.irq_seq = &rmesa->radeon.iw.irq_seq; + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_EMIT, &ie, sizeof(ie) ); if ( ret ) { fprintf( stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, ret ); @@ -371,8 +371,8 @@ static void r200WaitIrq( r200ContextPtr rmesa ) int ret; do { - ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_IRQ_WAIT, - &rmesa->iw, sizeof(rmesa->iw) ); + ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_WAIT, + &rmesa->radeon.iw, sizeof(rmesa->radeon.iw) ); } while (ret && (errno == EINTR || errno == EBUSY)); if ( ret ) { @@ -384,11 +384,11 @@ static void r200WaitIrq( r200ContextPtr rmesa ) static void r200WaitForFrameCompletion( r200ContextPtr rmesa ) { - drm_radeon_sarea_t *sarea = rmesa->sarea; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - if (rmesa->do_irqs) { + if (rmesa->radeon.do_irqs) { if (r200GetLastFrame(rmesa) < sarea->last_frame) { - if (!rmesa->irqsEmitted) { + if (!rmesa->radeon.irqsEmitted) { while (r200GetLastFrame (rmesa) < sarea->last_frame) ; } @@ -397,18 +397,18 @@ static void r200WaitForFrameCompletion( r200ContextPtr rmesa ) r200WaitIrq( rmesa ); LOCK_HARDWARE( rmesa ); } - rmesa->irqsEmitted = 10; + rmesa->radeon.irqsEmitted = 10; } - if (rmesa->irqsEmitted) { + if (rmesa->radeon.irqsEmitted) { r200EmitIrqLocked( rmesa ); - rmesa->irqsEmitted--; + rmesa->radeon.irqsEmitted--; } } else { while (r200GetLastFrame (rmesa) < sarea->last_frame) { UNLOCK_HARDWARE( rmesa ); - if (rmesa->do_usleeps) + if (rmesa->radeon.do_usleeps) DO_USLEEP( 1 ); LOCK_HARDWARE( rmesa ); } @@ -435,7 +435,7 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)rmesa->glCtx ); + fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)rmesa->radeon.glCtx ); } R200_FIREVERTICES( rmesa ); @@ -459,7 +459,7 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, for ( i = 0 ; i < nbox ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; GLint n = 0; for ( ; i < nr ; i++ ) { @@ -484,12 +484,12 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, b++; n++; } - rmesa->sarea->nbox = n; + rmesa->radeon.sarea->nbox = n; if (!n) continue; - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); + ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_SWAP ); if ( ret ) { fprintf( stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret ); @@ -503,14 +503,14 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, { rmesa->hw.all_dirty = GL_TRUE; - rmesa->swap_count++; + rmesa->radeon.swap_count++; (*psp->systemTime->getUST)( & ust ); if ( missed_target ) { - rmesa->swap_missed_count++; - rmesa->swap_missed_ust = ust - rmesa->swap_ust; + rmesa->radeon.swap_missed_count++; + rmesa->radeon.swap_missed_ust = ust - rmesa->radeon.swap_ust; } - rmesa->swap_ust = ust; + rmesa->radeon.swap_ust = ust; sched_yield(); } @@ -531,7 +531,7 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) if ( R200_DEBUG & DEBUG_IOCTL ) { fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); + rmesa->radeon.sarea->pfCurrentPage); } R200_FIREVERTICES( rmesa ); @@ -547,9 +547,9 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) */ { drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; b[0] = box[0]; - rmesa->sarea->nbox = 1; + rmesa->radeon.sarea->nbox = 1; } /* Throttle the frame rate -- only allow a few pending swap buffers @@ -559,12 +559,12 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) UNLOCK_HARDWARE( rmesa ); driWaitForVBlank( dPriv, & missed_target ); if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); + rmesa->radeon.swap_missed_count++; + (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust ); } LOCK_HARDWARE( rmesa ); - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); + ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP ); UNLOCK_HARDWARE( rmesa ); @@ -573,34 +573,34 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) exit( 1 ); } - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); + rmesa->radeon.swap_count++; + (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_ust ); #if 000 - if ( rmesa->sarea->pfCurrentPage == 1 ) { - rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset; - rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch; + if ( rmesa->radeon.sarea->pfCurrentPage == 1 ) { + rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset; + rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch; } else { - rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset; - rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch; + rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset; + rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch; } R200_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset - + rmesa->radeonScreen->fbLocation; + + rmesa->radeon.radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } #else /* Get ready for drawing next frame. Update the renderbuffers' * flippedOffset/Pitch fields so we draw into the right place. */ - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); + driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, + rmesa->radeon.sarea->pfCurrentPage); - r200UpdateDrawBuffer(rmesa->glCtx); + r200UpdateDrawBuffer(rmesa->radeon.glCtx); #endif } @@ -611,7 +611,7 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) static void r200Clear( GLcontext *ctx, GLbitfield mask ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLuint flags = 0; GLuint color_mask = 0; GLint ret, i; @@ -663,7 +663,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) if (rmesa->using_hyperz) { flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) +/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) flags |= RADEON_USE_HIERZ; */ if (!(rmesa->state.stencil.hwBuffer) || ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && @@ -693,7 +693,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&clear; - ret = drmCommandWriteRead( rmesa->dri.fd, + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { @@ -703,11 +703,11 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) /* Clear throttling needs more thought. */ - if ( rmesa->sarea->last_clear - clear <= 25 ) { + if ( rmesa->radeon.sarea->last_clear - clear <= 25 ) { break; } - if (rmesa->do_usleeps) { + if (rmesa->radeon.do_usleeps) { UNLOCK_HARDWARE( rmesa ); DO_USLEEP( 1 ); LOCK_HARDWARE( rmesa ); @@ -720,7 +720,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; GLint n = 0; @@ -755,7 +755,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } } - rmesa->sarea->nbox = n; + rmesa->radeon.sarea->nbox = n; clear.flags = flags; clear.clear_color = rmesa->state.color.clear; @@ -765,7 +765,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) clear.depth_boxes = depth_boxes; n--; - b = rmesa->sarea->boxes; + b = rmesa->radeon.sarea->boxes; for ( ; n >= 0 ; n-- ) { depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1; depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1; @@ -774,7 +774,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear; } - ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR, + ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR, &clear, sizeof(clear)); @@ -796,7 +796,7 @@ void r200WaitForIdleLocked( r200ContextPtr rmesa ) int i = 0; do { - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_CP_IDLE); + ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_CP_IDLE); if (ret) DO_USLEEP( 1 ); } while (ret && ++i < 100); @@ -825,7 +825,7 @@ void r200Flush( GLcontext *ctx ) fprintf(stderr, "%s\n", __FUNCTION__); if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( ctx ); r200EmitState( rmesa ); @@ -841,7 +841,7 @@ void r200Finish( GLcontext *ctx ) r200ContextPtr rmesa = R200_CONTEXT(ctx); r200Flush( ctx ); - if (rmesa->do_irqs) { + if (rmesa->radeon.do_irqs) { LOCK_HARDWARE( rmesa ); r200EmitIrqLocked( rmesa ); UNLOCK_HARDWARE( rmesa ); @@ -875,7 +875,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, writefreq, priority); - if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeonScreen->gartTextures.map) + if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeon.radeonScreen->gartTextures.map) return NULL; if (getenv("R200_NO_ALLOC")) @@ -886,7 +886,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, alloc.size = size; alloc.region_offset = ®ion_offset; - ret = drmCommandWriteRead( rmesa->radeonScreen->driScreen->fd, + ret = drmCommandWriteRead( rmesa->radeon.radeonScreen->driScreen->fd, DRM_RADEON_ALLOC, &alloc, sizeof(alloc)); @@ -896,7 +896,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, } { - char *region_start = (char *)rmesa->radeonScreen->gartTextures.map; + char *region_start = (char *)rmesa->radeon.radeonScreen->gartTextures.map; return (void *)(region_start + region_offset); } } @@ -914,24 +914,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %p\n", __FUNCTION__, pointer); - if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeonScreen->gartTextures.map) { + if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeon.radeonScreen->gartTextures.map) { fprintf(stderr, "%s: no context\n", __FUNCTION__); return; } - region_offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map; + region_offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map; if (region_offset < 0 || - region_offset > rmesa->radeonScreen->gartTextures.size) { + region_offset > rmesa->radeon.radeonScreen->gartTextures.size) { fprintf(stderr, "offset %d outside range 0..%d\n", region_offset, - rmesa->radeonScreen->gartTextures.size); + rmesa->radeon.radeonScreen->gartTextures.size); return; } memfree.region = RADEON_MEM_REGION_GART; memfree.region_offset = region_offset; - ret = drmCommandWrite( rmesa->radeonScreen->driScreen->fd, + ret = drmCommandWrite( rmesa->radeon.radeonScreen->driScreen->fd, DRM_RADEON_FREE, &memfree, sizeof(memfree)); @@ -956,16 +956,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer) card_offset = r200GartOffsetFromVirtual( rmesa, pointer ); - return card_offset - rmesa->radeonScreen->gart_base; + return card_offset - rmesa->radeon.radeonScreen->gart_base; } GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, GLint size ) { - ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map; + ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map; int valid = (size >= 0 && offset >= 0 && - offset + size < rmesa->radeonScreen->gartTextures.size); + offset + size < rmesa->radeon.radeonScreen->gartTextures.size); if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid ); @@ -976,12 +976,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) { - ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map; + ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map; - if (offset < 0 || offset > rmesa->radeonScreen->gartTextures.size) + if (offset < 0 || offset > rmesa->radeon.radeonScreen->gartTextures.size) return ~0; else - return rmesa->radeonScreen->gart_texture_offset + offset; + return rmesa->radeon.radeonScreen->gart_texture_offset + offset; } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index d37efddaef7..f52d2a7419d 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -52,7 +52,7 @@ extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ); -extern void r200FlushElts( r200ContextPtr rmesa ); +extern void r200FlushElts(GLcontext *ctx); extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, @@ -120,7 +120,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa ); #define R200_NEWPRIM( rmesa ) \ do { \ if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa ); \ + rmesa->dma.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -142,7 +142,7 @@ static INLINE int R200_DB_STATECHANGE( struct radeon_state_atom *atom ) { if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { - int *tmp; + GLuint *tmp; R200_NEWPRIM( rmesa ); atom->dirty = GL_TRUE; rmesa->hw.is_dirty = GL_TRUE; @@ -161,7 +161,7 @@ static INLINE int R200_DB_STATECHANGE( #define R200_FIREVERTICES( rmesa ) \ do { \ if ( rmesa->store.cmd_used || rmesa->dma.flush ) { \ - r200Flush( rmesa->glCtx ); \ + r200Flush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/r200/r200_lock.c b/src/mesa/drivers/dri/r200/r200_lock.c index 99661a4bfb4..c79603cdd5a 100644 --- a/src/mesa/drivers/dri/r200/r200_lock.c +++ b/src/mesa/drivers/dri/r200/r200_lock.c @@ -51,10 +51,10 @@ int prevLockLine = 0; static void r200UpdatePageFlipping( r200ContextPtr rmesa ) { - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); + rmesa->radeon.doPageFlip = rmesa->radeon.sarea->pfState; + if (rmesa->radeon.glCtx->WinSysDrawBuffer) { + driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, + rmesa->radeon.sarea->pfCurrentPage); } } @@ -70,13 +70,13 @@ r200UpdatePageFlipping( r200ContextPtr rmesa ) */ void r200GetLock( r200ContextPtr rmesa, GLuint flags ) { - __DRIdrawablePrivate *drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *readable = rmesa->dri.readable; - __DRIscreenPrivate *sPriv = rmesa->dri.screen; - drm_radeon_sarea_t *sarea = rmesa->sarea; + __DRIdrawablePrivate *drawable = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *readable = rmesa->radeon.dri.readable; + __DRIscreenPrivate *sPriv = rmesa->radeon.dri.screen; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; int i; - drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags ); + drmGetLock( rmesa->radeon.dri.fd, rmesa->radeon.dri.hwContext, flags ); /* The window might have moved, so we might need to get new clip * rects. @@ -91,26 +91,26 @@ void r200GetLock( r200ContextPtr rmesa, GLuint flags ) DRI_VALIDATE_DRAWABLE_INFO( sPriv, readable ); } - if ( rmesa->lastStamp != drawable->lastStamp ) { + if ( rmesa->radeon.lastStamp != drawable->lastStamp ) { r200UpdatePageFlipping( rmesa ); r200SetCliprects( rmesa ); - r200UpdateViewportOffset( rmesa->glCtx ); - driUpdateFramebufferSize(rmesa->glCtx, drawable); + r200UpdateViewportOffset( rmesa->radeon.glCtx ); + driUpdateFramebufferSize(rmesa->radeon.glCtx, drawable); } R200_STATECHANGE( rmesa, ctx ); - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE; - if ( sarea->ctx_owner != rmesa->dri.hwContext ) { - sarea->ctx_owner = rmesa->dri.hwContext; + if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) { + sarea->ctx_owner = rmesa->radeon.dri.hwContext; } - for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { - DRI_AGE_TEXTURES( rmesa->texture_heaps[ i ] ); + for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { + DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] ); } - rmesa->lost_context = GL_TRUE; + rmesa->radeon.lost_context = GL_TRUE; } diff --git a/src/mesa/drivers/dri/r200/r200_lock.h b/src/mesa/drivers/dri/r200/r200_lock.h index 4ff98907fbf..f1cb624d8fe 100644 --- a/src/mesa/drivers/dri/r200/r200_lock.h +++ b/src/mesa/drivers/dri/r200/r200_lock.h @@ -88,8 +88,8 @@ extern int prevLockLine; do { \ char __ret = 0; \ DEBUG_CHECK_LOCK(); \ - DRM_CAS( rmesa->dri.hwLock, rmesa->dri.hwContext, \ - (DRM_LOCK_HELD | rmesa->dri.hwContext), __ret ); \ + DRM_CAS( rmesa->radeon.dri.hwLock, rmesa->radeon.dri.hwContext, \ + (DRM_LOCK_HELD | rmesa->radeon.dri.hwContext), __ret ); \ if ( __ret ) \ r200GetLock( rmesa, 0 ); \ DEBUG_LOCK(); \ @@ -97,9 +97,9 @@ extern int prevLockLine; #define UNLOCK_HARDWARE( rmesa ) \ do { \ - DRM_UNLOCK( rmesa->dri.fd, \ - rmesa->dri.hwLock, \ - rmesa->dri.hwContext ); \ + DRM_UNLOCK( rmesa->radeon.dri.fd, \ + rmesa->radeon.dri.hwLock, \ + rmesa->radeon.dri.hwContext ); \ DEBUG_RESET(); \ } while (0) diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 77506c5532e..1b28a83d70a 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -51,7 +51,7 @@ check_color( const GLcontext *ctx, GLenum type, GLenum format, const void *pixels, GLint sz, GLint pitch ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint cpp = rmesa->radeonScreen->cpp; + GLuint cpp = rmesa->radeon.radeonScreen->cpp; if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -137,8 +137,8 @@ clip_pixelrect( const GLcontext *ctx, if (*height <= 0) return GL_FALSE; - *size = ((*y + *height - 1) * rmesa->radeonScreen->frontPitch + - (*x + *width - 1) * rmesa->radeonScreen->cpp); + *size = ((*y + *height - 1) * rmesa->radeon.radeonScreen->frontPitch + + (*x + *width - 1) * rmesa->radeon.radeonScreen->cpp); return GL_TRUE; } @@ -153,7 +153,7 @@ r200TryReadPixels( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT(ctx); GLint pitch = pack->RowLength ? pack->RowLength : width; GLint blit_format; - GLuint cpp = rmesa->radeonScreen->cpp; + GLuint cpp = rmesa->radeon.radeonScreen->cpp; GLint size = width * height * cpp; if (R200_DEBUG & DEBUG_PIXEL) @@ -162,7 +162,7 @@ r200TryReadPixels( GLcontext *ctx, /* Only accelerate reading to GART buffers. */ if ( !r200IsGartMemory(rmesa, pixels, - pitch * height * rmesa->radeonScreen->cpp ) ) { + pitch * height * rmesa->radeon.radeonScreen->cpp ) ) { if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: dest not GART\n", __FUNCTION__); return GL_FALSE; @@ -180,7 +180,7 @@ r200TryReadPixels( GLcontext *ctx, if (!check_color(ctx, type, format, pack, pixels, size, pitch)) return GL_FALSE; - switch ( rmesa->radeonScreen->cpp ) { + switch ( rmesa->radeon.radeonScreen->cpp ) { case 4: blit_format = R200_CP_COLOR_FORMAT_ARGB8888; break; @@ -212,14 +212,14 @@ r200TryReadPixels( GLcontext *ctx, } { - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; driRenderbuffer *drb = (driRenderbuffer *) ctx->ReadBuffer->_ColorReadBuffer; int nbox = dPriv->numClipRects; int src_offset = drb->offset - + rmesa->radeonScreen->fbLocation; + + rmesa->radeon.radeonScreen->fbLocation; int src_pitch = drb->pitch * drb->cpp; int dst_offset = r200GartOffsetFromVirtual( rmesa, pixels ); - int dst_pitch = pitch * rmesa->radeonScreen->cpp; + int dst_pitch = pitch * rmesa->radeon.radeonScreen->cpp; drm_clip_rect_t *box = dPriv->pClipRects; int i; @@ -292,7 +292,7 @@ static void do_draw_pix( GLcontext *ctx, GLuint planemask) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; drm_clip_rect_t *box = dPriv->pClipRects; struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorDrawBuffers[0]; driRenderbuffer *drb = (driRenderbuffer *) rb; @@ -301,12 +301,12 @@ static void do_draw_pix( GLcontext *ctx, int blit_format; int size; int src_offset = r200GartOffsetFromVirtual( rmesa, pixels ); - int src_pitch = pitch * rmesa->radeonScreen->cpp; + int src_pitch = pitch * rmesa->radeon.radeonScreen->cpp; if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); - switch ( rmesa->radeonScreen->cpp ) { + switch ( rmesa->radeon.radeonScreen->cpp ) { case 2: blit_format = R200_CP_COLOR_FORMAT_RGB565; break; @@ -357,7 +357,7 @@ static void do_draw_pix( GLcontext *ctx, blit_format, src_pitch, src_offset, drb->pitch * drb->cpp, - drb->offset + rmesa->radeonScreen->fbLocation, + drb->offset + rmesa->radeon.radeonScreen->fbLocation, bx - x, by - y, bx, by, bw, bh ); @@ -381,7 +381,7 @@ r200TryDrawPixels( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT(ctx); GLint pitch = unpack->RowLength ? unpack->RowLength : width; GLuint planemask; - GLuint cpp = rmesa->radeonScreen->cpp; + GLuint cpp = rmesa->radeon.radeonScreen->cpp; GLint size = height * pitch * cpp; if (R200_DEBUG & DEBUG_PIXEL) @@ -395,7 +395,7 @@ r200TryDrawPixels( GLcontext *ctx, case GL_RGB: case GL_RGBA: case GL_BGRA: - planemask = r200PackColor(cpp, + planemask = radeonPackColor(cpp, ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], @@ -471,7 +471,7 @@ r200Bitmap( GLcontext *ctx, GLint px, GLint py, { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (rmesa->Fallback) + if (rmesa->radeon.Fallback) _swrast_Bitmap( ctx, px, py, width, height, unpack, bitmap ); else r200PointsBitmap( ctx, px, py, width, height, unpack, bitmap ); diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index 9783678028a..361f0fde266 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -259,7 +259,7 @@ static void r200SpanRenderStart( GLcontext *ctx ) driRenderbuffer *drb = (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0]; volatile int *buf = - (volatile int *)(rmesa->dri.screen->pFB + drb->offset); + (volatile int *)(rmesa->radeon.dri.screen->pFB + drb->offset); p = *buf; *buf = p; } diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 8e9f2562a18..4cd87bd1b9d 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -114,7 +114,7 @@ static void r200BlendColor( GLcontext *ctx, const GLfloat cf[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); - if (rmesa->radeonScreen->drmSupportsBlendColor) + if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] ); } @@ -213,7 +213,7 @@ static void r200_set_blend_state( GLcontext * ctx ) R200_STATECHANGE( rmesa, ctx ); - if (rmesa->radeonScreen->drmSupportsBlendColor) { + if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) { if (ctx->Color.ColorLogicOpEnabled) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func; @@ -278,7 +278,7 @@ static void r200_set_blend_state( GLcontext * ctx ) return; } - if (!rmesa->radeonScreen->drmSupportsBlendColor) { + if (!rmesa->radeon.radeonScreen->drmSupportsBlendColor) { rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = eqn | func; return; } @@ -549,8 +549,8 @@ void r200RecalcScissorRects( r200ContextPtr rmesa ) /* Grow cliprect store? */ - if (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) { - while (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) { + if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { + while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */ rmesa->state.scissor.numAllocedClipRects *= 2; } @@ -571,9 +571,9 @@ void r200RecalcScissorRects( r200ContextPtr rmesa ) out = rmesa->state.scissor.pClipRects; rmesa->state.scissor.numClipRects = 0; - for ( i = 0 ; i < rmesa->numClipRects ; i++ ) { + for ( i = 0 ; i < rmesa->radeon.numClipRects ; i++ ) { if ( intersect_rect( out, - &rmesa->pClipRects[i], + &rmesa->radeon.pClipRects[i], &rmesa->state.scissor.rect ) ) { rmesa->state.scissor.numClipRects++; out++; @@ -586,8 +586,8 @@ static void r200UpdateScissor( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if ( rmesa->dri.drawable ) { - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + if ( rmesa->radeon.dri.drawable ) { + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; int x = ctx->Scissor.X; int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; @@ -803,7 +803,7 @@ static void r200ColorMask( GLcontext *ctx, GLboolean b, GLboolean a ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp, + GLuint mask = radeonPackColor( rmesa->radeon.radeonScreen->cpp, ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], @@ -867,7 +867,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* FIXME: Use window x,y offsets into stipple RAM. */ stipple.mask = rmesa->state.stipple.mask; - drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE, + drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, &stipple, sizeof(stipple) ); UNLOCK_HARDWARE( rmesa ); } @@ -881,7 +881,7 @@ static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) * cases work. */ TCL_FALLBACK( ctx, R200_TCL_FALLBACK_UNFILLED, flag); - if (rmesa->TclFallback) { + if (rmesa->radeon.TclFallback) { r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } @@ -958,7 +958,7 @@ static void r200UpdateSpecular( GLcontext *ctx ) /* Update vertex/render formats */ - if (rmesa->TclFallback) { + if (rmesa->radeon.TclFallback) { r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } @@ -1430,7 +1430,7 @@ static void r200LightModelfv( GLcontext *ctx, GLenum pname, rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHT_TWOSIDE; else rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~(R200_LIGHT_TWOSIDE); - if (rmesa->TclFallback) { + if (rmesa->radeon.TclFallback) { r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } @@ -1700,7 +1700,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1744,7 +1744,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, void r200UpdateViewportOffset( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1774,8 +1774,8 @@ void r200UpdateViewportOffset( GLcontext *ctx ) R200_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ - stx = 31 - ((rmesa->dri.drawable->x - 1) & R200_STIPPLE_COORD_MASK); - sty = 31 - ((rmesa->dri.drawable->y + rmesa->dri.drawable->h - 1) + stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & R200_STIPPLE_COORD_MASK); + sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1) & R200_STIPPLE_COORD_MASK); m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) | @@ -1805,7 +1805,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); - rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp, + rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, color[0], color[1], color[2], color[3] ); } @@ -1854,31 +1854,31 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) */ void r200SetCliprects( r200ContextPtr rmesa ) { - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->dri.readable; + __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable; GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate; GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate; if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BIT_BACK_LEFT) { /* Can't ignore 2d windows if we are page flipping. */ - if ( drawable->numBackClipRects == 0 || rmesa->doPageFlip ) { - rmesa->numClipRects = drawable->numClipRects; - rmesa->pClipRects = drawable->pClipRects; + if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) { + rmesa->radeon.numClipRects = drawable->numClipRects; + rmesa->radeon.pClipRects = drawable->pClipRects; } else { - rmesa->numClipRects = drawable->numBackClipRects; - rmesa->pClipRects = drawable->pBackClipRects; + rmesa->radeon.numClipRects = drawable->numBackClipRects; + rmesa->radeon.pClipRects = drawable->pBackClipRects; } } else { /* front buffer (or none, or multiple buffers) */ - rmesa->numClipRects = drawable->numClipRects; - rmesa->pClipRects = drawable->pClipRects; + rmesa->radeon.numClipRects = drawable->numClipRects; + rmesa->radeon.pClipRects = drawable->pClipRects; } if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(rmesa->glCtx, draw_fb, + _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb, drawable->w, drawable->h); draw_fb->Initialized = GL_TRUE; } @@ -1886,7 +1886,7 @@ void r200SetCliprects( r200ContextPtr rmesa ) if (drawable != readable) { if ((read_fb->Width != readable->w) || (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(rmesa->glCtx, read_fb, + _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb, readable->w, readable->h); read_fb->Initialized = GL_TRUE; } @@ -1895,7 +1895,7 @@ void r200SetCliprects( r200ContextPtr rmesa ) if (rmesa->state.scissor.enabled) r200RecalcScissorRects( rmesa ); - rmesa->lastStamp = drawable->lastStamp; + rmesa->radeon.lastStamp = drawable->lastStamp; } @@ -2031,7 +2031,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; } r200UpdateSpecular( ctx ); /* for PK_SPEC */ - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) r200ChooseVertexState( ctx ); _mesa_allow_light_in_model( ctx, !state ); break; @@ -2068,7 +2068,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_LIGHTING: r200UpdateSpecular(ctx); /* for reflection map fixup - might set recheck_texgen for all units too */ - rmesa->NewGLState |= _NEW_TEXTURE; + rmesa->radeon.NewGLState |= _NEW_TEXTURE; break; case GL_LINE_SMOOTH: @@ -2465,10 +2465,10 @@ r200UpdateDrawBuffer(GLcontext *ctx) /* Note: we used the (possibly) page-flipped values */ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->radeonScreen->fbLocation) + = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } } @@ -2478,7 +2478,7 @@ r200UpdateDrawBuffer(GLcontext *ctx) void r200ValidateState( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint new_state = rmesa->NewGLState; + GLuint new_state = rmesa->radeon.NewGLState; if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { r200UpdateDrawBuffer(ctx); @@ -2486,7 +2486,7 @@ void r200ValidateState( GLcontext *ctx ) if (new_state & (_NEW_TEXTURE | _NEW_PROGRAM)) { r200UpdateTextureState( ctx ); - new_state |= rmesa->NewGLState; /* may add TEXTURE_MATRIX */ + new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */ r200UpdateLocalViewer( ctx ); } @@ -2533,7 +2533,7 @@ void r200ValidateState( GLcontext *ctx ) else TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, 0); } - rmesa->NewGLState = 0; + rmesa->radeon.NewGLState = 0; } @@ -2544,7 +2544,7 @@ static void r200InvalidateState( GLcontext *ctx, GLuint new_state ) _vbo_InvalidateState( ctx, new_state ); _tnl_InvalidateState( ctx, new_state ); _ae_invalidate_state( ctx, new_state ); - R200_CONTEXT(ctx)->NewGLState |= new_state; + R200_CONTEXT(ctx)->radeon.NewGLState |= new_state; } /* A hack. The r200 can actually cope just fine with materials @@ -2573,11 +2573,11 @@ static void r200WrapRunPipeline( GLcontext *ctx ) GLboolean has_material; if (0) - fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->NewGLState); + fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->radeon.NewGLState); /* Validate state: */ - if (rmesa->NewGLState) + if (rmesa->radeon.NewGLState) r200ValidateState( ctx ); has_material = !ctx->VertexProgram._Enabled && ctx->Light.Enabled && check_material( ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h index a917163a00a..5d7347af311 100644 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ b/src/mesa/drivers/dri/r200/r200_state.h @@ -59,7 +59,7 @@ extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define FALLBACK( rmesa, bit, mode ) do { \ if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \ __FUNCTION__, bit, mode ); \ - r200Fallback( rmesa->glCtx, bit, mode ); \ + r200Fallback( rmesa->radeon.glCtx, bit, mode ); \ } while (0) extern void r200LightingSpaceChange( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 724c224c5e8..f03a47ef464 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -127,36 +127,36 @@ static int cmdscl2( int offset, int stride, int count ) } #define CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx, int idx ) \ +static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) idx; \ + (void) atom; \ (void) rmesa; \ return FLAG; \ } #define TCL_CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx, int idx ) \ -{ \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) idx; \ - return !rmesa->TclFallback && !ctx->VertexProgram._Enabled && (FLAG); \ +static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ +{ \ + r200ContextPtr rmesa = R200_CONTEXT(ctx); \ + (void) atom; \ + return !rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG); \ } #define TCL_OR_VP_CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx, int idx ) \ +static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) idx; \ - return !rmesa->TclFallback && (FLAG); \ + (void) atom; \ + return !rmesa->radeon.TclFallback && (FLAG); \ } #define VP_CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx, int idx ) \ -{ \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) idx; \ - return !rmesa->TclFallback && ctx->VertexProgram._Enabled && (FLAG); \ +static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ +{ \ + r200ContextPtr rmesa = R200_CONTEXT(ctx); \ + (void) atom; \ + return !rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG); \ } @@ -164,19 +164,19 @@ CHECK( always, GL_TRUE ) CHECK( never, GL_FALSE ) CHECK( tex_any, ctx->Texture._EnabledUnits ) CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) ); -CHECK( tex_pair, (rmesa->state.texture.unit[idx].unitneeded | rmesa->state.texture.unit[idx & ~1].unitneeded) ) -CHECK( tex, rmesa->state.texture.unit[idx].unitneeded ) +CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) ) +CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded ) CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled ) -CHECK( texenv, (rmesa->state.envneeded & (1 << idx) && !ctx->ATIFragmentShader._Enabled) ) + CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) ) CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) ) CHECK( afs, ctx->ATIFragmentShader._Enabled ) -CHECK( tex_cube, rmesa->state.texture.unit[idx].unitneeded & TEXTURE_CUBE_BIT ) +CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT ) TCL_CHECK( tcl_fog, ctx->Fog.Enabled ) TCL_CHECK( tcl, GL_TRUE ) -TCL_CHECK( tcl_tex, rmesa->state.texture.unit[idx].unitneeded ) +TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded ) TCL_CHECK( tcl_lighting, ctx->Light.Enabled ) -TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[idx].Enabled ) -TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << idx)) ) +TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled ) +TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) ) TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE ) VP_CHECK( tcl_vp, GL_TRUE ) VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 ) @@ -187,11 +187,11 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9 */ void r200InitState( r200ContextPtr rmesa ) { - GLcontext *ctx = rmesa->glCtx; + GLcontext *ctx = rmesa->radeon.glCtx; GLuint color_fmt, depth_fmt, i; GLint drawPitch, drawOffset; - switch ( rmesa->radeonScreen->cpp ) { + switch ( rmesa->radeon.radeonScreen->cpp ) { case 2: color_fmt = R200_COLOR_FORMAT_RGB565; break; @@ -228,22 +228,22 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && ctx->Visual.depthBits == 24 ); - rmesa->Fallback = 0; + rmesa->radeon.Fallback = 0; - if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - drawOffset = rmesa->radeonScreen->backOffset; - drawPitch = rmesa->radeonScreen->backPitch; + if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) { + drawOffset = rmesa->radeon.radeonScreen->backOffset; + drawPitch = rmesa->radeon.radeonScreen->backPitch; } else { - drawOffset = rmesa->radeonScreen->frontOffset; - drawPitch = rmesa->radeonScreen->frontPitch; + drawOffset = rmesa->radeon.radeonScreen->frontOffset; + drawPitch = rmesa->radeon.radeonScreen->frontPitch; } #if 000 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset; - rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch; + rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset; + rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch; } else { - rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset; - rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch; + rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset; + rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch; } rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; @@ -255,8 +255,8 @@ void r200InitState( r200ContextPtr rmesa ) #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ do { \ rmesa->hw.ATOM.cmd_size = SZ; \ - rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \ - rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ rmesa->hw.ATOM.name = NM; \ rmesa->hw.ATOM.idx = IDX; \ rmesa->hw.ATOM.check = check_##CHK; \ @@ -267,7 +267,7 @@ void r200InitState( r200ContextPtr rmesa ) /* Allocate state buffers: */ - if (rmesa->radeonScreen->drmSupportsBlendColor) + if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); @@ -282,8 +282,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); - if (rmesa->radeonScreen->drmSupportsFragShader) { - if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) { + if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { + if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); @@ -303,7 +303,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } else { - if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) { + if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); @@ -321,7 +321,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } - if (rmesa->radeonScreen->drmSupportsCubeMapsR200) { + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) { ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); @@ -337,7 +337,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); } - if (rmesa->radeonScreen->drmSupportsVertexProgram) { + if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) { ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); @@ -390,13 +390,13 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); - if (rmesa->radeonScreen->drmSupportsTriPerf) { + if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) { ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); } else { ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); } - if (rmesa->radeonScreen->drmSupportsPointSprites) { + if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) { ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 ); } @@ -412,7 +412,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); - if (rmesa->radeonScreen->drmSupportsBlendColor) + if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR); rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); @@ -429,7 +429,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3); rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0); - if (rmesa->radeonScreen->drmSupportsFragShader) { + if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR); rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0); rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0); @@ -567,7 +567,7 @@ void r200InitState( r200ContextPtr rmesa ) (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - if (rmesa->radeonScreen->drmSupportsBlendColor) { + if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) { rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | @@ -578,10 +578,10 @@ void r200InitState( r200ContextPtr rmesa ) } rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation; + rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = - ((rmesa->radeonScreen->depthPitch & + ((rmesa->radeon.radeonScreen->depthPitch & R200_DEPTHPITCH_MASK) | R200_DEPTH_ENDIAN_NO_SWAP); @@ -599,7 +599,7 @@ void r200InitState( r200ContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | R200_Z_DECOMPRESSION_ENABLE; -/* if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) +/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ } @@ -607,7 +607,7 @@ void r200InitState( r200ContextPtr rmesa ) | R200_TEX_BLEND_0_ENABLE); rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt; - switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) { + switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; break; @@ -615,12 +615,12 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; break; } - if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) == + if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == DRI_CONF_ROUND_ROUND ) rmesa->state.color.roundEnable = R200_ROUND_ENABLE; else rmesa->state.color.roundEnable = 0; - if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) == + if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == DRI_CONF_COLOR_REDUCTION_DITHER ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; else @@ -628,7 +628,7 @@ void r200InitState( r200ContextPtr rmesa ) #if 000 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + - rmesa->radeonScreen->fbLocation) + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & @@ -636,7 +636,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_COLOR_ENDIAN_NO_SWAP); #else rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + - rmesa->radeonScreen->fbLocation) + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & @@ -644,12 +644,12 @@ void r200InitState( r200ContextPtr rmesa ) R200_COLOR_ENDIAN_NO_SWAP); #endif /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * - driQueryOptionf (&rmesa->optionCache,"texture_blend_quality"); + driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality"); rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | @@ -704,7 +704,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_VC_NO_SWAP; #endif - if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { /* Bypass TCL */ rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); } @@ -743,28 +743,28 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ 0x100000); /* Small default bias */ - if (rmesa->radeonScreen->drmSupportsFragShader) { + if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; } else { rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; } rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = (R200_TXC_ARG_A_ZERO | diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 104c4945629..d5cba26ddd9 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -55,7 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_tcl.h" -static void flush_last_swtcl_prim( r200ContextPtr rmesa ); +static void flush_last_swtcl_prim( GLcontext *ctx ); /*********************************************************************** @@ -185,7 +185,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_SPEC_ALPHA; } - if (!RENDERINPUTS_EQUAL( rmesa->tnl_index_bitset, index_bitset ) || + if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) || (rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) || (rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) { R200_NEWPRIM(rmesa); @@ -199,7 +199,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) rmesa->swtcl.vertex_attr_count, NULL, 0 ); rmesa->swtcl.vertex_size /= 4; - RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset ); + RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset ); } } @@ -212,7 +212,7 @@ static void r200RenderStart( GLcontext *ctx ) if (rmesa->dma.flush != 0 && rmesa->dma.flush != flush_last_swtcl_prim) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( ctx ); } @@ -232,7 +232,7 @@ void r200ChooseVertexState( GLcontext *ctx ) * rasterization fallback. As this function will be called again when we * leave a rasterization fallback, we can just skip it for now. */ - if (rmesa->Fallback != 0) + if (rmesa->radeon.Fallback != 0) return; vte = rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]; @@ -276,8 +276,9 @@ void r200ChooseVertexState( GLcontext *ctx ) /* Flush vertices in the current dma region. */ -static void flush_last_swtcl_prim( r200ContextPtr rmesa ) +static void flush_last_swtcl_prim(GLcontext *ctx) { + r200ContextPtr rmesa = R200_CONTEXT(ctx); if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -285,7 +286,7 @@ static void flush_last_swtcl_prim( r200ContextPtr rmesa ) if (rmesa->dma.current.buf) { struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset + + GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset + current->buf->buf->idx * RADEON_BUFFER_SIZE + current->start); @@ -324,7 +325,7 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) r200RefillCurrentDmaRegion( rmesa ); if (!rmesa->dma.flush) { - rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->dma.flush = flush_last_swtcl_prim; } @@ -599,7 +600,7 @@ void r200ChooseRenderState( GLcontext *ctx ) GLuint index = 0; GLuint flags = ctx->_TriangleCaps; - if (!rmesa->TclFallback || rmesa->Fallback) + if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) return; if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R200_TWOSIDE_BIT; @@ -701,10 +702,10 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); - GLuint oldfallback = rmesa->Fallback; + GLuint oldfallback = rmesa->radeon.Fallback; if (mode) { - rmesa->Fallback |= bit; + rmesa->radeon.Fallback |= bit; if (oldfallback == 0) { R200_FIREVERTICES( rmesa ); TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE ); @@ -717,7 +718,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) } } else { - rmesa->Fallback &= ~bit; + rmesa->radeon.Fallback &= ~bit; if (oldfallback == bit) { _swrast_flush( ctx ); @@ -731,14 +732,14 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) tnl->Driver.Render.ResetLineStipple = r200ResetLineStipple; TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_FALSE ); - if (rmesa->TclFallback) { - /* These are already done if rmesa->TclFallback goes to + if (rmesa->radeon.TclFallback) { + /* These are already done if rmesa->radeon.TclFallback goes to * zero above. But not if it doesn't (R200_NO_TCL for * example?) */ _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); - RENDERINPUTS_ZERO( rmesa->tnl_index_bitset ); + RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset ); r200ChooseVertexState( ctx ); r200ChooseRenderState( ctx ); } @@ -873,8 +874,8 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, */ LOCK_HARDWARE( rmesa ); UNLOCK_HARDWARE( rmesa ); - h = rmesa->dri.drawable->h + rmesa->dri.drawable->y; - px += rmesa->dri.drawable->x; + h = rmesa->radeon.dri.drawable->h + rmesa->radeon.dri.drawable->y; + px += rmesa->radeon.dri.drawable->x; /* Clipping handled by existing mechansims in r200_ioctl.c? */ @@ -929,7 +930,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, /* Need to restore vertexformat? */ - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) r200ChooseVertexState( ctx ); } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 99aecfe1e90..d14564c29bf 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -154,7 +154,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) } else { if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); @@ -394,7 +394,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* TODO: separate this from the swtnl pipeline */ - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) return GL_TRUE; /* fallback to software t&l */ if (R200_DEBUG & DEBUG_PRIMS) @@ -405,7 +405,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Validate state: */ - if (rmesa->NewGLState) + if (rmesa->radeon.NewGLState) r200ValidateState( ctx ); if (!ctx->VertexProgram._Enabled) { @@ -566,7 +566,7 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; if ( rmesa->dma.flush ) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); rmesa->dma.flush = NULL; @@ -631,10 +631,10 @@ static char *getFallbackString(GLuint bit) void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint oldfallback = rmesa->TclFallback; + GLuint oldfallback = rmesa->radeon.TclFallback; if (mode) { - rmesa->TclFallback |= bit; + rmesa->radeon.TclFallback |= bit; if (oldfallback == 0) { if (R200_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "R200 begin tcl fallback %s\n", @@ -643,7 +643,7 @@ void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) } } else { - rmesa->TclFallback &= ~bit; + rmesa->radeon.TclFallback &= ~bit; if (oldfallback == bit) { if (R200_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "R200 end tcl fallback %s\n", diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 0cd93253664..525a9de4a0f 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -335,9 +335,9 @@ r200ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, { r200ContextPtr rmesa = R200_CONTEXT(ctx); const GLboolean do32bpt = - ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); + ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); const GLboolean force16bpt = - ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); + ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); (void) format; switch ( internalFormat ) { @@ -997,7 +997,7 @@ static void r200TexEnv( GLcontext *ctx, GLenum target, * NOTE: Add a small bias to the bias for conform mipsel.c test. */ bias = *param + .01; - min = driQueryOptionb (&rmesa->optionCache, "no_neg_lod_bias") ? + min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? 0.0 : -16.0; bias = CLAMP( bias, min, 16.0 ); b = (int)(bias * fixed_one) & R200_LOD_BIAS_MASK; @@ -1162,7 +1162,7 @@ r200NewTextureObject( GLcontext *ctx, GLuint name, GLenum target ) obj = _mesa_new_texture_object(ctx, name, target); if (!obj) return NULL; - obj->MaxAnisotropy = rmesa->initialMaxAnisotropy; + obj->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; r200AllocTexObj( obj ); return obj; } diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index 3a700def050..93ae3260cca 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -66,7 +66,7 @@ r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t ) unsigned i; - for ( i = 0 ; i < rmesa->glCtx->Const.MaxTextureUnits ; i++ ) { + for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { if ( t == rmesa->state.texture.unit[i].texobj ) { rmesa->state.texture.unit[i].texobj = NULL; rmesa->hw.tex[i].dirty = GL_FALSE; @@ -424,7 +424,7 @@ static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t, LOCK_HARDWARE( rmesa ); do { - ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE, + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE, &tex, sizeof(drm_radeon_texture_t) ); if (ret) { if (R200_DEBUG & DEBUG_IOCTL) @@ -464,7 +464,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) if ( R200_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__, - (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize, + (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize, t->base.firstLevel, t->base.lastLevel ); } @@ -473,7 +473,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - r200Finish( rmesa->glCtx ); + r200Finish( rmesa->radeon.glCtx ); } LOCK_HARDWARE( rmesa ); @@ -481,7 +481,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) if ( t->base.memBlock == NULL ) { int heap; - heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps, + heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, (driTextureObject *) t ); if ( heap == -1 ) { UNLOCK_HARDWARE( rmesa ); @@ -489,7 +489,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) } /* Set the base offset of the texture image */ - t->bufAddr = rmesa->radeonScreen->texOffset[heap] + t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] + t->base.memBlock->ofs; t->pp_txoffset = t->bufAddr; @@ -523,7 +523,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - r200Finish( rmesa->glCtx ); + r200Finish( rmesa->radeon.glCtx ); } return 0; diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index b5dfe304247..02f79bf3f80 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -981,7 +981,7 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, { r200ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = - _mesa_lookup_texture(rmesa->glCtx, texname); + _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t; if (!tObj) @@ -1212,7 +1212,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa, radeonTexObjPtr texobj ) { /* do not use RADEON_DB_STATE to avoid stale texture caches */ - int *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; + GLuint *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; R200_STATECHANGE( rmesa, tex[unit] ); @@ -1225,7 +1225,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa, cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */ cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */ cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; - if (rmesa->radeonScreen->drmSupportsFragShader) { + if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { cmd[TEX_PP_TXOFFSET_NEWDRM] = texobj->pp_txoffset; } else { @@ -1233,13 +1233,13 @@ static void import_tex_obj_state( r200ContextPtr rmesa, } if (texobj->base.tObj->Target == GL_TEXTURE_CUBE_MAP) { - int *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; + GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; GLuint bytesPerFace = texobj->base.totalSize / 6; ASSERT(texobj->base.totalSize % 6 == 0); R200_STATECHANGE( rmesa, cube[unit] ); cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; - if (rmesa->radeonScreen->drmSupportsFragShader) { + if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { /* that value is submitted twice. could change cube atom to not include that command when new drm is used */ cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces; @@ -1535,7 +1535,7 @@ static void disable_tex( GLcontext *ctx, int unit ) R200_STATECHANGE( rmesa, vtx ); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); - if (rmesa->TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<radeon.TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<TexGenEnabled) { rmesa->recheck_texgen[unit] = GL_TRUE; - rmesa->NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } } } @@ -1767,7 +1767,7 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit ) GLboolean fallback = !r200_validate_texgen( ctx, unit ); TCL_FALLBACK( ctx, (R200_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = 0; - rmesa->NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } FALLBACK( rmesa, R200_FALLBACK_BORDER_MODE, t->border_fallback ); @@ -1846,11 +1846,11 @@ void r200UpdateTextureState( GLcontext *ctx ) FALLBACK( rmesa, R200_FALLBACK_TEXTURE, !ok ); - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) r200ChooseVertexState( ctx ); - if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) { + if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { /* * T0 hang workaround ------------- diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c index 4a25031e039..888f91db73d 100644 --- a/src/mesa/drivers/dri/r200/r200_vertprog.c +++ b/src/mesa/drivers/dri/r200/r200_vertprog.c @@ -1110,9 +1110,9 @@ void r200SetupVertexProg( GLcontext *ctx ) { } /* could optimize setting up vertex progs away for non-tcl hw */ fallback = !(vp->native && r200VertexProgUpdateParams(ctx, vp) && - rmesa->radeonScreen->drmSupportsVertexProgram); + rmesa->radeon.radeonScreen->drmSupportsVertexProgram); TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, fallback); - if (rmesa->TclFallback) return; + if (rmesa->radeon.TclFallback) return; R200_STATECHANGE( rmesa, vap ); /* FIXME: fglrx sets R200_VAP_SINGLE_BUF_STATE_ENABLE too. Do we need it? diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 3d7122fce2d..7357cf74c98 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -77,7 +77,8 @@ COMMON_SYMLINKS = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ - radeon_cs_legacy.h + radeon_cs_legacy.h \ + common_context.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 4eac5183b2f..bd9d25d2f0d 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -136,10 +136,10 @@ void r300BeginBatch(r300ContextPtr r300, int n, } static void r300PrintStateAtom(r300ContextPtr r300, - struct r300_state_atom *state) + struct radeon_state_atom *state) { int i; - int dwords = (*state->check) (r300, state); + int dwords = (*state->check) (r300->radeon.glCtx, state); fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); @@ -160,7 +160,7 @@ static void r300PrintStateAtom(r300ContextPtr r300, static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) { BATCH_LOCALS(r300); - struct r300_state_atom *atom; + struct radeon_state_atom *atom; int dwords; cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); @@ -173,13 +173,13 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) /* Emit actual atoms */ foreach(atom, &r300->hw.atomlist) { if ((atom->dirty || r300->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r300, atom); + dwords = (*atom->check) (r300->radeon.glCtx, atom); if (dwords) { if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { r300PrintStateAtom(r300, atom); } if (atom->emit) { - (*atom->emit)(r300, atom); + (*atom->emit)(r300->radeon.glCtx, atom); } else { BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); @@ -246,15 +246,16 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) -void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) +void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i; if (!r300->radeon.radeonScreen->kernel_mm) { uint32_t dwords; - dwords = (*atom->check) (r300, atom); + dwords = (*atom->check) (ctx, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); END_BATCH(); @@ -284,8 +285,9 @@ void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) } } -void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) +void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i, sz; @@ -293,7 +295,7 @@ void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) if (!r300->radeon.radeonScreen->kernel_mm) { uint32_t dwords; - dwords = (*atom->check) (r300, atom); + dwords = (*atom->check) (ctx, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); END_BATCH(); @@ -323,8 +325,9 @@ void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) } } -static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) +static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); @@ -353,8 +356,9 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) } } -static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) +static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); struct radeon_renderbuffer *rrb; uint32_t cbpitch; @@ -362,7 +366,7 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) rrb = r300->radeon.state.color.rrb; if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; } if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); @@ -386,8 +390,9 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) END_BATCH(); } -static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) +static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); struct radeon_renderbuffer *rrb; uint32_t zbpitch; @@ -411,22 +416,23 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) END_BATCH(); } -static int check_always(r300ContextPtr r300, struct r300_state_atom *atom) +static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; } -static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom) +static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); int cnt; - if (atom->cmd[0] == CP_PACKET2) { - return 0; - } + if (atom->cmd[0] == CP_PACKET2) { + return 0; + } cnt = packet0_count(r300, atom->cmd); return cnt ? cnt + 1 : 0; } -int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) +int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom) { int cnt; @@ -434,7 +440,7 @@ int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) return cnt ? (cnt * 4) + 1 : 0; } -int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) +int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom) { int cnt; @@ -442,7 +448,7 @@ int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) return cnt ? (cnt * 6) + 1 : 0; } -int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) { int cnt; @@ -774,7 +780,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (size > 64 * 256) size = 64 * 256; - size = 64 * 1024 / 4; + size = 64 * 1024 / 4; if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", sizeof(drm_r300_cmd_header_t)); @@ -805,7 +811,7 @@ void r300InitCmdBuf(r300ContextPtr r300) */ void r300DestroyCmdBuf(r300ContextPtr r300) { - struct r300_state_atom *atom; + struct radeon_state_atom *atom; radeon_cs_destroy(r300->cmdbuf.cs); foreach(atom, &r300->hw.atomlist) { diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index bb7e0bf2960..f4cc5d3bb12 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -127,11 +127,11 @@ void r300BeginBatch(r300ContextPtr r300, do { \ } while(0) -void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom); -int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom); +void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); +int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); -void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom); -int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom); -int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom); +void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom); +int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom); +int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom); #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 30229ed4fbc..e631e810079 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -55,7 +55,7 @@ typedef struct r300_context *r300ContextPtr; #include "radeon_lock.h" #include "main/mm.h" -/* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . +/* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble with other compilers ... GLUE! */ @@ -194,24 +194,6 @@ struct r300_texture_state { int tc_count; /* number of incoming texture coordinates from VAP */ }; -/** - * A block of hardware state. - * - * When check returns non-zero, the returned number of dwords must be - * copied verbatim into the command buffer in order to update a state atom - * when it is dirty. - */ -struct r300_state_atom { - struct r300_state_atom *next, *prev; - const char *name; /* for debug */ - int cmd_size; /* maximum size in dwords */ - GLuint idx; /* index in an array (e.g. textures) */ - uint32_t *cmd; - GLboolean dirty; - - int (*check) (r300ContextPtr, struct r300_state_atom * atom); - void (*emit) (r300ContextPtr, struct r300_state_atom * atom); -}; #define R300_VPT_CMD_0 0 #define R300_VPT_XSCALE 1 @@ -428,96 +410,96 @@ struct r300_state_atom { * Cache for hardware register state. */ struct r300_hw_state { - struct r300_state_atom atomlist; + struct radeon_state_atom atomlist; GLboolean is_dirty; GLboolean all_dirty; int max_state_size; /* in dwords */ - struct r300_state_atom vpt; /* viewport (1D98) */ - struct r300_state_atom vap_cntl; - struct r300_state_atom vap_index_offset; /* 0x208c r5xx only */ - struct r300_state_atom vof; /* VAP output format register 0x2090 */ - struct r300_state_atom vte; /* (20B0) */ - struct r300_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ - struct r300_state_atom vap_cntl_status; - struct r300_state_atom vir[2]; /* vap input route (2150/21E0) */ - struct r300_state_atom vic; /* vap input control (2180) */ - struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */ - struct r300_state_atom vap_clip_cntl; - struct r300_state_atom vap_clip; - struct r300_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */ - struct r300_state_atom pvs; /* pvs_cntl (22D0) */ - struct r300_state_atom gb_enable; /* (4008) */ - struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ - struct r300_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ - struct r300_state_atom ga_triangle_stipple; /* (4214) */ - struct r300_state_atom ps; /* pointsize (421C) */ - struct r300_state_atom ga_point_minmax; /* (4230) */ - struct r300_state_atom lcntl; /* line control */ - struct r300_state_atom ga_line_stipple; /* (4260) */ - struct r300_state_atom shade; - struct r300_state_atom polygon_mode; - struct r300_state_atom fogp; /* fog parameters (4294) */ - struct r300_state_atom ga_soft_reset; /* (429C) */ - struct r300_state_atom zbias_cntl; - struct r300_state_atom zbs; /* zbias (42A4) */ - struct r300_state_atom occlusion_cntl; - struct r300_state_atom cul; /* cull cntl (42B8) */ - struct r300_state_atom su_depth_scale; /* (42C0) */ - struct r300_state_atom rc; /* rs control (4300) */ - struct r300_state_atom ri; /* rs interpolators (4310) */ - struct r300_state_atom rr; /* rs route (4330) */ - struct r300_state_atom sc_hyperz; /* (43A4) */ - struct r300_state_atom sc_screendoor; /* (43E8) */ - struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */ - struct r300_state_atom fpt; /* texi - (4620) */ - struct r300_state_atom us_out_fmt; /* (46A4) */ - struct r300_state_atom r500fp; /* r500 fp instructions */ - struct r300_state_atom r500fp_const; /* r500 fp constants */ - struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ - struct r300_state_atom fogs; /* fog state (4BC0) */ - struct r300_state_atom fogc; /* fog color (4BC8) */ - struct r300_state_atom at; /* alpha test (4BD4) */ - struct r300_state_atom fg_depth_src; /* (4BD8) */ - struct r300_state_atom fpp; /* 0x4C00 and following */ - struct r300_state_atom rb3d_cctl; /* (4E00) */ - struct r300_state_atom bld; /* blending (4E04) */ - struct r300_state_atom cmk; /* colormask (4E0C) */ - struct r300_state_atom blend_color; /* constant blend color */ - struct r300_state_atom rop; /* ropcntl */ - struct r300_state_atom cb; /* colorbuffer (4E28) */ - struct r300_state_atom rb3d_dither_ctl; /* (4E50) */ - struct r300_state_atom rb3d_aaresolve_ctl; /* (4E88) */ - struct r300_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ - struct r300_state_atom zs; /* zstencil control (4F00) */ - struct r300_state_atom zstencil_format; - struct r300_state_atom zb; /* z buffer (4F20) */ - struct r300_state_atom zb_depthclearvalue; /* (4F28) */ - struct r300_state_atom unk4F30; /* (4F30) */ - struct r300_state_atom zb_hiz_offset; /* (4F44) */ - struct r300_state_atom zb_hiz_pitch; /* (4F54) */ - - struct r300_state_atom vpi; /* vp instructions */ - struct r300_state_atom vpp; /* vp parameters */ - struct r300_state_atom vps; /* vertex point size (?) */ - struct r300_state_atom vpucp[6]; /* vp user clip plane - 6 */ + struct radeon_state_atom vpt; /* viewport (1D98) */ + struct radeon_state_atom vap_cntl; + struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ + struct radeon_state_atom vof; /* VAP output format register 0x2090 */ + struct radeon_state_atom vte; /* (20B0) */ + struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ + struct radeon_state_atom vap_cntl_status; + struct radeon_state_atom vir[2]; /* vap input route (2150/21E0) */ + struct radeon_state_atom vic; /* vap input control (2180) */ + struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */ + struct radeon_state_atom vap_clip_cntl; + struct radeon_state_atom vap_clip; + struct radeon_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */ + struct radeon_state_atom pvs; /* pvs_cntl (22D0) */ + struct radeon_state_atom gb_enable; /* (4008) */ + struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ + struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ + struct radeon_state_atom ga_triangle_stipple; /* (4214) */ + struct radeon_state_atom ps; /* pointsize (421C) */ + struct radeon_state_atom ga_point_minmax; /* (4230) */ + struct radeon_state_atom lcntl; /* line control */ + struct radeon_state_atom ga_line_stipple; /* (4260) */ + struct radeon_state_atom shade; + struct radeon_state_atom polygon_mode; + struct radeon_state_atom fogp; /* fog parameters (4294) */ + struct radeon_state_atom ga_soft_reset; /* (429C) */ + struct radeon_state_atom zbias_cntl; + struct radeon_state_atom zbs; /* zbias (42A4) */ + struct radeon_state_atom occlusion_cntl; + struct radeon_state_atom cul; /* cull cntl (42B8) */ + struct radeon_state_atom su_depth_scale; /* (42C0) */ + struct radeon_state_atom rc; /* rs control (4300) */ + struct radeon_state_atom ri; /* rs interpolators (4310) */ + struct radeon_state_atom rr; /* rs route (4330) */ + struct radeon_state_atom sc_hyperz; /* (43A4) */ + struct radeon_state_atom sc_screendoor; /* (43E8) */ + struct radeon_state_atom fp; /* fragment program cntl + nodes (4600) */ + struct radeon_state_atom fpt; /* texi - (4620) */ + struct radeon_state_atom us_out_fmt; /* (46A4) */ + struct radeon_state_atom r500fp; /* r500 fp instructions */ + struct radeon_state_atom r500fp_const; /* r500 fp constants */ + struct radeon_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ + struct radeon_state_atom fogs; /* fog state (4BC0) */ + struct radeon_state_atom fogc; /* fog color (4BC8) */ + struct radeon_state_atom at; /* alpha test (4BD4) */ + struct radeon_state_atom fg_depth_src; /* (4BD8) */ + struct radeon_state_atom fpp; /* 0x4C00 and following */ + struct radeon_state_atom rb3d_cctl; /* (4E00) */ + struct radeon_state_atom bld; /* blending (4E04) */ + struct radeon_state_atom cmk; /* colormask (4E0C) */ + struct radeon_state_atom blend_color; /* constant blend color */ + struct radeon_state_atom rop; /* ropcntl */ + struct radeon_state_atom cb; /* colorbuffer (4E28) */ + struct radeon_state_atom rb3d_dither_ctl; /* (4E50) */ + struct radeon_state_atom rb3d_aaresolve_ctl; /* (4E88) */ + struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ + struct radeon_state_atom zs; /* zstencil control (4F00) */ + struct radeon_state_atom zstencil_format; + struct radeon_state_atom zb; /* z buffer (4F20) */ + struct radeon_state_atom zb_depthclearvalue; /* (4F28) */ + struct radeon_state_atom unk4F30; /* (4F30) */ + struct radeon_state_atom zb_hiz_offset; /* (4F44) */ + struct radeon_state_atom zb_hiz_pitch; /* (4F54) */ + + struct radeon_state_atom vpi; /* vp instructions */ + struct radeon_state_atom vpp; /* vp parameters */ + struct radeon_state_atom vps; /* vertex point size (?) */ + struct radeon_state_atom vpucp[6]; /* vp user clip plane - 6 */ /* 8 texture units */ /* the state is grouped by function and not by texture unit. This makes single unit updates really awkward - we are much better off updating the whole thing at once */ struct { - struct r300_state_atom filter; - struct r300_state_atom filter_1; - struct r300_state_atom size; - struct r300_state_atom format; - struct r300_state_atom pitch; - struct r300_state_atom offset; - struct r300_state_atom chroma_key; - struct r300_state_atom border_color; + struct radeon_state_atom filter; + struct radeon_state_atom filter_1; + struct radeon_state_atom size; + struct radeon_state_atom format; + struct radeon_state_atom pitch; + struct radeon_state_atom offset; + struct radeon_state_atom chroma_key; + struct radeon_state_atom border_color; } tex; - struct r300_state_atom txe; /* tex enable (4104) */ + struct radeon_state_atom txe; /* tex enable (4104) */ r300TexObj *textures[R300_MAX_TEXTURE_UNITS]; }; @@ -841,10 +823,6 @@ struct r300_swtcl_info { /* Fallback rasterization functions */ - // r200_point_func draw_point; - // r200_line_func draw_line; - // r200_tri_func draw_tri; - GLuint hw_primitive; GLenum render_primitive; GLuint numverts; diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 6d7b191b24d..064732d4583 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -387,7 +387,7 @@ static void r300EmitClearState(GLcontext * ctx) FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); END_BATCH(); } else { - struct r300_state_atom r500fp; + struct radeon_state_atom r500fp; uint32_t _cmd[10]; R300_STATECHANGE(r300, fp); @@ -443,7 +443,7 @@ static void r300EmitClearState(GLcontext * ctx) R500_ALU_RGBA_A_SWIZ_0; r500fp.cmd[7] = 0; - emit_r500fp(r300, &r500fp); + emit_r500fp(ctx, &r500fp); } BEGIN_BATCH(2); @@ -484,7 +484,7 @@ static void r300EmitClearState(GLcontext * ctx) END_BATCH(); if (has_tcl) { - struct r300_state_atom vpu; + struct radeon_state_atom vpu; uint32_t _cmd[10]; R300_STATECHANGE(r300, pvs); R300_STATECHANGE(r300, vpi); @@ -528,7 +528,7 @@ static void r300EmitClearState(GLcontext * ctx) PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); vpu.cmd[8] = 0x0; - emit_vpu(r300, &vpu); + emit_vpu(ctx, &vpu); } } diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index d5bbf2928df..7dfc3b3b914 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -49,20 +49,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "dri_util.h" -struct radeon_context; -typedef struct radeon_context radeonContextRec; -typedef struct radeon_context *radeonContextPtr; - -/* Rasterizing fallbacks */ -/* See correponding strings in r200_swtcl.c */ -#define RADEON_FALLBACK_TEXTURE 0x0001 -#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 -#define RADEON_FALLBACK_STENCIL 0x0004 -#define RADEON_FALLBACK_RENDER_MODE 0x0008 -#define RADEON_FALLBACK_BLEND_EQ 0x0010 -#define RADEON_FALLBACK_BLEND_FUNC 0x0020 -#define RADEON_FALLBACK_DISABLE 0x0040 -#define RADEON_FALLBACK_BORDER_MODE 0x0080 +#include "radeon_screen.h" +#include "common_context.h" #if R200_MERGED extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode); @@ -99,96 +87,6 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); #define TCL_FALLBACK( ctx, bit, mode ) ; #endif -struct radeon_dri_mirror { - __DRIcontextPrivate *context; /* DRI context */ - __DRIscreenPrivate *screen; /* DRI screen */ - /** - * DRI drawable bound to this context for drawing. - */ - __DRIdrawablePrivate *drawable; - - /** - * DRI drawable bound to this context for reading. - */ - __DRIdrawablePrivate *readable; - - drm_context_t hwContext; - drm_hw_lock_t *hwLock; - int fd; - int drmMinor; -}; - -/** - * Derived state for internal purposes. - */ -struct radeon_scissor_state { - drm_clip_rect_t rect; - GLboolean enabled; - - GLuint numClipRects; /* Cliprects active */ - GLuint numAllocedClipRects; /* Cliprects available */ - drm_clip_rect_t *pClipRects; -}; - -struct radeon_colorbuffer_state { - GLuint clear; - struct radeon_renderbuffer *rrb; -}; - -struct radeon_state { - struct radeon_colorbuffer_state color; - struct radeon_scissor_state scissor; - struct radeon_renderbuffer *depth_buffer; -}; - -/** - * Common per-context variables shared by R200 and R300. - * R200- and R300-specific code "derive" their own context from this - * structure. - */ -struct radeon_context { - GLcontext *glCtx; /* Mesa context */ - radeonScreenPtr radeonScreen; /* Screen private DRI data */ - - /* Fallback state */ - GLuint Fallback; - GLuint TclFallback; - - /* Page flipping */ - GLuint doPageFlip; - - /* Drawable, cliprect and scissor information */ - GLuint numClipRects; /* Cliprects for the draw buffer */ - drm_clip_rect_t *pClipRects; - unsigned int lastStamp; - GLboolean lost_context; - drm_radeon_sarea_t *sarea; /* Private SAREA data */ - - /* Mirrors of some DRI state */ - struct radeon_dri_mirror dri; - - /* Busy waiting */ - GLuint do_usleeps; - GLuint do_irqs; - GLuint irqsEmitted; - drm_radeon_irq_wait_t iw; - - /* buffer swap */ - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; - - /* Derived state */ - struct radeon_state state; - - /* Configuration cache - */ - driOptionCache optionCache; -}; - -#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, @@ -216,18 +114,6 @@ extern int RADEON_DEBUG; #define RADEON_DEBUG 0 #endif -#define DEBUG_TEXTURE 0x0001 -#define DEBUG_STATE 0x0002 -#define DEBUG_IOCTL 0x0004 -#define DEBUG_PRIMS 0x0008 -#define DEBUG_VERTS 0x0010 -#define DEBUG_FALLBACKS 0x0020 -#define DEBUG_VFMT 0x0040 -#define DEBUG_CODEGEN 0x0080 -#define DEBUG_VERBOSE 0x0100 -#define DEBUG_DRI 0x0200 -#define DEBUG_DMA 0x0400 -#define DEBUG_SANITY 0x0800 #define DEBUG_SYNC 0x1000 #define DEBUG_PIXEL 0x2000 #define DEBUG_MEMORY 0x4000 diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 471763d4180..5778adf9fb9 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -1,9 +1,18 @@ + +#ifndef COMMON_CONTEXT_H +#define COMMON_CONTEXT_H /* This union is used to avoid warnings/miscompilation with float to uint32_t casts due to strict-aliasing */ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; +struct radeon_context; +typedef struct radeon_context radeonContextRec; +typedef struct radeon_context *radeonContextPtr; + #include "main/mm.h" #include "math/m_vector.h" +#include "texmem.h" +#include "tnl/t_context.h" #define TEX_0 0x1 @@ -45,11 +54,13 @@ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; struct radeon_colorbuffer_state { GLuint clear; int roundEnable; + struct radeon_renderbuffer *rrb; }; struct radeon_depthbuffer_state { GLuint clear; GLfloat scale; + struct radeon_renderbuffer *rrb; }; struct radeon_scissor_state { @@ -76,16 +87,18 @@ struct radeon_state_atom { int cmd_size; /* size in bytes */ GLuint idx; GLuint is_tcl; - int *cmd; /* one or more cmd's */ - int *lastcmd; /* one or more cmd's */ + GLuint *cmd; /* one or more cmd's */ + GLuint *lastcmd; /* one or more cmd's */ GLboolean dirty; /* dirty-mark in emit_state_list */ - GLboolean(*check) (GLcontext *, int idx); /* is this state active? */ + int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */ + void (*emit) (GLcontext *, struct radeon_state_atom *atom); }; typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; /* Texture object in locally shared texture space. */ +#ifndef RADEON_COMMON_FOR_R300 struct radeon_tex_obj { driTextureObject base; @@ -118,6 +131,7 @@ struct radeon_tex_obj { GLuint tile_bits; /* hw texture tile bits used on this texture */ }; +#endif /* Need refcounting on dma buffers: */ @@ -145,7 +159,7 @@ struct radeon_dma { */ struct radeon_dma_region current; - void (*flush)( void * ); + void (*flush)( GLcontext *ctx ); char *buf0_address; /* start of buf[0], for index calcs */ GLuint nr_released_bufs; /* flush after so many buffers released */ @@ -224,3 +238,77 @@ struct radeon_dri_mirror { #define DEBUG_PIXEL 0x2000 #define DEBUG_MEMORY 0x4000 + + +typedef void (*radeon_tri_func) (radeonContextPtr, + radeonVertex *, + radeonVertex *, radeonVertex *); + +typedef void (*radeon_line_func) (radeonContextPtr, + radeonVertex *, radeonVertex *); + +typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); + +struct r300_radeon_state { + struct radeon_colorbuffer_state color; + struct radeon_scissor_state scissor; + struct radeon_renderbuffer *depth_buffer; +}; + +struct radeon_context { + GLcontext *glCtx; + radeonScreenPtr radeonScreen; /* Screen private DRI data */ + + /* Texture object bookkeeping + */ + unsigned nr_heaps; + driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; + driTextureObject swapped; + int texture_depth; + float initialMaxAnisotropy; + + /* Rasterization and vertex state: + */ + GLuint TclFallback; + GLuint Fallback; + GLuint NewGLState; + DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ + + /* Page flipping */ + GLuint doPageFlip; + + /* Drawable, cliprect and scissor information */ + GLuint numClipRects; /* Cliprects for the draw buffer */ + drm_clip_rect_t *pClipRects; + unsigned int lastStamp; + GLboolean lost_context; + drm_radeon_sarea_t *sarea; /* Private SAREA data */ + + /* Mirrors of some DRI state */ + struct radeon_dri_mirror dri; + + /* Busy waiting */ + GLuint do_usleeps; + GLuint do_irqs; + GLuint irqsEmitted; + drm_radeon_irq_wait_t iw; + + /* buffer swap */ + int64_t swap_ust; + int64_t swap_missed_ust; + + GLuint swap_count; + GLuint swap_missed_count; + + /* Derived state - for r300 only */ + struct r300_radeon_state state; + + /* Configuration cache + */ + driOptionCache optionCache; + +}; + +#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 3aa1d869f10..e3474f791bb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -40,12 +40,13 @@ #include #include #include "xf86drm.h" +#include "texmem.h" #include "drm.h" #include "radeon_drm.h" #include "radeon_bo.h" #include "radeon_bo_legacy.h" #include "radeon_ioctl.h" -#include "texmem.h" + struct bo_legacy { struct radeon_bo base; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 1e992c0b3d6..e2b2323a65e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -84,11 +84,11 @@ int RADEON_DEBUG = (0); */ static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); static char buffer[128]; unsigned offset; - GLuint agp_mode = (rmesa->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : - rmesa->radeonScreen->AGPMode; + GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : + rmesa->radeon.radeonScreen->AGPMode; switch ( name ) { case GL_VENDOR: @@ -99,7 +99,7 @@ static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name ) agp_mode ); sprintf( & buffer[ offset ], " %sTCL", - !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) + !(rmesa->radeon.TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) ? "" : "NO-" ); return (GLubyte *)buffer; @@ -205,7 +205,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; - radeonContextPtr rmesa; + r100ContextPtr rmesa; GLcontext *ctx, *shareCtx; int i; int tcl_mode, fthrottle_mode; @@ -215,7 +215,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, assert(screen); /* Allocate the Radeon context */ - rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) ); + rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) ); if ( !rmesa ) return GL_FALSE; @@ -226,12 +226,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, * Do this here so that initialMaxAnisotropy is set before we create * the default textures. */ - driParseConfigFiles (&rmesa->optionCache, &screen->optionCache, + driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "radeon"); - rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache, + rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache, "def_max_anisotropy"); - if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) { + if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) { if ( sPriv->drm_version.minor < 13 ) fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " "disabling.\n", sPriv->drm_version.minor ); @@ -254,53 +254,53 @@ radeonCreateContext( const __GLcontextModes *glVisual, shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx; else shareCtx = NULL; - rmesa->glCtx = _mesa_create_context(glVisual, shareCtx, - &functions, (void *) rmesa); - if (!rmesa->glCtx) { + rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx, + &functions, (void *) rmesa); + if (!rmesa->radeon.glCtx) { FREE(rmesa); return GL_FALSE; } driContextPriv->driverPrivate = rmesa; /* Init radeon context data */ - rmesa->dri.context = driContextPriv; - rmesa->dri.screen = sPriv; - rmesa->dri.drawable = NULL; - rmesa->dri.readable = NULL; - rmesa->dri.hwContext = driContextPriv->hHWContext; - rmesa->dri.hwLock = &sPriv->pSAREA->lock; - rmesa->dri.fd = sPriv->fd; - rmesa->dri.drmMinor = sPriv->drm_version.minor; - - rmesa->radeonScreen = screen; - rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + + rmesa->radeon.dri.context = driContextPriv; + rmesa->radeon.dri.screen = sPriv; + rmesa->radeon.dri.drawable = NULL; + rmesa->radeon.dri.readable = NULL; + rmesa->radeon.dri.hwContext = driContextPriv->hHWContext; + rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock; + rmesa->radeon.dri.fd = sPriv->fd; + rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor; + + rmesa->radeon.radeonScreen = screen; + rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + screen->sarea_priv_offset); - rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address; + rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; - (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) ); - make_empty_list( & rmesa->swapped ); + (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); + make_empty_list( & rmesa->radeon.swapped ); - rmesa->nr_heaps = screen->numTexHeaps; - for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { - rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa, + rmesa->radeon.nr_heaps = screen->numTexHeaps; + for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { + rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa, screen->texSize[i], 12, RADEON_NR_TEX_REGIONS, - (drmTextureRegionPtr)rmesa->sarea->tex_list[i], - & rmesa->sarea->tex_age[i], - & rmesa->swapped, + (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i], + & rmesa->radeon.sarea->tex_age[i], + & rmesa->radeon.swapped, sizeof( radeonTexObj ), (destroy_texture_object_t *) radeonDestroyTexObj ); - driSetTextureSwapCounterLocation( rmesa->texture_heaps[i], + driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i], & rmesa->c_textureSwaps ); } - rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache, + rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, "texture_depth"); - if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - rmesa->texture_depth = ( screen->cpp == 4 ) ? + if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) + rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; rmesa->swtcl.RenderIndex = ~0; @@ -312,16 +312,16 @@ radeonCreateContext( const __GLcontextModes *glVisual, * setting allow larger textures. */ - ctx = rmesa->glCtx; - ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache, + ctx = rmesa->radeon.glCtx; + ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache, "texture_units"); ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits; ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; - i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures"); + i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); - driCalculateMaxTextureLevels( rmesa->texture_heaps, - rmesa->nr_heaps, + driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps, + rmesa->radeon.nr_heaps, & ctx->Const, 4, 11, /* max 2D texture size is 2048x2048 */ @@ -392,17 +392,17 @@ radeonCreateContext( const __GLcontextModes *glVisual, } driInitExtensions( ctx, card_extensions, GL_TRUE ); - if (rmesa->radeonScreen->drmSupportsCubeMapsR100) + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" ); - if (rmesa->glCtx->Mesa_DXTn) { + if (rmesa->radeon.glCtx->Mesa_DXTn) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); _mesa_enable_extension( ctx, "GL_S3_s3tc" ); } - else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) { + else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); } - if (rmesa->dri.drmMinor >= 9) + if (rmesa->radeon.dri.drmMinor >= 9) _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); /* XXX these should really go right after _mesa_init_driver_functions() */ @@ -415,15 +415,15 @@ radeonCreateContext( const __GLcontextModes *glVisual, _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, ctx->Const.MaxArrayLockSize, 32 ); - fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode"); - rmesa->iw.irq_seq = -1; - rmesa->irqsEmitted = 0; - rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 && - fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS); + fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); + rmesa->radeon.iw.irq_seq = -1; + rmesa->radeon.irqsEmitted = 0; + rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 && + fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS); - rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); + rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - (*sPriv->systemTime->getUST)( & rmesa->swap_ust ); + (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); #if DO_DEBUG @@ -431,20 +431,20 @@ radeonCreateContext( const __GLcontextModes *glVisual, debug_control ); #endif - tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode"); - if (driQueryOptionb(&rmesa->optionCache, "no_rast")) { + tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode"); + if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) { fprintf(stderr, "disabling 3D acceleration\n"); FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1); } else if (tcl_mode == DRI_CONF_TCL_SW || - !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { - if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; + !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; fprintf(stderr, "Disabling HW TCL support\n"); } - TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); + TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); } - if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */ } return GL_TRUE; @@ -458,8 +458,8 @@ radeonCreateContext( const __GLcontextModes *glVisual, void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) { GET_CURRENT_CONTEXT(ctx); - radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate; - radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; + r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate; + r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL; /* check if we're deleting the currently bound context */ if (rmesa == current) { @@ -473,14 +473,14 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) GLboolean release_texture_heaps; - release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1); - _swsetup_DestroyContext( rmesa->glCtx ); - _tnl_DestroyContext( rmesa->glCtx ); - _vbo_DestroyContext( rmesa->glCtx ); - _swrast_DestroyContext( rmesa->glCtx ); + release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1); + _swsetup_DestroyContext( rmesa->radeon.glCtx ); + _tnl_DestroyContext( rmesa->radeon.glCtx ); + _vbo_DestroyContext( rmesa->radeon.glCtx ); + _swrast_DestroyContext( rmesa->radeon.glCtx ); - radeonDestroySwtcl( rmesa->glCtx ); - radeonReleaseArrays( rmesa->glCtx, ~0 ); + radeonDestroySwtcl( rmesa->radeon.glCtx ); + radeonReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->dma.current.buf) { radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); radeonFlushCmdBuf( rmesa, __FUNCTION__ ); @@ -499,20 +499,20 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) */ int i; - for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { - driDestroyTextureHeap( rmesa->texture_heaps[ i ] ); - rmesa->texture_heaps[ i ] = NULL; + for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { + driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] ); + rmesa->radeon.texture_heaps[ i ] = NULL; } - assert( is_empty_list( & rmesa->swapped ) ); + assert( is_empty_list( & rmesa->radeon.swapped ) ); } /* free the Mesa context */ - rmesa->glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->glCtx ); + rmesa->radeon.glCtx->DriverCtx = NULL; + _mesa_destroy_context( rmesa->radeon.glCtx ); /* free the option cache */ - driDestroyOptionCache (&rmesa->optionCache); + driDestroyOptionCache (&rmesa->radeon.optionCache); FREE( rmesa ); } @@ -526,14 +526,14 @@ radeonSwapBuffers( __DRIdrawablePrivate *dPriv ) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - radeonContextPtr rmesa; + r100ContextPtr rmesa; GLcontext *ctx; - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = rmesa->glCtx; + rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate; + ctx = rmesa->radeon.glCtx; if (ctx->Visual.doubleBufferMode) { _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ - if ( rmesa->doPageFlip ) { + if ( rmesa->radeon.doPageFlip ) { radeonPageFlip( dPriv ); } else { @@ -627,10 +627,10 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv ) { - radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate; + r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate; if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx); + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 167f7de6187..fb2b6eac765 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -48,32 +48,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" #include "texmem.h" - #include "main/macros.h" #include "main/mtypes.h" #include "main/colormac.h" - -struct radeon_context; -typedef struct radeon_context radeonContextRec; -typedef struct radeon_context *radeonContextPtr; - -#include "radeon_lock.h" #include "radeon_screen.h" #include "common_context.h" -#define R100_TEX_ALL 0x7 -typedef void (*radeon_tri_func) (radeonContextPtr, - radeonVertex *, - radeonVertex *, radeonVertex *); +struct r100_context; +typedef struct r100_context r100ContextRec; +typedef struct r100_context *r100ContextPtr; -typedef void (*radeon_line_func) (radeonContextPtr, - radeonVertex *, radeonVertex *); +#include "radeon_lock.h" -typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); +#define R100_TEX_ALL 0x7 /* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ #define RADEON_ST_BIT(unit) \ @@ -336,9 +327,8 @@ struct radeon_hw_state { GLboolean is_dirty, all_dirty; }; + struct radeon_state { - /* Derived state for internal purposes: - */ struct radeon_colorbuffer_state color; struct radeon_depthbuffer_state depth; struct radeon_scissor_state scissor; @@ -347,7 +337,7 @@ struct radeon_state { struct radeon_texture_state texture; }; -#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ +#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ (rvb)->address - rmesa->dma.buf0_address + \ (rvb)->start) @@ -427,29 +417,14 @@ struct radeon_swtcl_info { */ #define RADEON_MAX_VERTEX_SIZE 20 -struct radeon_context { - GLcontext *glCtx; /* Mesa context */ +struct r100_context { + struct radeon_context radeon; /* Driver and hardware state management */ struct radeon_hw_state hw; struct radeon_state state; - /* Texture object bookkeeping - */ - unsigned nr_heaps; - driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS]; - driTextureObject swapped; - int texture_depth; - float initialMaxAnisotropy; - - /* Rasterization and vertex state: - */ - GLuint TclFallback; - GLuint Fallback; - GLuint NewGLState; - DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ - /* Vertex buffers */ struct radeon_ioctl ioctl; @@ -460,27 +435,6 @@ struct radeon_context { */ struct radeon_store backup_store; - /* Page flipping - */ - GLuint doPageFlip; - - /* Busy waiting - */ - GLuint do_usleeps; - GLuint do_irqs; - GLuint irqsEmitted; - drm_radeon_irq_wait_t iw; - - /* Drawable, cliprect and scissor information - */ - GLuint numClipRects; /* Cliprects for the draw buffer */ - drm_clip_rect_t *pClipRects; - unsigned int lastStamp; - GLboolean lost_context; - GLboolean save_on_next_emit; - radeonScreenPtr radeonScreen; /* Screen private DRI data */ - drm_radeon_sarea_t *sarea; /* Private SAREA data */ - /* TCL stuff */ GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; @@ -492,14 +446,6 @@ struct radeon_context { GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; GLuint last_ReallyEnabled; - /* VBI - */ - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; - /* radeon_tcl.c */ struct radeon_tcl_info tcl; @@ -508,14 +454,6 @@ struct radeon_context { */ struct radeon_swtcl_info swtcl; - /* Mirrors of some DRI state - */ - struct radeon_dri_mirror dri; - - /* Configuration cache - */ - driOptionCache optionCache; - GLboolean using_hyperz; GLboolean texmicrotile; @@ -528,9 +466,11 @@ struct radeon_context { GLuint c_textureSwaps; GLuint c_textureBytes; GLuint c_vertexBuffers; + + GLboolean save_on_next_emit; }; -#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) +#define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) #define RADEON_OLD_PACKETS 1 diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 9858dacc136..5e2b9867133 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -58,8 +58,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_IDLE_RETRY 16 -static void radeonWaitForIdle( radeonContextPtr rmesa ); -static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, +static void radeonWaitForIdle( r100ContextPtr rmesa ); +static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, const char * caller ); static void print_state_atom( struct radeon_state_atom *state ) @@ -74,7 +74,7 @@ static void print_state_atom( struct radeon_state_atom *state ) } -static void radeonSaveHwState( radeonContextPtr rmesa ) +static void radeonSaveHwState( r100ContextPtr rmesa ) { struct radeon_state_atom *atom; char * dest = rmesa->backup_store.cmd_buf; @@ -85,7 +85,7 @@ static void radeonSaveHwState( radeonContextPtr rmesa ) rmesa->backup_store.cmd_used = 0; foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->check( rmesa->glCtx, 0 ) ) { + if ( atom->check( rmesa->radeon.glCtx, 0 ) ) { int size = atom->cmd_size * 4; memcpy( dest, atom->cmd, size); dest += size; @@ -105,7 +105,7 @@ static void radeonSaveHwState( radeonContextPtr rmesa ) * it, flush it, and then put the current one back. This is so commands at the * start of a cmdbuf can rely on the state being kept from the previous one. */ -static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) +static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa ) { GLuint nr_released_bufs; struct radeon_store saved_store; @@ -116,7 +116,7 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "Emitting backup state on lost context\n"); - rmesa->lost_context = GL_FALSE; + rmesa->radeon.lost_context = GL_FALSE; nr_released_bufs = rmesa->dma.nr_released_bufs; saved_store = rmesa->store; @@ -134,9 +134,9 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. */ -void radeonSetUpAtomList( radeonContextPtr rmesa ) +void radeonSetUpAtomList( r100ContextPtr rmesa ) { - int i, mtu = rmesa->glCtx->Const.MaxTextureUnits; + int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; make_empty_list(&rmesa->hw.atomlist); rmesa->hw.atomlist.name = "atom-list"; @@ -167,7 +167,7 @@ void radeonSetUpAtomList( radeonContextPtr rmesa ) insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt); } -void radeonEmitState( radeonContextPtr rmesa ) +void radeonEmitState( r100ContextPtr rmesa ) { struct radeon_state_atom *atom; char *dest; @@ -198,7 +198,7 @@ void radeonEmitState( radeonContextPtr rmesa ) if (RADEON_DEBUG & DEBUG_STATE) { foreach(atom, &rmesa->hw.atomlist) { if (atom->dirty || rmesa->hw.all_dirty) { - if (atom->check(rmesa->glCtx, 0)) + if (atom->check(rmesa->radeon.glCtx, 0)) print_state_atom(atom); else fprintf(stderr, "skip state %s\n", atom->name); @@ -209,11 +209,11 @@ void radeonEmitState( radeonContextPtr rmesa ) foreach(atom, &rmesa->hw.atomlist) { if (rmesa->hw.all_dirty) atom->dirty = GL_TRUE; - if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) && + if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) && atom->is_tcl) atom->dirty = GL_FALSE; if (atom->dirty) { - if (atom->check(rmesa->glCtx, 0)) { + if (atom->check(rmesa->radeon.glCtx, 0)) { int size = atom->cmd_size * 4; memcpy(dest, atom->cmd, size); dest += size; @@ -232,7 +232,7 @@ void radeonEmitState( radeonContextPtr rmesa ) /* Fire a section of the retained (indexed_verts) buffer as a regular * primtive. */ -extern void radeonEmitVbufPrim( radeonContextPtr rmesa, +extern void radeonEmitVbufPrim( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint vertex_nr ) @@ -288,8 +288,9 @@ extern void radeonEmitVbufPrim( radeonContextPtr rmesa, } -void radeonFlushElts( radeonContextPtr rmesa ) +void radeonFlushElts( GLcontext *ctx ) { + r100ContextPtr rmesa = R100_CONTEXT(ctx); int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start); int dwords; #if RADEON_OLD_PACKETS @@ -319,12 +320,12 @@ void radeonFlushElts( radeonContextPtr rmesa ) if (RADEON_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); - radeonFinish( rmesa->glCtx ); + radeonFinish( rmesa->radeon.glCtx ); } } -GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa, +GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint min_nr ) @@ -375,7 +376,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa, cmd[1].i, vertex_format, primitive); assert(!rmesa->dma.flush); - rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->dma.flush = radeonFlushElts; rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; @@ -385,7 +386,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa, -void radeonEmitVertexAOS( radeonContextPtr rmesa, +void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, GLuint offset ) { @@ -412,7 +413,7 @@ void radeonEmitVertexAOS( radeonContextPtr rmesa, } -void radeonEmitAOS( radeonContextPtr rmesa, +void radeonEmitAOS( r100ContextPtr rmesa, struct radeon_dma_region **component, GLuint nr, GLuint offset ) @@ -467,7 +468,7 @@ void radeonEmitAOS( radeonContextPtr rmesa, } /* using already shifted color_fmt! */ -void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is required? */ +void radeonEmitBlit( r100ContextPtr rmesa, /* FIXME: which drmMinor is required? */ GLuint color_fmt, GLuint src_pitch, GLuint src_offset, @@ -518,7 +519,7 @@ void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is require } -void radeonEmitWait( radeonContextPtr rmesa, GLuint flags ) +void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ) { drm_radeon_cmd_header_t *cmd; @@ -532,13 +533,13 @@ void radeonEmitWait( radeonContextPtr rmesa, GLuint flags ) } -static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, +static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, const char * caller ) { int ret, i; drm_radeon_cmd_buffer_t cmd; - if (rmesa->lost_context) + if (rmesa->radeon.lost_context) radeonBackUpAndEmitLostStateLocked(rmesa); if (RADEON_DEBUG & DEBUG_IOCTL) { @@ -562,8 +563,8 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, rmesa->state.scissor.pClipRects); else ret = radeonSanityCmdBuffer( rmesa, - rmesa->numClipRects, - rmesa->pClipRects); + rmesa->radeon.numClipRects, + rmesa->radeon.pClipRects); if (ret) { fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); goto out; @@ -578,11 +579,11 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, cmd.nbox = rmesa->state.scissor.numClipRects; cmd.boxes = rmesa->state.scissor.pClipRects; } else { - cmd.nbox = rmesa->numClipRects; - cmd.boxes = rmesa->pClipRects; + cmd.nbox = rmesa->radeon.numClipRects; + cmd.boxes = rmesa->radeon.pClipRects; } - ret = drmCommandWrite( rmesa->dri.fd, + ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd) ); @@ -608,7 +609,7 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, /* Note: does not emit any commands to avoid recursion on * radeonAllocCmdBuf. */ -void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller ) +void radeonFlushCmdBuf( r100ContextPtr rmesa, const char *caller ) { int ret; @@ -630,10 +631,10 @@ void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller ) */ -void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ) +void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ) { struct radeon_dma_buffer *dmabuf; - int fd = rmesa->dri.fd; + int fd = rmesa->radeon.dri.fd; int index = 0; int size = 0; drmDMAReq dma; @@ -643,7 +644,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ) fprintf(stderr, "%s\n", __FUNCTION__); if (rmesa->dma.flush) { - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); } if (rmesa->dma.current.buf) @@ -652,7 +653,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ) if (rmesa->dma.nr_released_bufs > 4) radeonFlushCmdBuf( rmesa, __FUNCTION__ ); - dma.context = rmesa->dri.hwContext; + dma.context = rmesa->radeon.dri.hwContext; dma.send_count = 0; dma.send_list = NULL; dma.send_sizes = NULL; @@ -693,7 +694,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ) fprintf(stderr, "Allocated buffer %d\n", index); dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); - dmabuf->buf = &rmesa->radeonScreen->buffers->list[index]; + dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index]; dmabuf->refcount = 1; rmesa->dma.current.buf = dmabuf; @@ -705,7 +706,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ) rmesa->c_vertexBuffers++; } -void radeonReleaseDmaRegion( radeonContextPtr rmesa, +void radeonReleaseDmaRegion( r100ContextPtr rmesa, struct radeon_dma_region *region, const char *caller ) { @@ -716,7 +717,7 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa, return; if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); if (--region->buf->refcount == 0) { drm_radeon_cmd_header_t *cmd; @@ -740,7 +741,7 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa, /* Allocates a region from rmesa->dma.current. If there isn't enough * space in current, grab a new buffer (and discard what was left of current) */ -void radeonAllocDmaRegion( radeonContextPtr rmesa, +void radeonAllocDmaRegion( r100ContextPtr rmesa, struct radeon_dma_region *region, int bytes, int alignment ) @@ -749,7 +750,7 @@ void radeonAllocDmaRegion( radeonContextPtr rmesa, fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); if (region->buf) radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ ); @@ -777,7 +778,7 @@ void radeonAllocDmaRegion( radeonContextPtr rmesa, * SwapBuffers with client-side throttling */ -static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) +static uint32_t radeonGetLastFrame (r100ContextPtr rmesa) { drm_radeon_getparam_t gp; int ret; @@ -785,7 +786,7 @@ static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) gp.param = RADEON_PARAM_LAST_FRAME; gp.value = (int *)&frame; - ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM, + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { @@ -796,13 +797,13 @@ static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) return frame; } -static void radeonEmitIrqLocked( radeonContextPtr rmesa ) +static void radeonEmitIrqLocked( r100ContextPtr rmesa ) { drm_radeon_irq_emit_t ie; int ret; - ie.irq_seq = &rmesa->iw.irq_seq; - ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT, + ie.irq_seq = &rmesa->radeon.iw.irq_seq; + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_EMIT, &ie, sizeof(ie) ); if ( ret ) { fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret ); @@ -811,13 +812,13 @@ static void radeonEmitIrqLocked( radeonContextPtr rmesa ) } -static void radeonWaitIrq( radeonContextPtr rmesa ) +static void radeonWaitIrq( r100ContextPtr rmesa ) { int ret; do { - ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_IRQ_WAIT, - &rmesa->iw, sizeof(rmesa->iw) ); + ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_WAIT, + &rmesa->radeon.iw, sizeof(rmesa->radeon.iw) ); } while (ret && (errno == EINTR || errno == EBUSY)); if ( ret ) { @@ -827,13 +828,13 @@ static void radeonWaitIrq( radeonContextPtr rmesa ) } -static void radeonWaitForFrameCompletion( radeonContextPtr rmesa ) +static void radeonWaitForFrameCompletion( r100ContextPtr rmesa ) { - drm_radeon_sarea_t *sarea = rmesa->sarea; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - if (rmesa->do_irqs) { + if (rmesa->radeon.do_irqs) { if (radeonGetLastFrame(rmesa) < sarea->last_frame) { - if (!rmesa->irqsEmitted) { + if (!rmesa->radeon.irqsEmitted) { while (radeonGetLastFrame (rmesa) < sarea->last_frame) ; } @@ -842,18 +843,18 @@ static void radeonWaitForFrameCompletion( radeonContextPtr rmesa ) radeonWaitIrq( rmesa ); LOCK_HARDWARE( rmesa ); } - rmesa->irqsEmitted = 10; + rmesa->radeon.irqsEmitted = 10; } - if (rmesa->irqsEmitted) { + if (rmesa->radeon.irqsEmitted) { radeonEmitIrqLocked( rmesa ); - rmesa->irqsEmitted--; + rmesa->radeon.irqsEmitted--; } } else { while (radeonGetLastFrame (rmesa) < sarea->last_frame) { UNLOCK_HARDWARE( rmesa ); - if (rmesa->do_usleeps) + if (rmesa->radeon.do_usleeps) DO_USLEEP( 1 ); LOCK_HARDWARE( rmesa ); } @@ -865,7 +866,7 @@ static void radeonWaitForFrameCompletion( radeonContextPtr rmesa ) void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, const drm_clip_rect_t *rect) { - radeonContextPtr rmesa; + r100ContextPtr rmesa; GLint nbox, i, ret; GLboolean missed_target; int64_t ust; @@ -875,10 +876,10 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, assert(dPriv->driContextPriv); assert(dPriv->driContextPriv->driverPrivate); - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate; if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); + fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->radeon.glCtx ); } RADEON_FIREVERTICES( rmesa ); @@ -900,7 +901,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, for ( i = 0 ; i < nbox ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; GLint n = 0; for ( ; i < nr ; i++ ) { @@ -925,12 +926,12 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, b++; n++; } - rmesa->sarea->nbox = n; + rmesa->radeon.sarea->nbox = n; if (!n) continue; - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); + ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_SWAP ); if ( ret ) { fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); @@ -943,21 +944,21 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, if (!rect) { psp = dPriv->driScreenPriv; - rmesa->swap_count++; + rmesa->radeon.swap_count++; (*psp->systemTime->getUST)( & ust ); if ( missed_target ) { - rmesa->swap_missed_count++; - rmesa->swap_missed_ust = ust - rmesa->swap_ust; + rmesa->radeon.swap_missed_count++; + rmesa->radeon.swap_missed_ust = ust - rmesa->radeon.swap_ust; } - rmesa->swap_ust = ust; + rmesa->radeon.swap_ust = ust; rmesa->hw.all_dirty = GL_TRUE; } } void radeonPageFlip( __DRIdrawablePrivate *dPriv ) { - radeonContextPtr rmesa; + r100ContextPtr rmesa; GLint ret; GLboolean missed_target; __DRIscreenPrivate *psp; @@ -966,12 +967,12 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) assert(dPriv->driContextPriv); assert(dPriv->driContextPriv->driverPrivate); - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate; psp = dPriv->driScreenPriv; if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); + rmesa->radeon.sarea->pfCurrentPage); } RADEON_FIREVERTICES( rmesa ); @@ -982,9 +983,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) if (dPriv->numClipRects) { drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; b[0] = box[0]; - rmesa->sarea->nbox = 1; + rmesa->radeon.sarea->nbox = 1; } /* Throttle the frame rate -- only allow a few pending swap buffers @@ -994,12 +995,12 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) UNLOCK_HARDWARE( rmesa ); driWaitForVBlank( dPriv, & missed_target ); if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); + rmesa->radeon.swap_missed_count++; + (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust ); } LOCK_HARDWARE( rmesa ); - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); + ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP ); UNLOCK_HARDWARE( rmesa ); @@ -1008,16 +1009,16 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) exit( 1 ); } - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); + rmesa->radeon.swap_count++; + (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_ust ); /* Get ready for drawing next frame. Update the renderbuffers' * flippedOffset/Pitch fields so we draw into the right place. */ - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); + driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, + rmesa->radeon.sarea->pfCurrentPage); - radeonUpdateDrawBuffer(rmesa->glCtx); + radeonUpdateDrawBuffer(rmesa->radeon.glCtx); } @@ -1028,9 +1029,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) static void radeonClear( GLcontext *ctx, GLbitfield mask ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; - drm_radeon_sarea_t *sarea = rmesa->sarea; + r100ContextPtr rmesa = R100_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; uint32_t clear; GLuint flags = 0; GLuint color_mask = 0; @@ -1083,7 +1084,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) if (rmesa->using_hyperz) { flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) +/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) flags |= RADEON_USE_HIERZ; */ if (!(rmesa->state.stencil.hwBuffer) || ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && @@ -1112,7 +1113,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&clear; - ret = drmCommandWriteRead( rmesa->dri.fd, + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { @@ -1124,7 +1125,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) break; } - if ( rmesa->do_usleeps ) { + if ( rmesa->radeon.do_usleeps ) { UNLOCK_HARDWARE( rmesa ); DO_USLEEP( 1 ); LOCK_HARDWARE( rmesa ); @@ -1137,7 +1138,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; GLint n = 0; @@ -1172,7 +1173,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } } - rmesa->sarea->nbox = n; + rmesa->radeon.sarea->nbox = n; clear.flags = flags; clear.clear_color = rmesa->state.color.clear; @@ -1182,7 +1183,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) clear.depth_boxes = depth_boxes; n--; - b = rmesa->sarea->boxes; + b = rmesa->radeon.sarea->boxes; for ( ; n >= 0 ; n-- ) { depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1; depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1; @@ -1192,7 +1193,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) (float)rmesa->state.depth.clear; } - ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR, + ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR, &clear, sizeof(drm_radeon_clear_t)); if ( ret ) { @@ -1207,9 +1208,9 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } -void radeonWaitForIdleLocked( radeonContextPtr rmesa ) +void radeonWaitForIdleLocked( r100ContextPtr rmesa ) { - int fd = rmesa->dri.fd; + int fd = rmesa->radeon.dri.fd; int to = 0; int ret, i = 0; @@ -1229,7 +1230,7 @@ void radeonWaitForIdleLocked( radeonContextPtr rmesa ) } -static void radeonWaitForIdle( radeonContextPtr rmesa ) +static void radeonWaitForIdle( r100ContextPtr rmesa ) { LOCK_HARDWARE(rmesa); radeonWaitForIdleLocked( rmesa ); @@ -1239,13 +1240,13 @@ static void radeonWaitForIdle( radeonContextPtr rmesa ) void radeonFlush( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); radeonEmitState( rmesa ); @@ -1258,10 +1259,10 @@ void radeonFlush( GLcontext *ctx ) */ void radeonFinish( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); radeonFlush( ctx ); - if (rmesa->do_irqs) { + if (rmesa->radeon.do_irqs) { LOCK_HARDWARE( rmesa ); radeonEmitIrqLocked( rmesa ); UNLOCK_HARDWARE( rmesa ); diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index 4e3a44df075..c97f41d9a1f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -40,29 +40,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_lock.h" -extern void radeonEmitState( radeonContextPtr rmesa ); -extern void radeonEmitVertexAOS( radeonContextPtr rmesa, +extern void radeonEmitState( r100ContextPtr rmesa ); +extern void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, GLuint offset ); -extern void radeonEmitVbufPrim( radeonContextPtr rmesa, +extern void radeonEmitVbufPrim( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint vertex_nr ); -extern void radeonFlushElts( radeonContextPtr rmesa ); +extern void radeonFlushElts( GLcontext *ctx ); + -extern GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa, +extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint min_nr ); -extern void radeonEmitAOS( radeonContextPtr rmesa, +extern void radeonEmitAOS( r100ContextPtr rmesa, struct radeon_dma_region **regions, GLuint n, GLuint offset ); -extern void radeonEmitBlit( radeonContextPtr rmesa, +extern void radeonEmitBlit( r100ContextPtr rmesa, GLuint color_fmt, GLuint src_pitch, GLuint src_offset, @@ -72,17 +73,17 @@ extern void radeonEmitBlit( radeonContextPtr rmesa, GLint dstx, GLint dsty, GLuint w, GLuint h ); -extern void radeonEmitWait( radeonContextPtr rmesa, GLuint flags ); +extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ); -extern void radeonFlushCmdBuf( radeonContextPtr rmesa, const char * ); -extern void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ); +extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * ); +extern void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ); -extern void radeonAllocDmaRegion( radeonContextPtr rmesa, +extern void radeonAllocDmaRegion( r100ContextPtr rmesa, struct radeon_dma_region *region, int bytes, int alignment ); -extern void radeonReleaseDmaRegion( radeonContextPtr rmesa, +extern void radeonReleaseDmaRegion( r100ContextPtr rmesa, struct radeon_dma_region *region, const char *caller ); @@ -91,11 +92,11 @@ extern void radeonCopyBuffer( __DRIdrawablePrivate *drawable, extern void radeonPageFlip( __DRIdrawablePrivate *drawable ); extern void radeonFlush( GLcontext *ctx ); extern void radeonFinish( GLcontext *ctx ); -extern void radeonWaitForIdleLocked( radeonContextPtr rmesa ); -extern void radeonWaitForVBlank( radeonContextPtr rmesa ); +extern void radeonWaitForIdleLocked( r100ContextPtr rmesa ); +extern void radeonWaitForVBlank( r100ContextPtr rmesa ); extern void radeonInitIoctlFuncs( GLcontext *ctx ); -extern void radeonGetAllParams( radeonContextPtr rmesa ); -extern void radeonSetUpAtomList( radeonContextPtr rmesa ); +extern void radeonGetAllParams( r100ContextPtr rmesa ); +extern void radeonSetUpAtomList( r100ContextPtr rmesa ); /* ================================================================ * Helper macros: @@ -106,7 +107,7 @@ extern void radeonSetUpAtomList( radeonContextPtr rmesa ); #define RADEON_NEWPRIM( rmesa ) \ do { \ if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa ); \ + rmesa->dma.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -124,11 +125,11 @@ do { \ rmesa->hw.ATOM.cmd_size * 4) static INLINE int RADEON_DB_STATECHANGE( - radeonContextPtr rmesa, + r100ContextPtr rmesa, struct radeon_state_atom *atom ) { if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { - int *tmp; + GLuint *tmp; RADEON_NEWPRIM( rmesa ); atom->dirty = GL_TRUE; rmesa->hw.is_dirty = GL_TRUE; @@ -147,7 +148,7 @@ static INLINE int RADEON_DB_STATECHANGE( #define RADEON_FIREVERTICES( rmesa ) \ do { \ if ( rmesa->store.cmd_used || rmesa->dma.flush ) { \ - radeonFlush( rmesa->glCtx ); \ + radeonFlush( rmesa->radeon.glCtx ); \ } \ } while (0) @@ -176,7 +177,7 @@ do { \ * and hang on to the lock until the critical section is finished and we flush * the buffer again and unlock. */ -static INLINE void radeonEnsureCmdBufSpace( radeonContextPtr rmesa, +static INLINE void radeonEnsureCmdBufSpace( r100ContextPtr rmesa, int bytes ) { if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ) @@ -186,7 +187,7 @@ static INLINE void radeonEnsureCmdBufSpace( radeonContextPtr rmesa, /* Alloc space in the command buffer */ -static INLINE char *radeonAllocCmdBuf( radeonContextPtr rmesa, +static INLINE char *radeonAllocCmdBuf( r100ContextPtr rmesa, int bytes, const char *where ) { if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ) diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index 64bb3ca103f..0cf5574ba6e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -56,12 +56,12 @@ int prevLockLine = 0; /* Turn on/off page flipping according to the flags in the sarea: */ -static void radeonUpdatePageFlipping(radeonContextPtr rmesa) +static void radeonUpdatePageFlipping(r100ContextPtr rmesa) { - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); + rmesa->radeon.doPageFlip = rmesa->radeon.sarea->pfState; + if (rmesa->radeon.glCtx->WinSysDrawBuffer) { + driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, + rmesa->radeon.sarea->pfCurrentPage); } } @@ -73,14 +73,14 @@ static void radeonUpdatePageFlipping(radeonContextPtr rmesa) * the hardware lock when it changes the window state, this routine will * automatically be called after such a change. */ -void radeonGetLock(radeonContextPtr rmesa, GLuint flags) +void radeonGetLock(r100ContextPtr rmesa, GLuint flags) { - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->dri.readable; - __DRIscreenPrivate *sPriv = rmesa->dri.screen; - drm_radeon_sarea_t *sarea = rmesa->sarea; + __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable; + __DRIscreenPrivate *sPriv = rmesa->radeon.dri.screen; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); + drmGetLock(rmesa->radeon.dri.fd, rmesa->radeon.dri.hwContext, flags); /* The window might have moved, so we might need to get new clip * rects. @@ -95,15 +95,15 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); } - if (rmesa->lastStamp != drawable->lastStamp) { + if (rmesa->radeon.lastStamp != drawable->lastStamp) { radeonUpdatePageFlipping(rmesa); radeonSetCliprects(rmesa); - radeonUpdateViewportOffset(rmesa->glCtx); - driUpdateFramebufferSize(rmesa->glCtx, drawable); + radeonUpdateViewportOffset(rmesa->radeon.glCtx); + driUpdateFramebufferSize(rmesa->radeon.glCtx, drawable); } RADEON_STATECHANGE(rmesa, ctx); - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; } else { @@ -111,14 +111,14 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) ~RADEON_COLOR_TILE_ENABLE; } - if (sarea->ctx_owner != rmesa->dri.hwContext) { + if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { int i; - sarea->ctx_owner = rmesa->dri.hwContext; + sarea->ctx_owner = rmesa->radeon.dri.hwContext; - for (i = 0; i < rmesa->nr_heaps; i++) { - DRI_AGE_TEXTURES(rmesa->texture_heaps[i]); + for (i = 0; i < rmesa->radeon.nr_heaps; i++) { + DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]); } } - rmesa->lost_context = GL_TRUE; + rmesa->radeon.lost_context = GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h index 86e96aa7d2c..e4bfa1b9d67 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.h +++ b/src/mesa/drivers/dri/radeon/radeon_lock.h @@ -42,7 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_LOCK_H__ #define __RADEON_LOCK_H__ -extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); +extern void radeonGetLock(r100ContextPtr rmesa, GLuint flags); /* Turn DEBUG_LOCKING on to find locking conflicts. */ @@ -94,8 +94,8 @@ extern int prevLockLine; do { \ char __ret = 0; \ DEBUG_CHECK_LOCK(); \ - DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ + DRM_CAS( (rmesa)->radeon.dri.hwLock, (rmesa)->radeon.dri.hwContext, \ + (DRM_LOCK_HELD | (rmesa)->radeon.dri.hwContext), __ret ); \ if ( __ret ) \ radeonGetLock( (rmesa), 0 ); \ DEBUG_LOCK(); \ @@ -103,9 +103,9 @@ extern int prevLockLine; #define UNLOCK_HARDWARE( rmesa ) \ do { \ - DRM_UNLOCK( (rmesa)->dri.fd, \ - (rmesa)->dri.hwLock, \ - (rmesa)->dri.hwContext ); \ + DRM_UNLOCK( (rmesa)->radeon.dri.fd, \ + (rmesa)->radeon.dri.hwLock, \ + (rmesa)->radeon.dri.hwContext ); \ DEBUG_RESET(); \ } while (0) diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 126d0727c63..2abf644ef2d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -310,7 +310,7 @@ static void init_tcl_verts( void ) void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; GLuint req = 0; GLuint unit; @@ -437,7 +437,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); #if 0 if (RADEON_DEBUG & DEBUG_VERTS) diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c index 6613757fcea..bbed838b592 100644 --- a/src/mesa/drivers/dri/radeon/radeon_sanity.c +++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c @@ -973,7 +973,7 @@ static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf ) } -int radeonSanityCmdBuffer( radeonContextPtr rmesa, +int radeonSanityCmdBuffer( r100ContextPtr rmesa, int nbox, drm_clip_rect_t *boxes ) { diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.h b/src/mesa/drivers/dri/radeon/radeon_sanity.h index 1ec06bc586b..f30eb1c4f15 100644 --- a/src/mesa/drivers/dri/radeon/radeon_sanity.h +++ b/src/mesa/drivers/dri/radeon/radeon_sanity.h @@ -1,7 +1,7 @@ #ifndef RADEON_SANITY_H #define RADEON_SANITY_H -extern int radeonSanityCmdBuffer( radeonContextPtr rmesa, +extern int radeonSanityCmdBuffer( r100ContextPtr rmesa, int nbox, drm_clip_rect_t *boxes ); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 080fbfe5f41..0b64d6f4ac5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1572,11 +1572,7 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) { -#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) radeonContextPtr rmesa; -#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) - r200ContextPtr rmesa; -#endif if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) || (dPriv->driContextPriv->driverPrivate == NULL) diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 12051ff1c81..9733025fa9f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -282,16 +282,19 @@ static void radeonSpanRenderStart(GLcontext * ctx) #ifdef COMPILE_R300 r300ContextPtr r300 = (r300ContextPtr) rmesa; R300_FIREVERTICES(r300); + LOCK_HARDWARE(rmesa); #else - RADEON_FIREVERTICES(rmesa); + r100ContextPtr r100 = (r100ContextPtr) rmesa; + RADEON_FIREVERTICES(r100); + LOCK_HARDWARE(r100); #endif - LOCK_HARDWARE(rmesa); + radeonWaitForIdleLocked(rmesa); } static void radeonSpanRenderFinish(GLcontext * ctx) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); _swrast_flush(ctx); UNLOCK_HARDWARE(rmesa); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 32bcff33602..7e5306073f6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -62,7 +62,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ); static void radeonAlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; GLubyte refByte; @@ -106,7 +106,7 @@ static void radeonAlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref ) static void radeonBlendEquationSeparate( GLcontext *ctx, GLenum modeRGB, GLenum modeA ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK; GLboolean fallback = GL_FALSE; @@ -147,7 +147,7 @@ static void radeonBlendFuncSeparate( GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB, GLenum sfactorA, GLenum dfactorA ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK); GLboolean fallback = GL_FALSE; @@ -257,7 +257,7 @@ static void radeonBlendFuncSeparate( GLcontext *ctx, static void radeonDepthFunc( GLcontext *ctx, GLenum func ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK; @@ -293,7 +293,7 @@ static void radeonDepthFunc( GLcontext *ctx, GLenum func ) static void radeonDepthMask( GLcontext *ctx, GLboolean flag ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, ctx ); if ( ctx->Depth.Mask ) { @@ -305,7 +305,7 @@ static void radeonDepthMask( GLcontext *ctx, GLboolean flag ) static void radeonClearDepth( GLcontext *ctx, GLclampd d ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint format = (rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] & RADEON_DEPTH_FORMAT_MASK); @@ -327,7 +327,7 @@ static void radeonClearDepth( GLcontext *ctx, GLclampd d ) static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); union { int i; float f; } c, d; GLchan col[4]; @@ -427,15 +427,15 @@ static GLboolean intersect_rect( drm_clip_rect_t *out, } -void radeonRecalcScissorRects( radeonContextPtr rmesa ) +void radeonRecalcScissorRects( r100ContextPtr rmesa ) { drm_clip_rect_t *out; int i; /* Grow cliprect store? */ - if (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) { - while (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) { + if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { + while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */ rmesa->state.scissor.numAllocedClipRects *= 2; } @@ -456,9 +456,9 @@ void radeonRecalcScissorRects( radeonContextPtr rmesa ) out = rmesa->state.scissor.pClipRects; rmesa->state.scissor.numClipRects = 0; - for ( i = 0 ; i < rmesa->numClipRects ; i++ ) { + for ( i = 0 ; i < rmesa->radeon.numClipRects ; i++ ) { if ( intersect_rect( out, - &rmesa->pClipRects[i], + &rmesa->radeon.pClipRects[i], &rmesa->state.scissor.rect ) ) { rmesa->state.scissor.numClipRects++; out++; @@ -469,10 +469,10 @@ void radeonRecalcScissorRects( radeonContextPtr rmesa ) static void radeonUpdateScissor( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); - if ( rmesa->dri.drawable ) { - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + if ( rmesa->radeon.dri.drawable ) { + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; int x = ctx->Scissor.X; int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; @@ -492,7 +492,7 @@ static void radeonUpdateScissor( GLcontext *ctx ) static void radeonScissor( GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); if ( ctx->Scissor.Enabled ) { RADEON_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */ @@ -508,7 +508,7 @@ static void radeonScissor( GLcontext *ctx, static void radeonCullFace( GLcontext *ctx, GLenum unused ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL]; GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL]; @@ -545,7 +545,7 @@ static void radeonCullFace( GLcontext *ctx, GLenum unused ) static void radeonFrontFace( GLcontext *ctx, GLenum mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, set ); rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_FFACE_CULL_DIR_MASK; @@ -570,7 +570,7 @@ static void radeonFrontFace( GLcontext *ctx, GLenum mode ) */ static void radeonLineWidth( GLcontext *ctx, GLfloat widthf ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, lin ); RADEON_STATECHANGE( rmesa, set ); @@ -587,7 +587,7 @@ static void radeonLineWidth( GLcontext *ctx, GLfloat widthf ) static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, lin ); rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = @@ -602,8 +602,8 @@ static void radeonColorMask( GLcontext *ctx, GLboolean r, GLboolean g, GLboolean b, GLboolean a ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp, + r100ContextPtr rmesa = R100_CONTEXT(ctx); + GLuint mask = radeonPackColor( rmesa->radeon.radeonScreen->cpp, ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], @@ -623,7 +623,7 @@ static void radeonColorMask( GLcontext *ctx, static void radeonPolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); float_ui32_type constant = { units * rmesa->state.depth.scale }; float_ui32_type factoru = { factor }; @@ -634,7 +634,7 @@ static void radeonPolygonOffset( GLcontext *ctx, static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint i; drm_radeon_stipple_t stipple; @@ -652,21 +652,21 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* FIXME: Use window x,y offsets into stipple RAM. */ stipple.mask = rmesa->state.stipple.mask; - drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE, + drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, &stipple, sizeof(drm_radeon_stipple_t) ); UNLOCK_HARDWARE( rmesa ); } static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0; /* Can't generally do unfilled via tcl, but some good special * cases work. */ TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, flag); - if (rmesa->TclFallback) { + if (rmesa->radeon.TclFallback) { radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } @@ -686,7 +686,7 @@ static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) */ static void radeonUpdateSpecular( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; GLuint flag = 0; @@ -757,7 +757,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) /* Update vertex/render formats */ - if (rmesa->TclFallback) { + if (rmesa->radeon.TclFallback) { radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } @@ -774,7 +774,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) */ static void update_global_ambient( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); float *fcmd = (float *)RADEON_DB_STATE( glt ); /* Need to do more if both emmissive & ambient are PREMULT: @@ -809,7 +809,7 @@ static void update_light_colors( GLcontext *ctx, GLuint p ) /* fprintf(stderr, "%s\n", __FUNCTION__); */ if (l->Enabled) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); float *fcmd = (float *)RADEON_DB_STATE( lit[p] ); COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient ); @@ -849,7 +849,7 @@ static void check_twoside_fallback( GLcontext *ctx ) static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]; light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) | @@ -913,7 +913,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) void radeonUpdateMaterial( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLfloat (*mat)[4] = ctx->Light.Material.Attrib; GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl ); GLuint mask = ~0; @@ -978,7 +978,7 @@ void radeonUpdateMaterial( GLcontext *ctx ) */ static void update_light( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); /* Have to check these, or have an automatic shortcircuit mechanism * to remove noop statechanges. (Or just do a better job on the @@ -1043,7 +1043,7 @@ static void update_light( GLcontext *ctx ) static void radeonLightfv( GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLint p = light - GL_LIGHT0; struct gl_light *l = &ctx->Light.Light[p]; GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd; @@ -1164,7 +1164,7 @@ static void radeonLightfv( GLcontext *ctx, GLenum light, static void radeonLightModelfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); switch (pname) { case GL_LIGHT_MODEL_AMBIENT: @@ -1188,7 +1188,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, check_twoside_fallback( ctx ); - if (rmesa->TclFallback) { + if (rmesa->radeon.TclFallback) { radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } @@ -1205,7 +1205,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, static void radeonShadeModel( GLcontext *ctx, GLenum mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL]; s &= ~(RADEON_DIFFUSE_SHADE_MASK | @@ -1244,7 +1244,7 @@ static void radeonShadeModel( GLcontext *ctx, GLenum mode ) static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) { GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0; - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; RADEON_STATECHANGE( rmesa, ucp[p] ); @@ -1256,7 +1256,7 @@ static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) static void radeonUpdateClipPlanes( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint p; for (p = 0; p < ctx->Const.MaxClipPlanes; p++) { @@ -1281,7 +1281,7 @@ static void radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func, GLint ref, GLuint mask ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint refmask = (((ctx->Stencil.Ref[0] & 0xff) << RADEON_STENCIL_REF_SHIFT) | ((ctx->Stencil.ValueMask[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT)); @@ -1325,7 +1325,7 @@ radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func, static void radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, msk ); rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~RADEON_STENCIL_WRITE_MASK; @@ -1336,7 +1336,7 @@ radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask ) static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, GLenum zfail, GLenum zpass ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP, and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC, @@ -1349,7 +1349,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP; GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP; - if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) { + if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) { tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC; tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC; tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC; @@ -1455,7 +1455,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, static void radeonClearStencil( GLcontext *ctx, GLint s ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); rmesa->state.stencil.clear = ((GLuint) (ctx->Stencil.Clear & 0xff) | @@ -1481,8 +1481,8 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) */ void radeonUpdateWindow( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + r100ContextPtr rmesa = R100_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1524,8 +1524,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, void radeonUpdateViewportOffset( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + r100ContextPtr rmesa = R100_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1555,8 +1555,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) RADEON_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ - stx = 31 - ((rmesa->dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK); - sty = 31 - ((rmesa->dri.drawable->y + rmesa->dri.drawable->h - 1) + stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK); + sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1) & RADEON_STIPPLE_COORD_MASK); m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) | @@ -1580,20 +1580,20 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLubyte c[4]; CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); - rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp, + rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, c[0], c[1], c[2], c[3] ); } static void radeonRenderMode( GLcontext *ctx, GLenum mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) ); } @@ -1619,7 +1619,7 @@ static GLuint radeon_rop_tab[] = { static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint rop = (GLuint)opcode - GL_CLEAR; ASSERT( rop < 16 ); @@ -1632,40 +1632,40 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) /** * Set up the cliprects for either front or back-buffer drawing. */ -void radeonSetCliprects( radeonContextPtr rmesa ) +void radeonSetCliprects( r100ContextPtr rmesa ) { - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->dri.readable; + __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable; GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate; GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate; if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { /* Can't ignore 2d windows if we are page flipping. */ - if ( drawable->numBackClipRects == 0 || rmesa->doPageFlip ) { - rmesa->numClipRects = drawable->numClipRects; - rmesa->pClipRects = drawable->pClipRects; + if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) { + rmesa->radeon.numClipRects = drawable->numClipRects; + rmesa->radeon.pClipRects = drawable->pClipRects; } else { - rmesa->numClipRects = drawable->numBackClipRects; - rmesa->pClipRects = drawable->pBackClipRects; + rmesa->radeon.numClipRects = drawable->numBackClipRects; + rmesa->radeon.pClipRects = drawable->pBackClipRects; } } else { /* front buffer (or none, or multiple buffers */ - rmesa->numClipRects = drawable->numClipRects; - rmesa->pClipRects = drawable->pClipRects; + rmesa->radeon.numClipRects = drawable->numClipRects; + rmesa->radeon.pClipRects = drawable->pClipRects; } if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(rmesa->glCtx, draw_fb, + _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb, drawable->w, drawable->h); draw_fb->Initialized = GL_TRUE; } if (drawable != readable) { if ((read_fb->Width != readable->w) || (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(rmesa->glCtx, read_fb, + _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb, readable->w, readable->h); read_fb->Initialized = GL_TRUE; } @@ -1674,7 +1674,7 @@ void radeonSetCliprects( radeonContextPtr rmesa ) if (rmesa->state.scissor.enabled) radeonRecalcScissorRects( rmesa ); - rmesa->lastStamp = drawable->lastStamp; + rmesa->radeon.lastStamp = drawable->lastStamp; } @@ -1683,7 +1683,7 @@ void radeonSetCliprects( radeonContextPtr rmesa ) */ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "%s %s\n", __FUNCTION__, @@ -1726,7 +1726,7 @@ static void radeonReadBuffer( GLcontext *ctx, GLenum mode ) static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint p, flag; if ( RADEON_DEBUG & DEBUG_STATE ) @@ -2010,7 +2010,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) static void radeonLightingSpaceChange( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLboolean tmp; RADEON_STATECHANGE( rmesa, tcl ); @@ -2039,7 +2039,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx ) */ -void radeonUploadTexMatrix( radeonContextPtr rmesa, +void radeonUploadTexMatrix( r100ContextPtr rmesa, int unit, GLboolean swapcols ) { /* Here's how this works: on r100, only 3 tex coords can be submitted, so the @@ -2065,7 +2065,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, int idx = TEXMAT_0 + unit; float *dest = ((float *)RADEON_DB_STATE( mat[idx] )) + MAT_ELT_0; int i; - struct gl_texture_unit tUnit = rmesa->glCtx->Texture.Unit[unit]; + struct gl_texture_unit tUnit = rmesa->radeon.glCtx->Texture.Unit[unit]; GLfloat *src = rmesa->tmpmat[unit].m; rmesa->TexMatColSwap &= ~(1 << unit); @@ -2119,7 +2119,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, } -static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx ) +static void upload_matrix( r100ContextPtr rmesa, GLfloat *src, int idx ) { float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0; int i; @@ -2135,7 +2135,7 @@ static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx ) RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] ); } -static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx ) +static void upload_matrix_t( r100ContextPtr rmesa, GLfloat *src, int idx ) { float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0; memcpy(dest, src, 16*sizeof(float)); @@ -2145,7 +2145,7 @@ static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx ) static void update_texturematrix( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL]; GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]; int unit; @@ -2217,7 +2217,7 @@ static void update_texturematrix( GLcontext *ctx ) void radeonUpdateDrawBuffer(GLcontext *ctx) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; driRenderbuffer *drb; @@ -2241,10 +2241,10 @@ radeonUpdateDrawBuffer(GLcontext *ctx) /* Note: we used the (possibly) page-flipped values */ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->radeonScreen->fbLocation) + = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) & RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; } } @@ -2252,8 +2252,8 @@ radeonUpdateDrawBuffer(GLcontext *ctx) void radeonValidateState( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLuint new_state = rmesa->NewGLState; + r100ContextPtr rmesa = R100_CONTEXT(ctx); + GLuint new_state = rmesa->radeon.NewGLState; if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { radeonUpdateDrawBuffer(ctx); @@ -2261,7 +2261,7 @@ void radeonValidateState( GLcontext *ctx ) if (new_state & _NEW_TEXTURE) { radeonUpdateTextureState( ctx ); - new_state |= rmesa->NewGLState; /* may add TEXTURE_MATRIX */ + new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */ } /* Need an event driven matrix update? @@ -2295,7 +2295,7 @@ void radeonValidateState( GLcontext *ctx ) } - rmesa->NewGLState = 0; + rmesa->radeon.NewGLState = 0; } @@ -2306,7 +2306,7 @@ static void radeonInvalidateState( GLcontext *ctx, GLuint new_state ) _vbo_InvalidateState( ctx, new_state ); _tnl_InvalidateState( ctx, new_state ); _ae_invalidate_state( ctx, new_state ); - RADEON_CONTEXT(ctx)->NewGLState |= new_state; + R100_CONTEXT(ctx)->radeon.NewGLState |= new_state; } @@ -2330,15 +2330,15 @@ static GLboolean check_material( GLcontext *ctx ) static void radeonWrapRunPipeline( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLboolean has_material; if (0) - fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->NewGLState); + fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->radeon.NewGLState); /* Validate state: */ - if (rmesa->NewGLState) + if (rmesa->radeon.NewGLState) radeonValidateState( ctx ); has_material = (ctx->Light.Enabled && check_material( ctx )); diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h index 2171879f759..20b2d890019 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.h +++ b/src/mesa/drivers/dri/radeon/radeon_state.h @@ -39,22 +39,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" -extern void radeonInitState( radeonContextPtr rmesa ); +extern void radeonInitState( r100ContextPtr rmesa ); extern void radeonInitStateFuncs( GLcontext *ctx ); extern void radeonUpdateMaterial( GLcontext *ctx ); -extern void radeonSetCliprects( radeonContextPtr rmesa ); -extern void radeonRecalcScissorRects( radeonContextPtr rmesa ); +extern void radeonSetCliprects( r100ContextPtr rmesa ); +extern void radeonRecalcScissorRects( r100ContextPtr rmesa ); extern void radeonUpdateViewportOffset( GLcontext *ctx ); extern void radeonUpdateWindow( GLcontext *ctx ); extern void radeonUpdateDrawBuffer( GLcontext *ctx ); -extern void radeonUploadTexMatrix( radeonContextPtr rmesa, +extern void radeonUploadTexMatrix( r100ContextPtr rmesa, int unit, GLboolean swapcols ); extern void radeonValidateState( GLcontext *ctx ); -extern void radeonPrintDirty( radeonContextPtr rmesa, +extern void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ); @@ -62,7 +62,7 @@ extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define FALLBACK( rmesa, bit, mode ) do { \ if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \ __FUNCTION__, bit, mode ); \ - radeonFallback( rmesa->glCtx, bit, mode ); \ + radeonFallback( rmesa->radeon.glCtx, bit, mode ); \ } while (0) diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 5b1e79bad24..d5b83191b60 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -50,7 +50,7 @@ * State initialization */ -void radeonPrintDirty( radeonContextPtr rmesa, const char *msg ) +void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) { struct radeon_state_atom *l; @@ -97,16 +97,16 @@ static int cmdscl( int offset, int stride, int count ) } #define CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx, int idx ) \ +static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ return FLAG; \ } #define TCL_CHECK( NM, FLAG ) \ -static GLboolean check_##NM( GLcontext *ctx, int idx ) \ +static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ - return !rmesa->TclFallback && (FLAG); \ + r100ContextPtr rmesa = R100_CONTEXT(ctx); \ + return !rmesa->radeon.TclFallback && (FLAG); \ } @@ -150,13 +150,13 @@ CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) /* Initialize the context's hardware state. */ -void radeonInitState( radeonContextPtr rmesa ) +void radeonInitState( r100ContextPtr rmesa ) { - GLcontext *ctx = rmesa->glCtx; + GLcontext *ctx = rmesa->radeon.glCtx; GLuint color_fmt, depth_fmt, i; GLint drawPitch, drawOffset; - switch ( rmesa->radeonScreen->cpp ) { + switch ( rmesa->radeon.radeonScreen->cpp ) { case 2: color_fmt = RADEON_COLOR_FORMAT_RGB565; break; @@ -193,14 +193,14 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && ctx->Visual.depthBits == 24 ); - rmesa->Fallback = 0; + rmesa->radeon.Fallback = 0; - if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - drawOffset = rmesa->radeonScreen->backOffset; - drawPitch = rmesa->radeonScreen->backPitch; + if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) { + drawOffset = rmesa->radeon.radeonScreen->backOffset; + drawPitch = rmesa->radeon.radeonScreen->backPitch; } else { - drawOffset = rmesa->radeonScreen->frontOffset; - drawPitch = rmesa->radeonScreen->frontPitch; + drawOffset = rmesa->radeon.radeonScreen->frontOffset; + drawPitch = rmesa->radeon.radeonScreen->frontPitch; } rmesa->hw.max_state_size = 0; @@ -208,8 +208,8 @@ void radeonInitState( radeonContextPtr rmesa ) #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ do { \ rmesa->hw.ATOM.cmd_size = SZ; \ - rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \ - rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ rmesa->hw.ATOM.name = NM; \ rmesa->hw.ATOM.is_tcl = FLAG; \ rmesa->hw.ATOM.check = check_##CHK; \ @@ -236,7 +236,7 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 ); ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 ); - if (rmesa->radeonScreen->drmSupportsCubeMapsR100) + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) { ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0 ); @@ -353,10 +353,10 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_DST_BLEND_GL_ZERO ); rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation; + rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = - ((rmesa->radeonScreen->depthPitch & + ((rmesa->radeon.radeonScreen->depthPitch & RADEON_DEPTHPITCH_MASK) | RADEON_DEPTH_ENDIAN_NO_SWAP); @@ -374,7 +374,7 @@ void radeonInitState( radeonContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | RADEON_Z_DECOMPRESSION_ENABLE; - if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { /* works for q3, but slight rendering errors with glxgears ? */ /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ /* need this otherwise get lots of lockups with q3 ??? */ @@ -389,7 +389,7 @@ void radeonInitState( radeonContextPtr rmesa ) color_fmt | RADEON_ZBLOCK16); - switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) { + switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; break; @@ -397,19 +397,19 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; break; } - if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) == + if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == DRI_CONF_ROUND_ROUND ) rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE; else rmesa->state.color.roundEnable = 0; - if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) == + if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == DRI_CONF_COLOR_REDUCTION_DITHER ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; else rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + - rmesa->radeonScreen->fbLocation) + rmesa->radeon.radeonScreen->fbLocation) & RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & @@ -418,7 +418,7 @@ void radeonInitState( radeonContextPtr rmesa ) /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ - if (rmesa->sarea->tiling_enabled) { + if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; } @@ -444,7 +444,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_VC_NO_SWAP; #endif - if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; } @@ -492,7 +492,7 @@ void radeonInitState( radeonContextPtr rmesa ) /* Initialize the texture offset to the start of the card texture heap */ rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = @@ -513,15 +513,15 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] = - rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; } /* Can only add ST1 at the time of doing some multitex but can keep diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index ebea1fecdca..ef89d73bdda 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -52,7 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_tcl.h" -static void flush_last_swtcl_prim( radeonContextPtr rmesa ); +static void flush_last_swtcl_prim(GLcontext *ctx); /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */ /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */ @@ -87,7 +87,7 @@ static GLuint radeon_cp_vc_frmts[3][2] = static void radeonSetVertexFormat( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; DECLARE_RENDERINPUTS(index_bitset); @@ -204,7 +204,7 @@ static void radeonSetVertexFormat( GLcontext *ctx ) } } - if (!RENDERINPUTS_EQUAL( rmesa->tnl_index_bitset, index_bitset ) || + if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) || fmt_0 != rmesa->swtcl.vertex_format) { RADEON_NEWPRIM(rmesa); rmesa->swtcl.vertex_format = fmt_0; @@ -214,7 +214,7 @@ static void radeonSetVertexFormat( GLcontext *ctx ) rmesa->swtcl.vertex_attr_count, NULL, 0 ); rmesa->swtcl.vertex_size /= 4; - RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset ); + RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset ); if (RADEON_DEBUG & DEBUG_VERTS) fprintf( stderr, "%s: vertex_size= %d floats\n", __FUNCTION__, rmesa->swtcl.vertex_size); @@ -224,13 +224,13 @@ static void radeonSetVertexFormat( GLcontext *ctx ) static void radeonRenderStart( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); radeonSetVertexFormat( ctx ); if (rmesa->dma.flush != 0 && rmesa->dma.flush != flush_last_swtcl_prim) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( ctx ); } @@ -241,7 +241,7 @@ static void radeonRenderStart( GLcontext *ctx ) */ void radeonChooseVertexState( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; @@ -254,7 +254,7 @@ void radeonChooseVertexState( GLcontext *ctx ) * rasterization fallback. As this function will be called again when we * leave a rasterization fallback, we can just skip it for now. */ - if (rmesa->Fallback != 0) + if (rmesa->radeon.Fallback != 0) return; /* HW perspective divide is a win, but tiny vertex formats are a @@ -284,8 +284,9 @@ void radeonChooseVertexState( GLcontext *ctx ) /* Flush vertices in the current dma region. */ -static void flush_last_swtcl_prim( radeonContextPtr rmesa ) +static void flush_last_swtcl_prim(GLcontext *ctx) { + r100ContextPtr rmesa = R100_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -293,7 +294,7 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa ) if (rmesa->dma.current.buf) { struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset + + GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset + current->buf->buf->idx * RADEON_BUFFER_SIZE + current->start); @@ -326,7 +327,7 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa ) /* Alloc space in the current dma region. */ static INLINE void * -radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) +radeonAllocDmaLowVerts( r100ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; @@ -334,7 +335,7 @@ radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) radeonRefillCurrentDmaRegion( rmesa ); if (!rmesa->dma.flush) { - rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->dma.flush = flush_last_swtcl_prim; } @@ -387,14 +388,14 @@ static const GLuint hw_prim[GL_POLYGON+1] = { }; static INLINE void -radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim ) +radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim ) { RADEON_NEWPRIM( rmesa ); rmesa->swtcl.hw_primitive = hw_prim[prim]; assert(rmesa->dma.current.ptr == rmesa->dma.current.start); } -#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx) +#define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx) #define INIT( prim ) radeonDmaPrimitive( rmesa, prim ) #define FLUSH() RADEON_NEWPRIM( rmesa ) #define GET_CURRENT_VB_MAX_VERTS() \ @@ -418,7 +419,7 @@ radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim ) static GLboolean radeon_run_render( GLcontext *ctx, struct tnl_pipeline_stage *stage ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; tnl_render_func *tab = TAG(render_tab_verts); @@ -496,12 +497,12 @@ static void radeonResetLineStipple( GLcontext *ctx ); #undef LOCAL_VARS #undef ALLOC_VERTS -#define CTX_ARG radeonContextPtr rmesa +#define CTX_ARG r100ContextPtr rmesa #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 ) #undef LOCAL_VARS #define LOCAL_VARS \ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ + r100ContextPtr rmesa = R100_CONTEXT(ctx); \ const char *radeonverts = (char *)rmesa->swtcl.verts; #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int))) #define VERTEX radeonVertex @@ -606,7 +607,7 @@ do { \ #undef INIT #define LOCAL_VARS(n) \ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ + r100ContextPtr rmesa = R100_CONTEXT(ctx); \ GLuint color[n], spec[n]; \ GLuint coloroffset = rmesa->swtcl.coloroffset; \ GLuint specoffset = rmesa->swtcl.specoffset; \ @@ -673,7 +674,7 @@ static void init_rast_tab( void ) } while (0) #undef LOCAL_VARS #define LOCAL_VARS \ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ + r100ContextPtr rmesa = R100_CONTEXT(ctx); \ const GLuint vertsize = rmesa->swtcl.vertex_size; \ const char *radeonverts = (char *)rmesa->swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ @@ -700,11 +701,11 @@ static void init_rast_tab( void ) void radeonChooseRenderState( GLcontext *ctx ) { TNLcontext *tnl = TNL_CONTEXT(ctx); - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint index = 0; GLuint flags = ctx->_TriangleCaps; - if (!rmesa->TclFallback || rmesa->Fallback) + if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) return; if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT; @@ -739,7 +740,7 @@ void radeonChooseRenderState( GLcontext *ctx ) static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); if (rmesa->swtcl.hw_primitive != hwprim) { RADEON_NEWPRIM( rmesa ); @@ -749,7 +750,7 @@ static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim ) static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); rmesa->swtcl.render_primitive = prim; if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) radeonRasterPrimitive( ctx, reduced_hw_prim[prim] ); @@ -761,7 +762,7 @@ static void radeonRenderFinish( GLcontext *ctx ) static void radeonResetLineStipple( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, lin ); } @@ -795,12 +796,12 @@ static const char *getFallbackString(GLuint bit) void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); - GLuint oldfallback = rmesa->Fallback; + GLuint oldfallback = rmesa->radeon.Fallback; if (mode) { - rmesa->Fallback |= bit; + rmesa->radeon.Fallback |= bit; if (oldfallback == 0) { RADEON_FIREVERTICES( rmesa ); TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE ); @@ -813,7 +814,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) } } else { - rmesa->Fallback &= ~bit; + rmesa->radeon.Fallback &= ~bit; if (oldfallback == bit) { _swrast_flush( ctx ); tnl->Driver.Render.Start = radeonRenderStart; @@ -826,14 +827,14 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple; TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE ); - if (rmesa->TclFallback) { - /* These are already done if rmesa->TclFallback goes to + if (rmesa->radeon.TclFallback) { + /* These are already done if rmesa->radeon.TclFallback goes to * zero above. But not if it doesn't (RADEON_NO_TCL for * example?) */ _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); - RENDERINPUTS_ZERO( rmesa->tnl_index_bitset ); + RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset ); radeonChooseVertexState( ctx ); radeonChooseRenderState( ctx ); } @@ -853,7 +854,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) void radeonInitSwtcl( GLcontext *ctx ) { TNLcontext *tnl = TNL_CONTEXT(ctx); - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); static int firsttime = 1; if (firsttime) { @@ -881,7 +882,7 @@ void radeonInitSwtcl( GLcontext *ctx ) void radeonDestroySwtcl( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); if (rmesa->swtcl.indexed_verts.buf) radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 779e9ae5df0..b59685790c1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -104,7 +104,7 @@ static GLboolean discrete_prim[0x10] = { }; -#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx) +#define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx) #define ELT_TYPE GLushort #define ELT_INIT(prim, hw_prim) \ @@ -143,10 +143,10 @@ static GLboolean discrete_prim[0x10] = { #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr ) -static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr ) +static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) { if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr)); @@ -174,7 +174,7 @@ static void radeonEmitPrim( GLcontext *ctx, GLuint start, GLuint count) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); radeonTclPrimitive( ctx, prim, hwprim ); radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + @@ -254,7 +254,7 @@ void radeonTclPrimitive( GLcontext *ctx, GLenum prim, int hw_prim ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint se_cntl; GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE; @@ -371,7 +371,7 @@ radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord ) static GLboolean radeon_run_tcl_render( GLcontext *ctx, struct tnl_pipeline_stage *stage ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0; @@ -379,7 +379,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, /* TODO: separate this from the swtnl pipeline */ - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) return GL_TRUE; /* fallback to software t&l */ if (VB->Count == 0) @@ -461,7 +461,7 @@ const struct tnl_pipeline_stage _radeon_tcl_stage = static void transition_to_swtnl( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); GLuint se_cntl; @@ -490,7 +490,7 @@ static void transition_to_swtnl( GLcontext *ctx ) static void transition_to_hwtnl( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; @@ -510,7 +510,7 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial; if ( rmesa->dma.flush ) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); rmesa->dma.flush = NULL; rmesa->swtcl.vertex_format = 0; @@ -550,11 +550,11 @@ static char *getFallbackString(GLuint bit) void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLuint oldfallback = rmesa->TclFallback; + r100ContextPtr rmesa = R100_CONTEXT(ctx); + GLuint oldfallback = rmesa->radeon.TclFallback; if (mode) { - rmesa->TclFallback |= bit; + rmesa->radeon.TclFallback |= bit; if (oldfallback == 0) { if (RADEON_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "Radeon begin tcl fallback %s\n", @@ -563,7 +563,7 @@ void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) } } else { - rmesa->TclFallback &= ~bit; + rmesa->radeon.TclFallback &= ~bit; if (oldfallback == bit) { if (RADEON_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "Radeon end tcl fallback %s\n", diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 35774ab8c69..e4829aaeaba 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -287,11 +287,11 @@ static const struct gl_texture_format * radeonChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); const GLboolean do32bpt = - ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); + ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); const GLboolean force16bpt = - ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); + ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); (void) format; switch ( internalFormat ) { @@ -670,7 +670,7 @@ static void radeonCompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint static void radeonTexEnv( GLcontext *ctx, GLenum target, GLenum pname, const GLfloat *param ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint unit = ctx->Texture.CurrentUnit; struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; @@ -701,7 +701,7 @@ static void radeonTexEnv( GLcontext *ctx, GLenum target, * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping * [0.0,4.0] to [0,127]. */ - min = driQueryOptionb (&rmesa->optionCache, "no_neg_lod_bias") ? + min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? 0.0 : -1.0; bias = CLAMP( *param, min, 4.0 ); if ( bias == 0 ) { @@ -797,7 +797,7 @@ static void radeonBindTexture( GLcontext *ctx, GLenum target, static void radeonDeleteTexture( GLcontext *ctx, struct gl_texture_object *texObj ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); driTextureObject * t = (driTextureObject *) texObj->DriverData; if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { @@ -832,7 +832,7 @@ static void radeonTexGen( GLcontext *ctx, GLenum pname, const GLfloat *params ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint unit = ctx->Texture.CurrentUnit; rmesa->recheck_texgen[unit] = GL_TRUE; } @@ -846,12 +846,12 @@ static void radeonTexGen( GLcontext *ctx, static struct gl_texture_object * radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_object *obj; obj = _mesa_new_texture_object(ctx, name, target); if (!obj) return NULL; - obj->MaxAnisotropy = rmesa->initialMaxAnisotropy; + obj->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; radeonAllocTexObj( obj ); return obj; } diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h index 80008808289..8c2f9be241d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h @@ -43,10 +43,10 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, extern void radeonUpdateTextureState( GLcontext *ctx ); -extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, +extern int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face ); -extern void radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t ); +extern void radeonDestroyTexObj( r100ContextPtr rmesa, radeonTexObjPtr t ); extern void radeonInitTextureFuncs( struct dd_function_table *functions ); diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c index 786373d3004..77810ef7e19 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texmem.c +++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c @@ -53,7 +53,7 @@ SOFTWARE. * include NULLing out hardware state that points to the texture. */ void -radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t ) +radeonDestroyTexObj( r100ContextPtr rmesa, radeonTexObjPtr t ) { if ( RADEON_DEBUG & DEBUG_TEXTURE ) { fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj ); @@ -63,7 +63,7 @@ radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t ) unsigned i; - for ( i = 0 ; i < rmesa->glCtx->Const.MaxTextureUnits ; i++ ) { + for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { if ( t == rmesa->state.texture.unit[i].texobj ) { rmesa->state.texture.unit[i].texobj = NULL; } @@ -77,7 +77,7 @@ radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t ) */ -static void radeonUploadRectSubImage( radeonContextPtr rmesa, +static void radeonUploadRectSubImage( r100ContextPtr rmesa, radeonTexObjPtr t, struct gl_texture_image *texImage, GLint x, GLint y, @@ -172,7 +172,7 @@ static void radeonUploadRectSubImage( radeonContextPtr rmesa, * Upload the texture image associated with texture \a t at the specified * level at the address relative to \a start. */ -static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t, +static void uploadSubImage( r100ContextPtr rmesa, radeonTexObjPtr t, GLint hwlevel, GLint x, GLint y, GLint width, GLint height, GLuint face ) @@ -300,7 +300,7 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t, LOCK_HARDWARE( rmesa ); do { - ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE, + ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE, &tex, sizeof(drm_radeon_texture_t) ); } while ( ret == -EAGAIN ); @@ -329,7 +329,7 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t, * \param face Cube map face to be uploaded. Zero for non-cube maps. */ -int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint face ) +int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) { int numLevels; @@ -338,7 +338,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__, - (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize, + (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize, t->base.firstLevel, t->base.lastLevel ); } @@ -346,7 +346,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac if (RADEON_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - radeonFinish( rmesa->glCtx ); + radeonFinish( rmesa->radeon.glCtx ); } LOCK_HARDWARE( rmesa ); @@ -354,7 +354,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac if ( t->base.memBlock == NULL ) { int heap; - heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps, + heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, (driTextureObject *) t ); if ( heap == -1 ) { UNLOCK_HARDWARE( rmesa ); @@ -362,7 +362,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac } /* Set the base offset of the texture image */ - t->bufAddr = rmesa->radeonScreen->texOffset[heap] + t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] + t->base.memBlock->ofs; t->pp_txoffset = t->bufAddr; @@ -397,7 +397,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac if (RADEON_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - radeonFinish( rmesa->glCtx ); + radeonFinish( rmesa->radeon.glCtx ); } return 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 54674a7fa2a..911a0b3a0c5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -122,7 +122,7 @@ tx_table[] = * \param tObj GL texture object whose images are to be posted to * hardware state. */ -static void radeonSetTexImages( radeonContextPtr rmesa, +static void radeonSetTexImages( r100ContextPtr rmesa, struct gl_texture_object *tObj ) { radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData; @@ -503,7 +503,7 @@ do { \ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; GLuint color_combine, alpha_combine; const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO @@ -846,9 +846,9 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit ) void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch) { - radeonContextPtr rmesa = pDRICtx->driverPrivate; + r100ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = - _mesa_lookup_texture(rmesa->glCtx, texname); + _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t; if (tObj == NULL) @@ -901,7 +901,7 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, RADEON_TXFORMAT_NON_POWER2) -static void import_tex_obj_state( radeonContextPtr rmesa, +static void import_tex_obj_state( r100ContextPtr rmesa, int unit, radeonTexObjPtr texobj ) { @@ -958,7 +958,7 @@ static void import_tex_obj_state( radeonContextPtr rmesa, -static void set_texgen_matrix( radeonContextPtr rmesa, +static void set_texgen_matrix( r100ContextPtr rmesa, GLuint unit, const GLfloat *s_plane, const GLfloat *t_plane, @@ -986,14 +986,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa, rmesa->TexGenMatrix[unit].m[15] = q_plane[3]; rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit; - rmesa->NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } /* Returns GL_FALSE if fallback required. */ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4; GLuint tmp = rmesa->TexGenEnabled; @@ -1094,7 +1094,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) } if (tmp != rmesa->TexGenEnabled) { - rmesa->NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } return GL_TRUE; @@ -1103,7 +1103,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) static void disable_tex( GLcontext *ctx, int unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); if (rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | RADEON_Q_BIT(unit)); - if (rmesa->TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = GL_TRUE; } @@ -1151,7 +1151,7 @@ static void disable_tex( GLcontext *ctx, int unit ) if (tmp != rmesa->TexGenEnabled) { rmesa->recheck_texgen[unit] = GL_TRUE; - rmesa->NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } } } @@ -1159,7 +1159,7 @@ static void disable_tex( GLcontext *ctx, int unit ) static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; @@ -1186,7 +1186,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) static GLboolean enable_tex_cube( GLcontext *ctx, int unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; @@ -1228,7 +1228,7 @@ static GLboolean enable_tex_cube( GLcontext *ctx, int unit ) static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; @@ -1257,7 +1257,7 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) static GLboolean update_tex_common( GLcontext *ctx, int unit ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; @@ -1309,14 +1309,14 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit ) if (t->dirty_state & (1<NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } if (rmesa->recheck_texgen[unit]) { GLboolean fallback = !radeon_validate_texgen( ctx, unit ); TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = 0; - rmesa->NewGLState |= _NEW_TEXTURE_MATRIX; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } format = tObj->Image[0][tObj->BaseLevel]->_BaseFormat; @@ -1362,7 +1362,7 @@ static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) void radeonUpdateTextureState( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + r100ContextPtr rmesa = R100_CONTEXT(ctx); GLboolean ok; ok = (radeonUpdateTextureUnit( ctx, 0 ) && @@ -1371,6 +1371,6 @@ void radeonUpdateTextureState( GLcontext *ctx ) FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok ); - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) radeonChooseVertexState( ctx ); } -- cgit v1.2.3 From d29e96bf33e91d071770b86d87ffc4ef4dfc2f70 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 12:04:00 +1000 Subject: radeon/r200/r300: attempt to move lock to common code --- src/mesa/drivers/dri/r200/Makefile | 9 +- src/mesa/drivers/dri/r200/r200_context.c | 35 ++++- src/mesa/drivers/dri/r200/r200_context.h | 5 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 88 +++++------ src/mesa/drivers/dri/r200/r200_lock.h | 68 +-------- src/mesa/drivers/dri/r200/r200_pixel.c | 12 +- src/mesa/drivers/dri/r200/r200_span.c | 4 +- src/mesa/drivers/dri/r200/r200_state.c | 157 ++------------------ src/mesa/drivers/dri/r200/r200_state_init.c | 38 ++--- src/mesa/drivers/dri/r200/r200_swtcl.c | 4 +- src/mesa/drivers/dri/r200/r200_texmem.c | 10 +- src/mesa/drivers/dri/r300/Makefile | 9 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 2 +- src/mesa/drivers/dri/r300/r300_context.c | 18 +++ src/mesa/drivers/dri/r300/r300_context.h | 11 -- src/mesa/drivers/dri/r300/r300_ioctl.c | 2 +- src/mesa/drivers/dri/r300/r300_state.c | 16 +- src/mesa/drivers/dri/r300/radeon_context.c | 2 +- src/mesa/drivers/dri/r300/radeon_context.h | 1 + src/mesa/drivers/dri/r300/radeon_state.c | 129 ---------------- src/mesa/drivers/dri/r300/radeon_state.h | 4 - src/mesa/drivers/dri/radeon/Makefile | 5 +- src/mesa/drivers/dri/radeon/common_context.h | 11 +- src/mesa/drivers/dri/radeon/common_lock.c | 138 +++++++++++++++++ src/mesa/drivers/dri/radeon/common_lock.h | 111 ++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.c | 187 ++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 8 + src/mesa/drivers/dri/radeon/radeon_context.c | 37 ++++- src/mesa/drivers/dri/radeon/radeon_context.h | 9 +- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 86 +++++------ src/mesa/drivers/dri/radeon/radeon_lock.h | 67 +-------- src/mesa/drivers/dri/radeon/radeon_span.c | 6 +- src/mesa/drivers/dri/radeon/radeon_state.c | 156 ++------------------ src/mesa/drivers/dri/radeon/radeon_state.h | 2 - src/mesa/drivers/dri/radeon/radeon_state_init.c | 22 +-- src/mesa/drivers/dri/radeon/radeon_texmem.c | 10 +- 36 files changed, 738 insertions(+), 741 deletions(-) create mode 100644 src/mesa/drivers/dri/radeon/common_lock.c create mode 100644 src/mesa/drivers/dri/radeon/common_lock.h create mode 100644 src/mesa/drivers/dri/radeon/common_misc.c create mode 100644 src/mesa/drivers/dri/radeon/common_misc.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index f4c173085b1..34aa74735b8 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -13,7 +13,6 @@ endif DRIVER_SOURCES = r200_context.c \ r200_ioctl.c \ - r200_lock.c \ r200_state.c \ r200_state_init.c \ r200_cmdbuf.c \ @@ -29,6 +28,8 @@ DRIVER_SOURCES = r200_context.c \ r200_fragshader.c \ r200_vertprog.c \ radeon_screen.c \ + common_lock.c \ + common_misc.c \ $(EGL_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -51,7 +52,11 @@ COMMON_SYMLINKS = \ radeon_screen.h \ radeon_bo_legacy.h \ radeon_buffer.h \ - common_context.h + common_context.h \ + common_lock.c \ + common_lock.h \ + common_misc.h \ + common_misc.c ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 9e89c1d7433..9f882fe6155 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -242,6 +242,32 @@ static const struct dri_debug_control debug_control[] = { NULL, 0 } }; +static void r200_get_lock(radeonContextPtr radeon) +{ + r200ContextPtr rmesa = (r200ContextPtr)radeon; + drm_radeon_sarea_t *sarea = radeon->sarea; + int i; + + R200_STATECHANGE( rmesa, ctx ); + if (rmesa->radeon.sarea->tiling_enabled) { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; + } + else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE; + + if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) { + sarea->ctx_owner = rmesa->radeon.dri.hwContext; + } + + for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { + DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] ); + } +} + +static void r200_init_vtbl(radeonContextPtr radeon) +{ + radeon->vtbl.get_lock = r200_get_lock; + radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; +} /* Create the device specific rendering context. */ @@ -265,7 +291,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) ); if ( !rmesa ) return GL_FALSE; - + + r200_init_vtbl(&rmesa->radeon); /* init exp fog table data */ r200InitStaticFogData(); @@ -568,9 +595,9 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200FlushCmdBuf( rmesa, __FUNCTION__ ); } - if (rmesa->state.scissor.pClipRects) { - FREE(rmesa->state.scissor.pClipRects); - rmesa->state.scissor.pClipRects = NULL; + if (rmesa->radeon.state.scissor.pClipRects) { + FREE(rmesa->radeon.state.scissor.pClipRects); + rmesa->radeon.state.scissor.pClipRects = NULL; } if ( release_texture_heaps ) { diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 9ee6c15bf4e..94f9b86d2f2 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -55,6 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_screen.h" #include "common_context.h" +#include "common_misc.h" struct r200_context; typedef struct r200_context r200ContextRec; @@ -519,10 +520,6 @@ struct r200_hw_state { struct r200_state { /* Derived state for internal purposes: */ - struct radeon_colorbuffer_state color; - struct radeon_depthbuffer_state depth; - struct radeon_scissor_state scissor; - struct radeon_stencilbuffer_state stencil; struct radeon_stipple_state stipple; struct r200_texture_state texture; GLuint envneeded; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 16776abd027..09baffb5440 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -108,10 +108,10 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) if (R200_DEBUG & DEBUG_SANITY) { - if (rmesa->state.scissor.enabled) + if (rmesa->radeon.state.scissor.enabled) ret = r200SanityCmdBuffer( rmesa, - rmesa->state.scissor.numClipRects, - rmesa->state.scissor.pClipRects); + rmesa->radeon.state.scissor.numClipRects, + rmesa->radeon.state.scissor.pClipRects); else ret = r200SanityCmdBuffer( rmesa, rmesa->radeon.numClipRects, @@ -135,9 +135,9 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) cmd.bufsz = rmesa->store.cmd_used; cmd.buf = rmesa->store.cmd_buf; - if (rmesa->state.scissor.enabled) { - cmd.nbox = rmesa->state.scissor.numClipRects; - cmd.boxes = (drm_clip_rect_t *)rmesa->state.scissor.pClipRects; + if (rmesa->radeon.state.scissor.enabled) { + cmd.nbox = rmesa->radeon.state.scissor.numClipRects; + cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.state.scissor.pClipRects; } else { cmd.nbox = rmesa->radeon.numClipRects; cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects; @@ -174,11 +174,11 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) { int ret; - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); ret = r200FlushCmdBufLocked( rmesa, caller ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (ret) { fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret); @@ -225,7 +225,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) dma.request_sizes = &size; dma.granted_count = 0; - LOCK_HARDWARE(rmesa); /* no need to validate */ + LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ while (1) { ret = drmDMA( fd, &dma ); @@ -237,13 +237,13 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) } if (rmesa->radeon.do_usleeps) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } } - UNLOCK_HARDWARE(rmesa); + UNLOCK_HARDWARE(&rmesa->radeon); if (R200_DEBUG & DEBUG_DMA) fprintf(stderr, "Allocated buffer %d\n", index); @@ -393,9 +393,9 @@ static void r200WaitForFrameCompletion( r200ContextPtr rmesa ) ; } else { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); r200WaitIrq( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } rmesa->radeon.irqsEmitted = 10; } @@ -407,10 +407,10 @@ static void r200WaitForFrameCompletion( r200ContextPtr rmesa ) } else { while (r200GetLastFrame (rmesa) < sarea->last_frame) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (rmesa->radeon.do_usleeps) DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } } } @@ -440,7 +440,7 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, R200_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* Throttle the frame rate -- only allow one pending swap buffers @@ -449,9 +449,9 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, r200WaitForFrameCompletion( rmesa ); if (!rect) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); driWaitForVBlank( dPriv, & missed_target ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } nbox = dPriv->numClipRects; /* must be in locked region */ @@ -493,12 +493,12 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv, if ( ret ) { fprintf( stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); exit( 1 ); } } - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (!rect) { rmesa->hw.all_dirty = GL_TRUE; @@ -535,10 +535,10 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) } R200_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); if (!dPriv->numClipRects) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); usleep( 10000 ); /* throttle invisible client 10ms */ return; } @@ -556,17 +556,17 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv ) * request at a time. */ r200WaitForFrameCompletion( rmesa ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); driWaitForVBlank( dPriv, & missed_target ); if ( missed_target ) { rmesa->radeon.swap_missed_count++; (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust ); } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if ( ret ) { fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); @@ -622,8 +622,8 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } { - LOCK_HARDWARE( rmesa ); - UNLOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); + UNLOCK_HARDWARE( &rmesa->radeon ); if ( dPriv->numClipRects == 0 ) return; } @@ -647,7 +647,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) mask &= ~BUFFER_BIT_DEPTH; } - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) { + if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { flags |= RADEON_STENCIL; mask &= ~BUFFER_BIT_STENCIL; } @@ -665,14 +665,14 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) flags |= RADEON_USE_COMP_ZBUF; /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->state.stencil.hwBuffer) || + if (!(rmesa->radeon.state.stencil.hwBuffer) || ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && - ((rmesa->state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { + ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { flags |= RADEON_CLEAR_FASTZ; } } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* compute region after locking: */ cx = ctx->DrawBuffer->_Xmin; @@ -708,9 +708,9 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } if (rmesa->radeon.do_usleeps) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } } @@ -758,10 +758,10 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) rmesa->radeon.sarea->nbox = n; clear.flags = flags; - clear.clear_color = rmesa->state.color.clear; - clear.clear_depth = rmesa->state.depth.clear; /* needed for hyperz */ + clear.clear_color = rmesa->radeon.state.color.clear; + clear.clear_depth = rmesa->radeon.state.depth.clear; /* needed for hyperz */ clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; - clear.depth_mask = rmesa->state.stencil.clear; + clear.depth_mask = rmesa->radeon.state.stencil.clear; clear.depth_boxes = depth_boxes; n--; @@ -779,13 +779,13 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) if ( ret ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret ); exit( 1 ); } } - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); rmesa->hw.all_dirty = GL_TRUE; } @@ -802,7 +802,7 @@ void r200WaitForIdleLocked( r200ContextPtr rmesa ) } while (ret && ++i < 100); if ( ret < 0 ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); fprintf( stderr, "Error: R200 timed out... exiting\n" ); exit( -1 ); } @@ -811,9 +811,9 @@ void r200WaitForIdleLocked( r200ContextPtr rmesa ) static void r200WaitForIdle( r200ContextPtr rmesa ) { - LOCK_HARDWARE(rmesa); + LOCK_HARDWARE(&rmesa->radeon); r200WaitForIdleLocked( rmesa ); - UNLOCK_HARDWARE(rmesa); + UNLOCK_HARDWARE(&rmesa->radeon); } @@ -842,9 +842,9 @@ void r200Finish( GLcontext *ctx ) r200Flush( ctx ); if (rmesa->radeon.do_irqs) { - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); r200EmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); r200WaitIrq( rmesa ); } else diff --git a/src/mesa/drivers/dri/r200/r200_lock.h b/src/mesa/drivers/dri/r200/r200_lock.h index f1cb624d8fe..29cad5b226b 100644 --- a/src/mesa/drivers/dri/r200/r200_lock.h +++ b/src/mesa/drivers/dri/r200/r200_lock.h @@ -35,72 +35,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __R200_LOCK_H__ #define __R200_LOCK_H__ -extern void r200GetLock( r200ContextPtr rmesa, GLuint flags ); - -/* Turn DEBUG_LOCKING on to find locking conflicts. - */ -#define DEBUG_LOCKING 0 - -#if DEBUG_LOCKING -extern char *prevLockFile; -extern int prevLockLine; - -#define DEBUG_LOCK() \ - do { \ - prevLockFile = (__FILE__); \ - prevLockLine = (__LINE__); \ - } while (0) - -#define DEBUG_RESET() \ - do { \ - prevLockFile = 0; \ - prevLockLine = 0; \ - } while (0) - -#define DEBUG_CHECK_LOCK() \ - do { \ - if ( prevLockFile ) { \ - fprintf( stderr, \ - "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ - prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ - exit( 1 ); \ - } \ - } while (0) - -#else - -#define DEBUG_LOCK() -#define DEBUG_RESET() -#define DEBUG_CHECK_LOCK() - -#endif - -/* - * !!! We may want to separate locks from locks with validation. This - * could be used to improve performance for those things commands that - * do not do any drawing !!! - */ - - -/* Lock the hardware and validate our state. - */ -#define LOCK_HARDWARE( rmesa ) \ - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ - DRM_CAS( rmesa->radeon.dri.hwLock, rmesa->radeon.dri.hwContext, \ - (DRM_LOCK_HELD | rmesa->radeon.dri.hwContext), __ret ); \ - if ( __ret ) \ - r200GetLock( rmesa, 0 ); \ - DEBUG_LOCK(); \ - } while (0) - -#define UNLOCK_HARDWARE( rmesa ) \ - do { \ - DRM_UNLOCK( rmesa->radeon.dri.fd, \ - rmesa->radeon.dri.hwLock, \ - rmesa->radeon.dri.hwContext ); \ - DEBUG_RESET(); \ - } while (0) +#include "common_lock.h" #endif /* __R200_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 1b28a83d70a..60d25825e92 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -197,14 +197,14 @@ r200TryReadPixels( GLcontext *ctx, * a full command buffer expects to be called unlocked. As a * workaround, immediately flush the buffer on aquiring the lock. */ - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height, &size)) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s totally clipped -- nothing to do\n", __FUNCTION__); @@ -259,7 +259,7 @@ r200TryReadPixels( GLcontext *ctx, r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); } - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); r200Finish( ctx ); /* required by GL */ @@ -318,7 +318,7 @@ static void do_draw_pix( GLcontext *ctx, } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); @@ -328,7 +328,7 @@ static void do_draw_pix( GLcontext *ctx, if (!clip_pixelrect(ctx, ctx->DrawBuffer, &x, &y, &width, &height, &size)) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); return; } @@ -365,7 +365,7 @@ static void do_draw_pix( GLcontext *ctx, r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); r200WaitForIdleLocked( rmesa ); /* required by GL */ - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); } diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index 361f0fde266..dfe587401d9 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -242,7 +242,7 @@ static void r200SpanRenderStart( GLcontext *ctx ) r200ContextPtr rmesa = R200_CONTEXT( ctx ); R200_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); r200WaitForIdleLocked( rmesa ); /* Read & rewrite the first pixel in the frame buffer. This should @@ -269,7 +269,7 @@ static void r200SpanRenderFinish( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); _swrast_flush( ctx ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); } void r200InitSpanFuncs( GLcontext *ctx ) diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 4cd87bd1b9d..67357fadfd8 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -383,10 +383,10 @@ static void r200ClearDepth( GLcontext *ctx, GLclampd d ) switch ( format ) { case R200_DEPTH_FORMAT_16BIT_INT_Z: - rmesa->state.depth.clear = d * 0x0000ffff; + rmesa->radeon.state.depth.clear = d * 0x0000ffff; break; case R200_DEPTH_FORMAT_24BIT_INT_Z: - rmesa->state.depth.clear = d * 0x00ffffff; + rmesa->radeon.state.depth.clear = d * 0x00ffffff; break; } } @@ -527,83 +527,6 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) */ -static GLboolean intersect_rect( drm_clip_rect_t *out, - drm_clip_rect_t *a, - drm_clip_rect_t *b ) -{ - *out = *a; - if ( b->x1 > out->x1 ) out->x1 = b->x1; - if ( b->y1 > out->y1 ) out->y1 = b->y1; - if ( b->x2 < out->x2 ) out->x2 = b->x2; - if ( b->y2 < out->y2 ) out->y2 = b->y2; - if ( out->x1 >= out->x2 ) return GL_FALSE; - if ( out->y1 >= out->y2 ) return GL_FALSE; - return GL_TRUE; -} - - -void r200RecalcScissorRects( r200ContextPtr rmesa ) -{ - drm_clip_rect_t *out; - int i; - - /* Grow cliprect store? - */ - if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { - while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { - rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */ - rmesa->state.scissor.numAllocedClipRects *= 2; - } - - if (rmesa->state.scissor.pClipRects) - FREE(rmesa->state.scissor.pClipRects); - - rmesa->state.scissor.pClipRects = - MALLOC( rmesa->state.scissor.numAllocedClipRects * - sizeof(drm_clip_rect_t) ); - - if ( rmesa->state.scissor.pClipRects == NULL ) { - rmesa->state.scissor.numAllocedClipRects = 0; - return; - } - } - - out = rmesa->state.scissor.pClipRects; - rmesa->state.scissor.numClipRects = 0; - - for ( i = 0 ; i < rmesa->radeon.numClipRects ; i++ ) { - if ( intersect_rect( out, - &rmesa->radeon.pClipRects[i], - &rmesa->state.scissor.rect ) ) { - rmesa->state.scissor.numClipRects++; - out++; - } - } -} - - -static void r200UpdateScissor( GLcontext *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if ( rmesa->radeon.dri.drawable ) { - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - - int x = ctx->Scissor.X; - int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; - int w = ctx->Scissor.X + ctx->Scissor.Width - 1; - int h = dPriv->h - ctx->Scissor.Y - 1; - - rmesa->state.scissor.rect.x1 = x + dPriv->x; - rmesa->state.scissor.rect.y1 = y + dPriv->y; - rmesa->state.scissor.rect.x2 = w + dPriv->x + 1; - rmesa->state.scissor.rect.y2 = h + dPriv->y + 1; - - r200RecalcScissorRects( rmesa ); - } -} - - static void r200Scissor( GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h ) { @@ -611,7 +534,7 @@ static void r200Scissor( GLcontext *ctx, if ( ctx->Scissor.Enabled ) { R200_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */ - r200UpdateScissor( ctx ); + radeonUpdateScissor( ctx ); } } @@ -834,7 +757,7 @@ static void r200PolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - float_ui32_type constant = { units * rmesa->state.depth.scale }; + float_ui32_type constant = { units * rmesa->radeon.state.depth.scale }; float_ui32_type factoru = { factor }; /* factor *= 2; */ @@ -862,14 +785,14 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ R200_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* FIXME: Use window x,y offsets into stipple RAM. */ stipple.mask = rmesa->state.stipple.mask; drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, &stipple, sizeof(stipple) ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); } static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) @@ -1675,7 +1598,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - rmesa->state.stencil.clear = + rmesa->radeon.state.stencil.clear = ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << R200_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT)); @@ -1709,8 +1632,8 @@ void r200UpdateWindow( GLcontext *ctx ) float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; float_ui32_type sy = { - v[MAT_SY] }; float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; - float_ui32_type sz = { v[MAT_SZ] * rmesa->state.depth.scale }; - float_ui32_type tz = { v[MAT_TZ] * rmesa->state.depth.scale }; + float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; + float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; R200_FIREVERTICES( rmesa ); R200_STATECHANGE( rmesa, vpt ); @@ -1805,7 +1728,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); - rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, + rmesa->radeon.state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, color[0], color[1], color[2], color[3] ); } @@ -1849,56 +1772,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) } -/* - * Set up the cliprects for either front or back-buffer drawing. - */ -void r200SetCliprects( r200ContextPtr rmesa ) -{ - __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable; - GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate; - GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate; - - if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BIT_BACK_LEFT) { - /* Can't ignore 2d windows if we are page flipping. - */ - if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) { - rmesa->radeon.numClipRects = drawable->numClipRects; - rmesa->radeon.pClipRects = drawable->pClipRects; - } - else { - rmesa->radeon.numClipRects = drawable->numBackClipRects; - rmesa->radeon.pClipRects = drawable->pBackClipRects; - } - } - else { - /* front buffer (or none, or multiple buffers) */ - rmesa->radeon.numClipRects = drawable->numClipRects; - rmesa->radeon.pClipRects = drawable->pClipRects; - } - - if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb, - drawable->w, drawable->h); - draw_fb->Initialized = GL_TRUE; - } - - if (drawable != readable) { - if ((read_fb->Width != readable->w) || - (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb, - readable->w, readable->h); - read_fb->Initialized = GL_TRUE; - } - } - - if (rmesa->state.scissor.enabled) - r200RecalcScissorRects( rmesa ); - - rmesa->radeon.lastStamp = drawable->lastStamp; -} - - static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -1925,7 +1798,7 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) return; } - r200SetCliprects( rmesa ); + radeonSetCliprects( &rmesa->radeon ); /* We'll set the drawing engine's offset/pitch parameters later * when we update other state. @@ -2013,10 +1886,10 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) R200_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable; } else { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; } break; @@ -2182,12 +2055,12 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_SCISSOR_TEST: R200_FIREVERTICES( rmesa ); - rmesa->state.scissor.enabled = state; + rmesa->radeon.state.scissor.enabled = state; r200UpdateScissor( ctx ); break; case GL_STENCIL_TEST: - if ( rmesa->state.stencil.hwBuffer ) { + if ( rmesa->radeon.state.stencil.hwBuffer ) { R200_STATECHANGE( rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f03a47ef464..775ccb74825 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -203,20 +203,20 @@ void r200InitState( r200ContextPtr rmesa ) exit( -1 ); } - rmesa->state.color.clear = 0x00000000; + rmesa->radeon.state.color.clear = 0x00000000; switch ( ctx->Visual.depthBits ) { case 16: - rmesa->state.depth.clear = 0x0000ffff; - rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; + rmesa->radeon.state.depth.clear = 0x0000ffff; + rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z; - rmesa->state.stencil.clear = 0x00000000; + rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: - rmesa->state.depth.clear = 0x00ffffff; - rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; + rmesa->radeon.state.depth.clear = 0x00ffffff; + rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; - rmesa->state.stencil.clear = 0xffff0000; + rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: fprintf( stderr, "Error: Unsupported depth %d... exiting\n", @@ -225,7 +225,7 @@ void r200InitState( r200ContextPtr rmesa ) } /* Only have hw stencil when depth buffer is 24 bits deep */ - rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && + rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && ctx->Visual.depthBits == 24 ); rmesa->radeon.Fallback = 0; @@ -239,15 +239,15 @@ void r200InitState( r200ContextPtr rmesa ) } #if 000 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset; - rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch; + rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset; + rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch; } else { - rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset; - rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch; + rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset; + rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch; } - rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; - rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch; + rmesa->state.pixel.readOffset = rmesa->radeon.state.color.drawOffset; + rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch; #endif rmesa->hw.max_state_size = 0; @@ -617,21 +617,21 @@ void r200InitState( r200ContextPtr rmesa ) } if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == DRI_CONF_ROUND_ROUND ) - rmesa->state.color.roundEnable = R200_ROUND_ENABLE; + rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE; else - rmesa->state.color.roundEnable = 0; + rmesa->radeon.state.color.roundEnable = 0; if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == DRI_CONF_COLOR_REDUCTION_DITHER ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; else - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; #if 000 - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->radeon.state.color.drawOffset + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->radeon.state.color.drawPitch & R200_COLORPITCH_MASK) | R200_COLOR_ENDIAN_NO_SWAP); #else diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index d5cba26ddd9..1130c3544df 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -872,8 +872,8 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, /* Update window height */ - LOCK_HARDWARE( rmesa ); - UNLOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); + UNLOCK_HARDWARE( &rmesa->radeon ); h = rmesa->radeon.dri.drawable->h + rmesa->radeon.dri.drawable->y; px += rmesa->radeon.dri.drawable->x; diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index 93ae3260cca..e8b6876dd37 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -422,7 +422,7 @@ static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t, } } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); do { ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE, &tex, sizeof(drm_radeon_texture_t) ); @@ -433,7 +433,7 @@ static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t, } } while ( ret == -EAGAIN ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if ( ret ) { fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret ); @@ -476,7 +476,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) r200Finish( rmesa->radeon.glCtx ); } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); if ( t->base.memBlock == NULL ) { int heap; @@ -484,7 +484,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, (driTextureObject *) t ); if ( heap == -1 ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); return -1; } @@ -506,7 +506,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) /* Let the world know we've used this memory recently. */ driUpdateTextureLRU( (driTextureObject *) t ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); /* Upload any images that are new */ if (t->base.dirty_images[face]) { diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 7357cf74c98..18fab1d7800 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -24,9 +24,10 @@ DRIVER_SOURCES = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_screen.c \ + common_lock.c \ + common_misc.c \ radeon_context.c \ radeon_ioctl.c \ - radeon_lock.c \ radeon_span.c \ radeon_state.c \ r300_context.c \ @@ -78,7 +79,11 @@ COMMON_SYMLINKS = \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ radeon_cs_legacy.h \ - common_context.h + common_context.h \ + common_lock.c \ + common_lock.h \ + common_misc.c \ + common_misc.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index bd9d25d2f0d..32d0dcf5472 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -397,7 +397,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) struct radeon_renderbuffer *rrb; uint32_t zbpitch; - rrb = r300->radeon.state.depth_buffer; + rrb = r300->radeon.state.depth.rrb; if (!rrb) return; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5fce8413bbd..1958484b3cb 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -187,6 +187,23 @@ static void r300RunPipeline(GLcontext * ctx) _mesa_unlock_context_textures(ctx); } +static void r300_get_lock(radeonContextPtr rmesa) +{ + drm_radeon_sarea_t *sarea = rmesa->sarea; + + if (sarea->ctx_owner != rmesa->dri.hwContext) { + sarea->ctx_owner = rmesa->dri.hwContext; + if (!rmesa->radeonScreen->kernel_mm) + radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); + } +} + +static void r300_init_vtbl(radeonContextPtr radeon) +{ + radeon->vtbl.get_lock = r300_get_lock; + radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; +} + /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, @@ -212,6 +229,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; + r300_init_vtbl(&r300->radeon); /* Parse configuration files. * Do this here so that initialMaxAnisotropy is set before we create * the default textures. diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index e631e810079..de188c3f361 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -522,14 +522,6 @@ struct r300_cmdbuf { * State cache */ -struct r300_depthbuffer_state { - GLfloat scale; -}; - -struct r300_stencilbuffer_state { - GLboolean hw_stencil; -}; - /* Vertex shader state */ /* Perhaps more if we store programs in vmem? */ @@ -773,7 +765,6 @@ struct r300_aos { }; struct r300_state { - struct r300_depthbuffer_state depth; struct r300_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; struct r300_vertex_shader_state vertex_shader; @@ -786,8 +777,6 @@ struct r300_state { DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. They are the same as tnl->render_inputs for fixed pipeline */ - struct r300_stencilbuffer_state stencil; - }; #define R300_FALLBACK_NONE 0 diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 064732d4583..e70e5f6d52e 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -576,7 +576,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) mask &= ~BUFFER_BIT_DEPTH; } - if ((mask & BUFFER_BIT_STENCIL) && r300->state.stencil.hw_stencil) { + if ((mask & BUFFER_BIT_STENCIL) && r300->radeon.state.stencil.hwBuffer) { bits |= CLEARBUFFER_STENCIL; mask &= ~BUFFER_BIT_STENCIL; } diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index c79e69ae04c..d98b83c506b 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -591,7 +591,7 @@ static void r300SetStencilState(GLcontext * ctx, GLboolean state) { r300ContextPtr r300 = R300_CONTEXT(ctx); - if (r300->state.stencil.hw_stencil) { + if (r300->radeon.state.stencil.hwBuffer) { R300_STATECHANGE(r300, zs); if (state) { r300->hw.zs.cmd[R300_ZS_CNTL_0] |= @@ -1084,8 +1084,8 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; GLfloat sy = -v[MAT_SY]; GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; - GLfloat sz = v[MAT_SZ] * rmesa->state.depth.scale; - GLfloat tz = v[MAT_TZ] * rmesa->state.depth.scale; + GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; + GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; R300_FIREVERTICES(rmesa); R300_STATECHANGE(rmesa, vpt); @@ -2361,7 +2361,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - rrb = r300->radeon.state.depth_buffer; + rrb = r300->radeon.state.depth.rrb; if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { /* XXX: Turn off when clearing buffers ? */ r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; @@ -2694,11 +2694,11 @@ void r300InitState(r300ContextPtr r300) switch (ctx->Visual.depthBits) { case 16: - r300->state.depth.scale = 1.0 / (GLfloat) 0xffff; + r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffff; depth_fmt = R300_DEPTHFORMAT_16BIT_INT_Z; break; case 24: - r300->state.depth.scale = 1.0 / (GLfloat) 0xffffff; + r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffffff; depth_fmt = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; break; default: @@ -2708,8 +2708,8 @@ void r300InitState(r300ContextPtr r300) } /* Only have hw stencil when depth buffer is 24 bits deep */ - r300->state.stencil.hw_stencil = (ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24); + r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 && + ctx->Visual.depthBits == 24); memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 2bb679b4793..092562b8f97 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -554,7 +554,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, radeon_update_renderbuffers(driContextPriv, driReadPriv); radeon->state.color.rrb = (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - radeon->state.depth_buffer = + radeon->state.depth.rrb = (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; } diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index 7dfc3b3b914..d46a2d20ff3 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -51,6 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_screen.h" #include "common_context.h" +#include "common_misc.h" #if R200_MERGED extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode); diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c index 14d489bf1aa..0ee5313043e 100644 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ b/src/mesa/drivers/dri/r300/radeon_state.c @@ -56,83 +56,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Scissoring */ -static GLboolean intersect_rect(drm_clip_rect_t * out, - drm_clip_rect_t * a, drm_clip_rect_t * b) -{ - *out = *a; - if (b->x1 > out->x1) - out->x1 = b->x1; - if (b->y1 > out->y1) - out->y1 = b->y1; - if (b->x2 < out->x2) - out->x2 = b->x2; - if (b->y2 < out->y2) - out->y2 = b->y2; - if (out->x1 >= out->x2) - return GL_FALSE; - if (out->y1 >= out->y2) - return GL_FALSE; - return GL_TRUE; -} - -void radeonRecalcScissorRects(radeonContextPtr radeon) -{ - drm_clip_rect_t *out; - int i; - - /* Grow cliprect store? - */ - if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) { - while (radeon->state.scissor.numAllocedClipRects < - radeon->numClipRects) { - radeon->state.scissor.numAllocedClipRects += 1; /* zero case */ - radeon->state.scissor.numAllocedClipRects *= 2; - } - - if (radeon->state.scissor.pClipRects) - FREE(radeon->state.scissor.pClipRects); - - radeon->state.scissor.pClipRects = - MALLOC(radeon->state.scissor.numAllocedClipRects * - sizeof(drm_clip_rect_t)); - - if (radeon->state.scissor.pClipRects == NULL) { - radeon->state.scissor.numAllocedClipRects = 0; - return; - } - } - - out = radeon->state.scissor.pClipRects; - radeon->state.scissor.numClipRects = 0; - - for (i = 0; i < radeon->numClipRects; i++) { - if (intersect_rect(out, - &radeon->pClipRects[i], - &radeon->state.scissor.rect)) { - radeon->state.scissor.numClipRects++; - out++; - } - } -} - -void radeonUpdateScissor(GLcontext* ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - if (radeon->dri.drawable) { - __DRIdrawablePrivate *dPriv = radeon->dri.drawable; - int x1 = dPriv->x + ctx->Scissor.X; - int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height); - - radeon->state.scissor.rect.x1 = x1; - radeon->state.scissor.rect.y1 = y1; - radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width; - radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height; - - radeonRecalcScissorRects(radeon); - } -} - static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) { if (ctx->Scissor.Enabled) { @@ -142,58 +65,6 @@ static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h } } - -/** - * Update cliprects and scissors. - */ -void radeonSetCliprects(radeonContextPtr radeon) -{ - __DRIdrawablePrivate *const drawable = radeon->dri.drawable; - __DRIdrawablePrivate *const readable = radeon->dri.readable; - GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; - GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; - - if (!radeon->radeonScreen->driScreen->dri2.enabled) { - if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* Can't ignore 2d windows if we are page flipping. */ - if (drawable->numBackClipRects == 0 || radeon->doPageFlip || - radeon->sarea->pfCurrentPage == 1) { - radeon->numClipRects = drawable->numClipRects; - radeon->pClipRects = drawable->pClipRects; - } else { - radeon->numClipRects = drawable->numBackClipRects; - radeon->pClipRects = drawable->pBackClipRects; - } - } else { - /* front buffer (or none, or multiple buffers */ - radeon->numClipRects = drawable->numClipRects; - radeon->pClipRects = drawable->pClipRects; - } - } - - if ((draw_fb->Width != drawable->w) || - (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(radeon->glCtx, draw_fb, - drawable->w, drawable->h); - draw_fb->Initialized = GL_TRUE; - } - - if (drawable != readable) { - if ((read_fb->Width != readable->w) || - (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(radeon->glCtx, read_fb, - readable->w, readable->h); - read_fb->Initialized = GL_TRUE; - } - } - - if (radeon->state.scissor.enabled) - radeonRecalcScissorRects(radeon); - - radeon->lastStamp = drawable->lastStamp; -} - - /** * Handle common enable bits. * Called as a fallback by r200Enable/r300Enable. diff --git a/src/mesa/drivers/dri/r300/radeon_state.h b/src/mesa/drivers/dri/r300/radeon_state.h index 821cb40c7eb..279b1084122 100644 --- a/src/mesa/drivers/dri/r300/radeon_state.h +++ b/src/mesa/drivers/dri/r300/radeon_state.h @@ -31,10 +31,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_STATE_H__ #define __RADEON_STATE_H__ -extern void radeonRecalcScissorRects(radeonContextPtr radeon); -extern void radeonSetCliprects(radeonContextPtr radeon); -extern void radeonUpdateScissor(GLcontext* ctx); - extern void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state); extern void radeonInitState(radeonContextPtr radeon); diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index f223b2d9228..50c27b81bc5 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -11,7 +11,6 @@ MINIGLX_SOURCES = server/radeon_dri.c DRIVER_SOURCES = \ radeon_context.c \ radeon_ioctl.c \ - radeon_lock.c \ radeon_screen.c \ radeon_state.c \ radeon_state_init.c \ @@ -22,7 +21,9 @@ DRIVER_SOURCES = \ radeon_swtcl.c \ radeon_span.c \ radeon_maos.c \ - radeon_sanity.c + radeon_sanity.c \ + common_lock.c \ + common_misc.c C_SOURCES = \ $(COMMON_SOURCES) \ diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 5778adf9fb9..723f7d14fd5 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -249,10 +249,11 @@ typedef void (*radeon_line_func) (radeonContextPtr, typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); -struct r300_radeon_state { +struct radeon_state { struct radeon_colorbuffer_state color; + struct radeon_depthbuffer_state depth; struct radeon_scissor_state scissor; - struct radeon_renderbuffer *depth_buffer; + struct radeon_stencilbuffer_state stencil; }; struct radeon_context { @@ -301,12 +302,16 @@ struct radeon_context { GLuint swap_missed_count; /* Derived state - for r300 only */ - struct r300_radeon_state state; + struct radeon_state state; /* Configuration cache */ driOptionCache optionCache; + struct { + void (*get_lock)(radeonContextPtr radeon); + void (*update_viewport_offset)(GLcontext *ctx); + } vtbl; }; #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) diff --git a/src/mesa/drivers/dri/radeon/common_lock.c b/src/mesa/drivers/dri/radeon/common_lock.c new file mode 100644 index 00000000000..fe38fc95bc9 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/common_lock.c @@ -0,0 +1,138 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Gareth Hughes + * Keith Whitwell + * Kevin E. Martin + */ + +#include "main/glheader.h" +#include "main/mtypes.h" +#include "main/colormac.h" +#include "dri_util.h" +#include "radeon_screen.h" +#include "common_context.h" +#include "common_lock.h" + +#include "drirenderbuffer.h" + +#if DEBUG_LOCKING +char *prevLockFile = NULL; +int prevLockLine = 0; +#endif + +#ifdef RADEON_COMMON_FOR_R300 +/* Turn on/off page flipping according to the flags in the sarea: + */ +void radeonUpdatePageFlipping(radeonContextPtr rmesa) +{ + int use_back; + __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; + GLframebuffer *fb = drawable->driverPrivate; + + rmesa->doPageFlip = rmesa->sarea->pfState; + if (rmesa->glCtx->WinSysDrawBuffer) { + r300UpdateDrawBuffer(rmesa->glCtx); + } + + use_back = rmesa->glCtx->DrawBuffer ? + (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == + BUFFER_BACK_LEFT) : 1; + use_back ^= (rmesa->sarea->pfCurrentPage == 1); + + if (use_back) + rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + else + rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + + rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; +} +#else +/* Turn on/off page flipping according to the flags in the sarea: + */ +static void radeonUpdatePageFlipping(radeonContextPtr rmesa) +{ + rmesa->doPageFlip = rmesa->sarea->pfState; + if (rmesa->glCtx->WinSysDrawBuffer) { + driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, + rmesa->sarea->pfCurrentPage); + } +} +#endif + +/* Update the hardware state. This is called if another context has + * grabbed the hardware lock, which includes the X server. This + * function also updates the driver's window state after the X server + * moves, resizes or restacks a window -- the change will be reflected + * in the drawable position and clip rects. Since the X server grabs + * the hardware lock when it changes the window state, this routine will + * automatically be called after such a change. + */ +void radeonGetLock(radeonContextPtr rmesa, GLuint flags) +{ + __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; + __DRIdrawablePrivate *const readable = rmesa->dri.readable; + __DRIscreenPrivate *sPriv = rmesa->dri.screen; + drm_radeon_sarea_t *sarea = rmesa->sarea; + + assert(drawable != NULL); + + drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); + + /* The window might have moved, so we might need to get new clip + * rects. + * + * NOTE: This releases and regrabs the hw lock to allow the X server + * to respond to the DRI protocol request for new drawable info. + * Since the hardware state depends on having the latest drawable + * clip rects, all state checking must be done _after_ this call. + */ + DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); + if (drawable != readable) { + DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); + } + + if (rmesa->lastStamp != drawable->lastStamp) { + radeonUpdatePageFlipping(rmesa); + radeonSetCliprects(rmesa); + rmesa->vtbl.update_viewport_offset(rmesa->glCtx); + driUpdateFramebufferSize(rmesa->glCtx, drawable); + } + + rmesa->vtbl.get_lock(rmesa); + + rmesa->lost_context = GL_TRUE; +} diff --git a/src/mesa/drivers/dri/radeon/common_lock.h b/src/mesa/drivers/dri/radeon/common_lock.h new file mode 100644 index 00000000000..50a4a0b05a6 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/common_lock.h @@ -0,0 +1,111 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Gareth Hughes + * Keith Whitwell + * Kevin E. Martin + */ + +#ifndef COMMON_LOCK_H +#define COMMON_LOCK_H +extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); + +/* Turn DEBUG_LOCKING on to find locking conflicts. + */ +#define DEBUG_LOCKING 0 + +#if DEBUG_LOCKING +extern char *prevLockFile; +extern int prevLockLine; + +#define DEBUG_LOCK() \ + do { \ + prevLockFile = (__FILE__); \ + prevLockLine = (__LINE__); \ + } while (0) + +#define DEBUG_RESET() \ + do { \ + prevLockFile = 0; \ + prevLockLine = 0; \ + } while (0) + +#define DEBUG_CHECK_LOCK() \ + do { \ + if ( prevLockFile ) { \ + fprintf( stderr, \ + "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ + prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ + exit( 1 ); \ + } \ + } while (0) + +#else + +#define DEBUG_LOCK() +#define DEBUG_RESET() +#define DEBUG_CHECK_LOCK() + +#endif + +/* + * !!! We may want to separate locks from locks with validation. This + * could be used to improve performance for those things commands that + * do not do any drawing !!! + */ + +/* Lock the hardware and validate our state. + */ +#define LOCK_HARDWARE( rmesa ) \ + do { \ + char __ret = 0; \ + DEBUG_CHECK_LOCK(); \ + DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ + (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ + if ( __ret ) \ + radeonGetLock( (rmesa), 0 ); \ + DEBUG_LOCK(); \ + } while (0) + +#define UNLOCK_HARDWARE( rmesa ) \ + do { \ + DRM_UNLOCK( (rmesa)->dri.fd, \ + (rmesa)->dri.hwLock, \ + (rmesa)->dri.hwContext ); \ + DEBUG_RESET(); \ + } while (0) + +#endif diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c new file mode 100644 index 00000000000..3bfb61a0841 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -0,0 +1,187 @@ +/************************************************************************** + +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Keith Whitwell + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/api_arrayelt.h" +#include "main/enums.h" +#include "main/colormac.h" +#include "main/light.h" +#include "main/framebuffer.h" + +#include "swrast/swrast.h" +#include "vbo/vbo.h" +#include "tnl/tnl.h" +#include "tnl/t_pipeline.h" +#include "swrast_setup/swrast_setup.h" + +#include "dri_util.h" +#include "radeon_drm.h" +#include "radeon_screen.h" +#include "common_context.h" +#include "common_misc.h" +/* ============================================================= + * Scissoring + */ + +static GLboolean intersect_rect(drm_clip_rect_t * out, + drm_clip_rect_t * a, drm_clip_rect_t * b) +{ + *out = *a; + if (b->x1 > out->x1) + out->x1 = b->x1; + if (b->y1 > out->y1) + out->y1 = b->y1; + if (b->x2 < out->x2) + out->x2 = b->x2; + if (b->y2 < out->y2) + out->y2 = b->y2; + if (out->x1 >= out->x2) + return GL_FALSE; + if (out->y1 >= out->y2) + return GL_FALSE; + return GL_TRUE; +} + +void radeonRecalcScissorRects(radeonContextPtr radeon) +{ + drm_clip_rect_t *out; + int i; + + /* Grow cliprect store? + */ + if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) { + while (radeon->state.scissor.numAllocedClipRects < + radeon->numClipRects) { + radeon->state.scissor.numAllocedClipRects += 1; /* zero case */ + radeon->state.scissor.numAllocedClipRects *= 2; + } + + if (radeon->state.scissor.pClipRects) + FREE(radeon->state.scissor.pClipRects); + + radeon->state.scissor.pClipRects = + MALLOC(radeon->state.scissor.numAllocedClipRects * + sizeof(drm_clip_rect_t)); + + if (radeon->state.scissor.pClipRects == NULL) { + radeon->state.scissor.numAllocedClipRects = 0; + return; + } + } + + out = radeon->state.scissor.pClipRects; + radeon->state.scissor.numClipRects = 0; + + for (i = 0; i < radeon->numClipRects; i++) { + if (intersect_rect(out, + &radeon->pClipRects[i], + &radeon->state.scissor.rect)) { + radeon->state.scissor.numClipRects++; + out++; + } + } +} + +/** + * Update cliprects and scissors. + */ +void radeonSetCliprects(radeonContextPtr radeon) +{ + __DRIdrawablePrivate *const drawable = radeon->dri.drawable; + __DRIdrawablePrivate *const readable = radeon->dri.readable; + GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; + GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; + + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { + /* Can't ignore 2d windows if we are page flipping. */ + if (drawable->numBackClipRects == 0 || radeon->doPageFlip || + radeon->sarea->pfCurrentPage == 1) { + radeon->numClipRects = drawable->numClipRects; + radeon->pClipRects = drawable->pClipRects; + } else { + radeon->numClipRects = drawable->numBackClipRects; + radeon->pClipRects = drawable->pBackClipRects; + } + } else { + /* front buffer (or none, or multiple buffers */ + radeon->numClipRects = drawable->numClipRects; + radeon->pClipRects = drawable->pClipRects; + } + } + + if ((draw_fb->Width != drawable->w) || + (draw_fb->Height != drawable->h)) { + _mesa_resize_framebuffer(radeon->glCtx, draw_fb, + drawable->w, drawable->h); + draw_fb->Initialized = GL_TRUE; + } + + if (drawable != readable) { + if ((read_fb->Width != readable->w) || + (read_fb->Height != readable->h)) { + _mesa_resize_framebuffer(radeon->glCtx, read_fb, + readable->w, readable->h); + read_fb->Initialized = GL_TRUE; + } + } + + if (radeon->state.scissor.enabled) + radeonRecalcScissorRects(radeon); + + radeon->lastStamp = drawable->lastStamp; +} + +void radeonUpdateScissor( GLcontext *ctx ) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + + if ( rmesa->dri.drawable ) { + __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + + int x = ctx->Scissor.X; + int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; + int w = ctx->Scissor.X + ctx->Scissor.Width - 1; + int h = dPriv->h - ctx->Scissor.Y - 1; + + rmesa->state.scissor.rect.x1 = x + dPriv->x; + rmesa->state.scissor.rect.y1 = y + dPriv->y; + rmesa->state.scissor.rect.x2 = w + dPriv->x + 1; + rmesa->state.scissor.rect.y2 = h + dPriv->y + 1; + + radeonRecalcScissorRects( rmesa ); + } +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h new file mode 100644 index 00000000000..5653ef31830 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -0,0 +1,8 @@ +#ifndef COMMON_MISC_H +#define COMMON_MISC_H + +void radeonRecalcScissorRects(radeonContextPtr radeon); +void radeonSetCliprects(radeonContextPtr radeon); +void radeonUpdateScissor( GLcontext *ctx ); + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index e2b2323a65e..e49be4b23be 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -194,6 +194,35 @@ static const struct dri_debug_control debug_control[] = { NULL, 0 } }; +static void r100_get_lock(radeonContextPtr radeon) +{ + r100ContextPtr rmesa = (r100ContextPtr)radeon; + drm_radeon_sarea_t *sarea = radeon->sarea; + + RADEON_STATECHANGE(rmesa, ctx); + if (rmesa->radeon.sarea->tiling_enabled) { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= + RADEON_COLOR_TILE_ENABLE; + } else { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= + ~RADEON_COLOR_TILE_ENABLE; + } + + if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { + int i; + sarea->ctx_owner = rmesa->radeon.dri.hwContext; + + for (i = 0; i < rmesa->radeon.nr_heaps; i++) { + DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]); + } + } +} + +static void r100_init_vtbl(radeonContextPtr radeon) +{ + radeon->vtbl.get_lock = r100_get_lock; + radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; +} /* Create the device specific context. */ @@ -219,6 +248,8 @@ radeonCreateContext( const __GLcontextModes *glVisual, if ( !rmesa ) return GL_FALSE; + r100_init_vtbl(&rmesa->radeon); + /* init exp fog table data */ radeonInitStaticFogData(); @@ -488,9 +519,9 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) _mesa_vector4f_free( &rmesa->tcl.ObjClean ); - if (rmesa->state.scissor.pClipRects) { - FREE(rmesa->state.scissor.pClipRects); - rmesa->state.scissor.pClipRects = NULL; + if (rmesa->radeon.state.scissor.pClipRects) { + FREE(rmesa->radeon.state.scissor.pClipRects); + rmesa->radeon.state.scissor.pClipRects = NULL; } if ( release_texture_heaps ) { diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index fb2b6eac765..0ca49cc078d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -54,6 +54,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_screen.h" #include "common_context.h" +#include "common_misc.h" struct r100_context; @@ -328,11 +329,7 @@ struct radeon_hw_state { }; -struct radeon_state { - struct radeon_colorbuffer_state color; - struct radeon_depthbuffer_state depth; - struct radeon_scissor_state scissor; - struct radeon_stencilbuffer_state stencil; +struct r100_state { struct radeon_stipple_state stipple; struct radeon_texture_state texture; }; @@ -423,7 +420,7 @@ struct r100_context { /* Driver and hardware state management */ struct radeon_hw_state hw; - struct radeon_state state; + struct r100_state state; /* Vertex buffers */ diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 5e2b9867133..31f4778faba 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -557,10 +557,10 @@ static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, if (RADEON_DEBUG & DEBUG_SANITY) { - if (rmesa->state.scissor.enabled) + if (rmesa->radeon.state.scissor.enabled) ret = radeonSanityCmdBuffer( rmesa, - rmesa->state.scissor.numClipRects, - rmesa->state.scissor.pClipRects); + rmesa->radeon.state.scissor.numClipRects, + rmesa->radeon.state.scissor.pClipRects); else ret = radeonSanityCmdBuffer( rmesa, rmesa->radeon.numClipRects, @@ -575,9 +575,9 @@ static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, cmd.bufsz = rmesa->store.cmd_used; cmd.buf = rmesa->store.cmd_buf; - if (rmesa->state.scissor.enabled) { - cmd.nbox = rmesa->state.scissor.numClipRects; - cmd.boxes = rmesa->state.scissor.pClipRects; + if (rmesa->radeon.state.scissor.enabled) { + cmd.nbox = rmesa->radeon.state.scissor.numClipRects; + cmd.boxes = rmesa->radeon.state.scissor.pClipRects; } else { cmd.nbox = rmesa->radeon.numClipRects; cmd.boxes = rmesa->radeon.pClipRects; @@ -614,11 +614,11 @@ void radeonFlushCmdBuf( r100ContextPtr rmesa, const char *caller ) int ret; - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); ret = radeonFlushCmdBufLocked( rmesa, caller ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (ret) { fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret); @@ -664,7 +664,7 @@ void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ) dma.request_sizes = &size; dma.granted_count = 0; - LOCK_HARDWARE(rmesa); /* no need to validate */ + LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ ret = drmDMA( fd, &dma ); @@ -682,13 +682,13 @@ void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ) ret = drmDMA( fd, &dma ); if ( ret != 0 ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); fprintf( stderr, "Error: Could not get dma buffer... exiting\n" ); exit( -1 ); } } - UNLOCK_HARDWARE(rmesa); + UNLOCK_HARDWARE(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_DMA) fprintf(stderr, "Allocated buffer %d\n", index); @@ -839,9 +839,9 @@ static void radeonWaitForFrameCompletion( r100ContextPtr rmesa ) ; } else { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); radeonWaitIrq( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } rmesa->radeon.irqsEmitted = 10; } @@ -853,10 +853,10 @@ static void radeonWaitForFrameCompletion( r100ContextPtr rmesa ) } else { while (radeonGetLastFrame (rmesa) < sarea->last_frame) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (rmesa->radeon.do_usleeps) DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } } } @@ -883,7 +883,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, } RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* Throttle the frame rate -- only allow one pending swap buffers * request at a time. @@ -891,9 +891,9 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, radeonWaitForFrameCompletion( rmesa ); if (!rect) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); driWaitForVBlank( dPriv, & missed_target ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } nbox = dPriv->numClipRects; /* must be in locked region */ @@ -935,12 +935,12 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, if ( ret ) { fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); exit( 1 ); } } - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if (!rect) { psp = dPriv->driScreenPriv; @@ -976,7 +976,7 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) } RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* Need to do this for the perf box placement: */ @@ -992,17 +992,17 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) * request at a time. */ radeonWaitForFrameCompletion( rmesa ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); driWaitForVBlank( dPriv, & missed_target ); if ( missed_target ) { rmesa->radeon.swap_missed_count++; (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust ); } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if ( ret ) { fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); @@ -1043,8 +1043,8 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } { - LOCK_HARDWARE( rmesa ); - UNLOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); + UNLOCK_HARDWARE( &rmesa->radeon ); if ( dPriv->numClipRects == 0 ) return; } @@ -1068,7 +1068,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) mask &= ~BUFFER_BIT_DEPTH; } - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) { + if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { flags |= RADEON_STENCIL; mask &= ~BUFFER_BIT_STENCIL; } @@ -1086,14 +1086,14 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) flags |= RADEON_USE_COMP_ZBUF; /* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->state.stencil.hwBuffer) || + if (!(rmesa->radeon.state.stencil.hwBuffer) || ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && - ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { + ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { flags |= RADEON_CLEAR_FASTZ; } } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* compute region after locking: */ cx = ctx->DrawBuffer->_Xmin; @@ -1126,9 +1126,9 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } if ( rmesa->radeon.do_usleeps ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); } } @@ -1176,10 +1176,10 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) rmesa->radeon.sarea->nbox = n; clear.flags = flags; - clear.clear_color = rmesa->state.color.clear; - clear.clear_depth = rmesa->state.depth.clear; + clear.clear_color = rmesa->radeon.state.color.clear; + clear.clear_depth = rmesa->radeon.state.depth.clear; clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; - clear.depth_mask = rmesa->state.stencil.clear; + clear.depth_mask = rmesa->radeon.state.stencil.clear; clear.depth_boxes = depth_boxes; n--; @@ -1190,20 +1190,20 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2; depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2; depth_boxes[n].f[CLEAR_DEPTH] = - (float)rmesa->state.depth.clear; + (float)rmesa->radeon.state.depth.clear; } ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR, &clear, sizeof(drm_radeon_clear_t)); if ( ret ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret ); exit( 1 ); } } - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); rmesa->hw.all_dirty = GL_TRUE; } @@ -1223,7 +1223,7 @@ void radeonWaitForIdleLocked( r100ContextPtr rmesa ) } while ( ( ret == -EBUSY ) && ( to++ < RADEON_TIMEOUT ) ); if ( ret < 0 ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); fprintf( stderr, "Error: Radeon timed out... exiting\n" ); exit( -1 ); } @@ -1232,9 +1232,9 @@ void radeonWaitForIdleLocked( r100ContextPtr rmesa ) static void radeonWaitForIdle( r100ContextPtr rmesa ) { - LOCK_HARDWARE(rmesa); + LOCK_HARDWARE(&rmesa->radeon); radeonWaitForIdleLocked( rmesa ); - UNLOCK_HARDWARE(rmesa); + UNLOCK_HARDWARE(&rmesa->radeon); } @@ -1263,9 +1263,9 @@ void radeonFinish( GLcontext *ctx ) radeonFlush( ctx ); if (rmesa->radeon.do_irqs) { - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); radeonEmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); radeonWaitIrq( rmesa ); } else diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h index e4bfa1b9d67..f2d17a54d47 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.h +++ b/src/mesa/drivers/dri/radeon/radeon_lock.h @@ -42,71 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_LOCK_H__ #define __RADEON_LOCK_H__ -extern void radeonGetLock(r100ContextPtr rmesa, GLuint flags); - -/* Turn DEBUG_LOCKING on to find locking conflicts. - */ -#define DEBUG_LOCKING 0 - -#if DEBUG_LOCKING -extern char *prevLockFile; -extern int prevLockLine; - -#define DEBUG_LOCK() \ - do { \ - prevLockFile = (__FILE__); \ - prevLockLine = (__LINE__); \ - } while (0) - -#define DEBUG_RESET() \ - do { \ - prevLockFile = 0; \ - prevLockLine = 0; \ - } while (0) - -#define DEBUG_CHECK_LOCK() \ - do { \ - if ( prevLockFile ) { \ - fprintf( stderr, \ - "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ - prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ - exit( 1 ); \ - } \ - } while (0) - -#else - -#define DEBUG_LOCK() -#define DEBUG_RESET() -#define DEBUG_CHECK_LOCK() - -#endif - -/* - * !!! We may want to separate locks from locks with validation. This - * could be used to improve performance for those things commands that - * do not do any drawing !!! - */ - -/* Lock the hardware and validate our state. - */ -#define LOCK_HARDWARE( rmesa ) \ - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ - DRM_CAS( (rmesa)->radeon.dri.hwLock, (rmesa)->radeon.dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->radeon.dri.hwContext), __ret ); \ - if ( __ret ) \ - radeonGetLock( (rmesa), 0 ); \ - DEBUG_LOCK(); \ - } while (0) - -#define UNLOCK_HARDWARE( rmesa ) \ - do { \ - DRM_UNLOCK( (rmesa)->radeon.dri.fd, \ - (rmesa)->radeon.dri.hwLock, \ - (rmesa)->radeon.dri.hwContext ); \ - DEBUG_RESET(); \ - } while (0) +#include "common_lock.h" #endif /* __RADEON_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 9733025fa9f..423f3ca7e39 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -282,19 +282,17 @@ static void radeonSpanRenderStart(GLcontext * ctx) #ifdef COMPILE_R300 r300ContextPtr r300 = (r300ContextPtr) rmesa; R300_FIREVERTICES(r300); - LOCK_HARDWARE(rmesa); #else r100ContextPtr r100 = (r100ContextPtr) rmesa; RADEON_FIREVERTICES(r100); - LOCK_HARDWARE(r100); #endif - + LOCK_HARDWARE(rmesa); radeonWaitForIdleLocked(rmesa); } static void radeonSpanRenderFinish(GLcontext * ctx) { - r100ContextPtr rmesa = R100_CONTEXT(ctx); + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); _swrast_flush(ctx); UNLOCK_HARDWARE(rmesa); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 7e5306073f6..67f861a48ee 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -311,10 +311,10 @@ static void radeonClearDepth( GLcontext *ctx, GLclampd d ) switch ( format ) { case RADEON_DEPTH_FORMAT_16BIT_INT_Z: - rmesa->state.depth.clear = d * 0x0000ffff; + rmesa->radeon.state.depth.clear = d * 0x0000ffff; break; case RADEON_DEPTH_FORMAT_24BIT_INT_Z: - rmesa->state.depth.clear = d * 0x00ffffff; + rmesa->radeon.state.depth.clear = d * 0x00ffffff; break; } } @@ -410,85 +410,6 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) /* ============================================================= * Scissoring */ - - -static GLboolean intersect_rect( drm_clip_rect_t *out, - drm_clip_rect_t *a, - drm_clip_rect_t *b ) -{ - *out = *a; - if ( b->x1 > out->x1 ) out->x1 = b->x1; - if ( b->y1 > out->y1 ) out->y1 = b->y1; - if ( b->x2 < out->x2 ) out->x2 = b->x2; - if ( b->y2 < out->y2 ) out->y2 = b->y2; - if ( out->x1 >= out->x2 ) return GL_FALSE; - if ( out->y1 >= out->y2 ) return GL_FALSE; - return GL_TRUE; -} - - -void radeonRecalcScissorRects( r100ContextPtr rmesa ) -{ - drm_clip_rect_t *out; - int i; - - /* Grow cliprect store? - */ - if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { - while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) { - rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */ - rmesa->state.scissor.numAllocedClipRects *= 2; - } - - if (rmesa->state.scissor.pClipRects) - FREE(rmesa->state.scissor.pClipRects); - - rmesa->state.scissor.pClipRects = - MALLOC( rmesa->state.scissor.numAllocedClipRects * - sizeof(drm_clip_rect_t) ); - - if ( rmesa->state.scissor.pClipRects == NULL ) { - rmesa->state.scissor.numAllocedClipRects = 0; - return; - } - } - - out = rmesa->state.scissor.pClipRects; - rmesa->state.scissor.numClipRects = 0; - - for ( i = 0 ; i < rmesa->radeon.numClipRects ; i++ ) { - if ( intersect_rect( out, - &rmesa->radeon.pClipRects[i], - &rmesa->state.scissor.rect ) ) { - rmesa->state.scissor.numClipRects++; - out++; - } - } -} - - -static void radeonUpdateScissor( GLcontext *ctx ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - - if ( rmesa->radeon.dri.drawable ) { - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - - int x = ctx->Scissor.X; - int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; - int w = ctx->Scissor.X + ctx->Scissor.Width - 1; - int h = dPriv->h - ctx->Scissor.Y - 1; - - rmesa->state.scissor.rect.x1 = x + dPriv->x; - rmesa->state.scissor.rect.y1 = y + dPriv->y; - rmesa->state.scissor.rect.x2 = w + dPriv->x + 1; - rmesa->state.scissor.rect.y2 = h + dPriv->y + 1; - - radeonRecalcScissorRects( rmesa ); - } -} - - static void radeonScissor( GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h ) { @@ -624,7 +545,7 @@ static void radeonPolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - float_ui32_type constant = { units * rmesa->state.depth.scale }; + float_ui32_type constant = { units * rmesa->radeon.state.depth.scale }; float_ui32_type factoru = { factor }; RADEON_STATECHANGE( rmesa, zbs ); @@ -647,14 +568,14 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* FIXME: Use window x,y offsets into stipple RAM. */ stipple.mask = rmesa->state.stipple.mask; drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, &stipple, sizeof(drm_radeon_stipple_t) ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); } static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) @@ -1457,7 +1378,7 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - rmesa->state.stencil.clear = + rmesa->radeon.state.stencil.clear = ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << RADEON_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT)); @@ -1491,8 +1412,8 @@ void radeonUpdateWindow( GLcontext *ctx ) float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; float_ui32_type sy = { - v[MAT_SY] }; float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; - float_ui32_type sz = { v[MAT_SZ] * rmesa->state.depth.scale }; - float_ui32_type tz = { v[MAT_TZ] * rmesa->state.depth.scale }; + float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; + float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; RADEON_FIREVERTICES( rmesa ); RADEON_STATECHANGE( rmesa, vpt ); @@ -1586,7 +1507,7 @@ static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] ) CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); - rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, + rmesa->radeon.state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, c[0], c[1], c[2], c[3] ); } @@ -1629,55 +1550,6 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) } -/** - * Set up the cliprects for either front or back-buffer drawing. - */ -void radeonSetCliprects( r100ContextPtr rmesa ) -{ - __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable; - GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate; - GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate; - - if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* Can't ignore 2d windows if we are page flipping. - */ - if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) { - rmesa->radeon.numClipRects = drawable->numClipRects; - rmesa->radeon.pClipRects = drawable->pClipRects; - } - else { - rmesa->radeon.numClipRects = drawable->numBackClipRects; - rmesa->radeon.pClipRects = drawable->pBackClipRects; - } - } - else { - /* front buffer (or none, or multiple buffers */ - rmesa->radeon.numClipRects = drawable->numClipRects; - rmesa->radeon.pClipRects = drawable->pClipRects; - } - - if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb, - drawable->w, drawable->h); - draw_fb->Initialized = GL_TRUE; - } - - if (drawable != readable) { - if ((read_fb->Width != readable->w) || (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb, - readable->w, readable->h); - read_fb->Initialized = GL_TRUE; - } - } - - if (rmesa->state.scissor.enabled) - radeonRecalcScissorRects( rmesa ); - - rmesa->radeon.lastStamp = drawable->lastStamp; -} - - /** * Called via glDrawBuffer. */ @@ -1707,7 +1579,7 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) return; } - radeonSetCliprects( rmesa ); + radeonSetCliprects( &rmesa->radeon ); /* We'll set the drawing engine's offset/pitch parameters later * when we update other state. @@ -1821,10 +1693,10 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) RADEON_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable; } else { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; } break; @@ -1972,12 +1844,12 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_SCISSOR_TEST: RADEON_FIREVERTICES( rmesa ); - rmesa->state.scissor.enabled = state; + rmesa->radeon.state.scissor.enabled = state; radeonUpdateScissor( ctx ); break; case GL_STENCIL_TEST: - if ( rmesa->state.stencil.hwBuffer ) { + if ( rmesa->radeon.state.stencil.hwBuffer ) { RADEON_STATECHANGE( rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h index 20b2d890019..17c2b112225 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.h +++ b/src/mesa/drivers/dri/radeon/radeon_state.h @@ -44,8 +44,6 @@ extern void radeonInitStateFuncs( GLcontext *ctx ); extern void radeonUpdateMaterial( GLcontext *ctx ); -extern void radeonSetCliprects( r100ContextPtr rmesa ); -extern void radeonRecalcScissorRects( r100ContextPtr rmesa ); extern void radeonUpdateViewportOffset( GLcontext *ctx ); extern void radeonUpdateWindow( GLcontext *ctx ); extern void radeonUpdateDrawBuffer( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index d5b83191b60..affa9313c9e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -168,20 +168,20 @@ void radeonInitState( r100ContextPtr rmesa ) exit( -1 ); } - rmesa->state.color.clear = 0x00000000; + rmesa->radeon.state.color.clear = 0x00000000; switch ( ctx->Visual.depthBits ) { case 16: - rmesa->state.depth.clear = 0x0000ffff; - rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; + rmesa->radeon.state.depth.clear = 0x0000ffff; + rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - rmesa->state.stencil.clear = 0x00000000; + rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: - rmesa->state.depth.clear = 0x00ffffff; - rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; + rmesa->radeon.state.depth.clear = 0x00ffffff; + rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - rmesa->state.stencil.clear = 0xffff0000; + rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: fprintf( stderr, "Error: Unsupported depth %d... exiting\n", @@ -190,7 +190,7 @@ void radeonInitState( r100ContextPtr rmesa ) } /* Only have hw stencil when depth buffer is 24 bits deep */ - rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && + rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && ctx->Visual.depthBits == 24 ); rmesa->radeon.Fallback = 0; @@ -399,14 +399,14 @@ void radeonInitState( r100ContextPtr rmesa ) } if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == DRI_CONF_ROUND_ROUND ) - rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE; + rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE; else - rmesa->state.color.roundEnable = 0; + rmesa->radeon.state.color.roundEnable = 0; if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == DRI_CONF_COLOR_REDUCTION_DITHER ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; else - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + rmesa->radeon.radeonScreen->fbLocation) diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c index 77810ef7e19..0cf5badf4f4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texmem.c +++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c @@ -298,13 +298,13 @@ static void uploadSubImage( r100ContextPtr rmesa, radeonTexObjPtr t, } } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); do { ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE, &tex, sizeof(drm_radeon_texture_t) ); } while ( ret == -EAGAIN ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); if ( ret ) { fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret ); @@ -349,7 +349,7 @@ int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face radeonFinish( rmesa->radeon.glCtx ); } - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); if ( t->base.memBlock == NULL ) { int heap; @@ -357,7 +357,7 @@ int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, (driTextureObject *) t ); if ( heap == -1 ) { - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); return -1; } @@ -380,7 +380,7 @@ int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face /* Let the world know we've used this memory recently. */ driUpdateTextureLRU( (driTextureObject *) t ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( &rmesa->radeon ); /* Upload any images that are new */ -- cgit v1.2.3 From 7e5e327cea83d9f6d1485f9be440277540ace5c7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 13:23:24 +1000 Subject: radeon/r200/r300: consolidate the buffer copy/flip code into one place --- src/mesa/drivers/dri/r200/r200_context.c | 21 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 318 +------------------------ src/mesa/drivers/dri/r200/r200_ioctl.h | 5 - src/mesa/drivers/dri/r200/r200_pixel.c | 2 +- src/mesa/drivers/dri/r200/r200_span.c | 2 +- src/mesa/drivers/dri/r300/r300_context.c | 14 ++ src/mesa/drivers/dri/r300/radeon_ioctl.c | 322 +------------------------ src/mesa/drivers/dri/radeon/common_context.h | 3 + src/mesa/drivers/dri/radeon/common_misc.c | 340 +++++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 7 + src/mesa/drivers/dri/radeon/radeon_context.c | 14 ++ src/mesa/drivers/dri/radeon/radeon_ioctl.c | 295 +---------------------- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 5 - 13 files changed, 404 insertions(+), 944 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 9f882fe6155..85e508616b4 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -262,11 +262,26 @@ static void r200_get_lock(radeonContextPtr radeon) DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] ); } } - + + +static void r200_vtbl_flush(GLcontext *ctx) +{ + R200_FIREVERTICES(R200_CONTEXT(ctx)); +} + +static void r200_vtbl_set_all_dirty(GLcontext *ctx) +{ + r200ContextPtr rmesa = R200_CONTEXT(ctx); + rmesa->hw.all_dirty = GL_TRUE; +} + static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; + radeon->vtbl.flush = r200_vtbl_flush; + radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty; + radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; } /* Create the device specific rendering context. @@ -642,7 +657,7 @@ r200SwapBuffers( __DRIdrawablePrivate *dPriv ) r200PageFlip( dPriv ); } else { - r200CopyBuffer( dPriv, NULL ); + radeonCopyBuffer( dPriv, NULL ); } } } @@ -668,7 +683,7 @@ r200CopySubBuffer( __DRIdrawablePrivate *dPriv, rect.x2 = rect.x1 + w; rect.y2 = rect.y1 + h; _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ - r200CopyBuffer( dPriv, &rect ); + radeonCopyBuffer( dPriv, &rect ); } } else { diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 09baffb5440..fe3a471c8ab 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -55,9 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_IDLE_RETRY 16 -static void r200WaitForIdle( r200ContextPtr rmesa ); - - /* At this point we were in FlushCmdBufLocked but we had lost our context, so * we need to unwire our current cmdbuf, hook the one with the saved state in * it, flush it, and then put the current one back. This is so commands at the @@ -152,7 +149,7 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__); - r200WaitForIdleLocked( rmesa ); + radeonWaitForIdleLocked( &rmesa->radeon ); } @@ -329,281 +326,6 @@ void r200AllocDmaRegion( r200ContextPtr rmesa, assert( rmesa->dma.current.ptr <= rmesa->dma.current.end ); } -/* ================================================================ - * SwapBuffers with client-side throttling - */ - -static uint32_t r200GetLastFrame(r200ContextPtr rmesa) -{ - drm_radeon_getparam_t gp; - int ret; - uint32_t frame; - - gp.param = RADEON_PARAM_LAST_FRAME; - gp.value = (int *)&frame; - ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp) ); - if ( ret ) { - fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret ); - exit(1); - } - - return frame; -} - -static void r200EmitIrqLocked( r200ContextPtr rmesa ) -{ - drm_radeon_irq_emit_t ie; - int ret; - - ie.irq_seq = &rmesa->radeon.iw.irq_seq; - ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_EMIT, - &ie, sizeof(ie) ); - if ( ret ) { - fprintf( stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, ret ); - exit(1); - } -} - - -static void r200WaitIrq( r200ContextPtr rmesa ) -{ - int ret; - - do { - ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_WAIT, - &rmesa->radeon.iw, sizeof(rmesa->radeon.iw) ); - } while (ret && (errno == EINTR || errno == EBUSY)); - - if ( ret ) { - fprintf( stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, ret ); - exit(1); - } -} - - -static void r200WaitForFrameCompletion( r200ContextPtr rmesa ) -{ - drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - - if (rmesa->radeon.do_irqs) { - if (r200GetLastFrame(rmesa) < sarea->last_frame) { - if (!rmesa->radeon.irqsEmitted) { - while (r200GetLastFrame (rmesa) < sarea->last_frame) - ; - } - else { - UNLOCK_HARDWARE( &rmesa->radeon ); - r200WaitIrq( rmesa ); - LOCK_HARDWARE( &rmesa->radeon ); - } - rmesa->radeon.irqsEmitted = 10; - } - - if (rmesa->radeon.irqsEmitted) { - r200EmitIrqLocked( rmesa ); - rmesa->radeon.irqsEmitted--; - } - } - else { - while (r200GetLastFrame (rmesa) < sarea->last_frame) { - UNLOCK_HARDWARE( &rmesa->radeon ); - if (rmesa->radeon.do_usleeps) - DO_USLEEP( 1 ); - LOCK_HARDWARE( &rmesa->radeon ); - } - } -} - - - -/* Copy the back color buffer to the front color buffer. - */ -void r200CopyBuffer( __DRIdrawablePrivate *dPriv, - const drm_clip_rect_t *rect) -{ - r200ContextPtr rmesa; - GLint nbox, i, ret; - GLboolean missed_target; - int64_t ust; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)rmesa->radeon.glCtx ); - } - - R200_FIREVERTICES( rmesa ); - - LOCK_HARDWARE( &rmesa->radeon ); - - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. - */ - r200WaitForFrameCompletion( rmesa ); - if (!rect) - { - UNLOCK_HARDWARE( &rmesa->radeon ); - driWaitForVBlank( dPriv, & missed_target ); - LOCK_HARDWARE( &rmesa->radeon ); - } - - nbox = dPriv->numClipRects; /* must be in locked region */ - - for ( i = 0 ; i < nbox ; ) { - GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; - GLint n = 0; - - for ( ; i < nr ; i++ ) { - - *b = box[i]; - - if (rect) - { - if (rect->x1 > b->x1) - b->x1 = rect->x1; - if (rect->y1 > b->y1) - b->y1 = rect->y1; - if (rect->x2 < b->x2) - b->x2 = rect->x2; - if (rect->y2 < b->y2) - b->y2 = rect->y2; - - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } - - b++; - n++; - } - rmesa->radeon.sarea->nbox = n; - - if (!n) - continue; - - ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_SWAP ); - - if ( ret ) { - fprintf( stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( &rmesa->radeon ); - exit( 1 ); - } - } - - UNLOCK_HARDWARE( &rmesa->radeon ); - if (!rect) - { - rmesa->hw.all_dirty = GL_TRUE; - - rmesa->radeon.swap_count++; - (*psp->systemTime->getUST)( & ust ); - if ( missed_target ) { - rmesa->radeon.swap_missed_count++; - rmesa->radeon.swap_missed_ust = ust - rmesa->radeon.swap_ust; - } - - rmesa->radeon.swap_ust = ust; - - sched_yield(); - } -} - -void r200PageFlip( __DRIdrawablePrivate *dPriv ) -{ - r200ContextPtr rmesa; - GLint ret; - GLboolean missed_target; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->radeon.sarea->pfCurrentPage); - } - - R200_FIREVERTICES( rmesa ); - LOCK_HARDWARE( &rmesa->radeon ); - - if (!dPriv->numClipRects) { - UNLOCK_HARDWARE( &rmesa->radeon ); - usleep( 10000 ); /* throttle invisible client 10ms */ - return; - } - - /* Need to do this for the perf box placement: - */ - { - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; - b[0] = box[0]; - rmesa->radeon.sarea->nbox = 1; - } - - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ - r200WaitForFrameCompletion( rmesa ); - UNLOCK_HARDWARE( &rmesa->radeon ); - driWaitForVBlank( dPriv, & missed_target ); - if ( missed_target ) { - rmesa->radeon.swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust ); - } - LOCK_HARDWARE( &rmesa->radeon ); - - ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); - } - - rmesa->radeon.swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_ust ); - -#if 000 - if ( rmesa->radeon.sarea->pfCurrentPage == 1 ) { - rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset; - rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch; - } else { - rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset; - rmesa->state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch; - } - - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset - + rmesa->radeon.radeonScreen->fbLocation; - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; - } -#else - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. - */ - driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, - rmesa->radeon.sarea->pfCurrentPage); - - - r200UpdateDrawBuffer(rmesa->radeon.glCtx); -#endif -} - /* ================================================================ * Buffer clear @@ -790,33 +512,6 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } -void r200WaitForIdleLocked( r200ContextPtr rmesa ) -{ - int ret; - int i = 0; - - do { - ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_CP_IDLE); - if (ret) - DO_USLEEP( 1 ); - } while (ret && ++i < 100); - - if ( ret < 0 ) { - UNLOCK_HARDWARE( &rmesa->radeon ); - fprintf( stderr, "Error: R200 timed out... exiting\n" ); - exit( -1 ); - } -} - - -static void r200WaitForIdle( r200ContextPtr rmesa ) -{ - LOCK_HARDWARE(&rmesa->radeon); - r200WaitForIdleLocked( rmesa ); - UNLOCK_HARDWARE(&rmesa->radeon); -} - - void r200Flush( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); @@ -838,17 +533,8 @@ void r200Flush( GLcontext *ctx ) */ void r200Finish( GLcontext *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); r200Flush( ctx ); - - if (rmesa->radeon.do_irqs) { - LOCK_HARDWARE( &rmesa->radeon ); - r200EmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( &rmesa->radeon ); - r200WaitIrq( rmesa ); - } - else - r200WaitForIdle( rmesa ); + radeon_common_finish(ctx); } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index f52d2a7419d..1f92705685c 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -89,13 +89,8 @@ extern void r200ReleaseDmaRegion( r200ContextPtr rmesa, struct radeon_dma_region *region, const char *caller ); -extern void r200CopyBuffer( __DRIdrawablePrivate *drawable, - const drm_clip_rect_t *rect); -extern void r200PageFlip( __DRIdrawablePrivate *drawable ); extern void r200Flush( GLcontext *ctx ); extern void r200Finish( GLcontext *ctx ); -extern void r200WaitForIdleLocked( r200ContextPtr rmesa ); -extern void r200WaitForVBlank( r200ContextPtr rmesa ); extern void r200InitIoctlFuncs( struct dd_function_table *functions ); extern void *r200AllocateMemoryMESA( __DRIscreen *screen, GLsizei size, GLfloat readfreq, diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 60d25825e92..a8aa1a27731 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -364,7 +364,7 @@ static void do_draw_pix( GLcontext *ctx, } r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); - r200WaitForIdleLocked( rmesa ); /* required by GL */ + radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */ UNLOCK_HARDWARE( &rmesa->radeon ); } diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index dfe587401d9..b4da9ef6a38 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -243,7 +243,7 @@ static void r200SpanRenderStart( GLcontext *ctx ) R200_FIREVERTICES( rmesa ); LOCK_HARDWARE( &rmesa->radeon ); - r200WaitForIdleLocked( rmesa ); + radeonWaitForIdleLocked( &rmesa->radeon ); /* Read & rewrite the first pixel in the frame buffer. This should * be a noop, right? In fact without this conform fails as reading diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 1958484b3cb..3b8ba855bb5 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -198,12 +198,26 @@ static void r300_get_lock(radeonContextPtr rmesa) } } +static void r300_vtbl_flush(GLcontext *ctx) +{ + r300Flush(ctx); +} + +static void r300_vtbl_set_all_dirty(GLcontext *ctx) +{ + r300ContextPtr rmesa = R300_CONTEXT(ctx); + rmesa->hw.all_dirty = GL_TRUE; +} + static void r300_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r300_get_lock; radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; + radeon->vtbl.flush = r300_vtbl_flush; + radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty; } + /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.c b/src/mesa/drivers/dri/r300/radeon_ioctl.c index 87123170508..120d6c03ab8 100644 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.c +++ b/src/mesa/drivers/dri/r300/radeon_ioctl.c @@ -50,307 +50,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" #include "vblank.h" -static void radeonWaitForIdle(radeonContextPtr radeon); - -/* ================================================================ - * SwapBuffers with client-side throttling - */ - -static uint32_t radeonGetLastFrame(radeonContextPtr radeon) -{ - drm_radeon_getparam_t gp; - int ret; - uint32_t frame; - - gp.param = RADEON_PARAM_LAST_FRAME; - gp.value = (int *)&frame; - ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp)); - if (ret) { - fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, - ret); - exit(1); - } - - return frame; -} - -uint32_t radeonGetAge(radeonContextPtr radeon) -{ - drm_radeon_getparam_t gp; - int ret; - uint32_t age; - - gp.param = RADEON_PARAM_LAST_CLEAR; - gp.value = (int *)&age; - ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp)); - if (ret) { - fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, - ret); - exit(1); - } - - return age; -} - -static void radeonEmitIrqLocked(radeonContextPtr radeon) -{ - drm_radeon_irq_emit_t ie; - int ret; - - ie.irq_seq = &radeon->iw.irq_seq; - ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_IRQ_EMIT, - &ie, sizeof(ie)); - if (ret) { - fprintf(stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, - ret); - exit(1); - } -} - -static void radeonWaitIrq(radeonContextPtr radeon) -{ - int ret; - - do { - ret = drmCommandWrite(radeon->dri.fd, DRM_RADEON_IRQ_WAIT, - &radeon->iw, sizeof(radeon->iw)); - } while (ret && (errno == EINTR || errno == EBUSY)); - - if (ret) { - fprintf(stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, - ret); - exit(1); - } -} - -static void radeonWaitForFrameCompletion(radeonContextPtr radeon) -{ - drm_radeon_sarea_t *sarea = radeon->sarea; - - if (radeon->do_irqs) { - if (radeonGetLastFrame(radeon) < sarea->last_frame) { - if (!radeon->irqsEmitted) { - while (radeonGetLastFrame(radeon) < - sarea->last_frame) ; - } else { - UNLOCK_HARDWARE(radeon); - radeonWaitIrq(radeon); - LOCK_HARDWARE(radeon); - } - radeon->irqsEmitted = 10; - } - - if (radeon->irqsEmitted) { - radeonEmitIrqLocked(radeon); - radeon->irqsEmitted--; - } - } else { - while (radeonGetLastFrame(radeon) < sarea->last_frame) { - UNLOCK_HARDWARE(radeon); - if (radeon->do_usleeps) - DO_USLEEP(1); - LOCK_HARDWARE(radeon); - } - } -} - -/* Copy the back color buffer to the front color buffer. - */ -void radeonCopyBuffer(__DRIdrawablePrivate * dPriv, - const drm_clip_rect_t * rect) -{ - radeonContextPtr radeon; - GLint nbox, i, ret; - GLboolean missed_target; - int64_t ust; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "\n%s( %p )\n\n", __FUNCTION__, - (void *)radeon->glCtx); - } - - r300Flush(radeon->glCtx); - - LOCK_HARDWARE(radeon); - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion(radeon); - if (!rect) - { - UNLOCK_HARDWARE(radeon); - driWaitForVBlank(dPriv, &missed_target); - LOCK_HARDWARE(radeon); - } - - nbox = dPriv->numClipRects; /* must be in locked region */ - - for (i = 0; i < nbox;) { - GLint nr = MIN2(i + RADEON_NR_SAREA_CLIPRECTS, nbox); - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = radeon->sarea->boxes; - GLint n = 0; - - for ( ; i < nr ; i++ ) { - - *b = box[i]; - - if (rect) - { - if (rect->x1 > b->x1) - b->x1 = rect->x1; - if (rect->y1 > b->y1) - b->y1 = rect->y1; - if (rect->x2 < b->x2) - b->x2 = rect->x2; - if (rect->y2 < b->y2) - b->y2 = rect->y2; - - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } - - b++; - n++; - } - radeon->sarea->nbox = n; - - if (!n) - continue; - - ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_SWAP); - - if (ret) { - fprintf(stderr, "DRM_RADEON_SWAP: return = %d\n", - ret); - UNLOCK_HARDWARE(radeon); - exit(1); - } - } - - UNLOCK_HARDWARE(radeon); - if (!rect) - { - ((r300ContextPtr)radeon)->hw.all_dirty = GL_TRUE; - - radeon->swap_count++; - (*psp->systemTime->getUST) (&ust); - if (missed_target) { - radeon->swap_missed_count++; - radeon->swap_missed_ust = ust - radeon->swap_ust; - } - - radeon->swap_ust = ust; - - sched_yield(); - } -} - -void radeonPageFlip(__DRIdrawablePrivate * dPriv) -{ - radeonContextPtr radeon; - GLint ret; - GLboolean missed_target; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; - GLframebuffer *fb = dPriv->driverPrivate; - struct radeon_renderbuffer *rrb; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - - rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - - if (RADEON_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - radeon->sarea->pfCurrentPage); - } - - r300Flush(radeon->glCtx); - LOCK_HARDWARE(radeon); - - if (!dPriv->numClipRects) { - UNLOCK_HARDWARE(radeon); - usleep(10000); /* throttle invisible client 10ms */ - return; - } - - /* Need to do this for the perf box placement: - */ - { - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = radeon->sarea->boxes; - b[0] = box[0]; - radeon->sarea->nbox = 1; - } - - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion(radeon); - UNLOCK_HARDWARE(radeon); - driWaitForVBlank(dPriv, &missed_target); - if (missed_target) { - radeon->swap_missed_count++; - (void)(*psp->systemTime->getUST) (&radeon->swap_missed_ust); - } - LOCK_HARDWARE(radeon); - - ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_FLIP); - - UNLOCK_HARDWARE(radeon); - - if (ret) { - fprintf(stderr, "DRM_RADEON_FLIP: return = %d\n", ret); - exit(1); - } - - radeon->swap_count++; - (void)(*psp->systemTime->getUST) (&radeon->swap_ust); - - driFlipRenderbuffers(radeon->glCtx->WinSysDrawBuffer, - radeon->sarea->pfCurrentPage); - - radeon->state.color.rrb = rrb; -} - -void radeonWaitForIdleLocked(radeonContextPtr radeon) -{ - int ret; - int i = 0; - - do { - ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_CP_IDLE); - if (ret) - DO_USLEEP(1); - } while (ret && ++i < 100); - - if (ret < 0) { - UNLOCK_HARDWARE(radeon); - fprintf(stderr, "Error: R300 timed out... exiting\n"); - exit(-1); - } -} - -static void radeonWaitForIdle(radeonContextPtr radeon) -{ - LOCK_HARDWARE(radeon); - radeonWaitForIdleLocked(radeon); - UNLOCK_HARDWARE(radeon); -} - void radeonFlush(GLcontext * ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); @@ -365,25 +64,6 @@ void radeonFlush(GLcontext * ctx) */ void radeonFinish(GLcontext * ctx) { - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; - int i; - radeonFlush(ctx); - - if (radeon->radeonScreen->kernel_mm) { - for (i = 0; i < fb->_NumColorDrawBuffers; i++) { - struct radeon_renderbuffer *rrb; - rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; - if (rrb->bo) - radeon_bo_wait(rrb->bo); - } - } else if (radeon->do_irqs) { - LOCK_HARDWARE(radeon); - radeonEmitIrqLocked(radeon); - UNLOCK_HARDWARE(radeon); - radeonWaitIrq(radeon); - } else { - radeonWaitForIdle(radeon); - } + radeon_common_finish(ctx); } diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 723f7d14fd5..d157c93dcb2 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -311,6 +311,9 @@ struct radeon_context { struct { void (*get_lock)(radeonContextPtr radeon); void (*update_viewport_offset)(GLcontext *ctx); + void (*flush)(GLcontext *ctx); + void (*set_all_dirty)(GLcontext *ctx); + void (*update_draw_buffer)(GLcontext *ctx); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 3bfb61a0841..b14ca8b51b2 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -33,6 +33,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Keith Whitwell */ +#include #include "main/glheader.h" #include "main/imports.h" #include "main/api_arrayelt.h" @@ -47,11 +48,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "drirenderbuffer.h" +#include "vblank.h" + + #include "dri_util.h" #include "radeon_drm.h" #include "radeon_screen.h" +#include "radeon_buffer.h" #include "common_context.h" #include "common_misc.h" +#include "common_lock.h" + /* ============================================================= * Scissoring */ @@ -185,3 +193,335 @@ void radeonUpdateScissor( GLcontext *ctx ) radeonRecalcScissorRects( rmesa ); } } + +/* ================================================================ + * SwapBuffers with client-side throttling + */ + +static uint32_t radeonGetLastFrame(radeonContextPtr radeon) +{ + drm_radeon_getparam_t gp; + int ret; + uint32_t frame; + + gp.param = RADEON_PARAM_LAST_FRAME; + gp.value = (int *)&frame; + ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, + ret); + exit(1); + } + + return frame; +} + +uint32_t radeonGetAge(radeonContextPtr radeon) +{ + drm_radeon_getparam_t gp; + int ret; + uint32_t age; + + gp.param = RADEON_PARAM_LAST_CLEAR; + gp.value = (int *)&age; + ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, + ret); + exit(1); + } + + return age; +} + +static void radeonEmitIrqLocked(radeonContextPtr radeon) +{ + drm_radeon_irq_emit_t ie; + int ret; + + ie.irq_seq = &radeon->iw.irq_seq; + ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_IRQ_EMIT, + &ie, sizeof(ie)); + if (ret) { + fprintf(stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, + ret); + exit(1); + } +} + +static void radeonWaitIrq(radeonContextPtr radeon) +{ + int ret; + + do { + ret = drmCommandWrite(radeon->dri.fd, DRM_RADEON_IRQ_WAIT, + &radeon->iw, sizeof(radeon->iw)); + } while (ret && (errno == EINTR || errno == EBUSY)); + + if (ret) { + fprintf(stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, + ret); + exit(1); + } +} + +static void radeonWaitForFrameCompletion(radeonContextPtr radeon) +{ + drm_radeon_sarea_t *sarea = radeon->sarea; + + if (radeon->do_irqs) { + if (radeonGetLastFrame(radeon) < sarea->last_frame) { + if (!radeon->irqsEmitted) { + while (radeonGetLastFrame(radeon) < + sarea->last_frame) ; + } else { + UNLOCK_HARDWARE(radeon); + radeonWaitIrq(radeon); + LOCK_HARDWARE(radeon); + } + radeon->irqsEmitted = 10; + } + + if (radeon->irqsEmitted) { + radeonEmitIrqLocked(radeon); + radeon->irqsEmitted--; + } + } else { + while (radeonGetLastFrame(radeon) < sarea->last_frame) { + UNLOCK_HARDWARE(radeon); + if (radeon->do_usleeps) + DO_USLEEP(1); + LOCK_HARDWARE(radeon); + } + } +} + +/* wait for idle */ +void radeonWaitForIdleLocked(radeonContextPtr radeon) +{ + int ret; + int i = 0; + + do { + ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_CP_IDLE); + if (ret) + DO_USLEEP(1); + } while (ret && ++i < 100); + + if (ret < 0) { + UNLOCK_HARDWARE(radeon); + fprintf(stderr, "Error: R300 timed out... exiting\n"); + exit(-1); + } +} + +static void radeonWaitForIdle(radeonContextPtr radeon) +{ + LOCK_HARDWARE(radeon); + radeonWaitForIdleLocked(radeon); + UNLOCK_HARDWARE(radeon); +} + + +/* Copy the back color buffer to the front color buffer. + */ +void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, + const drm_clip_rect_t *rect) +{ + GLcontext *ctx; + radeonContextPtr rmesa; + GLint nbox, i, ret; + GLboolean missed_target; + int64_t ust; + __DRIscreenPrivate *psp; + + assert(dPriv); + assert(dPriv->driContextPriv); + assert(dPriv->driContextPriv->driverPrivate); + + ctx = (GLcontext *) dPriv->driContextPriv->driverPrivate; + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + +/// if ( RADEON_DEBUG & DEBUG_IOCTL ) { +// fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); +// } + + rmesa->vtbl.flush(ctx); + LOCK_HARDWARE( rmesa ); + + /* Throttle the frame rate -- only allow one pending swap buffers + * request at a time. + */ + radeonWaitForFrameCompletion( rmesa ); + if (!rect) + { + UNLOCK_HARDWARE( rmesa ); + driWaitForVBlank( dPriv, & missed_target ); + LOCK_HARDWARE( rmesa ); + } + + nbox = dPriv->numClipRects; /* must be in locked region */ + + for ( i = 0 ; i < nbox ; ) { + GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); + drm_clip_rect_t *box = dPriv->pClipRects; + drm_clip_rect_t *b = rmesa->sarea->boxes; + GLint n = 0; + + for ( ; i < nr ; i++ ) { + + *b = box[i]; + + if (rect) + { + if (rect->x1 > b->x1) + b->x1 = rect->x1; + if (rect->y1 > b->y1) + b->y1 = rect->y1; + if (rect->x2 < b->x2) + b->x2 = rect->x2; + if (rect->y2 < b->y2) + b->y2 = rect->y2; + + if (b->x1 >= b->x2 || b->y1 >= b->y2) + continue; + } + + b++; + n++; + } + rmesa->sarea->nbox = n; + + if (!n) + continue; + + ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); + + if ( ret ) { + fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); + UNLOCK_HARDWARE( rmesa ); + exit( 1 ); + } + } + + UNLOCK_HARDWARE( rmesa ); + if (!rect) + { + psp = dPriv->driScreenPriv; + rmesa->swap_count++; + (*psp->systemTime->getUST)( & ust ); + if ( missed_target ) { + rmesa->swap_missed_count++; + rmesa->swap_missed_ust = ust - rmesa->swap_ust; + } + + rmesa->swap_ust = ust; + rmesa->vtbl.set_all_dirty(ctx); + + } +} + +void radeonPageFlip( __DRIdrawablePrivate *dPriv ) +{ + radeonContextPtr rmesa; + GLint ret; + GLboolean missed_target; + __DRIscreenPrivate *psp; + struct radeon_renderbuffer *rrb; + GLframebuffer *fb = dPriv->driverPrivate; + + assert(dPriv); + assert(dPriv->driContextPriv); + assert(dPriv->driContextPriv->driverPrivate); + + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + + psp = dPriv->driScreenPriv; + +#if 0 + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, + rmesa->sarea->pfCurrentPage); + } +#endif + + rmesa->vtbl.flush(rmesa->glCtx); + + LOCK_HARDWARE( rmesa ); + + if (!dPriv->numClipRects) { + UNLOCK_HARDWARE(rmesa); + usleep(10000); /* throttle invisible client 10ms */ + return; + } + + drm_clip_rect_t *box = dPriv->pClipRects; + drm_clip_rect_t *b = rmesa->sarea->boxes; + b[0] = box[0]; + rmesa->sarea->nbox = 1; + + /* Throttle the frame rate -- only allow a few pending swap buffers + * request at a time. + */ + radeonWaitForFrameCompletion( rmesa ); + UNLOCK_HARDWARE( rmesa ); + driWaitForVBlank( dPriv, & missed_target ); + if ( missed_target ) { + rmesa->swap_missed_count++; + (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); + } + LOCK_HARDWARE( rmesa ); + + ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); + + UNLOCK_HARDWARE( rmesa ); + + if ( ret ) { + fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); + exit( 1 ); + } + + rmesa->swap_count++; + (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); + + /* Get ready for drawing next frame. Update the renderbuffers' + * flippedOffset/Pitch fields so we draw into the right place. + */ + driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, + rmesa->sarea->pfCurrentPage); + + rmesa->state.color.rrb = rrb; + + if (rmesa->vtbl.update_draw_buffer) + rmesa->vtbl.update_draw_buffer(rmesa->glCtx); +} + + +/* Make sure all commands have been sent to the hardware and have + * completed processing. + */ +void radeon_common_finish(GLcontext * ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct gl_framebuffer *fb = ctx->DrawBuffer; + int i; + + if (radeon->radeonScreen->kernel_mm) { + for (i = 0; i < fb->_NumColorDrawBuffers; i++) { + struct radeon_renderbuffer *rrb; + rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; + if (rrb->bo) + radeon_bo_wait(rrb->bo); + } + } else if (radeon->do_irqs) { + LOCK_HARDWARE(radeon); + radeonEmitIrqLocked(radeon); + UNLOCK_HARDWARE(radeon); + radeonWaitIrq(radeon); + } else { + radeonWaitForIdle(radeon); + } +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 5653ef31830..27e869d4bbb 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -5,4 +5,11 @@ void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); +void radeonWaitForIdleLocked(radeonContextPtr radeon); +extern uint32_t radeonGetAge(radeonContextPtr radeon); +void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, + const drm_clip_rect_t *rect); +void radeonPageFlip( __DRIdrawablePrivate *dPriv ); +void radeon_common_finish(GLcontext * ctx); + #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index e49be4b23be..ab2002cd903 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -218,10 +218,24 @@ static void r100_get_lock(radeonContextPtr radeon) } } +static void r100_vtbl_flush(GLcontext *ctx) +{ + RADEON_FIREVERTICES(R100_CONTEXT(ctx)); +} + +static void r100_vtbl_set_all_dirty(GLcontext *ctx) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + rmesa->hw.all_dirty = GL_TRUE; +} + static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; + radeon->vtbl.flush = r100_vtbl_flush; + radeon->vtbl.set_all_dirty = r100_vtbl_set_all_dirty; + radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; } /* Create the device specific context. diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 31f4778faba..2b02d0b71fc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -58,7 +58,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_IDLE_RETRY 16 -static void radeonWaitForIdle( r100ContextPtr rmesa ); static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, const char * caller ); @@ -592,7 +591,7 @@ static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, if (RADEON_DEBUG & DEBUG_SYNC) { fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__); - radeonWaitForIdleLocked( rmesa ); + radeonWaitForIdleLocked( &rmesa->radeon ); } out: @@ -678,7 +677,7 @@ void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ) if (RADEON_DEBUG & DEBUG_DMA) fprintf(stderr, "Waiting for buffers\n"); - radeonWaitForIdleLocked( rmesa ); + radeonWaitForIdleLocked( &rmesa->radeon ); ret = drmDMA( fd, &dma ); if ( ret != 0 ) { @@ -774,254 +773,6 @@ void radeonAllocDmaRegion( r100ContextPtr rmesa, rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; } -/* ================================================================ - * SwapBuffers with client-side throttling - */ - -static uint32_t radeonGetLastFrame (r100ContextPtr rmesa) -{ - drm_radeon_getparam_t gp; - int ret; - uint32_t frame; - - gp.param = RADEON_PARAM_LAST_FRAME; - gp.value = (int *)&frame; - ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp) ); - - if ( ret ) { - fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret ); - exit(1); - } - - return frame; -} - -static void radeonEmitIrqLocked( r100ContextPtr rmesa ) -{ - drm_radeon_irq_emit_t ie; - int ret; - - ie.irq_seq = &rmesa->radeon.iw.irq_seq; - ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_EMIT, - &ie, sizeof(ie) ); - if ( ret ) { - fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret ); - exit(1); - } -} - - -static void radeonWaitIrq( r100ContextPtr rmesa ) -{ - int ret; - - do { - ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_WAIT, - &rmesa->radeon.iw, sizeof(rmesa->radeon.iw) ); - } while (ret && (errno == EINTR || errno == EBUSY)); - - if ( ret ) { - fprintf( stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, ret ); - exit(1); - } -} - - -static void radeonWaitForFrameCompletion( r100ContextPtr rmesa ) -{ - drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - - if (rmesa->radeon.do_irqs) { - if (radeonGetLastFrame(rmesa) < sarea->last_frame) { - if (!rmesa->radeon.irqsEmitted) { - while (radeonGetLastFrame (rmesa) < sarea->last_frame) - ; - } - else { - UNLOCK_HARDWARE( &rmesa->radeon ); - radeonWaitIrq( rmesa ); - LOCK_HARDWARE( &rmesa->radeon ); - } - rmesa->radeon.irqsEmitted = 10; - } - - if (rmesa->radeon.irqsEmitted) { - radeonEmitIrqLocked( rmesa ); - rmesa->radeon.irqsEmitted--; - } - } - else { - while (radeonGetLastFrame (rmesa) < sarea->last_frame) { - UNLOCK_HARDWARE( &rmesa->radeon ); - if (rmesa->radeon.do_usleeps) - DO_USLEEP( 1 ); - LOCK_HARDWARE( &rmesa->radeon ); - } - } -} - -/* Copy the back color buffer to the front color buffer. - */ -void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, - const drm_clip_rect_t *rect) -{ - r100ContextPtr rmesa; - GLint nbox, i, ret; - GLboolean missed_target; - int64_t ust; - __DRIscreenPrivate *psp; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate; - - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->radeon.glCtx ); - } - - RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( &rmesa->radeon ); - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion( rmesa ); - if (!rect) - { - UNLOCK_HARDWARE( &rmesa->radeon ); - driWaitForVBlank( dPriv, & missed_target ); - LOCK_HARDWARE( &rmesa->radeon ); - } - - nbox = dPriv->numClipRects; /* must be in locked region */ - - for ( i = 0 ; i < nbox ; ) { - GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; - GLint n = 0; - - for ( ; i < nr ; i++ ) { - - *b = box[i]; - - if (rect) - { - if (rect->x1 > b->x1) - b->x1 = rect->x1; - if (rect->y1 > b->y1) - b->y1 = rect->y1; - if (rect->x2 < b->x2) - b->x2 = rect->x2; - if (rect->y2 < b->y2) - b->y2 = rect->y2; - - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } - - b++; - n++; - } - rmesa->radeon.sarea->nbox = n; - - if (!n) - continue; - - ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_SWAP ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( &rmesa->radeon ); - exit( 1 ); - } - } - - UNLOCK_HARDWARE( &rmesa->radeon ); - if (!rect) - { - psp = dPriv->driScreenPriv; - rmesa->radeon.swap_count++; - (*psp->systemTime->getUST)( & ust ); - if ( missed_target ) { - rmesa->radeon.swap_missed_count++; - rmesa->radeon.swap_missed_ust = ust - rmesa->radeon.swap_ust; - } - - rmesa->radeon.swap_ust = ust; - rmesa->hw.all_dirty = GL_TRUE; - } -} - -void radeonPageFlip( __DRIdrawablePrivate *dPriv ) -{ - r100ContextPtr rmesa; - GLint ret; - GLboolean missed_target; - __DRIscreenPrivate *psp; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate; - psp = dPriv->driScreenPriv; - - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->radeon.sarea->pfCurrentPage); - } - - RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( &rmesa->radeon ); - - /* Need to do this for the perf box placement: - */ - if (dPriv->numClipRects) - { - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->radeon.sarea->boxes; - b[0] = box[0]; - rmesa->radeon.sarea->nbox = 1; - } - - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion( rmesa ); - UNLOCK_HARDWARE( &rmesa->radeon ); - driWaitForVBlank( dPriv, & missed_target ); - if ( missed_target ) { - rmesa->radeon.swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust ); - } - LOCK_HARDWARE( &rmesa->radeon ); - - ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); - } - - rmesa->radeon.swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_ust ); - - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. - */ - driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, - rmesa->radeon.sarea->pfCurrentPage); - - radeonUpdateDrawBuffer(rmesa->radeon.glCtx); -} - - /* ================================================================ * Buffer clear */ @@ -1207,37 +958,6 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) rmesa->hw.all_dirty = GL_TRUE; } - -void radeonWaitForIdleLocked( r100ContextPtr rmesa ) -{ - int fd = rmesa->radeon.dri.fd; - int to = 0; - int ret, i = 0; - - rmesa->c_drawWaits++; - - do { - do { - ret = drmCommandNone( fd, DRM_RADEON_CP_IDLE); - } while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY ); - } while ( ( ret == -EBUSY ) && ( to++ < RADEON_TIMEOUT ) ); - - if ( ret < 0 ) { - UNLOCK_HARDWARE( &rmesa->radeon ); - fprintf( stderr, "Error: Radeon timed out... exiting\n" ); - exit( -1 ); - } -} - - -static void radeonWaitForIdle( r100ContextPtr rmesa ) -{ - LOCK_HARDWARE(&rmesa->radeon); - radeonWaitForIdleLocked( rmesa ); - UNLOCK_HARDWARE(&rmesa->radeon); -} - - void radeonFlush( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT( ctx ); @@ -1259,17 +979,8 @@ void radeonFlush( GLcontext *ctx ) */ void radeonFinish( GLcontext *ctx ) { - r100ContextPtr rmesa = R100_CONTEXT(ctx); radeonFlush( ctx ); - - if (rmesa->radeon.do_irqs) { - LOCK_HARDWARE( &rmesa->radeon ); - radeonEmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( &rmesa->radeon ); - radeonWaitIrq( rmesa ); - } - else - radeonWaitForIdle( rmesa ); + radeon_common_finish(ctx); } diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index c97f41d9a1f..d11feb58043 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -87,13 +87,8 @@ extern void radeonReleaseDmaRegion( r100ContextPtr rmesa, struct radeon_dma_region *region, const char *caller ); -extern void radeonCopyBuffer( __DRIdrawablePrivate *drawable, - const drm_clip_rect_t *rect); -extern void radeonPageFlip( __DRIdrawablePrivate *drawable ); extern void radeonFlush( GLcontext *ctx ); extern void radeonFinish( GLcontext *ctx ); -extern void radeonWaitForIdleLocked( r100ContextPtr rmesa ); -extern void radeonWaitForVBlank( r100ContextPtr rmesa ); extern void radeonInitIoctlFuncs( GLcontext *ctx ); extern void radeonGetAllParams( r100ContextPtr rmesa ); extern void radeonSetUpAtomList( r100ContextPtr rmesa ); -- cgit v1.2.3 From 44b916b2c0af0b451b8c45d5872663e61d9110e5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 13:38:03 +1000 Subject: radeon: remove old lock code --- src/mesa/drivers/dri/r200/r200_lock.c | 116 --------------------------- src/mesa/drivers/dri/r300/radeon_lock.c | 129 ------------------------------ src/mesa/drivers/dri/radeon/radeon_lock.c | 124 ---------------------------- 3 files changed, 369 deletions(-) delete mode 100644 src/mesa/drivers/dri/r200/r200_lock.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_lock.c delete mode 100644 src/mesa/drivers/dri/radeon/radeon_lock.c (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_lock.c b/src/mesa/drivers/dri/r200/r200_lock.c deleted file mode 100644 index c79603cdd5a..00000000000 --- a/src/mesa/drivers/dri/r200/r200_lock.c +++ /dev/null @@ -1,116 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include "r200_context.h" -#include "r200_lock.h" -#include "r200_tex.h" -#include "r200_state.h" -#include "r200_ioctl.h" - -#include "drirenderbuffer.h" - - -#if DEBUG_LOCKING -char *prevLockFile = NULL; -int prevLockLine = 0; -#endif - -/* Turn on/off page flipping according to the flags in the sarea: - */ -static void -r200UpdatePageFlipping( r200ContextPtr rmesa ) -{ - rmesa->radeon.doPageFlip = rmesa->radeon.sarea->pfState; - if (rmesa->radeon.glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, - rmesa->radeon.sarea->pfCurrentPage); - } -} - - - -/* Update the hardware state. This is called if another main/context.has - * grabbed the hardware lock, which includes the X server. This - * function also updates the driver's window state after the X server - * moves, resizes or restacks a window -- the change will be reflected - * in the drawable position and clip rects. Since the X server grabs - * the hardware lock when it changes the window state, this routine will - * automatically be called after such a change. - */ -void r200GetLock( r200ContextPtr rmesa, GLuint flags ) -{ - __DRIdrawablePrivate *drawable = rmesa->radeon.dri.drawable; - __DRIdrawablePrivate *readable = rmesa->radeon.dri.readable; - __DRIscreenPrivate *sPriv = rmesa->radeon.dri.screen; - drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - int i; - - drmGetLock( rmesa->radeon.dri.fd, rmesa->radeon.dri.hwContext, flags ); - - /* The window might have moved, so we might need to get new clip - * rects. - * - * NOTE: This releases and regrabs the hw lock to allow the X server - * to respond to the DRI protocol request for new drawable info. - * Since the hardware state depends on having the latest drawable - * clip rects, all state checking must be done _after_ this call. - */ - DRI_VALIDATE_DRAWABLE_INFO( sPriv, drawable ); - if (drawable != readable) { - DRI_VALIDATE_DRAWABLE_INFO( sPriv, readable ); - } - - if ( rmesa->radeon.lastStamp != drawable->lastStamp ) { - r200UpdatePageFlipping( rmesa ); - r200SetCliprects( rmesa ); - r200UpdateViewportOffset( rmesa->radeon.glCtx ); - driUpdateFramebufferSize(rmesa->radeon.glCtx, drawable); - } - - R200_STATECHANGE( rmesa, ctx ); - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; - } - else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE; - - if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) { - sarea->ctx_owner = rmesa->radeon.dri.hwContext; - } - - for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { - DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] ); - } - - rmesa->radeon.lost_context = GL_TRUE; -} diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c deleted file mode 100644 index a1b21634410..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ /dev/null @@ -1,129 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Gareth Hughes - * Keith Whitwell - * Kevin E. Martin - */ - -#include "radeon_lock.h" -#include "radeon_ioctl.h" -#include "radeon_state.h" -#include "r300_context.h" -#include "r300_state.h" - -#include "main/framebuffer.h" - -#include "drirenderbuffer.h" - -#if DEBUG_LOCKING -char *prevLockFile = NULL; -int prevLockLine = 0; -#endif - -/* Turn on/off page flipping according to the flags in the sarea: - */ -void radeonUpdatePageFlipping(radeonContextPtr rmesa) -{ - int use_back; - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - GLframebuffer *fb = drawable->driverPrivate; - - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - r300UpdateDrawBuffer(rmesa->glCtx); - } - - use_back = rmesa->glCtx->DrawBuffer ? - (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == - BUFFER_BACK_LEFT) : 1; - use_back ^= (rmesa->sarea->pfCurrentPage == 1); - - if (use_back) - rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - else - rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - - rmesa->state.depth_buffer = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; -} - -/* Update the hardware state. This is called if another context has - * grabbed the hardware lock, which includes the X server. This - * function also updates the driver's window state after the X server - * moves, resizes or restacks a window -- the change will be reflected - * in the drawable position and clip rects. Since the X server grabs - * the hardware lock when it changes the window state, this routine will - * automatically be called after such a change. - */ -void radeonGetLock(radeonContextPtr rmesa, GLuint flags) -{ - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->dri.readable; - __DRIscreenPrivate *sPriv = rmesa->dri.screen; - drm_radeon_sarea_t *sarea = rmesa->sarea; - - assert(drawable != NULL); - - drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); - - /* The window might have moved, so we might need to get new clip - * rects. - * - * NOTE: This releases and regrabs the hw lock to allow the X server - * to respond to the DRI protocol request for new drawable info. - * Since the hardware state depends on having the latest drawable - * clip rects, all state checking must be done _after_ this call. - */ - DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); - if (drawable != readable) { - DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); - } - - if (rmesa->lastStamp != drawable->lastStamp) { - radeonUpdatePageFlipping(rmesa); - radeonSetCliprects(rmesa); - r300UpdateViewportOffset(rmesa->glCtx); - driUpdateFramebufferSize(rmesa->glCtx, drawable); - } - - if (sarea->ctx_owner != rmesa->dri.hwContext) { - sarea->ctx_owner = rmesa->dri.hwContext; - if (!rmesa->radeonScreen->kernel_mm) - radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); - } - - rmesa->lost_context = GL_TRUE; -} diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c deleted file mode 100644 index 0cf5574ba6e..00000000000 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ /dev/null @@ -1,124 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Gareth Hughes - * Keith Whitwell - * Kevin E. Martin - */ - -#include "main/glheader.h" -#include "main/mtypes.h" -#include "radeon_context.h" -#include "radeon_lock.h" -#include "radeon_tex.h" -#include "radeon_state.h" -#include "radeon_ioctl.h" - -#include "drirenderbuffer.h" - -#if DEBUG_LOCKING -char *prevLockFile = NULL; -int prevLockLine = 0; -#endif - -/* Turn on/off page flipping according to the flags in the sarea: - */ -static void radeonUpdatePageFlipping(r100ContextPtr rmesa) -{ - rmesa->radeon.doPageFlip = rmesa->radeon.sarea->pfState; - if (rmesa->radeon.glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer, - rmesa->radeon.sarea->pfCurrentPage); - } -} - -/* Update the hardware state. This is called if another context has - * grabbed the hardware lock, which includes the X server. This - * function also updates the driver's window state after the X server - * moves, resizes or restacks a window -- the change will be reflected - * in the drawable position and clip rects. Since the X server grabs - * the hardware lock when it changes the window state, this routine will - * automatically be called after such a change. - */ -void radeonGetLock(r100ContextPtr rmesa, GLuint flags) -{ - __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable; - __DRIscreenPrivate *sPriv = rmesa->radeon.dri.screen; - drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - - drmGetLock(rmesa->radeon.dri.fd, rmesa->radeon.dri.hwContext, flags); - - /* The window might have moved, so we might need to get new clip - * rects. - * - * NOTE: This releases and regrabs the hw lock to allow the X server - * to respond to the DRI protocol request for new drawable info. - * Since the hardware state depends on having the latest drawable - * clip rects, all state checking must be done _after_ this call. - */ - DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); - if (drawable != readable) { - DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); - } - - if (rmesa->radeon.lastStamp != drawable->lastStamp) { - radeonUpdatePageFlipping(rmesa); - radeonSetCliprects(rmesa); - radeonUpdateViewportOffset(rmesa->radeon.glCtx); - driUpdateFramebufferSize(rmesa->radeon.glCtx, drawable); - } - - RADEON_STATECHANGE(rmesa, ctx); - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= - RADEON_COLOR_TILE_ENABLE; - } else { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= - ~RADEON_COLOR_TILE_ENABLE; - } - - if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { - int i; - sarea->ctx_owner = rmesa->radeon.dri.hwContext; - - for (i = 0; i < rmesa->radeon.nr_heaps; i++) { - DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]); - } - } - - rmesa->radeon.lost_context = GL_TRUE; -} -- cgit v1.2.3 From 23295cf8e84495af86f62395d32b3116261927e8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 13:38:12 +1000 Subject: radeon/r200/r300: consolidate swap buffers --- src/mesa/drivers/dri/r200/r200_context.c | 52 ---------------------- src/mesa/drivers/dri/r200/r200_context.h | 10 +---- src/mesa/drivers/dri/r300/r300_context.c | 1 + src/mesa/drivers/dri/r300/radeon_context.c | 54 ----------------------- src/mesa/drivers/dri/r300/radeon_context.h | 1 - src/mesa/drivers/dri/radeon/common_context.h | 11 +++++ src/mesa/drivers/dri/radeon/common_lock.c | 3 +- src/mesa/drivers/dri/radeon/common_misc.c | 64 +++++++++++++++++++++++++--- src/mesa/drivers/dri/radeon/common_misc.h | 5 +++ src/mesa/drivers/dri/radeon/radeon_context.c | 55 ------------------------ src/mesa/drivers/dri/radeon/radeon_context.h | 12 ------ src/mesa/drivers/dri/radeon/radeon_screen.c | 4 +- 12 files changed, 80 insertions(+), 192 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 85e508616b4..fd41171de81 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -640,58 +640,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) } } - - - -void -r200SwapBuffers( __DRIdrawablePrivate *dPriv ) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - r200ContextPtr rmesa; - GLcontext *ctx; - rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = rmesa->radeon.glCtx; - if (ctx->Visual.doubleBufferMode) { - _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ - if ( rmesa->radeon.doPageFlip ) { - r200PageFlip( dPriv ); - } - else { - radeonCopyBuffer( dPriv, NULL ); - } - } - } - else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__); - } -} - -void -r200CopySubBuffer( __DRIdrawablePrivate *dPriv, - int x, int y, int w, int h ) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - r200ContextPtr rmesa; - GLcontext *ctx; - rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = rmesa->radeon.glCtx; - if (ctx->Visual.doubleBufferMode) { - drm_clip_rect_t rect; - rect.x1 = x + dPriv->x; - rect.y1 = (dPriv->h - y - h) + dPriv->y; - rect.x2 = rect.x1 + w; - rect.y2 = rect.y1 + h; - _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ - radeonCopyBuffer( dPriv, &rect ); - } - } - else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__); - } -} - /* Force the context `c' to be the current context and associate with it * buffer `b'. */ diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 94f9b86d2f2..c1a68aa6941 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -677,9 +677,6 @@ extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, __DRIcontextPrivate *driContextPriv, void *sharedContextPrivate); -extern void r200SwapBuffers( __DRIdrawablePrivate *dPriv ); -extern void r200CopySubBuffer( __DRIdrawablePrivate * dPriv, - int x, int y, int w, int h ); extern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, __DRIdrawablePrivate *driDrawPriv, __DRIdrawablePrivate *driReadPriv ); @@ -688,13 +685,8 @@ extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); /* ================================================================ * Debugging: */ -#define DO_DEBUG 1 -#if DO_DEBUG -extern int R200_DEBUG; -#else -#define R200_DEBUG 0 -#endif +#define R200_DEBUG RADEON_DEBUG diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3b8ba855bb5..974cf5fcef6 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -215,6 +215,7 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; radeon->vtbl.flush = r300_vtbl_flush; radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty; + radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; } diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 092562b8f97..96478640cc1 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -248,60 +248,6 @@ void radeonCleanupContext(radeonContextPtr radeon) } } - -/** - * Swap front and back buffer. - */ -void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - radeonContextPtr radeon; - GLcontext *ctx; - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = radeon->glCtx; - - if (ctx->Visual.doubleBufferMode) { - _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ - if (radeon->doPageFlip) { - radeonPageFlip(dPriv); - } else { - radeonCopyBuffer(dPriv, NULL); - } - } - } else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", - __FUNCTION__); - } -} - -void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h ) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - radeonContextPtr radeon; - GLcontext *ctx; - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = radeon->glCtx; - - if (ctx->Visual.doubleBufferMode) { - drm_clip_rect_t rect; - rect.x1 = x + dPriv->x; - rect.y1 = (dPriv->h - y - h) + dPriv->y; - rect.x2 = rect.x1 + w; - rect.y2 = rect.y1 + h; - _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ - radeonCopyBuffer(dPriv, &rect); - } - } else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", - __FUNCTION__); - } -} - static void radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, GLframebuffer *draw) diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index d46a2d20ff3..be21a8cfbc9 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -89,7 +89,6 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); #endif -extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h); extern GLboolean radeonInitContext(radeonContextPtr radeon, diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index d157c93dcb2..e4d210392c4 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -319,4 +319,15 @@ struct radeon_context { #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) +/* ================================================================ + * Debugging: + */ +#define DO_DEBUG 1 + +#if DO_DEBUG +extern int RADEON_DEBUG; +#else +#define RADEON_DEBUG 0 +#endif + #endif diff --git a/src/mesa/drivers/dri/radeon/common_lock.c b/src/mesa/drivers/dri/radeon/common_lock.c index fe38fc95bc9..d983e8ce926 100644 --- a/src/mesa/drivers/dri/radeon/common_lock.c +++ b/src/mesa/drivers/dri/radeon/common_lock.c @@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_screen.h" #include "common_context.h" #include "common_lock.h" +#include "common_misc.h" #include "drirenderbuffer.h" @@ -65,7 +66,7 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) rmesa->doPageFlip = rmesa->sarea->pfState; if (rmesa->glCtx->WinSysDrawBuffer) { - r300UpdateDrawBuffer(rmesa->glCtx); + rmesa->vtbl.update_draw_buffer(rmesa->glCtx); } use_back = rmesa->glCtx->DrawBuffer ? diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index b14ca8b51b2..eab9cc74e32 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -344,9 +344,9 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, ctx = (GLcontext *) dPriv->driContextPriv->driverPrivate; rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; -/// if ( RADEON_DEBUG & DEBUG_IOCTL ) { -// fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); -// } + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); + } rmesa->vtbl.flush(ctx); LOCK_HARDWARE( rmesa ); @@ -437,16 +437,14 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) assert(dPriv->driContextPriv->driverPrivate); rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; psp = dPriv->driScreenPriv; -#if 0 if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, rmesa->sarea->pfCurrentPage); } -#endif rmesa->vtbl.flush(rmesa->glCtx); @@ -525,3 +523,57 @@ void radeon_common_finish(GLcontext * ctx) radeonWaitForIdle(radeon); } } + +/** + * Swap front and back buffer. + */ +void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) +{ + if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { + radeonContextPtr radeon; + GLcontext *ctx; + + radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + ctx = radeon->glCtx; + + if (ctx->Visual.doubleBufferMode) { + _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ + if (radeon->doPageFlip) { + radeonPageFlip(dPriv); + } else { + radeonCopyBuffer(dPriv, NULL); + } + } + } else { + /* XXX this shouldn't be an error but we can't handle it for now */ + _mesa_problem(NULL, "%s: drawable has no context!", + __FUNCTION__); + } +} + +void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, + int x, int y, int w, int h ) +{ + if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { + radeonContextPtr radeon; + GLcontext *ctx; + + radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + ctx = radeon->glCtx; + + if (ctx->Visual.doubleBufferMode) { + drm_clip_rect_t rect; + rect.x1 = x + dPriv->x; + rect.y1 = (dPriv->h - y - h) + dPriv->y; + rect.x2 = rect.x1 + w; + rect.y2 = rect.y1 + h; + _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ + radeonCopyBuffer(dPriv, &rect); + } + } else { + /* XXX this shouldn't be an error but we can't handle it for now */ + _mesa_problem(NULL, "%s: drawable has no context!", + __FUNCTION__); + } +} + diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 27e869d4bbb..cc4832c75ee 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -11,5 +11,10 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, const drm_clip_rect_t *rect); void radeonPageFlip( __DRIdrawablePrivate *dPriv ); void radeon_common_finish(GLcontext * ctx); +void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); +void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, + int x, int y, int w, int h ); + +void radeonUpdatePageFlipping(radeonContextPtr rmesa); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index ab2002cd903..1adef7c7020 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -563,61 +563,6 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) } } - - - -void -radeonSwapBuffers( __DRIdrawablePrivate *dPriv ) -{ - - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - r100ContextPtr rmesa; - GLcontext *ctx; - rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = rmesa->radeon.glCtx; - if (ctx->Visual.doubleBufferMode) { - _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ - - if ( rmesa->radeon.doPageFlip ) { - radeonPageFlip( dPriv ); - } - else { - radeonCopyBuffer( dPriv, NULL ); - } - } - } - else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__); - } -} - -void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h ) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - radeonContextPtr radeon; - GLcontext *ctx; - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = radeon->glCtx; - - if (ctx->Visual.doubleBufferMode) { - drm_clip_rect_t rect; - rect.x1 = x + dPriv->x; - rect.y1 = (dPriv->h - y - h) + dPriv->y; - rect.x2 = rect.x1 + w; - rect.y2 = rect.y1 + h; - _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ - radeonCopyBuffer(dPriv, &rect); - } - } else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", - __FUNCTION__); - } -} - /* Make context `c' the current context and bind it to the given * drawing and reading surfaces. */ diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 0ca49cc078d..dedc3626040 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -476,23 +476,11 @@ extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); -extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); -extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h); extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv); extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); -/* ================================================================ - * Debugging: - */ -#define DO_DEBUG 1 -#if DO_DEBUG -extern int RADEON_DEBUG; -#else -#define RADEON_DEBUG 0 -#endif #endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 0b64d6f4ac5..c099d0ee349 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1620,7 +1620,7 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyContext = r200DestroyContext, .CreateBuffer = radeonCreateBuffer, .DestroyBuffer = radeonDestroyBuffer, - .SwapBuffers = r200SwapBuffers, + .SwapBuffers = radeonSwapBuffers, .MakeCurrent = r200MakeCurrent, .UnbindContext = r200UnbindContext, .GetSwapInfo = getSwapInfo, @@ -1628,7 +1628,7 @@ const struct __DriverAPIRec driDriverAPI = { .WaitForMSC = driWaitForMSC32, .WaitForSBC = NULL, .SwapBuffersMSC = NULL, - .CopySubBuffer = r200CopySubBuffer, + .CopySubBuffer = radeonCopySubBuffer, }; #endif -- cgit v1.2.3 From 61da612a4f8862e0aac4ff4fc87c133cb8a1c4a5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 15:12:57 +1000 Subject: r300: start moving new r300 cmdbuf into common code --- src/mesa/drivers/dri/r200/Makefile | 2 + src/mesa/drivers/dri/r200/r200_state.c | 4 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 108 +++--------------------- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 13 ++- src/mesa/drivers/dri/r300/r300_context.c | 3 +- src/mesa/drivers/dri/r300/r300_context.h | 17 +--- src/mesa/drivers/dri/r300/r300_ioctl.c | 6 +- src/mesa/drivers/dri/r300/r300_render.c | 10 +-- src/mesa/drivers/dri/r300/r300_swtcl.c | 6 +- src/mesa/drivers/dri/r300/radeon_context.h | 1 - src/mesa/drivers/dri/r300/radeon_lock.h | 74 +--------------- src/mesa/drivers/dri/radeon/common_context.h | 29 +++++-- src/mesa/drivers/dri/radeon/common_lock.c | 2 +- src/mesa/drivers/dri/radeon/common_lock.h | 23 +++-- src/mesa/drivers/dri/radeon/common_misc.c | 112 ++++++++++++++++++++++++- src/mesa/drivers/dri/radeon/common_misc.h | 6 ++ src/mesa/drivers/dri/radeon/radeon_cs_legacy.h | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + 18 files changed, 194 insertions(+), 225 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 34aa74735b8..5ba1603d792 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -51,6 +51,7 @@ COMMON_SYMLINKS = \ radeon_screen.c \ radeon_screen.h \ radeon_bo_legacy.h \ + radeon_cs_legacy.h \ radeon_buffer.h \ common_context.h \ common_lock.c \ @@ -58,6 +59,7 @@ COMMON_SYMLINKS = \ common_misc.h \ common_misc.c + ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 67357fadfd8..997c1711f90 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1711,7 +1711,7 @@ void r200UpdateViewportOffset( GLcontext *ctx ) } } - r200UpdateScissor( ctx ); + radeonUpdateScissor( ctx ); } @@ -2056,7 +2056,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_SCISSOR_TEST: R200_FIREVERTICES( rmesa ); rmesa->radeon.state.scissor.enabled = state; - r200UpdateScissor( ctx ); + radeonUpdateScissor( ctx ); break; case GL_STENCIL_TEST: diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 32d0dcf5472..bbca71dd16a 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -69,70 +69,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define SPACE_FOR_FLUSHING 4 -/** - * Send the current command buffer via ioctl to the hardware. - */ -int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller) -{ - int ret = 0; - - if (r300->cmdbuf.flushing) { - fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n"); - exit(-1); - } - r300->cmdbuf.flushing = 1; - if (r300->cmdbuf.cs->cdw) { - ret = radeon_cs_emit(r300->cmdbuf.cs); - r300->hw.all_dirty = 1; - } - radeon_cs_erase(r300->cmdbuf.cs); - r300->cmdbuf.flushing = 0; - return ret; -} - -int r300FlushCmdBuf(r300ContextPtr r300, const char *caller) -{ - int ret; - - LOCK_HARDWARE(&r300->radeon); - ret = r300FlushCmdBufLocked(r300, caller); - UNLOCK_HARDWARE(&r300->radeon); - - if (ret) { - fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret); - _mesa_exit(ret); - } - - return ret; -} - -/** - * Make sure that enough space is available in the command buffer - * by flushing if necessary. - * - * \param dwords The number of dwords we need to be free on the command buffer - */ -void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller) -{ - if ((r300->cmdbuf.cs->cdw + dwords + 128) > r300->cmdbuf.size || - radeon_cs_need_flush(r300->cmdbuf.cs)) { - r300FlushCmdBuf(r300, caller); - } -} - void r300BeginBatch(r300ContextPtr r300, int n, int dostate, const char *file, const char *function, int line) { - r300EnsureCmdBufSpace(r300, n, function); - if (!r300->cmdbuf.cs->cdw && dostate) { + rcommonEnsureCmdBufSpace(&r300->radeon, n, function); + if (!r300->radeon.cmdbuf.cs->cdw && dostate) { if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "Reemit state after flush (from %s)\n", function); r300EmitState(r300); } - radeon_cs_begin(r300->cmdbuf.cs, n, file, function, line); + radeon_cs_begin(r300->radeon.cmdbuf.cs, n, file, function, line); } static void r300PrintStateAtom(r300ContextPtr r300, @@ -209,15 +158,15 @@ void r300EmitState(r300ContextPtr r300) if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); - if (r300->cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty) + if (r300->radeon.cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty) return; /* To avoid going across the entire set of states multiple times, just check * for enough space for the case of emitting all state. */ - r300EnsureCmdBufSpace(r300, r300->hw.max_state_size, __FUNCTION__); + rcommonEnsureCmdBufSpace(&r300->radeon, r300->hw.max_state_size, __FUNCTION__); - if (!r300->cmdbuf.cs->cdw) { + if (!r300->radeon.cmdbuf.cs->cdw) { if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "Begin reemit state\n"); @@ -473,7 +422,7 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) */ void r300InitCmdBuf(r300ContextPtr r300) { - int size, mtu; + int mtu; int has_tcl = 1; int is_r500 = 0; int i; @@ -770,40 +719,7 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.is_dirty = GL_TRUE; r300->hw.all_dirty = GL_TRUE; - /* Initialize command buffer */ - size = - 256 * driQueryOptioni(&r300->radeon.optionCache, - "command_buffer_size"); - if (size < 2 * r300->hw.max_state_size) { - size = 2 * r300->hw.max_state_size + 65535; - } - if (size > 64 * 256) - size = 64 * 256; - - size = 64 * 1024 / 4; - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { - fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", - sizeof(drm_r300_cmd_header_t)); - fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%zd\n", - sizeof(drm_radeon_cmd_buffer_t)); - fprintf(stderr, - "Allocating %d bytes command buffer (max state is %d bytes)\n", - size * 4, r300->hw.max_state_size * 4); - } - - if (r300->radeon.radeonScreen->kernel_mm) { - int fd = r300->radeon.radeonScreen->driScreen->fd; - r300->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); - } else { - r300->cmdbuf.csm = radeon_cs_manager_legacy_ctor(&r300->radeon); - } - if (r300->cmdbuf.csm == NULL) { - /* FIXME: fatal error */ - return; - } - r300->cmdbuf.cs = radeon_cs_create(r300->cmdbuf.csm, size); - assert(r300->cmdbuf.cs != NULL); - r300->cmdbuf.size = size; + rcommonInitCmdBuf(&r300->radeon, r300->hw.max_state_size); } /** @@ -813,13 +729,9 @@ void r300DestroyCmdBuf(r300ContextPtr r300) { struct radeon_state_atom *atom; - radeon_cs_destroy(r300->cmdbuf.cs); foreach(atom, &r300->hw.atomlist) { FREE(atom->cmd); } - if (r300->radeon.radeonScreen->driScreen->dri2.enabled || r300->radeon.radeonScreen->kernel_mm) { - radeon_cs_manager_gem_dtor(r300->cmdbuf.csm); - } else { - radeon_cs_manager_legacy_dtor(r300->cmdbuf.csm); - } + rcommonDestroyCmdBuf(&r300->radeon); + } diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index f4cc5d3bb12..0c76c6c99a7 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -39,14 +39,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "radeon_cs.h" -extern int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller); -extern int r300FlushCmdBuf(r300ContextPtr r300, const char *caller); extern void r300EmitState(r300ContextPtr r300); extern void r300InitCmdBuf(r300ContextPtr r300); extern void r300DestroyCmdBuf(r300ContextPtr r300); -extern void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller); void r300BeginBatch(r300ContextPtr r300, int n, @@ -78,7 +75,7 @@ void r300BeginBatch(r300ContextPtr r300, */ #define OUT_BATCH(data) \ do { \ - radeon_cs_write_dword(b_l_r300->cmdbuf.cs, data);\ + radeon_cs_write_dword(b_l_r300->radeon.cmdbuf.cs, data);\ } while(0) /** @@ -90,8 +87,8 @@ void r300BeginBatch(r300ContextPtr r300, fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ __FILE__, __FUNCTION__, __LINE__, offset);\ }\ - radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\ - radeon_cs_write_reloc(b_l_r300->cmdbuf.cs, \ + radeon_cs_write_dword(b_l_r300->radeon.cmdbuf.cs, offset);\ + radeon_cs_write_reloc(b_l_r300->radeon.cmdbuf.cs, \ bo, \ rd, \ wd, \ @@ -105,7 +102,7 @@ void r300BeginBatch(r300ContextPtr r300, do { \ int _i; \ for (_i=0; _i < n; _i++) {\ - radeon_cs_write_dword(b_l_r300->cmdbuf.cs, ptr[_i]);\ + radeon_cs_write_dword(b_l_r300->radeon.cmdbuf.cs, ptr[_i]);\ }\ } while(0) @@ -116,7 +113,7 @@ void r300BeginBatch(r300ContextPtr r300, */ #define END_BATCH() \ do { \ - radeon_cs_end(b_l_r300->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ + radeon_cs_end(b_l_r300->radeon.cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ } while(0) /** diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 974cf5fcef6..6b79e7dea3f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -65,6 +65,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_tex.h" #include "r300_emit.h" #include "r300_swtcl.h" +#include "radeon_bo_legacy.h" #include "vblank.h" @@ -443,7 +444,7 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) _vbo_DestroyContext(r300->radeon.glCtx); _swrast_DestroyContext(r300->radeon.glCtx); - r300FlushCmdBuf(r300, __FUNCTION__); + rcommonFlushCmdBuf(&r300->radeon, __FUNCTION__); r300DestroyCmdBuf(r300); if (radeon->state.scissor.pClipRects) { diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index de188c3f361..1a430169f5f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "dri_util.h" #include "texmem.h" +#include "radeon_context.h" #include "radeon_bo.h" #include "main/macros.h" @@ -504,20 +505,6 @@ struct r300_hw_state { r300TexObj *textures[R300_MAX_TEXTURE_UNITS]; }; -/** - * This structure holds the command buffer while it is being constructed. - * - * The first batch of commands in the buffer is always the state that needs - * to be re-emitted when the context is lost. This batch can be skipped - * otherwise. - */ -struct r300_cmdbuf { - struct radeon_cs_manager *csm; - struct radeon_cs *cs; - int size; /** # of dwords total */ - unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ -}; - /** * State cache */ @@ -838,7 +825,7 @@ struct r300_context { struct radeon_context radeon; /* parent class, must be first */ struct r300_hw_state hw; - struct r300_cmdbuf cmdbuf; + struct r300_state state; struct gl_vertex_program *curr_vp; struct r300_vertex_program *selected_vp; diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index e70e5f6d52e..63989636c2f 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -589,7 +589,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) } /* Make sure it fits there. */ - r300EnsureCmdBufSpace(r300, 421 * 3, __FUNCTION__); + rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; @@ -623,8 +623,8 @@ void r300Flush(GLcontext * ctx) rmesa->swtcl.flush(rmesa); } - if (rmesa->cmdbuf.cs->cdw) { - r300FlushCmdBuf(rmesa, __FUNCTION__); + if (rmesa->radeon.cmdbuf.cs->cdw) { + rcommonFlushCmdBuf(&rmesa->radeon, __FUNCTION__); } } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index ccc00b381fa..cb6652fabef 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -212,7 +212,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); OUT_BATCH(rmesa->state.elt_dma_offset); OUT_BATCH(vertex_count); - radeon_cs_write_reloc(rmesa->cmdbuf.cs, + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->state.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } @@ -295,13 +295,13 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) for (i = 0; i + 1 < nr; i += 2) { voffset = rmesa->state.aos[i + 0].offset + offset * 4 * rmesa->state.aos[i + 0].stride; - radeon_cs_write_reloc(rmesa->cmdbuf.cs, + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->state.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->state.aos[i + 1].offset + offset * 4 * rmesa->state.aos[i + 1].stride; - radeon_cs_write_reloc(rmesa->cmdbuf.cs, + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->state.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -309,7 +309,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) if (nr & 1) { voffset = rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride; - radeon_cs_write_reloc(rmesa->cmdbuf.cs, + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->state.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -346,7 +346,7 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, * This is supposed to ensure that we can get all rendering * commands into a single command buffer. */ - r300EnsureCmdBufSpace(rmesa, 64, __FUNCTION__); + rcommonEnsureCmdBufSpace(&rmesa->radeon, 64, __FUNCTION__); if (vb->Elts) { if (num_verts > 65535) { diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index fbfa8f452b0..0108f7cf6af 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -247,9 +247,9 @@ static void flush_last_swtcl_prim( r300ContextPtr rmesa ) fprintf(stderr, "%s\n", __FUNCTION__); rmesa->swtcl.flush = NULL; radeon_bo_unmap(rmesa->swtcl.bo); - r300EnsureCmdBufSpace(rmesa, - rmesa->hw.max_state_size + (12*sizeof(int)), - __FUNCTION__); + rcommonEnsureCmdBufSpace(rmesa, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); r300EmitState(rmesa); r300EmitVertexAOS(rmesa, rmesa->swtcl.vertex_size, diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index be21a8cfbc9..736bf7c6493 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -50,7 +50,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "dri_util.h" #include "radeon_screen.h" -#include "common_context.h" #include "common_misc.h" #if R200_MERGED diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h index eaef49c3253..f2d17a54d47 100644 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ b/src/mesa/drivers/dri/r300/radeon_lock.h @@ -42,78 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_LOCK_H__ #define __RADEON_LOCK_H__ -#include "radeon_context.h" - -extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); -extern void radeonUpdatePageFlipping(radeonContextPtr rmesa); - -/* Turn DEBUG_LOCKING on to find locking conflicts. - */ -#define DEBUG_LOCKING 0 - -#if DEBUG_LOCKING -extern char *prevLockFile; -extern int prevLockLine; - -#define DEBUG_LOCK() \ - do { \ - prevLockFile = (__FILE__); \ - prevLockLine = (__LINE__); \ - } while (0) - -#define DEBUG_RESET() \ - do { \ - prevLockFile = 0; \ - prevLockLine = 0; \ - } while (0) - -#define DEBUG_CHECK_LOCK() \ - do { \ - if (prevLockFile) { \ - fprintf(stderr, \ - "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ - prevLockFile, prevLockLine, __FILE__, __LINE__); \ - exit(1); \ - } \ - } while (0) - -#else - -#define DEBUG_LOCK() -#define DEBUG_RESET() -#define DEBUG_CHECK_LOCK() - -#endif - -/* - * !!! We may want to separate locks from locks with validation. This - * could be used to improve performance for those things commands that - * do not do any drawing !!! - */ - -/* Lock the hardware and validate our state. - */ -#define LOCK_HARDWARE( rmesa ) \ - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ - if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ - DRM_CAS((rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret); \ - if (__ret) \ - radeonGetLock((rmesa), 0); \ - }\ - DEBUG_LOCK(); \ - } while (0) - -#define UNLOCK_HARDWARE( rmesa ) \ - do { \ - if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ - DRM_UNLOCK((rmesa)->dri.fd, \ - (rmesa)->dri.hwLock, \ - (rmesa)->dri.hwContext); \ - DEBUG_RESET(); \ - }\ - } while (0) +#include "common_lock.h" #endif /* __RADEON_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index e4d210392c4..eb95dc9d75d 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -1,6 +1,14 @@ #ifndef COMMON_CONTEXT_H #define COMMON_CONTEXT_H + +#include "main/mm.h" +#include "math/m_vector.h" +#include "texmem.h" +#include "tnl/t_context.h" +#include "main/colormac.h" + + /* This union is used to avoid warnings/miscompilation with float to uint32_t casts due to strict-aliasing */ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; @@ -9,11 +17,6 @@ struct radeon_context; typedef struct radeon_context radeonContextRec; typedef struct radeon_context *radeonContextPtr; -#include "main/mm.h" -#include "math/m_vector.h" -#include "texmem.h" -#include "tnl/t_context.h" - #define TEX_0 0x1 #define TEX_1 0x2 @@ -256,6 +259,20 @@ struct radeon_state { struct radeon_stencilbuffer_state stencil; }; +/** + * This structure holds the command buffer while it is being constructed. + * + * The first batch of commands in the buffer is always the state that needs + * to be re-emitted when the context is lost. This batch can be skipped + * otherwise. + */ +struct radeon_cmdbuf { + struct radeon_cs_manager *csm; + struct radeon_cs *cs; + int size; /** # of dwords total */ + unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ +}; + struct radeon_context { GLcontext *glCtx; radeonScreenPtr radeonScreen; /* Screen private DRI data */ @@ -308,6 +325,8 @@ struct radeon_context { */ driOptionCache optionCache; + struct radeon_cmdbuf cmdbuf; + struct { void (*get_lock)(radeonContextPtr radeon); void (*update_viewport_offset)(GLcontext *ctx); diff --git a/src/mesa/drivers/dri/radeon/common_lock.c b/src/mesa/drivers/dri/radeon/common_lock.c index d983e8ce926..09517450a9b 100644 --- a/src/mesa/drivers/dri/radeon/common_lock.c +++ b/src/mesa/drivers/dri/radeon/common_lock.c @@ -84,7 +84,7 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) #else /* Turn on/off page flipping according to the flags in the sarea: */ -static void radeonUpdatePageFlipping(radeonContextPtr rmesa) +void radeonUpdatePageFlipping(radeonContextPtr rmesa) { rmesa->doPageFlip = rmesa->sarea->pfState; if (rmesa->glCtx->WinSysDrawBuffer) { diff --git a/src/mesa/drivers/dri/radeon/common_lock.h b/src/mesa/drivers/dri/radeon/common_lock.h index 50a4a0b05a6..431b076f025 100644 --- a/src/mesa/drivers/dri/radeon/common_lock.h +++ b/src/mesa/drivers/dri/radeon/common_lock.h @@ -41,6 +41,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef COMMON_LOCK_H #define COMMON_LOCK_H + +#include "main/colormac.h" +#include "radeon_screen.h" +#include "common_context.h" + extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); /* Turn DEBUG_LOCKING on to find locking conflicts. @@ -93,19 +98,23 @@ extern int prevLockLine; do { \ char __ret = 0; \ DEBUG_CHECK_LOCK(); \ - DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ - if ( __ret ) \ + if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ + DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ + (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ + if ( __ret ) \ radeonGetLock( (rmesa), 0 ); \ + } \ DEBUG_LOCK(); \ } while (0) #define UNLOCK_HARDWARE( rmesa ) \ do { \ - DRM_UNLOCK( (rmesa)->dri.fd, \ - (rmesa)->dri.hwLock, \ - (rmesa)->dri.hwContext ); \ - DEBUG_RESET(); \ + if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ + DRM_UNLOCK( (rmesa)->dri.fd, \ + (rmesa)->dri.hwLock, \ + (rmesa)->dri.hwContext ); \ + DEBUG_RESET(); \ + } \ } while (0) #endif diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index eab9cc74e32..ba3c76daa90 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -51,11 +51,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" #include "vblank.h" - +#include "radeon_bo.h" +#include "radeon_cs.h" +#include "radeon_bo_legacy.h" +#include "radeon_cs_legacy.h" +#include "radeon_bo_gem.h" +#include "radeon_cs_gem.h" #include "dri_util.h" #include "radeon_drm.h" -#include "radeon_screen.h" #include "radeon_buffer.h" +#include "radeon_screen.h" #include "common_context.h" #include "common_misc.h" #include "common_lock.h" @@ -577,3 +582,106 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, } } +/* cmdbuffer */ +/** + * Send the current command buffer via ioctl to the hardware. + */ +int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) +{ + int ret = 0; + + if (rmesa->cmdbuf.flushing) { + fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n"); + exit(-1); + } + rmesa->cmdbuf.flushing = 1; + if (rmesa->cmdbuf.cs->cdw) { + ret = radeon_cs_emit(rmesa->cmdbuf.cs); + rmesa->vtbl.set_all_dirty(rmesa->glCtx); + } + radeon_cs_erase(rmesa->cmdbuf.cs); + rmesa->cmdbuf.flushing = 0; + return ret; +} + +int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller) +{ + int ret; + + LOCK_HARDWARE(rmesa); + ret = rcommonFlushCmdBufLocked(rmesa, caller); + UNLOCK_HARDWARE(rmesa); + + if (ret) { + fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret); + _mesa_exit(ret); + } + + return ret; +} + +/** + * Make sure that enough space is available in the command buffer + * by flushing if necessary. + * + * \param dwords The number of dwords we need to be free on the command buffer + */ +void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller) +{ + if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size || + radeon_cs_need_flush(rmesa->cmdbuf.cs)) { + rcommonFlushCmdBuf(rmesa, caller); + } +} + +void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) +{ + GLuint size; + /* Initialize command buffer */ + size = 256 * driQueryOptioni(&rmesa->optionCache, + "command_buffer_size"); + if (size < 2 * max_state_size) { + size = 2 * max_state_size + 65535; + } + if (size > 64 * 256) + size = 64 * 256; + + size = 64 * 1024 / 4; + + if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { + fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", + sizeof(drm_r300_cmd_header_t)); + fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%zd\n", + sizeof(drm_radeon_cmd_buffer_t)); + fprintf(stderr, + "Allocating %d bytes command buffer (max state is %d bytes)\n", + size * 4, max_state_size * 4); + } + + if (rmesa->radeonScreen->kernel_mm) { + int fd = rmesa->radeonScreen->driScreen->fd; + rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); + } else { + rmesa->cmdbuf.csm = radeon_cs_manager_legacy_ctor(rmesa); + } + if (rmesa->cmdbuf.csm == NULL) { + /* FIXME: fatal error */ + return; + } + rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); + assert(rmesa->cmdbuf.cs != NULL); + rmesa->cmdbuf.size = size; + +} +/** + * Destroy the command buffer + */ +void rcommonDestroyCmdBuf(radeonContextPtr rmesa) +{ + radeon_cs_destroy(rmesa->cmdbuf.cs); + if (rmesa->radeonScreen->driScreen->dri2.enabled || rmesa->radeonScreen->kernel_mm) { + radeon_cs_manager_gem_dtor(rmesa->cmdbuf.csm); + } else { + radeon_cs_manager_legacy_dtor(rmesa->cmdbuf.csm); + } +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index cc4832c75ee..7057ad941fb 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -1,6 +1,7 @@ #ifndef COMMON_MISC_H #define COMMON_MISC_H +#include "common_context.h" void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); @@ -17,4 +18,9 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, void radeonUpdatePageFlipping(radeonContextPtr rmesa); +void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); +int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); +int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); +void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size); +void rcommonDestroyCmdBuf(radeonContextPtr rmesa); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h index 71a4dad58d4..4da2479eee7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h @@ -33,7 +33,7 @@ #define RADEON_CS_LEGACY_H #include "radeon_cs.h" -#include "radeon_context.h" +#include "common_context.h" struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index c099d0ee349..e655408338a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_macros.h" #include "radeon_screen.h" #include "radeon_buffer.h" +#include "common_misc.h" #if !RADEON_COMMON #include "radeon_context.h" #include "radeon_span.h" -- cgit v1.2.3 From e7d06a55c5443cfef73f5c2f60052cc26a1e9ff2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 15:21:45 +1000 Subject: radeon: move debug symbol add DRI2 --- src/mesa/drivers/dri/r200/r200_context.c | 3 --- src/mesa/drivers/dri/r300/radeon_context.c | 15 ++++++++++----- src/mesa/drivers/dri/radeon/common_misc.c | 4 ++++ src/mesa/drivers/dri/radeon/radeon_context.c | 4 ---- src/mesa/drivers/dri/radeon/radeon_screen.c | 1 - 5 files changed, 14 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index fd41171de81..856c5fc596c 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -82,9 +82,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ -#ifndef R200_DEBUG -int R200_DEBUG = (0); -#endif /* Return various strings for glGetString(). */ diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 96478640cc1..68849676639 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -84,6 +84,8 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) radeon->radeonScreen->AGPMode; const char* chipname; + + if (IS_R300_CLASS(radeon->radeonScreen)) chipname = "R300"; else @@ -93,15 +95,18 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) agp_mode); if (IS_R300_CLASS(radeon->radeonScreen)) { - sprintf(&buffer[offset], " %sTCL", - (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) - ? "" : "NO-"); + sprintf(&buffer[offset], " %sTCL", + (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) + ? "" : "NO-"); } else { sprintf(&buffer[offset], " %sTCL", - !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) - ? "" : "NO-"); + !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) + ? "" : "NO-"); } + if (radeon->radeonScreen->driScreen->dri2.enabled) + strcat(buffer, " DRI2"); + return (GLubyte *) buffer; } diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index ba3c76daa90..95e2efd5e8e 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -65,6 +65,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_misc.h" #include "common_lock.h" +#ifndef RADEON_DEBUG +int RADEON_DEBUG = (0); +#endif + /* ============================================================= * Scissoring */ diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 1adef7c7020..c7adf4975ba 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -75,10 +75,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ -#ifndef RADEON_DEBUG -int RADEON_DEBUG = (0); -#endif - /* Return various strings for glGetString(). */ diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e655408338a..0b6791f54c7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -212,7 +212,6 @@ DRI_CONF_END; static const GLuint __driNConfigOptions = 17; #ifndef RADEON_DEBUG -int RADEON_DEBUG = 0; static const struct dri_debug_control debug_control[] = { {"fall", DEBUG_FALLBACKS}, -- cgit v1.2.3 From 8c6a7d01744fe6164a868c5f691bb119109773c0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 15:45:29 +1000 Subject: radeon/r200/r300: make legacy emit non-r300 specific --- src/mesa/drivers/dri/r200/Makefile | 5 ++++ src/mesa/drivers/dri/r200/r200_context.c | 6 +++++ src/mesa/drivers/dri/r300/r300_context.c | 32 +++++++++++++++++++++++ src/mesa/drivers/dri/radeon/Makefile | 6 ++++- src/mesa/drivers/dri/radeon/common_context.h | 4 +++ src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 5 ++-- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 36 +++++--------------------- 7 files changed, 61 insertions(+), 33 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 5ba1603d792..91211e4d74d 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -30,6 +30,8 @@ DRIVER_SOURCES = r200_context.c \ radeon_screen.c \ common_lock.c \ common_misc.c \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ $(EGL_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -50,6 +52,8 @@ COMMON_SYMLINKS = \ radeon_chipset.h \ radeon_screen.c \ radeon_screen.h \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ radeon_bo_legacy.h \ radeon_cs_legacy.h \ radeon_buffer.h \ @@ -59,6 +63,7 @@ COMMON_SYMLINKS = \ common_misc.h \ common_misc.c +DRI_LIB_DEPS += -ldrm_radeon ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 856c5fc596c..ebd49132676 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -272,6 +272,10 @@ static void r200_vtbl_set_all_dirty(GLcontext *ctx) rmesa->hw.all_dirty = GL_TRUE; } +static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) +{ +} + static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; @@ -279,8 +283,10 @@ static void r200_init_vtbl(radeonContextPtr radeon) radeon->vtbl.flush = r200_vtbl_flush; radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; + radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; } + /* Create the device specific rendering context. */ GLboolean r200CreateContext( const __GLcontextModes *glVisual, diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 6b79e7dea3f..f8fb830abf9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -210,6 +210,37 @@ static void r300_vtbl_set_all_dirty(GLcontext *ctx) rmesa->hw.all_dirty = GL_TRUE; } +extern int cs_write_dword(struct radeon_cs *cs, uint32_t dword); + +static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) +{ + /* please flush pipe do all pending work */ + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_SC_SCREENDOOR, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_SC_SCREENDOOR, 1)); + cs_write_dword(cs, 0x00FFFFFF); + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_SC_HYPERZ, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_US_CONFIG, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_ZB_CNTL, 1)); + cs_write_dword(cs, 0x0); + cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D)); + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_RB3D_DSTCACHE_CTLSTAT, 1)); + cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + R300_ZB_ZCACHE_CTLSTAT, 1)); + cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); + cs_write_dword(cs, cmdwait(rmesa->radeonScreen, + R300_WAIT_3D | R300_WAIT_3D_CLEAN)); +} + static void r300_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r300_get_lock; @@ -217,6 +248,7 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.flush = r300_vtbl_flush; radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; + radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; } diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 50c27b81bc5..9c76abccd36 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -23,7 +23,9 @@ DRIVER_SOURCES = \ radeon_maos.c \ radeon_sanity.c \ common_lock.c \ - common_misc.c + common_misc.c \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c C_SOURCES = \ $(COMMON_SOURCES) \ @@ -31,6 +33,8 @@ C_SOURCES = \ DRIVER_DEFINES = -DRADEON_COMMON=0 +DRI_LIB_DEPS += -ldrm_radeon + X86_SOURCES = include ../Makefile.template diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index eb95dc9d75d..a3d9fd70a7a 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -8,6 +8,9 @@ #include "tnl/t_context.h" #include "main/colormac.h" +#include "radeon_screen.h" +#include "radeon_drm.h" +#include "dri_util.h" /* This union is used to avoid warnings/miscompilation with float to uint32_t casts due to strict-aliasing */ @@ -333,6 +336,7 @@ struct radeon_context { void (*flush)(GLcontext *ctx); void (*set_all_dirty)(GLcontext *ctx); void (*update_draw_buffer)(GLcontext *ctx); + void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index e3474f791bb..e378b118e0e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -41,12 +41,13 @@ #include #include "xf86drm.h" #include "texmem.h" +#include "main/simple_list.h" + #include "drm.h" #include "radeon_drm.h" #include "radeon_bo.h" #include "radeon_bo_legacy.h" -#include "radeon_ioctl.h" - +#include "common_context.h" struct bo_legacy { struct radeon_bo base; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 11b9f89ca7d..0c897815a7b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -30,13 +30,13 @@ * Jérôme Glisse */ #include -#include "r300_reg.h" -#include "r300_emit.h" -#include "r300_cmdbuf.h" + + +#include "common_context.h" #include "radeon_cs.h" #include "radeon_cs_legacy.h" #include "radeon_bo_legacy.h" -#include "radeon_context.h" + struct cs_manager_legacy { struct radeon_cs_manager base; @@ -73,7 +73,7 @@ static struct radeon_cs *cs_create(struct radeon_cs_manager *csm, return cs; } -static int cs_write_dword(struct radeon_cs *cs, uint32_t dword) +int cs_write_dword(struct radeon_cs *cs, uint32_t dword) { if (cs->cdw >= cs->ndw) { uint32_t tmp, *ptr; @@ -277,31 +277,7 @@ static int cs_emit(struct radeon_cs *cs) uint64_t ull; int r; - /* please flush pipe do all pending work */ - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_SC_SCREENDOOR, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_SC_SCREENDOOR, 1)); - cs_write_dword(cs, 0x00FFFFFF); - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_SC_HYPERZ, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_US_CONFIG, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_ZB_CNTL, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, R300_WAIT_3D)); - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_RB3D_DSTCACHE_CTLSTAT, 1)); - cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen, - R300_ZB_ZCACHE_CTLSTAT, 1)); - cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); - cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, - R300_WAIT_3D | R300_WAIT_3D_CLEAN)); + csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); /* append buffer age */ age.scratch.cmd_type = R300_CMD_SCRATCH; -- cgit v1.2.3 From 4aa874c6368f2485d4ef72e2dc0230b7d443f9f0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 15:48:02 +1000 Subject: r200: add missing symbols --- src/mesa/drivers/dri/r200/r200_context.c | 2 +- src/mesa/drivers/dri/r200/r200_state.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index ebd49132676..730831db042 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -672,7 +672,7 @@ r200MakeCurrent( __DRIcontextPrivate *driContextPriv, newCtx->radeon.dri.drawable = driDrawPriv; - r200SetCliprects(newCtx); + radeonSetCliprects(&newCtx->radeon); r200UpdateViewportOffset( newCtx->radeon.glCtx ); } diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h index 5d7347af311..741bf88e9c2 100644 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ b/src/mesa/drivers/dri/r200/r200_state.h @@ -43,8 +43,6 @@ extern void r200InitTnlFuncs( GLcontext *ctx ); extern void r200UpdateMaterial( GLcontext *ctx ); -extern void r200SetCliprects( r200ContextPtr rmesa ); -extern void r200RecalcScissorRects( r200ContextPtr rmesa ); extern void r200UpdateViewportOffset( GLcontext *ctx ); extern void r200UpdateWindow( GLcontext *ctx ); extern void r200UpdateDrawBuffer(GLcontext *ctx); -- cgit v1.2.3 From 47e3a7d7942d722bc679852fec167cc3a8b5bdd4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 15:54:28 +1000 Subject: radeon: get ctx right in copybuffer --- src/mesa/drivers/dri/radeon/common_misc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 95e2efd5e8e..7078757261c 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -339,7 +339,6 @@ static void radeonWaitForIdle(radeonContextPtr radeon) void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, const drm_clip_rect_t *rect) { - GLcontext *ctx; radeonContextPtr rmesa; GLint nbox, i, ret; GLboolean missed_target; @@ -350,14 +349,13 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, assert(dPriv->driContextPriv); assert(dPriv->driContextPriv->driverPrivate); - ctx = (GLcontext *) dPriv->driContextPriv->driverPrivate; rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); } - rmesa->vtbl.flush(ctx); + rmesa->vtbl.flush(rmesa->glCtx); LOCK_HARDWARE( rmesa ); /* Throttle the frame rate -- only allow one pending swap buffers @@ -427,7 +425,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, } rmesa->swap_ust = ust; - rmesa->vtbl.set_all_dirty(ctx); + rmesa->vtbl.set_all_dirty(rmesa->glCtx); } } -- cgit v1.2.3 From 0c0a55a21158e1f97cf140c0a1c0531c06751873 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 15 Jan 2009 16:25:37 +1000 Subject: r100/r200: move to new atom style emission --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 33 +++++++++++++++++-------- src/mesa/drivers/dri/r200/r200_state_init.c | 12 +++------ src/mesa/drivers/dri/radeon/radeon_ioctl.c | 15 ++++++++--- src/mesa/drivers/dri/radeon/radeon_state_init.c | 4 +-- 4 files changed, 40 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 4f0275cc875..53c6ecf6eea 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -120,18 +120,24 @@ static void r200SaveHwState( r200ContextPtr rmesa ) { struct radeon_state_atom *atom; char * dest = rmesa->backup_store.cmd_buf; - + uint32_t dwords; if (R200_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); rmesa->backup_store.cmd_used = 0; foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->check( rmesa->radeon.glCtx, atom ) ) { + dwords = atom->check( rmesa->radeon.glCtx, atom ); + if ( dwords ) { int size = atom->cmd_size * 4; - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->backup_store.cmd_used += size; + + if (atom->emit) { + (*atom->emit)(rmesa->radeon.glCtx, atom); + } else { + memcpy( dest, atom->cmd, size); + dest += size; + rmesa->backup_store.cmd_used += size; + } if (R200_DEBUG & DEBUG_STATE) print_state_atom( atom ); } @@ -147,6 +153,7 @@ void r200EmitState( r200ContextPtr rmesa ) char *dest; int mtu; struct radeon_state_atom *atom; + uint32_t dwords; if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); @@ -173,7 +180,8 @@ void r200EmitState( r200ContextPtr rmesa ) if (R200_DEBUG & DEBUG_STATE) { foreach( atom, &rmesa->hw.atomlist ) { if ( atom->dirty || rmesa->hw.all_dirty ) { - if ( atom->check( rmesa->radeon.glCtx, atom ) ) + dwords = atom->check( rmesa->radeon.glCtx, atom ); + if ( dwords ) print_state_atom( atom ); else fprintf(stderr, "skip state %s\n", atom->name); @@ -185,11 +193,16 @@ void r200EmitState( r200ContextPtr rmesa ) if ( rmesa->hw.all_dirty ) atom->dirty = GL_TRUE; if ( atom->dirty ) { - if ( atom->check( rmesa->radeon.glCtx, atom ) ) { + dwords = atom->check( rmesa->radeon.glCtx, atom ); + if ( dwords ) { int size = atom->cmd_size * 4; - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->store.cmd_used += size; + if (atom->emit) { + (*atom->emit)(rmesa->radeon.glCtx, atom); + } else { + memcpy( dest, atom->cmd, size); + dest += size; + rmesa->store.cmd_used += size; + } atom->dirty = GL_FALSE; } } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 775ccb74825..f68f5ae08ff 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -130,25 +130,22 @@ static int cmdscl2( int offset, int stride, int count ) static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) atom; \ (void) rmesa; \ - return FLAG; \ + return (FLAG) ? atom->cmd_size : 0; \ } #define TCL_CHECK( NM, FLAG ) \ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) atom; \ - return !rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG); \ + return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \ } #define TCL_OR_VP_CHECK( NM, FLAG ) \ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) atom; \ - return !rmesa->radeon.TclFallback && (FLAG); \ + return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \ } #define VP_CHECK( NM, FLAG ) \ @@ -156,10 +153,9 @@ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ (void) atom; \ - return !rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG); \ + return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \ } - CHECK( always, GL_TRUE ) CHECK( never, GL_FALSE ) CHECK( tex_any, ctx->Texture._EnabledUnits ) diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 2b02d0b71fc..cd0f90d748b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -170,6 +170,7 @@ void radeonEmitState( r100ContextPtr rmesa ) { struct radeon_state_atom *atom; char *dest; + uint32_t dwords; if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); @@ -212,11 +213,17 @@ void radeonEmitState( r100ContextPtr rmesa ) atom->is_tcl) atom->dirty = GL_FALSE; if (atom->dirty) { - if (atom->check(rmesa->radeon.glCtx, 0)) { + dwords = atom->check(rmesa->radeon.glCtx, atom); + if (dwords) { int size = atom->cmd_size * 4; - memcpy(dest, atom->cmd, size); - dest += size; - rmesa->store.cmd_used += size; + + if (atom->emit) { + (*atom->emit)(rmesa->radeon.glCtx, atom); + } else { + memcpy(dest, atom->cmd, size); + dest += size; + rmesa->store.cmd_used += size; + } atom->dirty = GL_FALSE; } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index affa9313c9e..f39fae8186c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -99,14 +99,14 @@ static int cmdscl( int offset, int stride, int count ) #define CHECK( NM, FLAG ) \ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ - return FLAG; \ + return FLAG ? atom->cmd_size : 0; \ } #define TCL_CHECK( NM, FLAG ) \ static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ { \ r100ContextPtr rmesa = R100_CONTEXT(ctx); \ - return !rmesa->radeon.TclFallback && (FLAG); \ + return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \ } -- cgit v1.2.3 From 1a51b76343255af9be6282f93614e92788ad4f0f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 15 Jan 2009 16:41:01 +1000 Subject: radeon/r200/r300: start to make cmd buf useful --- src/mesa/drivers/dri/r200/Makefile | 3 +- src/mesa/drivers/dri/r300/Makefile | 3 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 25 ++------ src/mesa/drivers/dri/r300/r300_cmdbuf.h | 79 +---------------------- src/mesa/drivers/dri/r300/r300_context.c | 6 ++ src/mesa/drivers/dri/radeon/common_cmdbuf.h | 93 ++++++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_context.h | 1 + src/mesa/drivers/dri/radeon/common_misc.c | 16 +++++ src/mesa/drivers/dri/radeon/common_misc.h | 5 -- 9 files changed, 126 insertions(+), 105 deletions(-) create mode 100644 src/mesa/drivers/dri/radeon/common_cmdbuf.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 91211e4d74d..6b90018a288 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -61,7 +61,8 @@ COMMON_SYMLINKS = \ common_lock.c \ common_lock.h \ common_misc.h \ - common_misc.c + common_misc.c \ + common_cmdbuf.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 18fab1d7800..942d76fcc88 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -83,7 +83,8 @@ COMMON_SYMLINKS = \ common_lock.c \ common_lock.h \ common_misc.c \ - common_misc.h + common_misc.h \ + common_cmdbuf.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index bbca71dd16a..f4b4848cee2 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -69,21 +69,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define SPACE_FOR_FLUSHING 4 -void r300BeginBatch(r300ContextPtr r300, int n, - int dostate, - const char *file, - const char *function, - int line) -{ - rcommonEnsureCmdBufSpace(&r300->radeon, n, function); - if (!r300->radeon.cmdbuf.cs->cdw && dostate) { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "Reemit state after flush (from %s)\n", function); - r300EmitState(r300); - } - radeon_cs_begin(r300->radeon.cmdbuf.cs, n, file, function, line); -} - static void r300PrintStateAtom(r300ContextPtr r300, struct radeon_state_atom *state) { @@ -108,7 +93,7 @@ static void r300PrintStateAtom(r300ContextPtr r300, */ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) { - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); struct radeon_state_atom *atom; int dwords; @@ -198,7 +183,7 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i; @@ -237,7 +222,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i, sz; int type, clamp, stride; @@ -277,7 +262,7 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); if (numtmus) { @@ -308,7 +293,7 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate; diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index 0c76c6c99a7..d8a1076e72b 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -39,90 +39,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "radeon_cs.h" +#include "common_cmdbuf.h" extern void r300EmitState(r300ContextPtr r300); extern void r300InitCmdBuf(r300ContextPtr r300); extern void r300DestroyCmdBuf(r300ContextPtr r300); -void r300BeginBatch(r300ContextPtr r300, - int n, - int dostate, - const char *file, - const char *function, - int line); - -/** - * Every function writing to the command buffer needs to declare this - * to get the necessary local variables. - */ -#define BATCH_LOCALS(r300) \ - const r300ContextPtr b_l_r300 = r300 - -/** - * Prepare writing n dwords to the command buffer, - * including producing any necessary state emits on buffer wraparound. - */ -#define BEGIN_BATCH(n) r300BeginBatch(b_l_r300, n, 1, __FILE__, __FUNCTION__, __LINE__) - -/** - * Same as BEGIN_BATCH, but do not cause automatic state emits. - */ -#define BEGIN_BATCH_NO_AUTOSTATE(n) r300BeginBatch(b_l_r300, n, 0, __FILE__, __FUNCTION__, __LINE__) - -/** - * Write one dword to the command buffer. - */ -#define OUT_BATCH(data) \ - do { \ - radeon_cs_write_dword(b_l_r300->radeon.cmdbuf.cs, data);\ - } while(0) - -/** - * Write a relocated dword to the command buffer. - */ -#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ - do { \ - if (offset) {\ - fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ - __FILE__, __FUNCTION__, __LINE__, offset);\ - }\ - radeon_cs_write_dword(b_l_r300->radeon.cmdbuf.cs, offset);\ - radeon_cs_write_reloc(b_l_r300->radeon.cmdbuf.cs, \ - bo, \ - rd, \ - wd, \ - flags);\ - } while(0) - -/** - * Write n dwords from ptr to the command buffer. - */ -#define OUT_BATCH_TABLE(ptr,n) \ - do { \ - int _i; \ - for (_i=0; _i < n; _i++) {\ - radeon_cs_write_dword(b_l_r300->radeon.cmdbuf.cs, ptr[_i]);\ - }\ - } while(0) - -/** - * Finish writing dwords to the command buffer. - * The number of (direct or indirect) OUT_BATCH calls between the previous - * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. - */ -#define END_BATCH() \ - do { \ - radeon_cs_end(b_l_r300->radeon.cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ - } while(0) - -/** - * After the last END_BATCH() of rendering, this indicates that flushing - * the command buffer now is okay. - */ -#define COMMIT_BATCH() \ - do { \ - } while(0) void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index f8fb830abf9..3647022622b 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -210,6 +210,11 @@ static void r300_vtbl_set_all_dirty(GLcontext *ctx) rmesa->hw.all_dirty = GL_TRUE; } +static void r300_vtbl_emit_state(radeonContextPtr rmesa) +{ + r300EmitState((r300ContextPtr)rmesa); +} + extern int cs_write_dword(struct radeon_cs *cs, uint32_t dword); static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) @@ -249,6 +254,7 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; + radeon->vtbl.emit_state = r300_vtbl_emit_state; } diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h new file mode 100644 index 00000000000..018049b4523 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -0,0 +1,93 @@ +#ifndef COMMON_CMDBUF_H +#define COMMON_CMDBUF_H + +void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); +int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); +int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); +void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size); +void rcommonDestroyCmdBuf(radeonContextPtr rmesa); + +void rcommonBeginBatch(radeonContextPtr rmesa, + int n, + int dostate, + const char *file, + const char *function, + int line); + + +/** + * Every function writing to the command buffer needs to declare this + * to get the necessary local variables. + */ +#define BATCH_LOCALS(rmesa) \ + const radeonContextPtr b_l_rmesa = rmesa + +/** + * Prepare writing n dwords to the command buffer, + * including producing any necessary state emits on buffer wraparound. + */ +#define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__) + +/** + * Same as BEGIN_BATCH, but do not cause automatic state emits. + */ +#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_r300, n, 0, __FILE__, __FUNCTION__, __LINE__) + +/** + * Write one dword to the command buffer. + */ +#define OUT_BATCH(data) \ + do { \ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ + } while(0) + +/** + * Write a relocated dword to the command buffer. + */ +#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ + do { \ + if (offset) {\ + fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ + __FILE__, __FUNCTION__, __LINE__, offset);\ + }\ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset);\ + radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ + bo, \ + rd, \ + wd, \ + flags);\ + } while(0) + + +/** + * Write n dwords from ptr to the command buffer. + */ +#define OUT_BATCH_TABLE(ptr,n) \ + do { \ + int _i; \ + for (_i=0; _i < n; _i++) {\ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\ + }\ + } while(0) + +/** + * Finish writing dwords to the command buffer. + * The number of (direct or indirect) OUT_BATCH calls between the previous + * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. + */ +#define END_BATCH() \ + do { \ + radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ + } while(0) + +/** + * After the last END_BATCH() of rendering, this indicates that flushing + * the command buffer now is okay. + */ +#define COMMIT_BATCH() \ + do { \ + } while(0) + + + +#endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index a3d9fd70a7a..2748c51a59c 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -337,6 +337,7 @@ struct radeon_context { void (*set_all_dirty)(GLcontext *ctx); void (*update_draw_buffer)(GLcontext *ctx); void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); + void (*emit_state)(radeonContextPtr rmesa); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 7078757261c..a2343526585 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_context.h" #include "common_misc.h" #include "common_lock.h" +#include "common_cmdbuf.h" #ifndef RADEON_DEBUG int RADEON_DEBUG = (0); @@ -687,3 +688,18 @@ void rcommonDestroyCmdBuf(radeonContextPtr rmesa) radeon_cs_manager_legacy_dtor(rmesa->cmdbuf.csm); } } + +void rcommonBeginBatch(radeonContextPtr rmesa, int n, + int dostate, + const char *file, + const char *function, + int line) +{ + rcommonEnsureCmdBufSpace(rmesa, n, function); + if (!rmesa->cmdbuf.cs->cdw && dostate) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "Reemit state after flush (from %s)\n", function); + rmesa->vtbl.emit_state(rmesa); + } + radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 7057ad941fb..d7161c4b96a 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -18,9 +18,4 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, void radeonUpdatePageFlipping(radeonContextPtr rmesa); -void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); -int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); -int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); -void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size); -void rcommonDestroyCmdBuf(radeonContextPtr rmesa); #endif -- cgit v1.2.3 From 08d90fe8a5e12d92994c05b2ec9f68ab7232275c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 15 Jan 2009 16:50:58 +1000 Subject: r300: move some more function to generic --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 2 +- src/mesa/drivers/dri/r300/r300_context.h | 46 +----- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_emit.h | 95 +++++------- src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_render.c | 220 +++++++++++++-------------- src/mesa/drivers/dri/r300/r300_swtcl.c | 4 +- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 14 +- src/mesa/drivers/dri/radeon/common_context.h | 45 ++++++ 9 files changed, 217 insertions(+), 215 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index f4b4848cee2..30314d454ff 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -327,7 +327,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; uint32_t zbpitch; diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 1a430169f5f..8449d00d37a 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -75,50 +75,7 @@ typedef struct r300_context *r300ContextPtr; #include "r300_vertprog.h" #include "r500_fragprog.h" -/** - * This function takes a float and packs it into a uint32_t - */ -static INLINE uint32_t r300PackFloat32(float fl) -{ - union { - float fl; - uint32_t u; - } u; - - u.fl = fl; - return u.u; -} - -/* This is probably wrong for some values, I need to test this - * some more. Range checking would be a good idea also.. - * - * But it works for most things. I'll fix it later if someone - * else with a better clue doesn't - */ -static INLINE uint32_t r300PackFloat24(float f) -{ - float mantissa; - int exponent; - uint32_t float24 = 0; - - if (f == 0.0) - return 0; - - mantissa = frexpf(f, &exponent); - /* Handle -ve */ - if (mantissa < 0) { - float24 |= (1 << 23); - mantissa = mantissa * -1.0; - } - /* Handle exponent, bias of 63 */ - exponent += 62; - float24 |= (exponent << 16); - /* Kill 7 LSB of mantissa */ - float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7; - - return float24; -} /************ DMA BUFFERS **************/ @@ -869,4 +826,7 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx, #define RADEON_D_PLAYBACK_RAW 2 #define RADEON_D_T 3 +#define r300PackFloat32 radeonPackFloat32 +#define r300PackFloat24 radeonPackFloat24 + #endif /* __R300_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index a984f552bdf..bf33c18979d 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -493,7 +493,7 @@ void r300ReleaseArrays(GLcontext * ctx) void r300EmitCacheFlush(r300ContextPtr rmesa) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); BEGIN_BATCH(4); OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index db43cc3beed..1e7a639c000 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -138,28 +138,13 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) return cmd.u; } - -/** Single register write to command buffer; requires 2 dwords. */ -#define OUT_BATCH_REGVAL(reg, val) \ - OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), 1)); \ - OUT_BATCH((val)) - -/** Continuous register range write to command buffer; requires 1 dword, - * expects count dwords afterwards for register contents. */ -#define OUT_BATCH_REGSEQ(reg, count) \ - OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), (count))); - -/** Write a 32 bit float to the ring; requires 1 dword. */ -#define OUT_BATCH_FLOAT32(f) \ - OUT_BATCH(r300PackFloat32((f))); - /** * Write the header of a packet3 to the command buffer. * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_r300->radeon.radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ R300_CMD_PACKET3_RAW)); \ }\ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ @@ -170,7 +155,7 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) */ void static INLINE end_3d(r300ContextPtr rmesa) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(1); @@ -181,7 +166,7 @@ void static INLINE end_3d(r300ContextPtr rmesa) void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(1); @@ -192,42 +177,42 @@ void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) { - BATCH_LOCALS(rmesa); - uint32_t wait_until; - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); - END_BATCH(); - } else { - switch(flags) { - case R300_WAIT_2D: - wait_until = (1 << 14); - break; - case R300_WAIT_3D: - wait_until = (1 << 15); - break; - case R300_NEW_WAIT_2D_3D: - wait_until = (1 << 14) | (1 << 15); - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = (1 << 15) | (1 << 17) | (1 << 18); - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - wait_until |= (1 << 15) | (1 << 17) | (1 << 18); - break; - default: - return; - } - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH(wait_until); - END_BATCH(); - } + BATCH_LOCALS(&rmesa->radeon); + uint32_t wait_until; + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); + END_BATCH(); + } else { + switch(flags) { + case R300_WAIT_2D: + wait_until = (1 << 14); + break; + case R300_WAIT_3D: + wait_until = (1 << 15); + break; + case R300_NEW_WAIT_2D_3D: + wait_until = (1 << 14) | (1 << 15); + break; + case R300_NEW_WAIT_2D_2D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + break; + case R300_NEW_WAIT_3D_3D_CLEAN: + wait_until = (1 << 15) | (1 << 17) | (1 << 18); + break; + case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: + wait_until = (1 << 14) | (1 << 16) | (1 << 18); + wait_until |= (1 << 15) | (1 << 17) | (1 << 18); + break; + default: + return; + } + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH(wait_until); + END_BATCH(); + } } extern int r300EmitArrays(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 63989636c2f..02c4b1cb408 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -70,7 +70,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, struct radeon_renderbuffer *rrb, struct radeon_renderbuffer *rrbd) { - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); GLcontext *ctx = r300->radeon.glCtx; __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; GLuint cbpitch = 0; @@ -205,7 +205,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, static void r300EmitClearState(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(r300); + BATCH_LOCALS(&r300->radeon); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; int i; int has_tcl = 1; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index cb6652fabef..c81393e7476 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -189,44 +189,44 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) { - BATCH_LOCALS(rmesa); - - if (vertex_count > 0) { - BEGIN_BATCH(8); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - ((vertex_count + 0) << 16) | - type | - R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, - rmesa->state.elt_dma_bo, - rmesa->state.elt_dma_offset, - RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(vertex_count); - } else { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - OUT_BATCH(rmesa->state.elt_dma_offset); - OUT_BATCH(vertex_count); - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.elt_dma_bo, - RADEON_GEM_DOMAIN_GTT, 0, 0); - } - END_BATCH(); - } + BATCH_LOCALS(&rmesa->radeon); + + if (vertex_count > 0) { + BEGIN_BATCH(8); + OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | + ((vertex_count + 0) << 16) | + type | + R300_VAP_VF_CNTL__INDEX_SIZE_32bit); + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); + OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, + rmesa->state.elt_dma_bo, + rmesa->state.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(vertex_count); + } else { + OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); + OUT_BATCH(rmesa->state.elt_dma_offset); + OUT_BATCH(vertex_count); + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0, 0); + } + END_BATCH(); + } } static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) { - BATCH_LOCALS(rmesa); - uint32_t voffset; + BATCH_LOCALS(&rmesa->radeon); + uint32_t voffset; int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; - + if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); @@ -236,91 +236,91 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); - - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; - OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; - OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i+1].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - - if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | - (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; - OUT_BATCH_RELOC(voffset, - rmesa->state.aos[nr - 1].bo, - voffset, + if (!rmesa->radeon.radeonScreen->kernel_mm) { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->state.aos[i].components << 0) | + (rmesa->state.aos[i].stride << 8) | + (rmesa->state.aos[i + 1].components << 16) | + (rmesa->state.aos[i + 1].stride << 24)); + + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i].bo, + voffset, RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - } else { - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); - - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; - OUT_BATCH(voffset); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; - OUT_BATCH(voffset); - } - - if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | + 0, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + + if (nr & 1) { + OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | + (rmesa->state.aos[nr - 1].stride << 8)); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->state.aos[i].components << 0) | + (rmesa->state.aos[i].stride << 8) | + (rmesa->state.aos[i + 1].components << 16) | + (rmesa->state.aos[i + 1].stride << 24)); + + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; - OUT_BATCH(voffset); - } - for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+0].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - if (nr & 1) { - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[nr-1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH(voffset); + } + for (i = 0; i + 1 < nr; i += 2) { + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.aos[i+0].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.aos[i+1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + if (nr & 1) { + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->state.aos[nr-1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } } - } END_BATCH(); } static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); BEGIN_BATCH(3); OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); @@ -331,7 +331,7 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, int start, int end, int prim) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); int type, num_verts; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 0108f7cf6af..03fc2107dba 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -636,7 +636,7 @@ void r300DestroySwtcl(GLcontext *ctx) void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", @@ -652,7 +652,7 @@ void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_b void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) { - BATCH_LOCALS(rmesa); + BATCH_LOCALS(&rmesa->radeon); int type, num_verts; type = r300PrimitiveType(rmesa, primitive); diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index 018049b4523..fbcbf72b2bf 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -31,7 +31,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, /** * Same as BEGIN_BATCH, but do not cause automatic state emits. */ -#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_r300, n, 0, __FILE__, __FUNCTION__, __LINE__) +#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__) /** * Write one dword to the command buffer. @@ -89,5 +89,17 @@ void rcommonBeginBatch(radeonContextPtr rmesa, } while(0) +/** Single register write to command buffer; requires 2 dwords. */ +#define OUT_BATCH_REGVAL(reg, val) \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ + OUT_BATCH((val)) +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define OUT_BATCH_REGSEQ(reg, count) \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))); + +/** Write a 32 bit float to the ring; requires 1 dword. */ +#define OUT_BATCH_FLOAT32(f) \ + OUT_BATCH(radeonPackFloat32((f))); #endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 2748c51a59c..d6e15bc3b86 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -343,6 +343,51 @@ struct radeon_context { #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) +/** + * This function takes a float and packs it into a uint32_t + */ +static INLINE uint32_t radeonPackFloat32(float fl) +{ + union { + float fl; + uint32_t u; + } u; + + u.fl = fl; + return u.u; +} + +/* This is probably wrong for some values, I need to test this + * some more. Range checking would be a good idea also.. + * + * But it works for most things. I'll fix it later if someone + * else with a better clue doesn't + */ +static INLINE uint32_t radeonPackFloat24(float f) +{ + float mantissa; + int exponent; + uint32_t float24 = 0; + + if (f == 0.0) + return 0; + + mantissa = frexpf(f, &exponent); + + /* Handle -ve */ + if (mantissa < 0) { + float24 |= (1 << 23); + mantissa = mantissa * -1.0; + } + /* Handle exponent, bias of 63 */ + exponent += 62; + float24 |= (exponent << 16); + /* Kill 7 LSB of mantissa */ + float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7; + + return float24; +} + /* ================================================================ * Debugging: */ -- cgit v1.2.3 From ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 20 Jan 2009 22:51:04 +1000 Subject: r200: clear is working at least - not much else --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 226 +++++++--- src/mesa/drivers/dri/r200/r200_context.c | 112 +---- src/mesa/drivers/dri/r200/r200_context.h | 8 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 20 +- src/mesa/drivers/dri/r200/r200_ioctl.h | 59 ++- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 34 +- src/mesa/drivers/dri/r200/r200_pixel.c | 8 +- src/mesa/drivers/dri/r200/r200_span.c | 46 +- src/mesa/drivers/dri/r200/r200_span.h | 3 +- src/mesa/drivers/dri/r200/r200_state.c | 33 +- src/mesa/drivers/dri/r200/r200_state_init.c | 146 ++++++ src/mesa/drivers/dri/r200/r200_swtcl.c | 70 ++- src/mesa/drivers/dri/r200/r200_tcl.c | 18 +- src/mesa/drivers/dri/r200/r200_texmem.c | 4 +- src/mesa/drivers/dri/r300/r300_context.c | 2 - src/mesa/drivers/dri/r300/r300_context.h | 10 +- src/mesa/drivers/dri/r300/r300_emit.c | 143 +----- src/mesa/drivers/dri/r300/r300_emit.h | 7 - src/mesa/drivers/dri/r300/r300_render.c | 6 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 14 +- src/mesa/drivers/dri/r300/radeon_context.c | 496 --------------------- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 4 + src/mesa/drivers/dri/radeon/common_context.h | 17 + src/mesa/drivers/dri/radeon/common_misc.c | 634 +++++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 14 + src/mesa/drivers/dri/radeon/radeon_context.c | 56 +-- src/mesa/drivers/dri/radeon/radeon_screen.c | 122 +----- src/mesa/drivers/dri/radeon/radeon_span.c | 25 +- src/mesa/drivers/dri/radeon/radeon_span.h | 4 - src/mesa/drivers/dri/radeon/radeon_state.c | 4 +- 30 files changed, 1200 insertions(+), 1145 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 53c6ecf6eea..f107ff56245 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -38,7 +38,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "main/simple_list.h" +#include "radeon_cs.h" #include "r200_context.h" +#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" @@ -148,6 +150,40 @@ static void r200SaveHwState( r200ContextPtr rmesa ) fprintf(stderr, "Returning to r200EmitState\n"); } +static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) +{ + BATCH_LOCALS(&r200->radeon); + struct radeon_state_atom *atom; + int dwords; + + /* Emit actual atoms */ + foreach(atom, &r200->hw.atomlist) { + if ((atom->dirty || r200->hw.all_dirty) == dirty) { + dwords = (*atom->check) (r200->radeon.glCtx, atom); + if (dwords) { + // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + // r300PrintStateAtom(r300, atom); + // } + if (atom->emit) { + (*atom->emit)(r200->radeon.glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + // fprintf(stderr, " skip state %s\n", + // atom->name); + // } + } + } + } + + COMMIT_BATCH(); +} + void r200EmitState( r200ContextPtr rmesa ) { char *dest; @@ -163,8 +199,8 @@ void r200EmitState( r200ContextPtr rmesa ) rmesa->save_on_next_emit = GL_FALSE; } - if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty) - return; + if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty) + return; mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; @@ -172,44 +208,19 @@ void r200EmitState( r200ContextPtr rmesa ) * for enough space for the case of emitting all state, and inline the * r200AllocCmdBuf code here without all the checks. */ - r200EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size ); - - /* we need to calculate dest after EnsureCmdBufSpace - as we may flush the buffer - airlied */ - dest = rmesa->store.cmd_buf + rmesa->store.cmd_used; - if (R200_DEBUG & DEBUG_STATE) { - foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->dirty || rmesa->hw.all_dirty ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) - print_state_atom( atom ); - else - fprintf(stderr, "skip state %s\n", atom->name); - } - } - } + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - foreach( atom, &rmesa->hw.atomlist ) { - if ( rmesa->hw.all_dirty ) - atom->dirty = GL_TRUE; - if ( atom->dirty ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) { - int size = atom->cmd_size * 4; - if (atom->emit) { - (*atom->emit)(rmesa->radeon.glCtx, atom); - } else { - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->store.cmd_used += size; - } - atom->dirty = GL_FALSE; - } - } + if (!rmesa->radeon.cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + r200EmitAtoms(rmesa, GL_FALSE); } - assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + r200EmitAtoms(rmesa, GL_TRUE); rmesa->hw.is_dirty = GL_FALSE; rmesa->hw.all_dirty = GL_FALSE; } @@ -222,6 +233,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint vertex_nr ) { drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & R200_VF_PRIM_WALK_IND)); @@ -230,7 +242,13 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, rmesa->store.cmd_used/4, primitive, vertex_nr); - + + BEGIN_BATCH(3); + OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); + OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | + (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); + END_BATCH(); +#if 0 cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ, __FUNCTION__ ); cmd[0].i = 0; @@ -240,6 +258,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); +#endif } @@ -285,8 +304,8 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, r200EmitState( rmesa ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), + // __FUNCTION__ ); cmd[0].i = 0; cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2; @@ -314,26 +333,124 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - GLuint offset ) + GLuint vertex_size, + struct radeon_bo *bo, + GLuint offset ) { - drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL)) fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", __FUNCTION__, vertex_size, offset); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ, - __FUNCTION__ ); - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16); - cmd[2].i = 1; - cmd[3].i = vertex_size | (vertex_size << 8); - cmd[4].i = offset; + BEGIN_BATCH(5); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); + OUT_BATCH(1); + OUT_BATCH(vertex_size | (vertex_size << 8)); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); } - +void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) +{ + BATCH_LOCALS(&rmesa->radeon); + uint32_t voffset; + int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, + offset); + + BEGIN_BATCH(sz+2); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH(voffset); + } + for (i = 0; i + 1 < nr; i += 2) { + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+0].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + if (nr & 1) { + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[nr-1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } + END_BATCH(); +} + +#if 0 void r200EmitAOS( r200ContextPtr rmesa, struct radeon_dma_region **component, GLuint nr, @@ -377,6 +494,7 @@ void r200EmitAOS( r200ContextPtr rmesa, fprintf(stderr, " %d: %x\n", i, tmp[i]); } } +#endif void r200EmitBlit( r200ContextPtr rmesa, GLuint color_fmt, @@ -404,8 +522,8 @@ void r200EmitBlit( r200ContextPtr rmesa, assert( w < (1<<16) ); assert( h < (1<<16) ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), + // __FUNCTION__ ); cmd[0].header.cmd_type = RADEON_CMD_PACKET3; @@ -434,8 +552,8 @@ void r200EmitWait( r200ContextPtr rmesa, GLuint flags ) assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), + // __FUNCTION__ ); cmd[0].i = 0; cmd[0].wait.cmd_type = RADEON_CMD_WAIT; cmd[0].wait.flags = flags; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 730831db042..acbfdb2db6d 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -297,9 +297,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r200ContextPtr rmesa; - GLcontext *ctx, *shareCtx; + GLcontext *ctx; int i; - int tcl_mode, fthrottle_mode; + int tcl_mode; assert(glVisual); assert(driContextPriv); @@ -344,31 +344,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitTextureFuncs(&functions); r200InitShaderFuncs(&functions); - /* Allocate and initialize the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((r200ContextPtr) sharedContextPrivate)->radeon.glCtx; - else - shareCtx = NULL; - rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx, - &functions, (void *) rmesa); - if (!rmesa->radeon.glCtx) { - FREE(rmesa); - return GL_FALSE; + if (!radeonInitContext(&rmesa->radeon, &functions, + glVisual, driContextPriv, + sharedContextPrivate)) { + FREE(rmesa); + return GL_FALSE; } - driContextPriv->driverPrivate = rmesa; - - /* Init r200 context data */ - rmesa->radeon.dri.context = driContextPriv; - rmesa->radeon.dri.screen = sPriv; - rmesa->radeon.dri.drawable = NULL; /* Set by XMesaMakeCurrent */ - rmesa->radeon.dri.hwContext = driContextPriv->hHWContext; - rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock; - rmesa->radeon.dri.fd = sPriv->fd; - rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor; - - rmesa->radeon.radeonScreen = screen; - rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + - screen->sarea_priv_offset); rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; @@ -531,27 +512,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitState( rmesa ); r200InitSwtcl( ctx ); - fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); - rmesa->radeon.iw.irq_seq = -1; - rmesa->radeon.irqsEmitted = 0; - rmesa->radeon.do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - rmesa->radeon.radeonScreen->irq); - - rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - - if (!rmesa->radeon.do_irqs) - fprintf(stderr, - "IRQ's not enabled, falling back to %s: %d %d\n", - rmesa->radeon.do_usleeps ? "usleeps" : "busy waits", - fthrottle_mode, - rmesa->radeon.radeonScreen->irq); - rmesa->prefer_gart_client_texturing = (getenv("R200_GART_CLIENT_TEXTURES") != 0); - (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); - - #if DO_DEBUG R200_DEBUG = driParseDebugString( getenv( "R200_DEBUG" ), debug_control ); @@ -609,8 +572,8 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->dma.current.buf) { - r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + // r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } if (rmesa->radeon.state.scissor.pClipRects) { @@ -618,6 +581,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) rmesa->radeon.state.scissor.pClipRects = NULL; } + if ( release_texture_heaps ) { /* This share group is about to go away, free our private * texture object data. @@ -632,67 +596,13 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) assert( is_empty_list( & rmesa->radeon.swapped ) ); } - /* free the Mesa context */ - rmesa->radeon.glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->radeon.glCtx ); - - /* free the option cache */ - driDestroyOptionCache (&rmesa->radeon.optionCache); + radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); } } -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean -r200MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) -{ - if ( driContextPriv ) { - r200ContextPtr newCtx = - (r200ContextPtr) driContextPriv->driverPrivate; - - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->radeon.glCtx); - - newCtx->radeon.dri.readable = driReadPriv; - - if ( newCtx->radeon.dri.drawable != driDrawPriv || - newCtx->radeon.lastStamp != driDrawPriv->lastStamp ) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->radeon.radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&newCtx->radeon.optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank( driDrawPriv ); - } - - newCtx->radeon.dri.drawable = driDrawPriv; - - radeonSetCliprects(&newCtx->radeon); - r200UpdateViewportOffset( newCtx->radeon.glCtx ); - } - - _mesa_make_current( newCtx->radeon.glCtx, - (GLframebuffer *) driDrawPriv->driverPrivate, - (GLframebuffer *) driReadPriv->driverPrivate ); - - _mesa_update_state( newCtx->radeon.glCtx ); - r200ValidateState( newCtx->radeon.glCtx ); - - } else { - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current( NULL, NULL, NULL ); - } - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} /* Force the context `c' to be unbound from its buffer. */ diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index c1a68aa6941..5ecf7979994 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -538,7 +538,8 @@ struct r200_tcl_info { GLuint hw_primitive; /* hw can handle 12 components max */ - struct radeon_dma_region *aos_components[12]; + struct radeon_aos aos[12]; + // struct radeon_dma_region *aos_components[12]; GLuint nr_aos_components; GLuint *Elts; @@ -600,6 +601,8 @@ struct r200_swtcl_info { */ GLboolean needproj; + struct radeon_bo *bo; + void (*flush) (r200ContextPtr); struct radeon_dma_region indexed_verts; }; @@ -619,7 +622,6 @@ struct r200_swtcl_info { #define R200_MAX_VERTEX_SIZE ((3*6)+11) - struct r200_context { struct radeon_context radeon; @@ -641,7 +643,7 @@ struct r200_context { /* Clientdata textures; */ - GLuint prefer_gart_client_texturing; + GLuint prefer_gart_client_texturing; GLboolean save_on_next_emit; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index fe3a471c8ab..1bb97c50023 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" @@ -77,11 +78,12 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) saved_store = rmesa->store; rmesa->dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); rmesa->dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } +#if 0 int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) { int ret, i; @@ -163,7 +165,6 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) return ret; } - /* Note: does not emit any commands to avoid recursion on * r200AllocCmdBuf. */ @@ -173,7 +174,7 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) LOCK_HARDWARE( &rmesa->radeon ); - ret = r200FlushCmdBufLocked( rmesa, caller ); + ret = rcommonFlushCmdBufLocked( rmesa, caller ); UNLOCK_HARDWARE( &rmesa->radeon ); @@ -182,13 +183,14 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) exit(ret); } } +#endif /* ============================================================= * Hardware vertex buffer handling */ - +#if 0 void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) { struct radeon_dma_buffer *dmabuf; @@ -209,7 +211,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); if (rmesa->dma.nr_released_bufs > 4) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); dma.context = rmesa->radeon.dri.hwContext; dma.send_count = 0; @@ -230,7 +232,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) break; if (rmesa->dma.nr_released_bufs) { - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } if (rmesa->radeon.do_usleeps) { @@ -325,7 +327,7 @@ void r200AllocDmaRegion( r200ContextPtr rmesa, assert( rmesa->dma.current.ptr <= rmesa->dma.current.end ); } - +#endif /* ================================================================ * Buffer clear @@ -437,7 +439,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } /* Send current state to the hardware */ - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); @@ -525,7 +527,7 @@ void r200Flush( GLcontext *ctx ) r200EmitState( rmesa ); if (rmesa->store.cmd_used) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } /* Make sure all commands have been sent to the hardware and have diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 1f92705685c..f36a6fd90f6 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -45,8 +45,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - GLuint offset ); + GLuint vertex_size, + struct radeon_bo *bo, + GLuint offset ); extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, @@ -58,10 +59,7 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, GLuint min_nr ); -extern void r200EmitAOS( r200ContextPtr rmesa, - struct radeon_dma_region **regions, - GLuint n, - GLuint offset ); +extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); extern void r200EmitBlit( r200ContextPtr rmesa, GLuint color_fmt, @@ -75,8 +73,8 @@ extern void r200EmitBlit( r200ContextPtr rmesa, extern void r200EmitWait( r200ContextPtr rmesa, GLuint flags ); -extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); -extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); +//extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); +//extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ); @@ -178,10 +176,11 @@ do { \ * and hang on to the lock until the critical section is finished and we flush * the buffer again and unlock. */ +#if 0 static INLINE void r200EnsureCmdBufSpace( r200ContextPtr rmesa, int bytes ) { if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( rmesa, __FUNCTION__ ); assert( bytes <= R200_CMD_BUF_SZ ); } @@ -200,5 +199,47 @@ static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa, assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); return head; } +#endif + +static inline uint32_t cmdpacket3_clip(int cmd_type) +{ + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP; + + return (uint32_t)cmd.i; + +} +#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3_clip(0)); \ + OUT_BATCH(packet); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + +static inline uint32_t cmdpacket3(int cmd_type) +{ + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = RADEON_CMD_PACKET3; + + return (uint32_t)cmd.i; + +} +#define OUT_BATCH_PACKET3(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(0)); \ + OUT_BATCH(packet); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + #endif /* __R200_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 838dfe79f9d..7fe1590c8dc 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -123,14 +123,14 @@ static void emit_ubyte_rgba( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = 1; } else { - r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = 1; rvb->aos_size = 1; @@ -193,14 +193,14 @@ static void emit_vecfog( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = 1; } else { - r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = 1; rvb->aos_size = 1; @@ -334,14 +334,14 @@ static void emit_vector( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = size; } else { - r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = size; rvb->aos_size = size; @@ -379,7 +379,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - struct radeon_dma_region **component = rmesa->tcl.aos_components; + // struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt0 = 0, vfmt1 = 0; GLuint count = VB->Count; @@ -418,12 +418,12 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) assert(attrib == VERT_ATTRIB_FOG); if (!rmesa->tcl.vertex_data[i].buf) { if (ctx->VertexProgram._Enabled) - emit_vector( ctx, - &(rmesa->tcl.vertex_data[i]), - (char *)VB->AttribPtr[attrib]->data, - 1, - VB->AttribPtr[attrib]->stride, - count); + rcommon_emit_vector( ctx, + &(rmesa->tcl.vertex_data[i]), + (char *)VB->AttribPtr[attrib]->data, + 1, + VB->AttribPtr[attrib]->stride, + count); else emit_vecfog( ctx, &(rmesa->tcl.vertex_data[i]), @@ -483,7 +483,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } after_emit: assert(nr < 12); - component[nr++] = &rmesa->tcl.vertex_data[i]; + // component[nr++] = &rmesa->tcl.vertex_data[i]; } } @@ -505,8 +505,8 @@ void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) /* only do it for changed inputs ? */ int i; for (i = 0; i < 15; i++) { - if (newinputs & (1 << i)) - r200ReleaseDmaRegion( rmesa, - &rmesa->tcl.vertex_data[i], __FUNCTION__ ); + // if (newinputs & (1 << i)) + // r200ReleaseDmaRegion( rmesa, + // &rmesa->tcl.vertex_data[i], __FUNCTION__ ); } } diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index a8aa1a27731..930d797f45c 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -200,7 +200,7 @@ r200TryReadPixels( GLcontext *ctx, LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height, &size)) { @@ -257,7 +257,7 @@ r200TryReadPixels( GLcontext *ctx, bw, bh ); } - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); } UNLOCK_HARDWARE( &rmesa->radeon ); @@ -321,7 +321,7 @@ static void do_draw_pix( GLcontext *ctx, LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); y -= height; /* cope with pixel zoom */ @@ -363,7 +363,7 @@ static void do_draw_pix( GLcontext *ctx, bw, bh ); } - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */ UNLOCK_HARDWARE( &rmesa->radeon ); } diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index b4da9ef6a38..df0172f64ed 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "radeon_buffer.h" #include "r200_ioctl.h" #include "r200_state.h" #include "r200_span.h" @@ -86,8 +87,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SPANTMP_PIXEL_FMT GL_RGB #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 -#define TAG(x) r200##x##_RGB565 -#define TAG2(x,y) r200##x##_RGB565##y +#define TAG(x) radeon##x##_RGB565 +#define TAG2(x,y) radeon##x##_RGB565##y #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) #include "spantmp2.h" @@ -96,8 +97,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SPANTMP_PIXEL_FMT GL_BGRA #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV -#define TAG(x) r200##x##_ARGB8888 -#define TAG2(x,y) r200##x##_ARGB8888##y +#define TAG(x) radeon##x##_ARGB8888 +#define TAG2(x,y) radeon##x##_ARGB8888##y #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) #include "spantmp2.h" @@ -180,7 +181,7 @@ r200_mba_z16( driRenderbuffer *drb, GLint x, GLint y ) #define READ_DEPTH( d, _x, _y ) \ d = *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo )); -#define TAG(x) r200##x##_z16 +#define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -201,7 +202,7 @@ do { \ d = *(GLuint *)(buf + r200_mba_z32( drb, _x + xo, \ _y + yo )) & 0x00ffffff; -#define TAG(x) r200##x##_z24_s8 +#define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" @@ -228,7 +229,7 @@ do { \ d = tmp >> 24; \ } while (0) -#define TAG(x) r200##x##_z24_s8 +#define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" @@ -284,24 +285,17 @@ void r200InitSpanFuncs( GLcontext *ctx ) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void -radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis) +void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) { - r200InitPointers_RGB565(&drb->Base); - } - else { - r200InitPointers_ARGB8888(&drb->Base); - } - } - else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) { - r200InitDepthPointers_z16(&drb->Base); - } - else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) { - r200InitDepthPointers_z24_s8(&drb->Base); - } - else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - r200InitStencilPointers_z24_s8(&drb->Base); - } + if (rrb->base.InternalFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); + } else if (rrb->base.InternalFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); + } } diff --git a/src/mesa/drivers/dri/r200/r200_span.h b/src/mesa/drivers/dri/r200/r200_span.h index bae56443092..b2f3d5e43c8 100644 --- a/src/mesa/drivers/dri/r200/r200_span.h +++ b/src/mesa/drivers/dri/r200/r200_span.h @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r200InitSpanFuncs( GLcontext *ctx ); -extern void -radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis); +extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); #endif diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 997c1711f90..f2e62d1bf78 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "radeon_buffer.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -1624,8 +1625,8 @@ void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - GLfloat xoffset = (GLfloat)dPriv->x; - GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; float_ui32_type sx = { v[MAT_SX] }; @@ -2316,34 +2317,34 @@ r200UpdateDrawBuffer(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - driRenderbuffer *drb; + struct radeon_renderbuffer *rrb; if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } - else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } - else { - /* drawing to multiple buffers, or none */ - return; + /* draw to front */ + rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { + /* draw to back */ + rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } else { + /* drawing to multiple buffers, or none */ + return; } - assert(drb); - assert(drb->flippedPitch); + assert(rrb); + assert(rrb->pitch); R200_STATECHANGE( rmesa, ctx ); +#if 0 /* Note: we used the (possibly) page-flipped values */ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) + = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } +#endif } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f68f5ae08ff..f46b01b56a6 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -52,6 +52,115 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" +/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in + * 1.3 cmdbuffers allow all previous state to be updated as well as + * the tcl scalar and vector areas. + */ +static struct { + int start; + int len; + const char *name; +} packet[RADEON_MAX_STATE_PACKETS] = { + {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, + {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, + {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, + {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, + {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, + {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, + {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, + {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, + {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, + {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, + {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, + {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, + {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, + {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, + {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, + {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, + {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, + {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, + {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, + {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, + {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, + "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, + {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, + {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, + {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, + {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, + {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, + {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, + {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, + {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, + {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, + {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, + {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, + {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, + {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, + {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, + {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, + {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, + {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, + {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, + {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, + {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, + {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, + {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, + {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, + {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, + {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, + {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, + {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, + {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, + {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, + "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, + {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, + {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, + {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, + {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, + {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, + {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, + {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, + {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, + {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, + {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, + {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, + "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, + {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ + {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ + {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, + {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, + {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, + {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, + {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, + {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, + {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, + {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, + {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, + {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, + {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, + {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, + {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, + {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, + {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, + {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, + {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, + {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, + {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, + {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, + {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ + {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, + {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, + {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, + {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, + {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, + {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, + {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, + {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, + {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, +}; + /* ============================================================= * State initialization */ @@ -179,6 +288,39 @@ VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 ) +#if 0 +static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; + GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; + + rrb = r200->radeon.state.color.rrb; + if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + ; + else + ; + +} +#endif + +static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + +} + + /* Initialize the context's hardware state. */ void r200InitState( r200ContextPtr rmesa ) @@ -267,6 +409,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); + + // rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); @@ -964,4 +1108,6 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); rmesa->hw.all_dirty = GL_TRUE; + + rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 1130c3544df..0be772d0158 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -48,6 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "tnl/t_pipeline.h" +#include "radeon_bo.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -284,33 +285,24 @@ static void flush_last_swtcl_prim(GLcontext *ctx) rmesa->dma.flush = NULL; - if (rmesa->dma.current.buf) { - struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset + - current->buf->buf->idx * RADEON_BUFFER_SIZE + - current->start); + radeon_bo_unmap(rmesa->swtcl.bo); + rcommonEnsureCmdBufSpace(rmesa, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); - assert (!(rmesa->swtcl.hw_primitive & R200_VF_PRIM_WALK_IND)); - assert (current->start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - current->ptr); + r200EmitState(rmesa); + r200EmitVertexAOS( rmesa, + rmesa->swtcl.vertex_size, + rmesa->swtcl.bo, 0); - if (rmesa->dma.current.start != rmesa->dma.current.ptr) { - r200EnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ + - rmesa->hw.max_state_size + VBUF_BUFSZ ); - r200EmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - current_offset); + + r200EmitVbufPrim( rmesa, + rmesa->swtcl.hw_primitive, + rmesa->swtcl.numverts); - r200EmitVbufPrim( rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - } - - rmesa->swtcl.numverts = 0; - current->start = current->ptr; - } + // COMMIT_BATCH(); + rmesa->swtcl.numverts = 0; } @@ -321,28 +313,16 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - r200RefillCurrentDmaRegion( rmesa ); - - if (!rmesa->dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->dma.current.start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current.ptr ); - - - { - GLubyte *head = (GLubyte *) (rmesa->dma.current.address + rmesa->dma.current.ptr); - rmesa->dma.current.ptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; + rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); + radeon_bo_map(rmesa->swtcl.bo, 1); + if (rmesa->swtcl.flush == NULL) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->swtcl.flush = flush_last_swtcl_prim; } + return rmesa->swtcl.bo->ptr; + } @@ -974,6 +954,6 @@ void r200DestroySwtcl( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (rmesa->swtcl.indexed_verts.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index d14564c29bf..4a31578c891 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -156,11 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->dma.flush) rmesa->dma.flush( rmesa->radeon.glCtx ); - r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); r200EmitAOS( rmesa, - rmesa->tcl.aos_components, rmesa->tcl.nr_aos_components, 0 ); return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); @@ -188,13 +187,12 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rmesa->hw.max_state_size + VBUF_BUFSZ ); r200EmitAOS( rmesa, - rmesa->tcl.aos_components, - rmesa->tcl.nr_aos_components, - start ); + rmesa->tcl.nr_aos_components, + start ); /* Why couldn't this packet have taken an offset param? */ @@ -570,9 +568,9 @@ static void transition_to_hwtnl( GLcontext *ctx ) rmesa->dma.flush = NULL; - if (rmesa->swtcl.indexed_verts.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + // __FUNCTION__ ); R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index e8b6876dd37..5a0922de215 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -226,7 +226,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, tex = (char *)texImage->Data + done * src_pitch; memset(®ion, 0, sizeof(region)); - r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); + // r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); /* Copy texdata to dma: */ @@ -262,7 +262,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, r200EmitWait( rmesa, RADEON_WAIT_2D ); - r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); + // r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); done += lines; } } diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3647022622b..798f1f58c9e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -496,8 +496,6 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) * state, so don't destroy it earlier */ - /* free the option cache */ - driDestroyOptionCache(&r300->radeon.optionCache); FREE(r300); } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 8449d00d37a..477756774d6 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -700,19 +700,11 @@ struct r500_fragment_program { #define REG_COLOR0 1 #define REG_TEX0 2 -struct r300_aos { - struct radeon_bo *bo; /** Buffer object where vertex data is stored */ - int offset; /** Offset into buffer object, in bytes */ - int components; /** Number of components per vertex */ - int stride; /** Stride in dwords (may be 0 for repeating) */ - int count; /** Number of vertices */ -}; - struct r300_state { struct r300_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; struct r300_vertex_shader_state vertex_shader; - struct r300_aos aos[R300_MAX_AOS_ARRAYS]; + struct radeon_aos aos[R300_MAX_AOS_ARRAYS]; int aos_count; struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index bf33c18979d..e2d90a843ef 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -63,141 +63,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DEBUG_ALL DEBUG_VERTS -#if defined(USE_X86_ASM) -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int __tmp; \ - __asm__ __volatile__( "rep ; movsl" \ - : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ - : "0" (nr), \ - "D" ((long)dst), \ - "S" ((long)src) ); \ -} while (0) -#else -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int j; \ - for ( j = 0 ; j < nr ; j++ ) \ - dst[j] = ((int *)src)[j]; \ - dst += nr; \ -} while (0) -#endif - -static void r300EmitVec4(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 4) - COPY_DWORDS(out, data, count); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out++; - data += stride; - } -} - -static void r300EmitVec8(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 8) - COPY_DWORDS(out, data, count * 2); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out += 2; - data += stride; - } -} - -static void r300EmitVec12(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 12) { - COPY_DWORDS(out, data, count * 3); - } - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out += 3; - data += stride; - } -} - -static void r300EmitVec16(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 16) - COPY_DWORDS(out, data, count * 4); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out[3] = *(int *)(data + 12); - out += 4; - data += stride; - } -} - -static void r300EmitVec(GLcontext * ctx, struct r300_aos *aos, - GLvoid * data, int size, int stride, int count) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - uint32_t *out; - uint32_t bo_size; - - memset(aos, 0, sizeof(struct r300_aos)); - if (stride == 0) { - bo_size = size * 4; - count = 1; - aos->stride = 0; - } else { - bo_size = size * count * 4; - aos->stride = size; - } - aos->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); - aos->offset = 0; - aos->components = size; - aos->count = count; - - radeon_bo_map(aos->bo, 1); - out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); - switch (size) { - case 1: r300EmitVec4(out, data, stride, count); break; - case 2: r300EmitVec8(out, data, stride, count); break; - case 3: r300EmitVec12(out, data, stride, count); break; - case 4: r300EmitVec16(out, data, stride, count); break; - default: - assert(0); - break; - } - radeon_bo_unmap(aos->bo); -} - #define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \ (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT) @@ -429,10 +294,10 @@ int r300EmitArrays(GLcontext * ctx) for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] = ci; } - r300EmitVec(ctx, &rmesa->state.aos[i], - vb->AttribPtr[tab[i]]->data, - vb->AttribPtr[tab[i]]->size, - vb->AttribPtr[tab[i]]->stride, count); + rcommon_emit_vector(ctx, &rmesa->state.aos[i], + vb->AttribPtr[tab[i]]->data, + vb->AttribPtr[tab[i]]->size, + vb->AttribPtr[tab[i]]->stride, count); } /* Setup INPUT_ROUTE. */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 1e7a639c000..d6df2e9edf0 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -44,13 +44,6 @@ #include "r300_cmdbuf.h" #include "radeon_reg.h" -/* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up - * with DRM */ -#define CP_PACKET2 (2 << 30) -#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, int reg, int count) { diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index c81393e7476..ef3671eadbd 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -180,11 +180,11 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, n_elts * 4, 4, RADEON_GEM_DOMAIN_GTT, 0); - rmesa->state.elt_dma_offset = 0; - radeon_bo_map(rmesa->state.elt_dma_bo, 1); + rmesa->state.elt_dma_offset = 0; + radeon_bo_map(rmesa->state.elt_dma_bo, 1); out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; memcpy(out, elts, n_elts * 4); - radeon_bo_unmap(rmesa->state.elt_dma_bo); + radeon_bo_unmap(rmesa->state.elt_dma_bo); } static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 03fc2107dba..eb86bd3bdd6 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -271,13 +271,13 @@ r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) GLuint bytes = vsize * nverts; rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); - radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->swtcl.flush == NULL) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->swtcl.flush = flush_last_swtcl_prim; - } - return rmesa->swtcl.bo->ptr; + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); + radeon_bo_map(rmesa->swtcl.bo, 1); + if (rmesa->swtcl.flush == NULL) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->swtcl.flush = flush_last_swtcl_prim; + } + return rmesa->swtcl.bo->ptr; } static GLuint reduced_prim[] = { diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 68849676639..13a76824165 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -60,502 +60,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" /* for symbolic values of enum-type options */ #include "drirenderbuffer.h" -#define DRIVER_DATE "20060815" - - -/* Return various strings for glGetString(). - */ -static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - static char buffer[128]; - - switch (name) { - case GL_VENDOR: - if (IS_R300_CLASS(radeon->radeonScreen)) - return (GLubyte *) "DRI R300 Project"; - else - return (GLubyte *) "Tungsten Graphics, Inc."; - - case GL_RENDERER: - { - unsigned offset; - GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : - radeon->radeonScreen->AGPMode; - const char* chipname; - - - - if (IS_R300_CLASS(radeon->radeonScreen)) - chipname = "R300"; - else - chipname = "R200"; - - offset = driGetRendererString(buffer, chipname, DRIVER_DATE, - agp_mode); - - if (IS_R300_CLASS(radeon->radeonScreen)) { - sprintf(&buffer[offset], " %sTCL", - (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) - ? "" : "NO-"); - } else { - sprintf(&buffer[offset], " %sTCL", - !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) - ? "" : "NO-"); - } - - if (radeon->radeonScreen->driScreen->dri2.enabled) - strcat(buffer, " DRI2"); - - return (GLubyte *) buffer; - } - - default: - return NULL; - } -} - -/* Initialize the driver's misc functions. - */ -static void radeonInitDriverFuncs(struct dd_function_table *functions) -{ - functions->GetString = radeonGetString; -} - - -/** - * Create and initialize all common fields of the context, - * including the Mesa context itself. - */ -GLboolean radeonInitContext(radeonContextPtr radeon, - struct dd_function_table* functions, - const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate) -{ - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); - GLcontext* ctx; - GLcontext* shareCtx; - int fthrottle_mode; - - /* Fill in additional standard functions. */ - radeonInitDriverFuncs(functions); - - radeon->radeonScreen = screen; - /* Allocate and initialize the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx; - else - shareCtx = NULL; - radeon->glCtx = _mesa_create_context(glVisual, shareCtx, - functions, (void *)radeon); - if (!radeon->glCtx) - return GL_FALSE; - - ctx = radeon->glCtx; - driContextPriv->driverPrivate = radeon; - - /* DRI fields */ - radeon->dri.context = driContextPriv; - radeon->dri.screen = sPriv; - radeon->dri.drawable = NULL; - radeon->dri.readable = NULL; - radeon->dri.hwContext = driContextPriv->hHWContext; - radeon->dri.hwLock = &sPriv->pSAREA->lock; - radeon->dri.fd = sPriv->fd; - radeon->dri.drmMinor = sPriv->drm_version.minor; - - radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + - screen->sarea_priv_offset); - - /* Setup IRQs */ - fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); - radeon->iw.irq_seq = -1; - radeon->irqsEmitted = 0; - radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - radeon->radeonScreen->irq); - - radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - - if (!radeon->do_irqs) - fprintf(stderr, - "IRQ's not enabled, falling back to %s: %d %d\n", - radeon->do_usleeps ? "usleeps" : "busy waits", - fthrottle_mode, radeon->radeonScreen->irq); - - (*sPriv->systemTime->getUST) (&radeon->swap_ust); - - return GL_TRUE; -} - - -/** - * Cleanup common context fields. - * Called by r200DestroyContext/r300DestroyContext - */ -void radeonCleanupContext(radeonContextPtr radeon) -{ - FILE *track; - struct radeon_renderbuffer *rb; - GLframebuffer *fb; - - fb = (void*)radeon->dri.drawable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - fb = (void*)radeon->dri.readable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - - /* _mesa_destroy_context() might result in calls to functions that - * depend on the DriverCtx, so don't set it to NULL before. - * - * radeon->glCtx->DriverCtx = NULL; - */ - - /* free the Mesa context */ - _mesa_destroy_context(radeon->glCtx); - - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = 0; - } - track = fopen("/tmp/tracklog", "w"); - if (track) { - radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); - fclose(track); - } -} - -static void -radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) -{ - /* if radeon->fake */ - struct radeon_renderbuffer *rb; - - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } -} - -static void -radeon_make_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) -{ - int size = 4096*4096*4; - /* if radeon->fake */ - struct radeon_renderbuffer *rb; - - if (radeon->radeonScreen->kernel_mm) { - radeon_make_kernel_renderbuffer_current(radeon, draw); - return; - } - - - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } -} - - -void -radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) -{ - unsigned int attachments[10]; - __DRIbuffer *buffers; - __DRIscreen *screen; - struct radeon_renderbuffer *rb; - int i, count; - GLframebuffer *draw; - radeonContextPtr radeon; - - draw = drawable->driverPrivate; - screen = context->driScreenPriv; - radeon = (radeonContextPtr) context->driverPrivate; - i = 0; - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_FRONT_LEFT; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_BACK_LEFT; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_DEPTH; - } - - buffers = (*screen->dri2.loader->getBuffers)(drawable, - &drawable->w, - &drawable->h, - attachments, i, - &count, - drawable->loaderPrivate); - if (buffers == NULL) - return; - - /* set one cliprect to cover the whole drawable */ - drawable->x = 0; - drawable->y = 0; - drawable->backX = 0; - drawable->backY = 0; - drawable->numClipRects = 1; - drawable->pClipRects[0].x1 = 0; - drawable->pClipRects[0].y1 = 0; - drawable->pClipRects[0].x2 = drawable->w; - drawable->pClipRects[0].y2 = drawable->h; - drawable->numBackClipRects = 1; - drawable->pBackClipRects[0].x1 = 0; - drawable->pBackClipRects[0].y1 = 0; - drawable->pBackClipRects[0].x2 = drawable->w; - drawable->pBackClipRects[0].y2 = drawable->h; - for (i = 0; i < count; i++) { - switch (buffers[i].attachment) { - case __DRI_BUFFER_FRONT_LEFT: - rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - if (rb->bo == NULL) { - fprintf(stderr, "failled to attach front %d\n", - buffers[i].name); - } - break; - case __DRI_BUFFER_BACK_LEFT: - rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - break; - case __DRI_BUFFER_DEPTH: - rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - break; - case __DRI_BUFFER_STENCIL: - break; - case __DRI_BUFFER_ACCUM: - default: - fprintf(stderr, - "unhandled buffer attach event, attacment type %d\n", - buffers[i].attachment); - return; - } - } - radeon = (radeonContextPtr) context->driverPrivate; - driUpdateFramebufferSize(radeon->glCtx, drawable); -} - - -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) -{ - radeonContextPtr radeon; - GLframebuffer *dfb, *rfb; - - if (!driContextPriv) { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current(NULL, NULL, NULL); - return GL_TRUE; - } - radeon = (radeonContextPtr) driContextPriv->driverPrivate; - dfb = driDrawPriv->driverPrivate; - rfb = driReadPriv->driverPrivate; - - if (driContextPriv->driScreenPriv->dri2.enabled) { - radeon_update_renderbuffers(driContextPriv, driDrawPriv); - if (driDrawPriv != driReadPriv) - radeon_update_renderbuffers(driContextPriv, driReadPriv); - radeon->state.color.rrb = - (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - radeon->state.depth.rrb = - (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; - } - - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); - - driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); - if (driReadPriv != driDrawPriv) - driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeon_make_renderbuffer_current(radeon, dfb); - } - - _mesa_make_current(radeon->glCtx, dfb, rfb); - - if (radeon->dri.drawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = - (radeon->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&radeon-> - optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank(driDrawPriv); - } - } - - radeon->dri.readable = driReadPriv; - - if (radeon->dri.drawable != driDrawPriv || - radeon->lastStamp != driDrawPriv->lastStamp) { - radeon->dri.drawable = driDrawPriv; - - radeonSetCliprects(radeon); - r300UpdateViewportOffset(radeon->glCtx); - } - - _mesa_update_state(radeon->glCtx); - - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeonUpdatePageFlipping(radeon); - } - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} - /* Force the context `c' to be unbound from its buffer. */ GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index fbcbf72b2bf..d6fa50a0290 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -14,6 +14,10 @@ void rcommonBeginBatch(radeonContextPtr rmesa, const char *function, int line); +#define CP_PACKET2 (2 << 30) +#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) /** * Every function writing to the command buffer needs to declare this diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index d6e15bc3b86..22fb908fb4b 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -46,6 +46,16 @@ typedef struct radeon_context *radeonContextPtr; #define R200_FALLBACK_DISABLE 0x10 #define R200_FALLBACK_BORDER_MODE 0x20 +#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ +#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ +#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ +#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ +#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ +#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ +#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ +#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ +#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ + /* The blit width for texture uploads */ #define BLIT_WIDTH_BYTES 1024 @@ -157,6 +167,13 @@ struct radeon_dma_region { int aos_size; }; +struct radeon_aos { + struct radeon_bo *bo; /** Buffer object where vertex data is stored */ + int offset; /** Offset into buffer object, in bytes */ + int components; /** Number of components per vertex */ + int stride; /** Stride in dwords (may be 0 for repeating) */ + int count; /** Number of vertices */ +}; struct radeon_dma { /* Active dma region. Allocations for vertices and retained diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index a2343526585..383334a0052 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -50,6 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" #include "vblank.h" +#include "xmlpool.h" /* for symbolic values of enum-type options */ #include "radeon_bo.h" #include "radeon_cs.h" @@ -66,6 +67,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_lock.h" #include "common_cmdbuf.h" +#define DRIVER_DATE "20090101" + #ifndef RADEON_DEBUG int RADEON_DEBUG = (0); #endif @@ -703,3 +706,634 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n, } radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); } + + + +/* Return various strings for glGetString(). + */ +static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + static char buffer[128]; + + switch (name) { + case GL_VENDOR: + if (IS_R300_CLASS(radeon->radeonScreen)) + return (GLubyte *) "DRI R300 Project"; + else + return (GLubyte *) "Tungsten Graphics, Inc."; + + case GL_RENDERER: + { + unsigned offset; + GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : + radeon->radeonScreen->AGPMode; + const char* chipname; + + + + if (IS_R300_CLASS(radeon->radeonScreen)) + chipname = "R300"; + else + chipname = "R200"; + + offset = driGetRendererString(buffer, chipname, DRIVER_DATE, + agp_mode); + + if (IS_R300_CLASS(radeon->radeonScreen)) { + sprintf(&buffer[offset], " %sTCL", + (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) + ? "" : "NO-"); + } else { + sprintf(&buffer[offset], " %sTCL", + !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) + ? "" : "NO-"); + } + + if (radeon->radeonScreen->driScreen->dri2.enabled) + strcat(buffer, " DRI2"); + + return (GLubyte *) buffer; + } + + default: + return NULL; + } +} + +/* Initialize the driver's misc functions. + */ +static void radeonInitDriverFuncs(struct dd_function_table *functions) +{ + functions->GetString = radeonGetString; +} + +/** + * Create and initialize all common fields of the context, + * including the Mesa context itself. + */ +GLboolean radeonInitContext(radeonContextPtr radeon, + struct dd_function_table* functions, + const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPrivate) +{ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + GLcontext* ctx; + GLcontext* shareCtx; + int fthrottle_mode; + + /* Fill in additional standard functions. */ + radeonInitDriverFuncs(functions); + + radeon->radeonScreen = screen; + /* Allocate and initialize the Mesa context */ + if (sharedContextPrivate) + shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx; + else + shareCtx = NULL; + radeon->glCtx = _mesa_create_context(glVisual, shareCtx, + functions, (void *)radeon); + if (!radeon->glCtx) + return GL_FALSE; + + ctx = radeon->glCtx; + driContextPriv->driverPrivate = radeon; + + /* DRI fields */ + radeon->dri.context = driContextPriv; + radeon->dri.screen = sPriv; + radeon->dri.drawable = NULL; + radeon->dri.readable = NULL; + radeon->dri.hwContext = driContextPriv->hHWContext; + radeon->dri.hwLock = &sPriv->pSAREA->lock; + radeon->dri.fd = sPriv->fd; + radeon->dri.drmMinor = sPriv->drm_version.minor; + + radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + + screen->sarea_priv_offset); + + /* Setup IRQs */ + fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); + radeon->iw.irq_seq = -1; + radeon->irqsEmitted = 0; + radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && + radeon->radeonScreen->irq); + + radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); + + if (!radeon->do_irqs) + fprintf(stderr, + "IRQ's not enabled, falling back to %s: %d %d\n", + radeon->do_usleeps ? "usleeps" : "busy waits", + fthrottle_mode, radeon->radeonScreen->irq); + + (*sPriv->systemTime->getUST) (&radeon->swap_ust); + + return GL_TRUE; +} + +/** + * Cleanup common context fields. + * Called by r200DestroyContext/r300DestroyContext + */ +void radeonCleanupContext(radeonContextPtr radeon) +{ + FILE *track; + struct radeon_renderbuffer *rb; + GLframebuffer *fb; + + fb = (void*)radeon->dri.drawable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + fb = (void*)radeon->dri.readable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + + /* _mesa_destroy_context() might result in calls to functions that + * depend on the DriverCtx, so don't set it to NULL before. + * + * radeon->glCtx->DriverCtx = NULL; + */ + + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); + + /* free the option cache */ + driDestroyOptionCache(&radeon->optionCache); + + if (radeon->state.scissor.pClipRects) { + FREE(radeon->state.scissor.pClipRects); + radeon->state.scissor.pClipRects = 0; + } + track = fopen("/tmp/tracklog", "w"); + if (track) { + radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); + fclose(track); + } +} + +void +radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + +static void +radeon_make_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + int size = 4096*4096*4; + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if (radeon->radeonScreen->kernel_mm) { + radeon_make_kernel_renderbuffer_current(radeon, draw); + return; + } + + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + + +void +radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) +{ + unsigned int attachments[10]; + __DRIbuffer *buffers; + __DRIscreen *screen; + struct radeon_renderbuffer *rb; + int i, count; + GLframebuffer *draw; + radeonContextPtr radeon; + + draw = drawable->driverPrivate; + screen = context->driScreenPriv; + radeon = (radeonContextPtr) context->driverPrivate; + i = 0; + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_DEPTH; + } + + buffers = (*screen->dri2.loader->getBuffers)(drawable, + &drawable->w, + &drawable->h, + attachments, i, + &count, + drawable->loaderPrivate); + if (buffers == NULL) + return; + + /* set one cliprect to cover the whole drawable */ + drawable->x = 0; + drawable->y = 0; + drawable->backX = 0; + drawable->backY = 0; + drawable->numClipRects = 1; + drawable->pClipRects[0].x1 = 0; + drawable->pClipRects[0].y1 = 0; + drawable->pClipRects[0].x2 = drawable->w; + drawable->pClipRects[0].y2 = drawable->h; + drawable->numBackClipRects = 1; + drawable->pBackClipRects[0].x1 = 0; + drawable->pBackClipRects[0].y1 = 0; + drawable->pBackClipRects[0].x2 = drawable->w; + drawable->pBackClipRects[0].y2 = drawable->h; + for (i = 0; i < count; i++) { + switch (buffers[i].attachment) { + case __DRI_BUFFER_FRONT_LEFT: + rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + if (rb->bo == NULL) { + fprintf(stderr, "failled to attach front %d\n", + buffers[i].name); + } + break; + case __DRI_BUFFER_BACK_LEFT: + rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_DEPTH: + rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_STENCIL: + break; + case __DRI_BUFFER_ACCUM: + default: + fprintf(stderr, + "unhandled buffer attach event, attacment type %d\n", + buffers[i].attachment); + return; + } + } + radeon = (radeonContextPtr) context->driverPrivate; + driUpdateFramebufferSize(radeon->glCtx, drawable); +} + +/* Force the context `c' to be the current context and associate with it + * buffer `b'. + */ +GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, + __DRIdrawablePrivate * driDrawPriv, + __DRIdrawablePrivate * driReadPriv) +{ + radeonContextPtr radeon; + GLframebuffer *dfb, *rfb; + + if (!driContextPriv) { + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx is null\n", __FUNCTION__); + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; + } + radeon = (radeonContextPtr) driContextPriv->driverPrivate; + dfb = driDrawPriv->driverPrivate; + rfb = driReadPriv->driverPrivate; + + if (driContextPriv->driScreenPriv->dri2.enabled) { + radeon_update_renderbuffers(driContextPriv, driDrawPriv); + if (driDrawPriv != driReadPriv) + radeon_update_renderbuffers(driContextPriv, driReadPriv); + radeon->state.color.rrb = + (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon->state.depth.rrb = + (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + } + + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); + + driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); + if (driReadPriv != driDrawPriv) + driUpdateFramebufferSize(radeon->glCtx, driReadPriv); + + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeon_make_renderbuffer_current(radeon, dfb); + } + + _mesa_make_current(radeon->glCtx, dfb, rfb); + + if (radeon->dri.drawable != driDrawPriv) { + if (driDrawPriv->swap_interval == (unsigned)-1) { + driDrawPriv->vblFlags = + (radeon->radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; + + driDrawableInitVBlank(driDrawPriv); + } + } + + radeon->dri.readable = driReadPriv; + + if (radeon->dri.drawable != driDrawPriv || + radeon->lastStamp != driDrawPriv->lastStamp) { + radeon->dri.drawable = driDrawPriv; + + radeonSetCliprects(radeon); + radeon->vtbl.update_viewport_offset(radeon->glCtx); + } + + _mesa_update_state(radeon->glCtx); + + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeonUpdatePageFlipping(radeon); + } + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "End %s\n", __FUNCTION__); + return GL_TRUE; +} + + +#if defined(USE_X86_ASM) +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int __tmp; \ + __asm__ __volatile__( "rep ; movsl" \ + : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ + : "0" (nr), \ + "D" ((long)dst), \ + "S" ((long)src) ); \ +} while (0) +#else +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int j; \ + for ( j = 0 ; j < nr ; j++ ) \ + dst[j] = ((int *)src)[j]; \ + dst += nr; \ +} while (0) +#endif + +static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 4) + COPY_DWORDS(out, data, count); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out++; + data += stride; + } +} + +static void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 8) + COPY_DWORDS(out, data, count * 2); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out += 2; + data += stride; + } +} + +static void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 12) { + COPY_DWORDS(out, data, count * 3); + } + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out += 3; + data += stride; + } +} + +static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 16) + COPY_DWORDS(out, data, count * 4); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out[3] = *(int *)(data + 12); + out += 4; + data += stride; + } +} + +void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, + GLvoid * data, int size, int stride, int count) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + uint32_t *out; + uint32_t bo_size; + + memset(aos, 0, sizeof(struct radeon_aos)); + if (stride == 0) { + bo_size = size * 4; + count = 1; + aos->stride = 0; + } else { + bo_size = size * count * 4; + aos->stride = size; + } + aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, + 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); + aos->offset = 0; + aos->components = size; + aos->count = count; + + radeon_bo_map(aos->bo, 1); + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); + switch (size) { + case 1: radeonEmitVec4(out, data, stride, count); break; + case 2: radeonEmitVec8(out, data, stride, count); break; + case 3: radeonEmitVec12(out, data, stride, count); break; + case 4: radeonEmitVec16(out, data, stride, count); break; + default: + assert(0); + break; + } + radeon_bo_unmap(aos->bo); +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index d7161c4b96a..32cbae7ad3f 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -18,4 +18,18 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, void radeonUpdatePageFlipping(radeonContextPtr rmesa); +GLboolean radeonInitContext(radeonContextPtr radeon, + struct dd_function_table* functions, + const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPrivate); + +void radeonCleanupContext(radeonContextPtr radeon); +void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); +GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, + __DRIdrawablePrivate * driDrawPriv, + __DRIdrawablePrivate * driReadPriv); + +void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, + GLvoid * data, int size, int stride, int count); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index c7adf4975ba..b87275c56b8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -527,6 +527,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) radeonFlushCmdBuf( rmesa, __FUNCTION__ ); } + radeonCleanupContext(&rmesa->radeon); _mesa_vector4f_free( &rmesa->tcl.ObjClean ); if (rmesa->radeon.state.scissor.pClipRects) { @@ -548,65 +549,12 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) assert( is_empty_list( & rmesa->radeon.swapped ) ); } - /* free the Mesa context */ - rmesa->radeon.glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->radeon.glCtx ); - - /* free the option cache */ - driDestroyOptionCache (&rmesa->radeon.optionCache); + radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); } } -/* Make context `c' the current context and bind it to the given - * drawing and reading surfaces. - */ -GLboolean -radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) -{ - if ( driContextPriv ) { - radeonContextPtr newCtx = - (radeonContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx); - - newCtx->dri.readable = driReadPriv; - - if ( (newCtx->dri.drawable != driDrawPriv) || - newCtx->lastStamp != driDrawPriv->lastStamp ) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&newCtx->optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank( driDrawPriv ); - } - - newCtx->dri.drawable = driDrawPriv; - - radeonSetCliprects(newCtx); - radeonUpdateViewportOffset( newCtx->glCtx ); - } - - _mesa_make_current( newCtx->glCtx, - (GLframebuffer *) driDrawPriv->driverPrivate, - (GLframebuffer *) driReadPriv->driverPrivate ); - - _mesa_update_state( newCtx->glCtx ); - } else { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current( NULL, NULL, NULL ); - } - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} /* Force the context `c' to be unbound from its buffer. */ diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 0b6791f54c7..320bf9244b0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -76,6 +76,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_bo_legacy.h" #include "radeon_bo_gem.h" +#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ + DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ +DRI_CONF_OPT_END + #if !RADEON_COMMON /* R100 */ PUBLIC const char __driConfigOptions[] = DRI_CONF_BEGIN @@ -85,6 +91,7 @@ DRI_CONF_BEGIN DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) DRI_CONF_HYPERZ(false) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) @@ -100,7 +107,7 @@ DRI_CONF_BEGIN DRI_CONF_NO_RAST(false) DRI_CONF_SECTION_END DRI_CONF_END; -static const GLuint __driNConfigOptions = 14; +static const GLuint __driNConfigOptions = 15; #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) @@ -112,6 +119,7 @@ DRI_CONF_BEGIN DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) DRI_CONF_HYPERZ(false) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) @@ -131,7 +139,7 @@ DRI_CONF_BEGIN DRI_CONF_NV_VERTEX_PROGRAM(false) DRI_CONF_SECTION_END DRI_CONF_END; -static const GLuint __driNConfigOptions = 16; +static const GLuint __driNConfigOptions = 17; extern const struct dri_extension blend_extensions[]; extern const struct dri_extension ARB_vp_extension[]; @@ -154,11 +162,7 @@ DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ DRI_CONF_OPT_END -#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ -DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ - DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ - DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ -DRI_CONF_OPT_END + #define DRI_CONF_DISABLE_S3TC(def) \ DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ @@ -1152,7 +1156,6 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) return GL_TRUE; } -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) static GLboolean radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, GLenum intFormat, GLuint w, GLuint h) @@ -1308,107 +1311,6 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, return (driDrawPriv->driverPrivate != NULL); } -#else - -/** - * Create the Mesa framebuffer and renderbuffers for a given window/drawable. - * - * \todo This function (and its interface) will need to be updated to support - * pbuffers. - */ -static GLboolean -radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, - const __GLcontextModes *mesaVis, - GLboolean isPixmap ) -{ - radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; - - if (isPixmap) { - return GL_FALSE; /* not implemented */ - } - else { - const GLboolean swDepth = GL_FALSE; - const GLboolean swAlpha = GL_FALSE; - const GLboolean swAccum = mesaVis->accumRedBits > 0; - const GLboolean swStencil = mesaVis->stencilBits > 0 && - mesaVis->depthBits != 24; - struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); - - /* front color renderbuffer */ - { - driRenderbuffer *frontRb - = driNewRenderbuffer(GL_RGBA, - driScrnPriv->pFB + screen->frontOffset, - screen->cpp, - screen->frontOffset, screen->frontPitch, - driDrawPriv); - radeonSetSpanFunctions(frontRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); - } - - /* back color renderbuffer */ - if (mesaVis->doubleBufferMode) { - driRenderbuffer *backRb - = driNewRenderbuffer(GL_RGBA, - driScrnPriv->pFB + screen->backOffset, - screen->cpp, - screen->backOffset, screen->backPitch, - driDrawPriv); - radeonSetSpanFunctions(backRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); - } - - /* depth renderbuffer */ - if (mesaVis->depthBits == 16) { - driRenderbuffer *depthRb - = driNewRenderbuffer(GL_DEPTH_COMPONENT16, - driScrnPriv->pFB + screen->depthOffset, - screen->cpp, - screen->depthOffset, screen->depthPitch, - driDrawPriv); - radeonSetSpanFunctions(depthRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - // depthRb->has_surface = screen->depthHasSurface; - } - else if (mesaVis->depthBits == 24) { - driRenderbuffer *depthRb - = driNewRenderbuffer(GL_DEPTH_COMPONENT24, - driScrnPriv->pFB + screen->depthOffset, - screen->cpp, - screen->depthOffset, screen->depthPitch, - driDrawPriv); - radeonSetSpanFunctions(depthRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - // depthRb->has_surface = screen->depthHasSurface; - } - - /* stencil renderbuffer */ - if (mesaVis->stencilBits > 0 && !swStencil) { - driRenderbuffer *stencilRb - = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, - driScrnPriv->pFB + screen->depthOffset, - screen->cpp, - screen->depthOffset, screen->depthPitch, - driDrawPriv); - radeonSetSpanFunctions(stencilRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); - //stencilRb->has_surface = screen->depthHasSurface; - } - - _mesa_add_soft_renderbuffers(fb, - GL_FALSE, /* color */ - swDepth, - swStencil, - swAccum, - swAlpha, - GL_FALSE /* aux */); - driDrawPriv->driverPrivate = (void *) fb; - - return (driDrawPriv->driverPrivate != NULL); - } -} -#endif static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) @@ -1621,7 +1523,7 @@ const struct __DriverAPIRec driDriverAPI = { .CreateBuffer = radeonCreateBuffer, .DestroyBuffer = radeonDestroyBuffer, .SwapBuffers = radeonSwapBuffers, - .MakeCurrent = r200MakeCurrent, + .MakeCurrent = radeonMakeCurrent, .UnbindContext = r200UnbindContext, .GetSwapInfo = getSwapInfo, .GetDrawableMSC = driDrawableGetMSC32, diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 423f3ca7e39..a850baea296 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -308,20 +308,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis) +void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 - && vis->blueBits == 5) { - radeonInitPointers_RGB565(&drb->Base); - } else { - radeonInitPointers_ARGB8888(&drb->Base); - } - } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) { - radeonInitDepthPointers_z16(&drb->Base); - } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) { - radeonInitDepthPointers_z24_s8(&drb->Base); - } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&drb->Base); + if (rrb->base.InternalFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); + } else if (rrb->base.InternalFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h index 1650a9bea98..93d76303109 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h @@ -48,9 +48,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void radeonInitSpanFuncs(GLcontext * ctx); -#if COMPILE_R300 extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); -#else -extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis); -#endif #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 67f861a48ee..0c9fb14857c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1404,8 +1404,8 @@ void radeonUpdateWindow( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - GLfloat xoffset = (GLfloat)dPriv->x; - GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; float_ui32_type sx = { v[MAT_SX] }; -- cgit v1.2.3 From 04029e5ddb030445edc98305b091b9a35479282a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 20 Jan 2009 22:59:34 +1000 Subject: r200: tri runs without crashing - doesn't draw anything --- src/mesa/drivers/dri/r200/r200_context.c | 6 + src/mesa/drivers/dri/r200/r200_maos_arrays.c | 248 +++++---------------------- src/mesa/drivers/dri/radeon/common_misc.c | 6 +- 3 files changed, 52 insertions(+), 208 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index acbfdb2db6d..741d051818d 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -276,6 +276,11 @@ static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes { } +static void r200_vtbl_emit_state(radeonContextPtr rmesa) +{ + r200EmitState((r200ContextPtr)rmesa); +} + static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; @@ -284,6 +289,7 @@ static void r200_init_vtbl(radeonContextPtr radeon) radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; + radeon->vtbl.emit_state = r200_vtbl_emit_state; } diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 7fe1590c8dc..c3c2b973b59 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -174,200 +174,38 @@ do { \ } while (0) #endif - -static void emit_vecfog( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - GLfloat *out; - - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - assert (!rvb->buf); - - if (stride == 0) { - // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); - count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = 1; - } - else { - // r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 1; - rvb->aos_size = 1; - } - - /* Emit the data - */ - out = (GLfloat *)(rvb->address + rvb->start); - for (i = 0; i < count; i++) { - out[0] = r200ComputeFogBlendFactor( ctx, *(GLfloat *)data ); - out++; - data += stride; - } - -} - - -static void emit_vec4( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 4) - COPY_DWORDS( out, data, count ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out++; - data += stride; - } -} - - -static void emit_vec8( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) +static void r200_emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, + GLvoid *data, int stride, int count) { - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 8) - COPY_DWORDS( out, data, count*2 ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data+4); - out += 2; - data += stride; - } -} - -static void emit_vec12( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 12) - COPY_DWORDS( out, data, count*3 ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data+4); - out[2] = *(int *)(data+8); - out += 3; - data += stride; - } -} - -static void emit_vec16( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 16) - COPY_DWORDS( out, data, count*4 ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data+4); - out[2] = *(int *)(data+8); - out[3] = *(int *)(data+12); - out += 4; - data += stride; - } -} - - -static void emit_vector( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int size, - int stride, - int count ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d size %d stride %d\n", - __FUNCTION__, count, size, stride); - - assert (!rvb->buf); - - if (stride == 0) { - // r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); - count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = size; - } - else { - // r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = size; - rvb->aos_size = size; - } - - /* Emit the data - */ - switch (size) { - case 1: - emit_vec4( ctx, rvb, data, stride, count ); - break; - case 2: - emit_vec8( ctx, rvb, data, stride, count ); - break; - case 3: - emit_vec12( ctx, rvb, data, stride, count ); - break; - case 4: - emit_vec16( ctx, rvb, data, stride, count ); - break; - default: - assert(0); - exit(1); - break; - } - + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + uint32_t *out; + uint32_t bo_size; + int i; + int size = 1; + + memset(aos, 0, sizeof(struct radeon_aos)); + if (stride == 0) { + bo_size = size * 4; + count = 1; + aos->stride = 0; + } else { + bo_size = size * count * 4; + aos->stride = size; + } + aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, + 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); + aos->offset = 0; + aos->components = size; + aos->count = count; + + radeon_bo_map(aos->bo, 1); + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); + for (i = 0; i < count; i++) { + out[0] = r200ComputeFogBlendFactor( ctx, *(GLfloat *)data ); + out++; + data += stride; + } + radeon_bo_unmap(aos->bo); } @@ -419,17 +257,17 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) if (!rmesa->tcl.vertex_data[i].buf) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, - &(rmesa->tcl.vertex_data[i]), + &(rmesa->tcl.aos[i]), (char *)VB->AttribPtr[attrib]->data, 1, VB->AttribPtr[attrib]->stride, count); else - emit_vecfog( ctx, - &(rmesa->tcl.vertex_data[i]), - (char *)VB->AttribPtr[attrib]->data, - VB->AttribPtr[attrib]->stride, - count); + r200_emit_vecfog( ctx, + &(rmesa->tcl.aos[i]), + (char *)VB->AttribPtr[attrib]->data, + VB->AttribPtr[attrib]->stride, + count); } vfmt0 |= R200_VTX_DISCRETE_FOG; goto after_emit; @@ -474,12 +312,12 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) assert(0); } if (!rmesa->tcl.vertex_data[i].buf) { - emit_vector( ctx, - &(rmesa->tcl.vertex_data[i]), - (char *)VB->AttribPtr[attrib]->data, - emitsize, - VB->AttribPtr[attrib]->stride, - count ); + rcommon_emit_vector( ctx, + &(rmesa->tcl.aos[i]), + (char *)VB->AttribPtr[attrib]->data, + emitsize, + VB->AttribPtr[attrib]->stride, + count ); } after_emit: assert(nr < 12); diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 383334a0052..51cbe590244 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1311,15 +1311,15 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, memset(aos, 0, sizeof(struct radeon_aos)); if (stride == 0) { - bo_size = size * 4; + bo_size = size * 4; count = 1; aos->stride = 0; } else { - bo_size = size * count * 4; + bo_size = size * count * 4; aos->stride = size; } aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); + 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); aos->offset = 0; aos->components = size; aos->count = count; -- cgit v1.2.3 From d9c4a01bad3a7d4a965fc09d8605afc6ca48f6f9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 21 Jan 2009 01:40:33 +1000 Subject: r200: make tri render on my r200. --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 28 ++++-------- src/mesa/drivers/dri/r200/r200_ioctl.c | 6 ++- src/mesa/drivers/dri/r200/r200_ioctl.h | 27 ++++------- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 18 ++++---- src/mesa/drivers/dri/r200/r200_state_init.c | 62 +++++++++++++++++++++----- src/mesa/drivers/dri/r200/r200_tcl.c | 2 + src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_state.c | 2 +- src/mesa/drivers/dri/radeon/common_lock.c | 13 ------ src/mesa/drivers/dri/radeon/common_misc.c | 13 ++++++ src/mesa/drivers/dri/radeon/common_misc.h | 1 + src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 47 +++++++++++-------- 12 files changed, 129 insertions(+), 94 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index f107ff56245..6d421f5d5ec 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -47,17 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_sanity.h" #include "radeon_reg.h" -static void print_state_atom( struct radeon_state_atom *state ) -{ - int i; - - fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); - - if (0 & R200_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < state->cmd_size ; i++) - fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); - -} +#define DEBUG_CMDBUF 0 /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. @@ -141,7 +131,7 @@ static void r200SaveHwState( r200ContextPtr rmesa ) rmesa->backup_store.cmd_used += size; } if (R200_DEBUG & DEBUG_STATE) - print_state_atom( atom ); + radeon_print_state_atom( atom ); } } @@ -161,9 +151,9 @@ static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) if ((atom->dirty || r200->hw.all_dirty) == dirty) { dwords = (*atom->check) (r200->radeon.glCtx, atom); if (dwords) { - // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - // r300PrintStateAtom(r300, atom); - // } + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + radeon_print_state_atom(atom); + } if (atom->emit) { (*atom->emit)(r200->radeon.glCtx, atom); } else { @@ -173,10 +163,10 @@ static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) } atom->dirty = GL_FALSE; } else { - // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - // fprintf(stderr, " skip state %s\n", - // atom->name); - // } + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } } } } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 1bb97c50023..1fbbbfbb569 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -41,7 +41,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" +#include "radeon_cs.h" #include "r200_context.h" + #include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" @@ -525,8 +527,8 @@ void r200Flush( GLcontext *ctx ) rmesa->dma.flush( ctx ); r200EmitState( rmesa ); - - if (rmesa->store.cmd_used) + + if (rmesa->radeon.cmdbuf.cs->cdw) rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index f36a6fd90f6..1ae0dd114b5 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -201,40 +201,31 @@ static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa, } #endif -static inline uint32_t cmdpacket3_clip(int cmd_type) +static inline uint32_t cmdpacket3(int cmd_type) { drm_radeon_cmd_header_t cmd; cmd.i = 0; - cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP; + cmd.header.cmd_type = cmd_type; return (uint32_t)cmd.i; } -#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ + +#define OUT_BATCH_PACKET3(packet, num_extra) do { \ if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3_clip(0)); \ - OUT_BATCH(packet); \ + OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3)); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } else { \ OUT_BATCH(CP_PACKET2); \ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } \ } while(0) -static inline uint32_t cmdpacket3(int cmd_type) -{ - drm_radeon_cmd_header_t cmd; - - cmd.i = 0; - cmd.header.cmd_type = RADEON_CMD_PACKET3; - - return (uint32_t)cmd.i; - -} -#define OUT_BATCH_PACKET3(packet, num_extra) do { \ +#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(0)); \ - OUT_BATCH(packet); \ + OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP)); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } else { \ OUT_BATCH(CP_PACKET2); \ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index c3c2b973b59..7f7ae2ba792 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -223,6 +223,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) GLuint count = VB->Count; GLuint i, emitsize; + fprintf(stderr,"emit arrays\n"); for ( i = 0; i < 15; i++ ) { GLubyte attrib = vimap_rev[i]; if (attrib != 255) { @@ -257,14 +258,14 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) if (!rmesa->tcl.vertex_data[i].buf) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[i]), + &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, 1, VB->AttribPtr[attrib]->stride, count); else r200_emit_vecfog( ctx, - &(rmesa->tcl.aos[i]), + &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, VB->AttribPtr[attrib]->stride, count); @@ -313,7 +314,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } if (!rmesa->tcl.vertex_data[i].buf) { rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[i]), + &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, emitsize, VB->AttribPtr[attrib]->stride, @@ -321,6 +322,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } after_emit: assert(nr < 12); + nr++; // component[nr++] = &rmesa->tcl.vertex_data[i]; } } @@ -339,12 +341,10 @@ after_emit: void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); - - /* only do it for changed inputs ? */ int i; - for (i = 0; i < 15; i++) { - // if (newinputs & (1 << i)) - // r200ReleaseDmaRegion( rmesa, - // &rmesa->tcl.vertex_data[i], __FUNCTION__ ); + for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { + if (rmesa->tcl.aos[i].bo) { + rmesa->tcl.aos[i].bo = radeon_bo_unref(rmesa->tcl.aos[i].bo); + } } } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f46b01b56a6..3b56fec78ac 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -43,6 +43,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "radeon_buffer.h" +#include "radeon_cs.h" +#include "common_context.h" +#include "common_cmdbuf.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -288,32 +292,66 @@ VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 ) -#if 0 -static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; + uint32_t zbpitch; + uint32_t dwords = atom->cmd_size; GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; - + + /* output the first 7 bytes of context */ + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, 5); + + rrb = r200->radeon.state.depth.rrb; + if (!rrb) { + OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]); + OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]); + } else { + zbpitch = (rrb->pitch / rrb->cpp); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH(zbpitch); + } + + OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); + OUT_BATCH(atom->cmd[CTX_CMD_1]); + OUT_BATCH(atom->cmd[CTX_PP_CNTL]); + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + rrb = r200->radeon.state.color.rrb; if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; } if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); - return; + OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); + } else { + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); } - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->cpp == 4) - ; - else - ; + OUT_BATCH(atom->cmd[CTX_CMD_2]); + + if (!rrb || !rrb->bo) { + OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); + } else { + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + ; + else + ; + if (r200->radeon.sarea->tiling_enabled) + cbpitch |= R200_COLOR_TILE_ENABLE; + OUT_BATCH(cbpitch); + } + + if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) + OUT_BATCH_TABLE((atom->cmd + 14), 4); + + END_BATCH(); } -#endif static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) { @@ -410,7 +448,7 @@ void r200InitState( r200ContextPtr rmesa ) else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); - // rmesa->hw.ctx.emit = ctx_emit; + rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 4a31578c891..226bf1620c4 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,6 +142,7 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { + fprintf(stderr,"alloc elts\n"); if (rmesa->dma.flush == r200FlushElts && rmesa->store.cmd_used + nr*2 < R200_CMD_BUF_SZ) { @@ -187,6 +188,7 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); + fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + VBUF_BUFSZ ); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 02c4b1cb408..eb500379118 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -68,7 +68,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static void r300ClearBuffer(r300ContextPtr r300, int flags, struct radeon_renderbuffer *rrb, - struct radeon_renderbuffer *rrbd) + struct radeon_renderbuffer *rrbd) { BATCH_LOCALS(&r300->radeon); GLcontext *ctx = r300->radeon.glCtx; @@ -592,7 +592,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); - rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index d98b83c506b..b1048f3b0c2 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2362,7 +2362,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; rrb = r300->radeon.state.depth.rrb; - if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { + if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { /* XXX: Turn off when clearing buffers ? */ r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; diff --git a/src/mesa/drivers/dri/radeon/common_lock.c b/src/mesa/drivers/dri/radeon/common_lock.c index 09517450a9b..91600ac4cda 100644 --- a/src/mesa/drivers/dri/radeon/common_lock.c +++ b/src/mesa/drivers/dri/radeon/common_lock.c @@ -55,7 +55,6 @@ char *prevLockFile = NULL; int prevLockLine = 0; #endif -#ifdef RADEON_COMMON_FOR_R300 /* Turn on/off page flipping according to the flags in the sarea: */ void radeonUpdatePageFlipping(radeonContextPtr rmesa) @@ -81,18 +80,6 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; } -#else -/* Turn on/off page flipping according to the flags in the sarea: - */ -void radeonUpdatePageFlipping(radeonContextPtr rmesa) -{ - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); - } -} -#endif /* Update the hardware state. This is called if another context has * grabbed the hardware lock, which includes the X server. This diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 51cbe590244..d7c16c4957a 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1337,3 +1337,16 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, } radeon_bo_unmap(aos->bo); } + + +void radeon_print_state_atom( struct radeon_state_atom *state ) +{ + int i; + + fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); + + if (RADEON_DEBUG & DEBUG_VERBOSE) + for (i = 0 ; i < state->cmd_size ; i++) + fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); + +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 32cbae7ad3f..e4f200d6a53 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -32,4 +32,5 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, GLvoid * data, int size, int stride, int count); +void radeon_print_state_atom( struct radeon_state_atom *state ); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 0c897815a7b..af9ee4df472 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -206,8 +206,8 @@ static int cs_end(struct radeon_cs *cs, } cs->section = 0; if (cs->section_ndw != cs->section_cdw) { - fprintf(stderr, "CS section size missmatch start at (%s,%s,%d)\n", - cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", + cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); fprintf(stderr, "CS section end at (%s,%s,%d)\n", file, func, line); return -EPIPE; @@ -221,10 +221,6 @@ static int cs_process_relocs(struct radeon_cs *cs) struct cs_reloc_legacy *relocs; int i, j, r; - if (!IS_R300_CLASS(csm->ctx->radeonScreen)) { - /* FIXME: r300 only right now */ - return -EINVAL; - } csm = (struct cs_manager_legacy*)cs->csm; relocs = (struct cs_reloc_legacy *)cs->relocs; for (i = 0; i < cs->crelocs; i++) { @@ -238,6 +234,8 @@ static int cs_process_relocs(struct radeon_cs *cs) relocs[i].base.bo, soffset, eoffset); return r; } + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); cs->packets[relocs[i].indices[j]] += soffset; if (cs->packets[relocs[i].indices[j]] >= eoffset) { radeon_bo_debug(relocs[i].base.bo, 12); @@ -269,6 +267,14 @@ static int cs_set_age(struct radeon_cs *cs) return 0; } +static void dump_cmdbuf(struct radeon_cs *cs) +{ + int i; + for (i = 0; i < cs->cdw; i++){ + fprintf(stderr,"%x: %08x\n", i, cs->packets[i]); + } + +} static int cs_emit(struct radeon_cs *cs) { struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm; @@ -279,19 +285,22 @@ static int cs_emit(struct radeon_cs *cs) csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); + /* append buffer age */ - age.scratch.cmd_type = R300_CMD_SCRATCH; - /* Scratch register 2 corresponds to what radeonGetAge polls */ - csm->pending_age = 0; - csm->pending_count = 1; - ull = (uint64_t) (intptr_t) &csm->pending_age; - age.scratch.reg = 2; - age.scratch.n_bufs = 1; - age.scratch.flags = 0; - radeon_cs_write_dword(cs, age.u); - radeon_cs_write_dword(cs, ull & 0xffffffff); - radeon_cs_write_dword(cs, ull >> 32); - radeon_cs_write_dword(cs, 0); + if (IS_R300_CLASS(csm->ctx->radeonScreen)) { + age.scratch.cmd_type = R300_CMD_SCRATCH; + /* Scratch register 2 corresponds to what radeonGetAge polls */ + csm->pending_age = 0; + csm->pending_count = 1; + ull = (uint64_t) (intptr_t) &csm->pending_age; + age.scratch.reg = 2; + age.scratch.n_bufs = 1; + age.scratch.flags = 0; + radeon_cs_write_dword(cs, age.u); + radeon_cs_write_dword(cs, ull & 0xffffffff); + radeon_cs_write_dword(cs, ull >> 32); + radeon_cs_write_dword(cs, 0); + } r = cs_process_relocs(cs); if (r) { @@ -308,6 +317,8 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } + dump_cmdbuf(cs); + r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { return r; -- cgit v1.2.3 From 33dc14c707734df37fb02b7bcc278ddeb94036f1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 21 Jan 2009 02:10:32 +1000 Subject: radeon/r200/r300: start to move to common miptree/texobj --- src/mesa/drivers/dri/r200/Makefile | 5 +- src/mesa/drivers/dri/r300/Makefile | 7 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 4 +- src/mesa/drivers/dri/r300/r300_context.c | 1 - src/mesa/drivers/dri/r300/r300_context.h | 42 +-- src/mesa/drivers/dri/r300/r300_mipmap_tree.c | 319 ----------------------- src/mesa/drivers/dri/r300/r300_mipmap_tree.h | 97 ------- src/mesa/drivers/dri/r300/r300_state.c | 18 +- src/mesa/drivers/dri/r300/r300_tex.c | 68 ++--- src/mesa/drivers/dri/r300/r300_texstate.c | 100 +++---- src/mesa/drivers/dri/radeon/common_context.h | 30 ++- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 319 +++++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h | 97 +++++++ 13 files changed, 547 insertions(+), 560 deletions(-) delete mode 100644 src/mesa/drivers/dri/r300/r300_mipmap_tree.c delete mode 100644 src/mesa/drivers/dri/r300/r300_mipmap_tree.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 6b90018a288..5f1cfc889ee 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -32,6 +32,7 @@ DRIVER_SOURCES = r200_context.c \ common_misc.c \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ + radeon_mipmap_tree.c \ $(EGL_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -62,7 +63,9 @@ COMMON_SYMLINKS = \ common_lock.h \ common_misc.h \ common_misc.c \ - common_cmdbuf.h + common_cmdbuf.h \ + radeon_mipmap_tree.c \ + radeon_mipmap_tree.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 942d76fcc88..ce425e1d61a 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -35,10 +35,8 @@ DRIVER_SOURCES = \ r300_cmdbuf.c \ r300_state.c \ r300_render.c \ - r300_texmem.c \ r300_tex.c \ r300_texstate.c \ - r300_mipmap_tree.c \ radeon_program.c \ radeon_program_alu.c \ radeon_program_pair.c \ @@ -52,6 +50,7 @@ DRIVER_SOURCES = \ r300_shader.c \ r300_emit.c \ r300_swtcl.c \ + radeon_mipmap_tree.c \ $(EGL_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -84,7 +83,9 @@ COMMON_SYMLINKS = \ common_lock.h \ common_misc.c \ common_misc.h \ - common_cmdbuf.h + common_cmdbuf.h \ + radeon_mipmap_tree.c \ + radeon_mipmap_tree.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 30314d454ff..04bb76bb301 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -52,7 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_reg.h" #include "r300_cmdbuf.h" #include "r300_emit.h" -#include "r300_mipmap_tree.h" +#include "radeon_mipmap_tree.h" #include "r300_state.h" #include "radeon_cs_legacy.h" #include "radeon_cs_gem.h" @@ -271,7 +271,7 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) for(i = 0; i < numtmus; ++i) { BEGIN_BATCH(2); OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - r300TexObj *t = r300->hw.textures[i]; + radeonTexObj *t = r300->hw.textures[i]; if (t && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 798f1f58c9e..e84d0acd6d8 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -59,7 +59,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_span.h" #include "r300_context.h" #include "r300_cmdbuf.h" -#include "r300_mipmap_tree.h" #include "r300_state.h" #include "r300_ioctl.h" #include "r300_tex.h" diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 477756774d6..1c228b42efb 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -81,7 +81,6 @@ typedef struct r300_context *r300ContextPtr; /* Texture related */ -typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr; typedef struct _r300_texture_image r300_texture_image; @@ -96,8 +95,8 @@ struct _r300_texture_image { * If mt == 0, the image is stored in normal memory pointed to * by base.Data. */ - struct _r300_mipmap_tree *mt; - struct radeon_bo *bo; + struct _radeon_mipmap_tree *mt; + struct radeon_bo *bo; int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ @@ -108,41 +107,6 @@ static INLINE r300_texture_image *get_r300_texture_image(struct gl_texture_image return (r300_texture_image*)image; } - -/* Texture object in locally shared texture space. - */ -struct r300_tex_obj { - struct gl_texture_object base; - struct _r300_mipmap_tree *mt; - - /** - * This is true if we've verified that the mipmap tree above is complete - * and so on. - */ - GLboolean validated; - - GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ - GLuint override_offset; - - /* hardware register values */ - /* Note that R200 has 8 registers per texture and R300 only 7 */ - GLuint filter; - GLuint filter_1; - GLuint pitch_reg; - GLuint size; /* npot only */ - GLuint format; - GLuint pp_border_color; - /* end hardware registers */ - - GLuint tile_bits; /* hw texture tile bits used on this texture */ - struct radeon_bo *bo; -}; - -static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj) -{ - return (r300TexObj*)texObj; -} - /* The blit width for texture uploads */ #define R300_BLIT_WIDTH_BYTES 1024 @@ -459,7 +423,7 @@ struct r300_hw_state { } tex; struct radeon_state_atom txe; /* tex enable (4104) */ - r300TexObj *textures[R300_MAX_TEXTURE_UNITS]; + radeonTexObj *textures[R300_MAX_TEXTURE_UNITS]; }; /** diff --git a/src/mesa/drivers/dri/r300/r300_mipmap_tree.c b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c deleted file mode 100644 index 097f9cdfece..00000000000 --- a/src/mesa/drivers/dri/r300/r300_mipmap_tree.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright (C) 2008 Nicolai Haehnle. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "r300_mipmap_tree.h" - -#include -#include - -#include "main/simple_list.h" -#include "main/texcompress.h" -#include "main/texformat.h" - -#include "radeon_buffer.h" - -static GLuint r300_compressed_texture_size(GLcontext *ctx, - GLsizei width, GLsizei height, GLsizei depth, - GLuint mesaFormat) -{ - GLuint size = _mesa_compressed_texture_size(ctx, width, height, depth, mesaFormat); - - if (mesaFormat == MESA_FORMAT_RGB_DXT1 || - mesaFormat == MESA_FORMAT_RGBA_DXT1) { - if (width + 3 < 8) /* width one block */ - size = size * 4; - else if (width + 3 < 16) - size = size * 2; - } else { - /* DXT3/5, 16 bytes per block */ - WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n"); - if (width + 3 < 8) - size = size * 2; - } - - return size; -} - -/** - * Compute sizes and fill in offset and blit information for the given - * image (determined by \p face and \p level). - * - * \param curOffset points to the offset at which the image is to be stored - * and is updated by this function according to the size of the image. - */ -static void compute_tex_image_offset(r300_mipmap_tree *mt, - GLuint face, GLuint level, GLuint* curOffset) -{ - r300_mipmap_level *lvl = &mt->levels[level]; - - /* Find image size in bytes */ - if (mt->compressed) { - /* TODO: Is this correct? Need test cases for compressed textures! */ - GLuint align; - - if (mt->target == GL_TEXTURE_RECTANGLE_NV) - align = 64 / mt->bpp; - else - align = 32 / mt->bpp; - lvl->rowstride = (lvl->width + align - 1) & ~(align - 1); - lvl->size = r300_compressed_texture_size(mt->r300->radeon.glCtx, - lvl->width, lvl->height, lvl->depth, mt->compressed); - } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { - lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; - lvl->size = lvl->rowstride * lvl->height; - } else if (mt->tilebits & R300_TXO_MICRO_TILE) { - /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, - * though the actual offset may be different (if texture is less than - * 32 bytes width) to the untiled case */ - lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; - lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; - } else { - lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; - lvl->size = lvl->rowstride * lvl->height * lvl->depth; - } - assert(lvl->size > 0); - - /* All images are aligned to a 32-byte offset */ - *curOffset = (*curOffset + 0x1f) & ~0x1f; - lvl->faces[face].offset = *curOffset; - *curOffset += lvl->size; -} - -static GLuint minify(GLuint size, GLuint levels) -{ - size = size >> levels; - if (size < 1) - size = 1; - return size; -} - -static void calculate_miptree_layout(r300_mipmap_tree *mt) -{ - GLuint curOffset; - GLuint numLevels; - GLuint i; - - numLevels = mt->lastLevel - mt->firstLevel + 1; - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); - - curOffset = 0; - for(i = 0; i < numLevels; i++) { - GLuint face; - - mt->levels[i].width = minify(mt->width0, i); - mt->levels[i].height = minify(mt->height0, i); - mt->levels[i].depth = minify(mt->depth0, i); - - for(face = 0; face < mt->faces; face++) - compute_tex_image_offset(mt, face, i, &curOffset); - } - - /* Note the required size in memory */ - mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; -} - - -/** - * Create a new mipmap tree, calculate its layout and allocate memory. - */ -r300_mipmap_tree* r300_miptree_create(r300ContextPtr rmesa, r300TexObj *t, - GLenum target, GLuint firstLevel, GLuint lastLevel, - GLuint width0, GLuint height0, GLuint depth0, - GLuint bpp, GLuint tilebits, GLuint compressed) -{ - r300_mipmap_tree *mt = CALLOC_STRUCT(_r300_mipmap_tree); - - mt->r300 = rmesa; - mt->refcount = 1; - mt->t = t; - mt->target = target; - mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; - mt->firstLevel = firstLevel; - mt->lastLevel = lastLevel; - mt->width0 = width0; - mt->height0 = height0; - mt->depth0 = depth0; - mt->bpp = bpp; - mt->tilebits = tilebits; - mt->compressed = compressed; - - calculate_miptree_layout(mt); - - mt->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, mt->totalsize, 1024, - RADEON_GEM_DOMAIN_VRAM, - 0); - - return mt; -} - -void r300_miptree_reference(r300_mipmap_tree *mt) -{ - mt->refcount++; - assert(mt->refcount > 0); -} - -void r300_miptree_unreference(r300_mipmap_tree *mt) -{ - if (!mt) - return; - - assert(mt->refcount > 0); - mt->refcount--; - if (!mt->refcount) { - radeon_bo_unref(mt->bo); - free(mt); - } -} - - -static void calculate_first_last_level(struct gl_texture_object *tObj, - GLuint *pfirstLevel, GLuint *plastLevel) -{ - const struct gl_texture_image * const baseImage = - tObj->Image[0][tObj->BaseLevel]; - - /* These must be signed values. MinLod and MaxLod can be negative numbers, - * and having firstLevel and lastLevel as signed prevents the need for - * extra sign checks. - */ - int firstLevel; - int lastLevel; - - /* Yes, this looks overly complicated, but it's all needed. - */ - switch (tObj->Target) { - case GL_TEXTURE_1D: - case GL_TEXTURE_2D: - case GL_TEXTURE_3D: - case GL_TEXTURE_CUBE_MAP: - if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) { - /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL. - */ - firstLevel = lastLevel = tObj->BaseLevel; - } else { - firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5); - firstLevel = MAX2(firstLevel, tObj->BaseLevel); - firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); - lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); - lastLevel = MAX2(lastLevel, tObj->BaseLevel); - lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); - lastLevel = MIN2(lastLevel, tObj->MaxLevel); - lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ - } - break; - case GL_TEXTURE_RECTANGLE_NV: - case GL_TEXTURE_4D_SGIS: - firstLevel = lastLevel = 0; - break; - default: - return; - } - - /* save these values */ - *pfirstLevel = firstLevel; - *plastLevel = lastLevel; -} - - -/** - * Checks whether the given miptree can hold the given texture image at the - * given face and level. - */ -GLboolean r300_miptree_matches_image(r300_mipmap_tree *mt, - struct gl_texture_image *texImage, GLuint face, GLuint level) -{ - r300_mipmap_level *lvl; - - if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel) - return GL_FALSE; - - if (texImage->TexFormat->TexelBytes != mt->bpp) - return GL_FALSE; - - lvl = &mt->levels[level - mt->firstLevel]; - if (lvl->width != texImage->Width || - lvl->height != texImage->Height || - lvl->depth != texImage->Depth) - return GL_FALSE; - - return GL_TRUE; -} - - -/** - * Checks whether the given miptree has the right format to store the given texture object. - */ -GLboolean r300_miptree_matches_texture(r300_mipmap_tree *mt, struct gl_texture_object *texObj) -{ - struct gl_texture_image *firstImage; - GLuint compressed; - GLuint numfaces = 1; - GLuint firstLevel, lastLevel; - - calculate_first_last_level(texObj, &firstLevel, &lastLevel); - if (texObj->Target == GL_TEXTURE_CUBE_MAP) - numfaces = 6; - - firstImage = texObj->Image[0][firstLevel]; - compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0; - - return (mt->firstLevel == firstLevel && - mt->lastLevel == lastLevel && - mt->width0 == firstImage->Width && - mt->height0 == firstImage->Height && - mt->depth0 == firstImage->Depth && - mt->bpp == firstImage->TexFormat->TexelBytes && - mt->compressed == compressed); -} - - -/** - * Try to allocate a mipmap tree for the given texture that will fit the - * given image in the given position. - */ -void r300_try_alloc_miptree(r300ContextPtr rmesa, r300TexObj *t, - struct gl_texture_image *texImage, GLuint face, GLuint level) -{ - GLuint compressed = texImage->IsCompressed ? texImage->TexFormat->MesaFormat : 0; - GLuint numfaces = 1; - GLuint firstLevel, lastLevel; - - assert(!t->mt); - - calculate_first_last_level(&t->base, &firstLevel, &lastLevel); - if (t->base.Target == GL_TEXTURE_CUBE_MAP) - numfaces = 6; - - if (level != firstLevel || face >= numfaces) - return; - - t->mt = r300_miptree_create(rmesa, t, t->base.Target, - firstLevel, lastLevel, - texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->TexelBytes, t->tile_bits, compressed); -} diff --git a/src/mesa/drivers/dri/r300/r300_mipmap_tree.h b/src/mesa/drivers/dri/r300/r300_mipmap_tree.h deleted file mode 100644 index aeb52dc1353..00000000000 --- a/src/mesa/drivers/dri/r300/r300_mipmap_tree.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2008 Nicolai Haehnle. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __R300_MIPMAP_TREE_H_ -#define __R300_MIPMAP_TREE_H_ - -#include "r300_context.h" - -typedef struct _r300_mipmap_tree r300_mipmap_tree; -typedef struct _r300_mipmap_level r300_mipmap_level; -typedef struct _r300_mipmap_image r300_mipmap_image; - -struct _r300_mipmap_image { - GLuint offset; /** Offset of this image from the start of mipmap tree buffer, in bytes */ -}; - -struct _r300_mipmap_level { - GLuint width; - GLuint height; - GLuint depth; - GLuint size; /** Size of each image, in bytes */ - GLuint rowstride; /** in bytes */ - r300_mipmap_image faces[6]; -}; - - -/** - * A mipmap tree contains texture images in the layout that the hardware - * expects. - * - * The meta-data of mipmap trees is immutable, i.e. you cannot change the - * layout on-the-fly; however, the texture contents (i.e. texels) can be - * changed. - */ -struct _r300_mipmap_tree { - r300ContextPtr r300; - r300TexObj *t; - struct radeon_bo *bo; - GLuint refcount; - - GLuint totalsize; /** total size of the miptree, in bytes */ - - GLenum target; /** GL_TEXTURE_xxx */ - GLuint faces; /** # of faces: 6 for cubemaps, 1 otherwise */ - GLuint firstLevel; /** First mip level stored in this mipmap tree */ - GLuint lastLevel; /** Last mip level stored in this mipmap tree */ - - GLuint width0; /** Width of firstLevel image */ - GLuint height0; /** Height of firstLevel image */ - GLuint depth0; /** Depth of firstLevel image */ - - GLuint bpp; /** Bytes per texel */ - GLuint tilebits; /** R300_TXO_xxx_TILE */ - GLuint compressed; /** MESA_FORMAT_xxx indicating a compressed format, or 0 if uncompressed */ - - r300_mipmap_level levels[RADEON_MAX_TEXTURE_LEVELS]; -}; - -r300_mipmap_tree* r300_miptree_create(r300ContextPtr rmesa, r300TexObj *t, - GLenum target, GLuint firstLevel, GLuint lastLevel, - GLuint width0, GLuint height0, GLuint depth0, - GLuint bpp, GLuint tilebits, GLuint compressed); -void r300_miptree_reference(r300_mipmap_tree *mt); -void r300_miptree_unreference(r300_mipmap_tree *mt); - -GLboolean r300_miptree_matches_image(r300_mipmap_tree *mt, - struct gl_texture_image *texImage, GLuint face, GLuint level); -GLboolean r300_miptree_matches_texture(r300_mipmap_tree *mt, struct gl_texture_object *texObj); -void r300_try_alloc_miptree(r300ContextPtr rmesa, r300TexObj *t, - struct gl_texture_image *texImage, GLuint face, GLuint level); - - -#endif /* __R300_MIPMAP_TREE_H_ */ diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index b1048f3b0c2..ea5d65542b2 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1444,7 +1444,7 @@ static GLuint translate_lod_bias(GLfloat bias) static void r300SetupTextures(GLcontext * ctx) { int i, mtu; - struct r300_tex_obj *t; + struct radeon_tex_obj *t; r300ContextPtr r300 = R300_CONTEXT(ctx); int hw_tmu = 0; int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */ @@ -1480,14 +1480,14 @@ static void r300SetupTextures(GLcontext * ctx) if (ctx->Texture.Unit[i]._ReallyEnabled) { tmu_mappings[i] = hw_tmu; - t = r300_tex_obj(ctx->Texture.Unit[i]._Current); + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); if (!t) continue; - if ((t->format & 0xffffff00) == 0xffffff00) { + if ((t->pp_txformat & 0xffffff00) == 0xffffff00) { WARN_ONCE ("unknown texture format (entry %x) encountered. Help me !\n", - t->format & 0xff); + t->pp_txformat & 0xff); } if (RADEON_DEBUG & DEBUG_STATE) @@ -1498,21 +1498,21 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + hw_tmu] = - gen_fixed_filter(t->filter) | (hw_tmu << 28); + gen_fixed_filter(t->pp_txfilter) | (hw_tmu << 28); /* Note: There is a LOD bias per texture unit and a LOD bias * per texture object. We add them here to get the correct behaviour. * (The per-texture object LOD bias was introduced in OpenGL 1.4 * and is not present in the EXT_texture_object extension). */ r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = - t->filter_1 | + t->pp_txfilter_1 | translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.LodBias); r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] = - t->size; + t->pp_txsize; r300->hw.tex.format.cmd[R300_TEX_VALUE_0 + - hw_tmu] = t->format; + hw_tmu] = t->pp_txformat; r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] = - t->pitch_reg; + t->pp_txpitch; r300->hw.textures[hw_tmu] = t; if (t->tile_bits & R300_TXO_MACRO_TILE) { diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 9ceac70f5e3..e3b871c991d 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -50,7 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "r300_state.h" #include "r300_ioctl.h" -#include "r300_mipmap_tree.h" +#include "radeon_mipmap_tree.h" #include "r300_tex.h" #include "xmlpool.h" @@ -79,20 +79,20 @@ static unsigned int translate_wrap_mode(GLenum wrapmode) * * \param t Texture object whose wrap modes are to be set */ -static void r300UpdateTexWrap(r300TexObjPtr t) +static void r300UpdateTexWrap(radeonTexObjPtr t) { struct gl_texture_object *tObj = &t->base; - t->filter &= + t->pp_txfilter &= ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK); - t->filter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT; + t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT; if (tObj->Target != GL_TEXTURE_1D) { - t->filter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT; + t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT; if (tObj->Target == GL_TEXTURE_3D) - t->filter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT; + t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT; } } @@ -119,13 +119,13 @@ static GLuint aniso_filter(GLfloat anisotropy) * \param magf Texture magnification mode * \param anisotropy Maximum anisotropy level */ -static void r300SetTexFilter(r300TexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) +static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) { /* Force revalidation to account for switches from/to mipmapping. */ t->validated = GL_FALSE; - t->filter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK); - t->filter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY; + t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK); + t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY; /* Note that EXT_texture_filter_anisotropic is extremely vague about * how anisotropic filtering interacts with the "normal" filter modes. @@ -133,7 +133,7 @@ static void r300SetTexFilter(r300TexObjPtr t, GLenum minf, GLenum magf, GLfloat * filter settings completely. This includes driconf's settings. */ if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) { - t->filter |= R300_TX_MAG_FILTER_ANISO + t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO | R300_TX_MIN_FILTER_ANISO | R300_TX_MIN_FILTER_MIP_LINEAR | aniso_filter(anisotropy); @@ -144,22 +144,22 @@ static void r300SetTexFilter(r300TexObjPtr t, GLenum minf, GLenum magf, GLfloat switch (minf) { case GL_NEAREST: - t->filter |= R300_TX_MIN_FILTER_NEAREST; + t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST; break; case GL_LINEAR: - t->filter |= R300_TX_MIN_FILTER_LINEAR; + t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR; break; case GL_NEAREST_MIPMAP_NEAREST: - t->filter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST; + t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST; break; case GL_NEAREST_MIPMAP_LINEAR: - t->filter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR; + t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR; break; case GL_LINEAR_MIPMAP_NEAREST: - t->filter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST; + t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST; break; case GL_LINEAR_MIPMAP_LINEAR: - t->filter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR; + t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR; break; } @@ -168,15 +168,15 @@ static void r300SetTexFilter(r300TexObjPtr t, GLenum minf, GLenum magf, GLfloat */ switch (magf) { case GL_NEAREST: - t->filter |= R300_TX_MAG_FILTER_NEAREST; + t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST; break; case GL_LINEAR: - t->filter |= R300_TX_MAG_FILTER_LINEAR; + t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR; break; } } -static void r300SetTexBorderColor(r300TexObjPtr t, GLubyte c[4]) +static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4]) { t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); } @@ -423,7 +423,7 @@ static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage r300_texture_image* image = get_r300_texture_image(timage); if (image->mt) { - r300_miptree_unreference(image->mt); + radeon_miptree_unreference(image->mt); image->mt = 0; assert(!image->base.Data); } else { @@ -439,7 +439,7 @@ static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage /* Set Data pointer and additional data for mapped texture image */ static void teximage_set_map_data(r300_texture_image *image) { - r300_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; image->base.RowStride = lvl->rowstride / image->mt->bpp; } @@ -474,7 +474,7 @@ static void r300_teximage_unmap(r300_texture_image *image) */ static void r300MapTexture(GLcontext *ctx, struct gl_texture_object *texObj) { - r300TexObj* t = r300_tex_obj(texObj); + radeonTexObj* t = radeon_tex_obj(texObj); int face, level; assert(texObj->_Complete); @@ -489,7 +489,7 @@ static void r300MapTexture(GLcontext *ctx, struct gl_texture_object *texObj) static void r300UnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) { - r300TexObj* t = r300_tex_obj(texObj); + radeonTexObj* t = radeon_tex_obj(texObj); int face, level; assert(texObj->_Complete); @@ -518,7 +518,7 @@ static void r300_teximage( int compressed) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300TexObj* t = r300_tex_obj(texObj); + radeonTexObj* t = radeon_tex_obj(texObj); r300_texture_image* image = get_r300_texture_image(texImage); R300_FIREVERTICES(rmesa); @@ -544,12 +544,12 @@ static void r300_teximage( r300FreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ if (!t->mt) - r300_try_alloc_miptree(rmesa, t, texImage, face, level); - if (t->mt && r300_miptree_matches_image(t->mt, texImage, face, level)) { + radeon_try_alloc_miptree(&rmesa->radeon, t, texImage, face, level); + if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { image->mt = t->mt; image->mtlevel = level - t->mt->firstLevel; image->mtface = face; - r300_miptree_reference(t->mt); + radeon_miptree_reference(t->mt); } else { int size; if (texImage->IsCompressed) { @@ -578,7 +578,7 @@ static void r300_teximage( } else { GLuint dstRowStride; if (image->mt) { - r300_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; @@ -700,7 +700,7 @@ static void r300_texsubimage(GLcontext* ctx, int dims, int level, r300_teximage_map(image, GL_TRUE); if (image->mt) { - r300_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; @@ -806,7 +806,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, struct gl_texture_object *texObj, GLenum pname, const GLfloat * params) { - r300TexObj* t = r300_tex_obj(texObj); + radeonTexObj* t = radeon_tex_obj(texObj); if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { fprintf(stderr, "%s( %s )\n", __FUNCTION__, @@ -840,7 +840,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, * to simulate a clamped LOD. */ if (t->mt) { - r300_miptree_unreference(t->mt); + radeon_miptree_unreference(t->mt); t->mt = 0; t->validated = GL_FALSE; } @@ -869,7 +869,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300TexObj* t = r300_tex_obj(texObj); + radeonTexObj* t = radeon_tex_obj(texObj); if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, @@ -887,7 +887,7 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) } if (t->mt) { - r300_miptree_unreference(t->mt); + radeon_miptree_unreference(t->mt); t->mt = 0; } _mesa_delete_texture_object(ctx, texObj); @@ -905,7 +905,7 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, GLenum target) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300TexObj* t = CALLOC_STRUCT(r300_tex_obj); + radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index ed75bdd2c96..11c53d02700 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -48,7 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_ioctl.h" #include "radeon_ioctl.h" -#include "r300_mipmap_tree.h" +#include "radeon_mipmap_tree.h" #include "r300_tex.h" #include "r300_reg.h" #include "radeon_buffer.h" @@ -145,12 +145,12 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) }, }; const GLuint *format; - r300TexObjPtr t; + radeonTexObjPtr t; if (!tObj) return; - t = r300_tex_obj(tObj); + t = radeon_tex_obj(tObj); switch (tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat) { case MESA_FORMAT_Z16: @@ -172,13 +172,13 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) switch (tObj->DepthMode) { case GL_LUMINANCE: - t->format = format[0]; + t->pp_txformat = format[0]; break; case GL_INTENSITY: - t->format = format[1]; + t->pp_txformat = format[1]; break; case GL_ALPHA: - t->format = format[2]; + t->pp_txformat = format[2]; break; default: /* Error...which should have already been caught by higher @@ -196,7 +196,7 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) * \param rmesa Context pointer * \param t the r300 texture object */ -static void setup_hardware_state(r300ContextPtr rmesa, r300TexObj *t) +static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) { const struct gl_texture_image *firstImage = t->base.Image[0][t->mt->firstLevel]; @@ -206,10 +206,10 @@ static void setup_hardware_state(r300ContextPtr rmesa, r300TexObj *t) if (firstImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) { r300SetDepthTexMode(&t->base); } else { - t->format = tx_table[firstImage->TexFormat->MesaFormat].format; + t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format; } - t->filter |= tx_table[firstImage->TexFormat->MesaFormat].filter; + t->pp_txfilter |= tx_table[firstImage->TexFormat->MesaFormat].filter; } else if (!t->image_override) { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); @@ -219,26 +219,26 @@ static void setup_hardware_state(r300ContextPtr rmesa, r300TexObj *t) t->tile_bits = 0; if (t->base.Target == GL_TEXTURE_CUBE_MAP) - t->format |= R300_TX_FORMAT_CUBIC_MAP; + t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP; if (t->base.Target == GL_TEXTURE_3D) - t->format |= R300_TX_FORMAT_3D; + t->pp_txformat |= R300_TX_FORMAT_3D; - t->size = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) + t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)) | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT); if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { unsigned int align = (64 / t->mt->bpp) - 1; - t->size |= R300_TX_SIZE_TXPITCH_EN; + t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; if (!t->image_override) - t->pitch_reg = ((firstImage->Width + align) & ~align) - 1; + t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1; } if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { if (firstImage->Width > 2048) - t->pitch_reg |= R500_TXWIDTH_BIT11; + t->pp_txpitch |= R500_TXWIDTH_BIT11; if (firstImage->Height > 2048) - t->pitch_reg |= R500_TXHEIGHT_BIT11; + t->pp_txpitch |= R500_TXHEIGHT_BIT11; } } @@ -265,9 +265,9 @@ static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcst /** * Ensure that the given image is stored in the given miptree from now on. */ -static void migrate_image_to_miptree(r300_mipmap_tree *mt, r300_texture_image *image, int face, int level) +static void migrate_image_to_miptree(radeon_mipmap_tree *mt, r300_texture_image *image, int face, int level) { - r300_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; + radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; unsigned char *dest; assert(image->mt != mt); @@ -283,7 +283,7 @@ static void migrate_image_to_miptree(r300_mipmap_tree *mt, r300_texture_image *i * In fact, that memcpy() could be done by the hardware in many * cases, provided that we have a proper memory manager. */ - r300_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; + radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; assert(srclvl->size == dstlvl->size); assert(srclvl->rowstride == dstlvl->rowstride); @@ -294,7 +294,7 @@ static void migrate_image_to_miptree(r300_mipmap_tree *mt, r300_texture_image *i dstlvl->size); radeon_bo_unmap(image->mt->bo); - r300_miptree_unreference(image->mt); + radeon_miptree_unreference(image->mt); } else { uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; @@ -313,7 +313,7 @@ static void migrate_image_to_miptree(r300_mipmap_tree *mt, r300_texture_image *i image->mt = mt; image->mtface = face; image->mtlevel = level; - r300_miptree_reference(image->mt); + radeon_miptree_reference(image->mt); } @@ -325,7 +325,7 @@ static void migrate_image_to_miptree(r300_mipmap_tree *mt, r300_texture_image *i static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300TexObj *t = r300_tex_obj(texObj); + radeonTexObj *t = radeon_tex_obj(texObj); r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[0][texObj->BaseLevel]); int face, level; @@ -350,19 +350,19 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object */ if (baseimage->mt && baseimage->mt != t->mt && - r300_miptree_matches_texture(baseimage->mt, &t->base)) { - r300_miptree_unreference(t->mt); + radeon_miptree_matches_texture(baseimage->mt, &t->base)) { + radeon_miptree_unreference(t->mt); t->mt = baseimage->mt; - r300_miptree_reference(t->mt); - } else if (t->mt && !r300_miptree_matches_texture(t->mt, &t->base)) { - r300_miptree_unreference(t->mt); + radeon_miptree_reference(t->mt); + } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) { + radeon_miptree_unreference(t->mt); t->mt = 0; } if (!t->mt) { if (RADEON_DEBUG & DEBUG_TEXTURE) fprintf(stderr, " Allocate new miptree\n"); - r300_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel); + radeon_try_alloc_miptree(&rmesa->radeon, t, &baseimage->base, 0, texObj->BaseLevel); if (!t->mt) { _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree"); return GL_FALSE; @@ -421,7 +421,7 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, r300ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); - r300TexObjPtr t = r300_tex_obj(tObj); + radeonTexObjPtr t = radeon_tex_obj(tObj); uint32_t pitch_val; if (!tObj) @@ -433,30 +433,30 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, return; t->bo = NULL; t->override_offset = offset; - t->pitch_reg &= (1 << 13) -1; + t->pp_txpitch &= (1 << 13) -1; pitch_val = pitch; switch (depth) { case 32: - t->format = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); - t->filter |= tx_table[2].filter; + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + t->pp_txfilter |= tx_table[2].filter; pitch_val /= 4; break; case 24: default: - t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - t->filter |= tx_table[4].filter; + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + t->pp_txfilter |= tx_table[4].filter; pitch_val /= 4; break; case 16: - t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); - t->filter |= tx_table[5].filter; + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); + t->pp_txfilter |= tx_table[5].filter; pitch_val /= 2; break; } pitch_val--; - t->pitch_reg |= pitch_val; + t->pp_txpitch |= pitch_val; } void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) @@ -469,7 +469,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeonContextPtr radeon; r300ContextPtr rmesa; GLframebuffer *fb; - r300TexObjPtr t; + radeonTexObjPtr t; uint32_t pitch_val; target = GL_TEXTURE_RECTANGLE_ARB; @@ -483,7 +483,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); rImage = get_r300_texture_image(texImage); - t = r300_tex_obj(texObj); + t = radeon_tex_obj(texObj); if (t == NULL) { return; } @@ -514,7 +514,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) t->mt = NULL; } if (rImage->mt) { - r300_miptree_unreference(rImage->mt); + radeon_miptree_unreference(rImage->mt); rImage->mt = NULL; } fprintf(stderr,"settexbuf %dx%d@%d\n", rb->width, rb->height, rb->cpp); @@ -527,31 +527,31 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) t->tile_bits = 0; t->image_override = GL_TRUE; t->override_offset = 0; - t->pitch_reg &= (1 << 13) -1; + t->pp_txpitch &= (1 << 13) -1; pitch_val = rb->pitch; switch (rb->cpp) { case 4: - t->format = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); - t->filter |= tx_table[2].filter; + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + t->pp_txfilter |= tx_table[2].filter; pitch_val /= 4; break; case 3: default: - t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - t->filter |= tx_table[4].filter; + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + t->pp_txfilter |= tx_table[4].filter; pitch_val /= 4; break; case 2: - t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); - t->filter |= tx_table[5].filter; + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); + t->pp_txfilter |= tx_table[5].filter; pitch_val /= 2; break; } pitch_val--; - t->size = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) | + t->pp_txsize = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) | ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT); - t->size |= R300_TX_SIZE_TXPITCH_EN; - t->pitch_reg |= pitch_val; + t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; + t->pp_txpitch |= pitch_val; t->validated = GL_TRUE; _mesa_unlock_texture(radeon->glCtx, texObj); return; diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 22fb908fb4b..462b072676a 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -112,11 +112,25 @@ struct radeon_state_atom { typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; +#define RADEON_TXO_MICRO_TILE (1 << 3) + /* Texture object in locally shared texture space. */ -#ifndef RADEON_COMMON_FOR_R300 struct radeon_tex_obj { - driTextureObject base; + // driTextureObject base; + struct gl_texture_object base; + struct _radeon_mipmap_tree *mt; + + /** + * This is true if we've verified that the mipmap tree above is complete + * and so on. + */ + GLboolean validated; + + GLuint override_offset; + GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + GLuint tile_bits; /* hw texture tile bits used on this texture */ + struct radeon_bo *bo; GLuint bufAddr; /* Offset to start of locally shared texture block */ @@ -131,7 +145,7 @@ struct radeon_tex_obj { drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; /* Six, for the cube faces */ - GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + GLuint pp_txfilter; /* hardware register values */ GLuint pp_txformat; @@ -143,11 +157,17 @@ struct radeon_tex_obj { GLuint pp_border_color; GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ + GLuint pp_txfilter_1; /* r300 */ + GLboolean border_fallback; - GLuint tile_bits; /* hw texture tile bits used on this texture */ + }; -#endif + +static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj) +{ + return (radeonTexObj*)texObj; +} /* Need refcounting on dma buffers: */ diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c new file mode 100644 index 00000000000..955d4b71ed5 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "radeon_mipmap_tree.h" + +#include +#include + +#include "main/simple_list.h" +#include "main/texcompress.h" +#include "main/texformat.h" + +#include "radeon_buffer.h" + +static GLuint radeon_compressed_texture_size(GLcontext *ctx, + GLsizei width, GLsizei height, GLsizei depth, + GLuint mesaFormat) +{ + GLuint size = _mesa_compressed_texture_size(ctx, width, height, depth, mesaFormat); + + if (mesaFormat == MESA_FORMAT_RGB_DXT1 || + mesaFormat == MESA_FORMAT_RGBA_DXT1) { + if (width + 3 < 8) /* width one block */ + size = size * 4; + else if (width + 3 < 16) + size = size * 2; + } else { + /* DXT3/5, 16 bytes per block */ + // WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n"); + if (width + 3 < 8) + size = size * 2; + } + + return size; +} + +/** + * Compute sizes and fill in offset and blit information for the given + * image (determined by \p face and \p level). + * + * \param curOffset points to the offset at which the image is to be stored + * and is updated by this function according to the size of the image. + */ +static void compute_tex_image_offset(radeon_mipmap_tree *mt, + GLuint face, GLuint level, GLuint* curOffset) +{ + radeon_mipmap_level *lvl = &mt->levels[level]; + + /* Find image size in bytes */ + if (mt->compressed) { + /* TODO: Is this correct? Need test cases for compressed textures! */ + GLuint align; + + if (mt->target == GL_TEXTURE_RECTANGLE_NV) + align = 64 / mt->bpp; + else + align = 32 / mt->bpp; + lvl->rowstride = (lvl->width + align - 1) & ~(align - 1); + lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, + lvl->width, lvl->height, lvl->depth, mt->compressed); + } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { + lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; + lvl->size = lvl->rowstride * lvl->height; + } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { + /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, + * though the actual offset may be different (if texture is less than + * 32 bytes width) to the untiled case */ + lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; + lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; + } else { + lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; + lvl->size = lvl->rowstride * lvl->height * lvl->depth; + } + assert(lvl->size > 0); + + /* All images are aligned to a 32-byte offset */ + *curOffset = (*curOffset + 0x1f) & ~0x1f; + lvl->faces[face].offset = *curOffset; + *curOffset += lvl->size; +} + +static GLuint minify(GLuint size, GLuint levels) +{ + size = size >> levels; + if (size < 1) + size = 1; + return size; +} + +static void calculate_miptree_layout(radeon_mipmap_tree *mt) +{ + GLuint curOffset; + GLuint numLevels; + GLuint i; + + numLevels = mt->lastLevel - mt->firstLevel + 1; + assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + + curOffset = 0; + for(i = 0; i < numLevels; i++) { + GLuint face; + + mt->levels[i].width = minify(mt->width0, i); + mt->levels[i].height = minify(mt->height0, i); + mt->levels[i].depth = minify(mt->depth0, i); + + for(face = 0; face < mt->faces; face++) + compute_tex_image_offset(mt, face, i, &curOffset); + } + + /* Note the required size in memory */ + mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; +} + + +/** + * Create a new mipmap tree, calculate its layout and allocate memory. + */ +radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *t, + GLenum target, GLuint firstLevel, GLuint lastLevel, + GLuint width0, GLuint height0, GLuint depth0, + GLuint bpp, GLuint tilebits, GLuint compressed) +{ + radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree); + + mt->radeon = rmesa; + mt->refcount = 1; + mt->t = t; + mt->target = target; + mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; + mt->firstLevel = firstLevel; + mt->lastLevel = lastLevel; + mt->width0 = width0; + mt->height0 = height0; + mt->depth0 = depth0; + mt->bpp = bpp; + mt->tilebits = tilebits; + mt->compressed = compressed; + + calculate_miptree_layout(mt); + + mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, + 0, mt->totalsize, 1024, + RADEON_GEM_DOMAIN_VRAM, + 0); + + return mt; +} + +void radeon_miptree_reference(radeon_mipmap_tree *mt) +{ + mt->refcount++; + assert(mt->refcount > 0); +} + +void radeon_miptree_unreference(radeon_mipmap_tree *mt) +{ + if (!mt) + return; + + assert(mt->refcount > 0); + mt->refcount--; + if (!mt->refcount) { + radeon_bo_unref(mt->bo); + free(mt); + } +} + + +static void calculate_first_last_level(struct gl_texture_object *tObj, + GLuint *pfirstLevel, GLuint *plastLevel) +{ + const struct gl_texture_image * const baseImage = + tObj->Image[0][tObj->BaseLevel]; + + /* These must be signed values. MinLod and MaxLod can be negative numbers, + * and having firstLevel and lastLevel as signed prevents the need for + * extra sign checks. + */ + int firstLevel; + int lastLevel; + + /* Yes, this looks overly complicated, but it's all needed. + */ + switch (tObj->Target) { + case GL_TEXTURE_1D: + case GL_TEXTURE_2D: + case GL_TEXTURE_3D: + case GL_TEXTURE_CUBE_MAP: + if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) { + /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL. + */ + firstLevel = lastLevel = tObj->BaseLevel; + } else { + firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5); + firstLevel = MAX2(firstLevel, tObj->BaseLevel); + firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); + lastLevel = MAX2(lastLevel, tObj->BaseLevel); + lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = MIN2(lastLevel, tObj->MaxLevel); + lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ + } + break; + case GL_TEXTURE_RECTANGLE_NV: + case GL_TEXTURE_4D_SGIS: + firstLevel = lastLevel = 0; + break; + default: + return; + } + + /* save these values */ + *pfirstLevel = firstLevel; + *plastLevel = lastLevel; +} + + +/** + * Checks whether the given miptree can hold the given texture image at the + * given face and level. + */ +GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, + struct gl_texture_image *texImage, GLuint face, GLuint level) +{ + radeon_mipmap_level *lvl; + + if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel) + return GL_FALSE; + + if (texImage->TexFormat->TexelBytes != mt->bpp) + return GL_FALSE; + + lvl = &mt->levels[level - mt->firstLevel]; + if (lvl->width != texImage->Width || + lvl->height != texImage->Height || + lvl->depth != texImage->Depth) + return GL_FALSE; + + return GL_TRUE; +} + + +/** + * Checks whether the given miptree has the right format to store the given texture object. + */ +GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj) +{ + struct gl_texture_image *firstImage; + GLuint compressed; + GLuint numfaces = 1; + GLuint firstLevel, lastLevel; + + calculate_first_last_level(texObj, &firstLevel, &lastLevel); + if (texObj->Target == GL_TEXTURE_CUBE_MAP) + numfaces = 6; + + firstImage = texObj->Image[0][firstLevel]; + compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0; + + return (mt->firstLevel == firstLevel && + mt->lastLevel == lastLevel && + mt->width0 == firstImage->Width && + mt->height0 == firstImage->Height && + mt->depth0 == firstImage->Depth && + mt->bpp == firstImage->TexFormat->TexelBytes && + mt->compressed == compressed); +} + + +/** + * Try to allocate a mipmap tree for the given texture that will fit the + * given image in the given position. + */ +void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, + struct gl_texture_image *texImage, GLuint face, GLuint level) +{ + GLuint compressed = texImage->IsCompressed ? texImage->TexFormat->MesaFormat : 0; + GLuint numfaces = 1; + GLuint firstLevel, lastLevel; + + assert(!t->mt); + + calculate_first_last_level(&t->base, &firstLevel, &lastLevel); + if (t->base.Target == GL_TEXTURE_CUBE_MAP) + numfaces = 6; + + if (level != firstLevel || face >= numfaces) + return; + + t->mt = radeon_miptree_create(rmesa, t, t->base.Target, + firstLevel, lastLevel, + texImage->Width, texImage->Height, texImage->Depth, + texImage->TexFormat->TexelBytes, t->tile_bits, compressed); +} diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h new file mode 100644 index 00000000000..875e5e5aee6 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RADEON_MIPMAP_TREE_H_ +#define __RADEON_MIPMAP_TREE_H_ + +#include "common_context.h" + +typedef struct _radeon_mipmap_tree radeon_mipmap_tree; +typedef struct _radeon_mipmap_level radeon_mipmap_level; +typedef struct _radeon_mipmap_image radeon_mipmap_image; + +struct _radeon_mipmap_image { + GLuint offset; /** Offset of this image from the start of mipmap tree buffer, in bytes */ +}; + +struct _radeon_mipmap_level { + GLuint width; + GLuint height; + GLuint depth; + GLuint size; /** Size of each image, in bytes */ + GLuint rowstride; /** in bytes */ + radeon_mipmap_image faces[6]; +}; + + +/** + * A mipmap tree contains texture images in the layout that the hardware + * expects. + * + * The meta-data of mipmap trees is immutable, i.e. you cannot change the + * layout on-the-fly; however, the texture contents (i.e. texels) can be + * changed. + */ +struct _radeon_mipmap_tree { + radeonContextPtr radeon; + radeonTexObj *t; + struct radeon_bo *bo; + GLuint refcount; + + GLuint totalsize; /** total size of the miptree, in bytes */ + + GLenum target; /** GL_TEXTURE_xxx */ + GLuint faces; /** # of faces: 6 for cubemaps, 1 otherwise */ + GLuint firstLevel; /** First mip level stored in this mipmap tree */ + GLuint lastLevel; /** Last mip level stored in this mipmap tree */ + + GLuint width0; /** Width of firstLevel image */ + GLuint height0; /** Height of firstLevel image */ + GLuint depth0; /** Depth of firstLevel image */ + + GLuint bpp; /** Bytes per texel */ + GLuint tilebits; /** RADEON_TXO_xxx_TILE */ + GLuint compressed; /** MESA_FORMAT_xxx indicating a compressed format, or 0 if uncompressed */ + + radeon_mipmap_level levels[RADEON_MAX_TEXTURE_LEVELS]; +}; + +radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *t, + GLenum target, GLuint firstLevel, GLuint lastLevel, + GLuint width0, GLuint height0, GLuint depth0, + GLuint bpp, GLuint tilebits, GLuint compressed); +void radeon_miptree_reference(radeon_mipmap_tree *mt); +void radeon_miptree_unreference(radeon_mipmap_tree *mt); + +GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, + struct gl_texture_image *texImage, GLuint face, GLuint level); +GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj); +void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, + struct gl_texture_image *texImage, GLuint face, GLuint level); + + +#endif /* __RADEON_MIPMAP_TREE_H_ */ -- cgit v1.2.3 From ddbd6ed326275de0c22011a2700f342409beee76 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 21 Jan 2009 02:15:28 +1000 Subject: r300: move to common texture_image object --- src/mesa/drivers/dri/r300/r300_context.h | 28 --------------------------- src/mesa/drivers/dri/r300/r300_tex.c | 18 ++++++++--------- src/mesa/drivers/dri/r300/r300_texstate.c | 10 +++++----- src/mesa/drivers/dri/radeon/common_context.h | 29 ++++++++++++++++++++++++++++ 4 files changed, 43 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 1c228b42efb..54844370ea1 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -79,34 +79,6 @@ typedef struct r300_context *r300ContextPtr; /************ DMA BUFFERS **************/ - -/* Texture related */ -typedef struct _r300_texture_image r300_texture_image; - - -struct _r300_texture_image { - struct gl_texture_image base; - - /** - * If mt != 0, the image is stored in hardware format in the - * given mipmap tree. In this case, base.Data may point into the - * mapping of the buffer object that contains the mipmap tree. - * - * If mt == 0, the image is stored in normal memory pointed to - * by base.Data. - */ - struct _radeon_mipmap_tree *mt; - struct radeon_bo *bo; - - int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ - int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ -}; - -static INLINE r300_texture_image *get_r300_texture_image(struct gl_texture_image *image) -{ - return (r300_texture_image*)image; -} - /* The blit width for texture uploads */ #define R300_BLIT_WIDTH_BYTES 1024 diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index e3b871c991d..a77ceb66360 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -412,7 +412,7 @@ static const struct gl_texture_format *r300ChooseTextureFormat(GLcontext * ctx, */ static struct gl_texture_image *r300NewTextureImage(GLcontext *ctx) { - return CALLOC(sizeof(r300_texture_image)); + return CALLOC(sizeof(radeon_texture_image)); } /** @@ -420,7 +420,7 @@ static struct gl_texture_image *r300NewTextureImage(GLcontext *ctx) */ static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) { - r300_texture_image* image = get_r300_texture_image(timage); + radeon_texture_image* image = get_radeon_texture_image(timage); if (image->mt) { radeon_miptree_unreference(image->mt); @@ -437,7 +437,7 @@ static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage /* Set Data pointer and additional data for mapped texture image */ -static void teximage_set_map_data(r300_texture_image *image) +static void teximage_set_map_data(radeon_texture_image *image) { radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; @@ -448,7 +448,7 @@ static void teximage_set_map_data(r300_texture_image *image) /** * Map a single texture image for glTexImage and friends. */ -static void r300_teximage_map(r300_texture_image *image, GLboolean write_enable) +static void r300_teximage_map(radeon_texture_image *image, GLboolean write_enable) { if (image->mt) { assert(!image->base.Data); @@ -459,7 +459,7 @@ static void r300_teximage_map(r300_texture_image *image, GLboolean write_enable) } -static void r300_teximage_unmap(r300_texture_image *image) +static void r300_teximage_unmap(radeon_texture_image *image) { if (image->mt) { assert(image->base.Data); @@ -483,7 +483,7 @@ static void r300MapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeon_bo_map(t->mt->bo, GL_FALSE); for(face = 0; face < t->mt->faces; ++face) { for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) - teximage_set_map_data(get_r300_texture_image(texObj->Image[face][level])); + teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level])); } } @@ -519,7 +519,7 @@ static void r300_teximage( { r300ContextPtr rmesa = R300_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); - r300_texture_image* image = get_r300_texture_image(texImage); + radeon_texture_image* image = get_radeon_texture_image(texImage); R300_FIREVERTICES(rmesa); @@ -688,7 +688,7 @@ static void r300_texsubimage(GLcontext* ctx, int dims, int level, int compressed) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300_texture_image* image = get_r300_texture_image(texImage); + radeon_texture_image* image = get_radeon_texture_image(texImage); R300_FIREVERTICES(rmesa); @@ -788,7 +788,7 @@ r300TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, static void r300_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) { GLuint face = face_for_target(target); - r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[face][texObj->BaseLevel]); + radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); r300_teximage_map(baseimage, GL_FALSE); _mesa_generate_mipmap(ctx, target, texObj); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 11c53d02700..77d9a9b3bfb 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -265,7 +265,7 @@ static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcst /** * Ensure that the given image is stored in the given miptree from now on. */ -static void migrate_image_to_miptree(radeon_mipmap_tree *mt, r300_texture_image *image, int face, int level) +static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level) { radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; unsigned char *dest; @@ -326,7 +326,7 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object { r300ContextPtr rmesa = R300_CONTEXT(ctx); radeonTexObj *t = radeon_tex_obj(texObj); - r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[0][texObj->BaseLevel]); + radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]); int face, level; if (t->validated || t->image_override) @@ -372,7 +372,7 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object /* Ensure all images are stored in the single main miptree */ for(face = 0; face < t->mt->faces; ++face) { for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { - r300_texture_image *image = get_r300_texture_image(texObj->Image[face][level]); + radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); if (RADEON_DEBUG & DEBUG_TEXTURE) fprintf(stderr, " face %i, level %i... ", face, level); if (t->mt == image->mt) { @@ -465,7 +465,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) struct gl_texture_object *texObj; struct gl_texture_image *texImage; struct radeon_renderbuffer *rb; - r300_texture_image *rImage; + radeon_texture_image *rImage; radeonContextPtr radeon; r300ContextPtr rmesa; GLframebuffer *fb; @@ -482,7 +482,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); - rImage = get_r300_texture_image(texImage); + rImage = get_radeon_texture_image(texImage); t = radeon_tex_obj(texObj); if (t == NULL) { return; diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 462b072676a..6cbcffd2830 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -110,6 +110,35 @@ struct radeon_state_atom { void (*emit) (GLcontext *, struct radeon_state_atom *atom); }; + +/* Texture related */ +typedef struct _radeon_texture_image radeon_texture_image; + +struct _radeon_texture_image { + struct gl_texture_image base; + + /** + * If mt != 0, the image is stored in hardware format in the + * given mipmap tree. In this case, base.Data may point into the + * mapping of the buffer object that contains the mipmap tree. + * + * If mt == 0, the image is stored in normal memory pointed to + * by base.Data. + */ + struct _radeon_mipmap_tree *mt; + struct radeon_bo *bo; + + int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ + int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ +}; + + +static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image) +{ + return (radeon_texture_image*)image; +} + + typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; #define RADEON_TXO_MICRO_TILE (1 << 3) -- cgit v1.2.3 From e0ec3243e87cbdfb5db2657fe791748e145930e8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 21 Jan 2009 02:21:45 +1000 Subject: r300: start migrating common functions into common code --- src/mesa/drivers/dri/r300/r300_tex.c | 133 +++--------------------------- src/mesa/drivers/dri/radeon/common_misc.c | 114 +++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 9 ++ 3 files changed, 133 insertions(+), 123 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index a77ceb66360..3ef1cc28594 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -406,102 +406,6 @@ static const struct gl_texture_format *r300ChooseTextureFormat(GLcontext * ctx, return NULL; /* never get here */ } - -/** - * Allocate an empty texture image object. - */ -static struct gl_texture_image *r300NewTextureImage(GLcontext *ctx) -{ - return CALLOC(sizeof(radeon_texture_image)); -} - -/** - * Free memory associated with this texture image. - */ -static void r300FreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) -{ - radeon_texture_image* image = get_radeon_texture_image(timage); - - if (image->mt) { - radeon_miptree_unreference(image->mt); - image->mt = 0; - assert(!image->base.Data); - } else { - _mesa_free_texture_image_data(ctx, timage); - } - if (image->bo) { - radeon_bo_unref(image->bo); - image->bo = NULL; - } -} - - -/* Set Data pointer and additional data for mapped texture image */ -static void teximage_set_map_data(radeon_texture_image *image) -{ - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; - image->base.RowStride = lvl->rowstride / image->mt->bpp; -} - - -/** - * Map a single texture image for glTexImage and friends. - */ -static void r300_teximage_map(radeon_texture_image *image, GLboolean write_enable) -{ - if (image->mt) { - assert(!image->base.Data); - - radeon_bo_map(image->mt->bo, write_enable); - teximage_set_map_data(image); - } -} - - -static void r300_teximage_unmap(radeon_texture_image *image) -{ - if (image->mt) { - assert(image->base.Data); - - image->base.Data = 0; - radeon_bo_unmap(image->mt->bo); - } -} - -/** - * Map a validated texture for reading during software rendering. - */ -static void r300MapTexture(GLcontext *ctx, struct gl_texture_object *texObj) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - int face, level; - - assert(texObj->_Complete); - assert(t->mt); - - radeon_bo_map(t->mt->bo, GL_FALSE); - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) - teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level])); - } -} - -static void r300UnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - int face, level; - - assert(texObj->_Complete); - assert(t->mt); - - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) - texObj->Image[face][level]->Data = 0; - } - radeon_bo_unmap(t->mt->bo); -} - /** * All glTexImage calls go through this function. */ @@ -541,7 +445,7 @@ static void r300_teximage( } /* Allocate memory for image */ - r300FreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ + radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ if (!t->mt) radeon_try_alloc_miptree(&rmesa->radeon, t, texImage, face, level); @@ -571,7 +475,7 @@ static void r300_teximage( } if (pixels) { - r300_teximage_map(image, GL_TRUE); + radeon_teximage_map(image, GL_TRUE); if (compressed) { memcpy(texImage->Data, pixels, imageSize); @@ -594,7 +498,7 @@ static void r300_teximage( _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); } - r300_teximage_unmap(image); + radeon_teximage_unmap(image); } _mesa_unmap_teximage_pbo(ctx, packing); @@ -697,7 +601,7 @@ static void r300_texsubimage(GLcontext* ctx, int dims, int level, if (pixels) { GLint dstRowStride; - r300_teximage_map(image, GL_TRUE); + radeon_teximage_map(image, GL_TRUE); if (image->mt) { radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; @@ -715,7 +619,7 @@ static void r300_texsubimage(GLcontext* ctx, int dims, int level, format, type, pixels, packing)) _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); - r300_teximage_unmap(image); + radeon_teximage_unmap(image); } _mesa_unmap_teximage_pbo(ctx, packing); @@ -779,23 +683,6 @@ r300TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, } -/** - * Wraps Mesa's implementation to ensure that the base level image is mapped. - * - * This relies on internal details of _mesa_generate_mipmap, in particular - * the fact that the memory for recreated texture images is always freed. - */ -static void r300_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) -{ - GLuint face = face_for_target(target); - radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); - - r300_teximage_map(baseimage, GL_FALSE); - _mesa_generate_mipmap(ctx, target, texObj); - r300_teximage_unmap(baseimage); -} - - /** * Changes variables and flags for a state update, which will happen at the @@ -929,10 +816,10 @@ void r300InitTextureFuncs(struct dd_function_table *functions) /* Note: we only plug in the functions we implement in the driver * since _mesa_init_driver_functions() was already called. */ - functions->NewTextureImage = r300NewTextureImage; - functions->FreeTexImageData = r300FreeTexImageData; - functions->MapTexture = r300MapTexture; - functions->UnmapTexture = r300UnmapTexture; + functions->NewTextureImage = radeonNewTextureImage; + functions->FreeTexImageData = radeonFreeTexImageData; + functions->MapTexture = radeonMapTexture; + functions->UnmapTexture = radeonUnmapTexture; functions->ChooseTextureFormat = r300ChooseTextureFormat; functions->TexImage1D = r300TexImage1D; @@ -950,7 +837,7 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->CompressedTexImage2D = r300CompressedTexImage2D; functions->CompressedTexSubImage2D = r300CompressedTexSubImage2D; - functions->GenerateMipmap = r300_generate_mipmap; + functions->GenerateMipmap = radeon_generate_mipmap; driInitTextureFormats(); } diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index d7c16c4957a..f70a694eb92 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -66,6 +66,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_misc.h" #include "common_lock.h" #include "common_cmdbuf.h" +#include "radeon_mipmap_tree.h" #define DRIVER_DATE "20090101" @@ -1350,3 +1351,116 @@ void radeon_print_state_atom( struct radeon_state_atom *state ) fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); } + +/* textures */ +/** + * Allocate an empty texture image object. + */ +struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx) +{ + return CALLOC(sizeof(radeon_texture_image)); +} + +/** + * Free memory associated with this texture image. + */ +void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) +{ + radeon_texture_image* image = get_radeon_texture_image(timage); + + if (image->mt) { + radeon_miptree_unreference(image->mt); + image->mt = 0; + assert(!image->base.Data); + } else { + _mesa_free_texture_image_data(ctx, timage); + } + if (image->bo) { + radeon_bo_unref(image->bo); + image->bo = NULL; + } +} + +/* Set Data pointer and additional data for mapped texture image */ +static void teximage_set_map_data(radeon_texture_image *image) +{ + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; + image->base.RowStride = lvl->rowstride / image->mt->bpp; +} + + +/** + * Map a single texture image for glTexImage and friends. + */ +void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable) +{ + if (image->mt) { + assert(!image->base.Data); + + radeon_bo_map(image->mt->bo, write_enable); + teximage_set_map_data(image); + } +} + + +void radeon_teximage_unmap(radeon_texture_image *image) +{ + if (image->mt) { + assert(image->base.Data); + + image->base.Data = 0; + radeon_bo_unmap(image->mt->bo); + } +} + +/** + * Map a validated texture for reading during software rendering. + */ +void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + int face, level; + + assert(texObj->_Complete); + assert(t->mt); + + radeon_bo_map(t->mt->bo, GL_FALSE); + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level])); + } +} + +void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + int face, level; + + assert(texObj->_Complete); + assert(t->mt); + + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + texObj->Image[face][level]->Data = 0; + } + radeon_bo_unmap(t->mt->bo); +} + + + +/** + * Wraps Mesa's implementation to ensure that the base level image is mapped. + * + * This relies on internal details of _mesa_generate_mipmap, in particular + * the fact that the memory for recreated texture images is always freed. + */ +void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) +{ + GLuint face = face_for_target(target); + radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); + + radeon_teximage_map(baseimage, GL_FALSE); + _mesa_generate_mipmap(ctx, target, texObj); + radeon_teximage_unmap(baseimage); +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index e4f200d6a53..a55e00a76c5 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -33,4 +33,13 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, GLvoid * data, int size, int stride, int count); void radeon_print_state_atom( struct radeon_state_atom *state ); + +struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx); +void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage); + +void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable); +void radeon_teximage_unmap(radeon_texture_image *image); +void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj); +void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); +void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); #endif -- cgit v1.2.3 From 2bf31b7ffdee0b84e916d5ee4aa487f2e61a1ff7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 21 Jan 2009 18:41:11 +1000 Subject: r300/radeon: move face_for_target --- src/mesa/drivers/dri/r300/r300_tex.c | 21 ++------------------- src/mesa/drivers/dri/radeon/common_misc.c | 17 +++++++++++++++-- src/mesa/drivers/dri/radeon/common_misc.h | 1 + 3 files changed, 18 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 3ef1cc28594..7363c045716 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -509,23 +509,6 @@ static void r300_teximage( } } - -static GLuint face_for_target(GLenum target) -{ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - default: - return 0; - } -} - - static void r300TexImage1D(GLcontext * ctx, GLenum target, GLint level, GLint internalFormat, GLint width, GLint border, @@ -546,7 +529,7 @@ static void r300TexImage2D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - GLuint face = face_for_target(target); + GLuint face = radeon_face_for_target(target); r300_teximage(ctx, 2, face, level, internalFormat, width, height, 1, 0, format, type, pixels, packing, texObj, texImage, 0); @@ -559,7 +542,7 @@ static void r300CompressedTexImage2D(GLcontext * ctx, GLenum target, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - GLuint face = face_for_target(target); + GLuint face = radeon_face_for_target(target); r300_teximage(ctx, 2, face, level, internalFormat, width, height, 1, imageSize, 0, 0, data, 0, texObj, texImage, 1); diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index f70a694eb92..2d0fc3a0dd3 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1447,7 +1447,20 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeon_bo_unmap(t->mt->bo); } - +GLuint radeon_face_for_target(GLenum target) +{ + switch (target) { + case GL_TEXTURE_CUBE_MAP_POSITIVE_X: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: + case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: + case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: + return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; + default: + return 0; + } +} /** * Wraps Mesa's implementation to ensure that the base level image is mapped. @@ -1457,7 +1470,7 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) */ void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) { - GLuint face = face_for_target(target); + GLuint face = radeon_face_for_target(target); radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); radeon_teximage_map(baseimage, GL_FALSE); diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index a55e00a76c5..828fb85b38b 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -42,4 +42,5 @@ void radeon_teximage_unmap(radeon_texture_image *image); void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); +GLuint radeon_face_for_target(GLenum target); #endif -- cgit v1.2.3 From 61bb82636f7b1681b5509e1a9038bbcc1feea35c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 01:05:43 +1000 Subject: r200/r300: port r200 texture handling to common code we now get texrect + trivial textures working --- src/mesa/drivers/dri/r200/r200_context.c | 9 + src/mesa/drivers/dri/r200/r200_reg.h | 3 + src/mesa/drivers/dri/r200/r200_state_init.c | 29 +- src/mesa/drivers/dri/r200/r200_tex.c | 819 +++------------------------ src/mesa/drivers/dri/r200/r200_texmem.c | 3 +- src/mesa/drivers/dri/r200/r200_texstate.c | 390 +++++-------- src/mesa/drivers/dri/r300/r300_context.c | 13 +- src/mesa/drivers/dri/r300/r300_context.h | 5 - src/mesa/drivers/dri/r300/r300_state.c | 6 +- src/mesa/drivers/dri/r300/r300_tex.c | 506 +---------------- src/mesa/drivers/dri/r300/r300_texstate.c | 211 ++----- src/mesa/drivers/dri/radeon/common_context.h | 1 + src/mesa/drivers/dri/radeon/common_misc.c | 633 +++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 68 +++ 14 files changed, 1009 insertions(+), 1687 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 741d051818d..d8e28cd7531 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -266,6 +266,11 @@ static void r200_vtbl_flush(GLcontext *ctx) R200_FIREVERTICES(R200_CONTEXT(ctx)); } +static void r200_vtbl_flush_vertices(radeonContextPtr rmesa) +{ + R200_FIREVERTICES(((r200ContextPtr)rmesa)); +} + static void r200_vtbl_set_all_dirty(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -281,11 +286,13 @@ static void r200_vtbl_emit_state(radeonContextPtr rmesa) r200EmitState((r200ContextPtr)rmesa); } + static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; radeon->vtbl.flush = r200_vtbl_flush; + radeon->vtbl.flush_vertices = r200_vtbl_flush_vertices; radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; @@ -365,6 +372,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa->radeon.nr_heaps = 1 /* screen->numTexHeaps */ ; assert(rmesa->radeon.nr_heaps < RADEON_NR_TEX_HEAPS); +#if 0 for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa, screen->texSize[i], @@ -376,6 +384,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, sizeof( radeonTexObj ), (destroy_texture_object_t *) r200DestroyTexObj ); } +#endif rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, "texture_depth"); if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h index 5ce287f7a5f..a8b0ae7e29d 100644 --- a/src/mesa/drivers/dri/r200/r200_reg.h +++ b/src/mesa/drivers/dri/r200/r200_reg.h @@ -949,6 +949,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_LOD_BIAS_MASK (0xfff80000) #define R200_LOD_BIAS_SHIFT 19 #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TX_WIDTHMASK_SHIFT 0 +#define R200_PP_TX_HEIGHTMASK_SHIFT 16 + #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ #define R200_PP_BORDER_COLOR_0 0x2c14 #define R200_PP_CUBIC_FACES_0 0x2c18 diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 3b56fec78ac..249f4eb4ce6 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_buffer.h" +#include "radeon_mipmap_tree.h" #include "radeon_cs.h" #include "common_context.h" #include "common_cmdbuf.h" @@ -353,9 +354,32 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) } -static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) { + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r200->state.texture.unit[i].texobj; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + fprintf(stderr,"atom state is %x, %x %x %x %x %x\n", atom->cmd[0], + atom->cmd[1], + atom->cmd[2], + atom->cmd[3], + atom->cmd[4], + atom->cmd[5]); + OUT_BATCH_TABLE(atom->cmd, 10); + if (t && !t->image_override) { + fprintf(stderr,"emitting reloc for %d\n", i); + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else if (!t) { + + OUT_BATCH(atom->cmd[10]); + } + END_BATCH(); } @@ -499,6 +523,9 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } + + for (i = 0; i < 5; i++) + rmesa->hw.tex[i].emit = tex_emit; if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) { ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 525a9de4a0f..7c433cc6b71 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -45,6 +45,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "texmem.h" +#include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_state.h" #include "r200_ioctl.h" @@ -67,6 +68,7 @@ static void r200SetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap, GLenu { GLboolean is_clamp = GL_FALSE; GLboolean is_clamp_to_border = GL_FALSE; + struct gl_texture_object *tObj = &t->base; t->pp_txfilter &= ~(R200_CLAMP_S_MASK | R200_CLAMP_T_MASK | R200_BORDER_MODE_D3D); @@ -103,7 +105,7 @@ static void r200SetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap, GLenu _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__); } - if (t->base.tObj->Target != GL_TEXTURE_1D) { + if (tObj->Target != GL_TEXTURE_1D) { switch ( twrap ) { case GL_REPEAT: t->pp_txfilter |= R200_CLAMP_T_WRAP; @@ -273,687 +275,6 @@ static void r200SetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] ) } -/** - * Allocate space for and load the mesa images into the texture memory block. - * This will happen before drawing with a new texture, or drawing with a - * texture after it was swapped out or teximaged again. - */ - -static radeonTexObjPtr r200AllocTexObj( struct gl_texture_object *texObj ) -{ - radeonTexObjPtr t; - - t = CALLOC_STRUCT( radeon_tex_obj ); - texObj->DriverData = t; - if ( t != NULL ) { - if ( R200_DEBUG & DEBUG_TEXTURE ) { - fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)texObj, - (void *)t ); - } - - /* Initialize non-image-dependent parts of the state: - */ - t->base.tObj = texObj; - t->border_fallback = GL_FALSE; - - make_empty_list( & t->base ); - - r200SetTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR ); - r200SetTexMaxAnisotropy( t, texObj->MaxAnisotropy ); - r200SetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - r200SetTexBorderColor( t, texObj->_BorderChan ); - } - - return t; -} - -/* try to find a format which will only need a memcopy */ -static const struct gl_texture_format * -r200Choose8888TexFormat( GLenum srcFormat, GLenum srcType ) -{ - const GLuint ui = 1; - const GLubyte littleEndian = *((const GLubyte *) &ui); - - if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { - return &_mesa_texformat_rgba8888; - } - else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { - return &_mesa_texformat_rgba8888_rev; - } - else return _dri_texformat_argb8888; -} - -static const struct gl_texture_format * -r200ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, - GLenum format, GLenum type ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const GLboolean do32bpt = - ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); - const GLboolean force16bpt = - ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); - (void) format; - - switch ( internalFormat ) { - case 4: - case GL_RGBA: - case GL_COMPRESSED_RGBA: - switch ( type ) { - case GL_UNSIGNED_INT_10_10_10_2: - case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - default: - return do32bpt ? - r200Choose8888TexFormat(format, type) : _dri_texformat_argb4444; - } - - case 3: - case GL_RGB: - case GL_COMPRESSED_RGB: - switch ( type ) { - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_5_6_5: - case GL_UNSIGNED_SHORT_5_6_5_REV: - return _dri_texformat_rgb565; - default: - return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_rgb565; - } - - case GL_RGBA8: - case GL_RGB10_A2: - case GL_RGBA12: - case GL_RGBA16: - return !force16bpt ? - r200Choose8888TexFormat(format, type) : _dri_texformat_argb4444; - - case GL_RGBA4: - case GL_RGBA2: - return _dri_texformat_argb4444; - - case GL_RGB5_A1: - return _dri_texformat_argb1555; - - case GL_RGB8: - case GL_RGB10: - case GL_RGB12: - case GL_RGB16: - return !force16bpt ? _dri_texformat_argb8888 : _dri_texformat_rgb565; - - case GL_RGB5: - case GL_RGB4: - case GL_R3_G3_B2: - return _dri_texformat_rgb565; - - case GL_ALPHA: - case GL_ALPHA4: - case GL_ALPHA8: - case GL_ALPHA12: - case GL_ALPHA16: - case GL_COMPRESSED_ALPHA: - /* can't use a8 format since interpreting hw I8 as a8 would result - in wrong rgb values (same as alpha value instead of 0). */ - return _dri_texformat_al88; - - case 1: - case GL_LUMINANCE: - case GL_LUMINANCE4: - case GL_LUMINANCE8: - case GL_LUMINANCE12: - case GL_LUMINANCE16: - case GL_COMPRESSED_LUMINANCE: - return _dri_texformat_l8; - - case 2: - case GL_LUMINANCE_ALPHA: - case GL_LUMINANCE4_ALPHA4: - case GL_LUMINANCE6_ALPHA2: - case GL_LUMINANCE8_ALPHA8: - case GL_LUMINANCE12_ALPHA4: - case GL_LUMINANCE12_ALPHA12: - case GL_LUMINANCE16_ALPHA16: - case GL_COMPRESSED_LUMINANCE_ALPHA: - return _dri_texformat_al88; - - case GL_INTENSITY: - case GL_INTENSITY4: - case GL_INTENSITY8: - case GL_INTENSITY12: - case GL_INTENSITY16: - case GL_COMPRESSED_INTENSITY: - return _dri_texformat_i8; - - case GL_YCBCR_MESA: - if (type == GL_UNSIGNED_SHORT_8_8_APPLE || - type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; - else - return &_mesa_texformat_ycbcr_rev; - - case GL_RGB_S3TC: - case GL_RGB4_S3TC: - case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; - - case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; - - case GL_RGBA_S3TC: - case GL_RGBA4_S3TC: - case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; - - case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; - - default: - _mesa_problem(ctx, - "unexpected internalFormat 0x%x in r200ChooseTextureFormat", - (int) internalFormat); - return NULL; - } - - return NULL; /* never get here */ -} - - -static GLboolean -r200ValidateClientStorage( GLcontext *ctx, GLenum target, - GLint internalFormat, - GLint srcWidth, GLint srcHeight, - GLenum format, GLenum type, const void *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) - -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf(stderr, "intformat %s format %s type %s\n", - _mesa_lookup_enum_by_nr( internalFormat ), - _mesa_lookup_enum_by_nr( format ), - _mesa_lookup_enum_by_nr( type )); - - if (!ctx->Unpack.ClientStorage) - return 0; - - if (ctx->_ImageTransferState || - texImage->IsCompressed || - texObj->GenerateMipmap) - return 0; - - - /* This list is incomplete, may be different on ppc??? - */ - switch ( internalFormat ) { - case GL_RGBA: - if ( format == GL_BGRA && type == GL_UNSIGNED_INT_8_8_8_8_REV ) { - texImage->TexFormat = _dri_texformat_argb8888; - } - else - return 0; - break; - - case GL_RGB: - if ( format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5 ) { - texImage->TexFormat = _dri_texformat_rgb565; - } - else - return 0; - break; - - case GL_YCBCR_MESA: - if ( format == GL_YCBCR_MESA && - type == GL_UNSIGNED_SHORT_8_8_REV_APPLE ) { - texImage->TexFormat = &_mesa_texformat_ycbcr_rev; - } - else if ( format == GL_YCBCR_MESA && - (type == GL_UNSIGNED_SHORT_8_8_APPLE || - type == GL_UNSIGNED_BYTE)) { - texImage->TexFormat = &_mesa_texformat_ycbcr; - } - else - return 0; - break; - - default: - return 0; - } - - /* Could deal with these packing issues, but currently don't: - */ - if (packing->SkipPixels || - packing->SkipRows || - packing->SwapBytes || - packing->LsbFirst) { - return 0; - } - - { - GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, - format, type); - - - if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf(stderr, "%s: srcRowStride %d/%x\n", - __FUNCTION__, srcRowStride, srcRowStride); - - /* Could check this later in upload, pitch restrictions could be - * relaxed, but would need to store the image pitch somewhere, - * as packing details might change before image is uploaded: - */ - if (!r200IsGartMemory( rmesa, pixels, srcHeight * srcRowStride ) || - (srcRowStride & 63)) - return 0; - - - /* Have validated that _mesa_transfer_teximage would be a straight - * memcpy at this point. NOTE: future calls to TexSubImage will - * overwrite the client data. This is explicitly mentioned in the - * extension spec. - */ - texImage->Data = (void *)pixels; - texImage->IsClientData = GL_TRUE; - texImage->RowStride = srcRowStride / texImage->TexFormat->TexelBytes; - - return 1; - } -} - - -static void r200TexImage1D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D"); - return; - } - } - - /* Note, this will call ChooseTextureFormat */ - _mesa_store_teximage1d(ctx, target, level, internalFormat, - width, border, format, type, pixels, - &ctx->Unpack, texObj, texImage); - - t->dirty_images[0] |= (1 << level); -} - - -static void r200TexSubImage1D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage1D"); - return; - } - } - - _mesa_store_texsubimage1d(ctx, target, level, xoffset, width, - format, type, pixels, packing, texObj, - texImage); - - t->dirty_images[0] |= (1 << level); -} - - -static void r200TexImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - if ( t != NULL ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D"); - return; - } - } - - texImage->IsClientData = GL_FALSE; - - if (r200ValidateClientStorage( ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) { - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using client storage\n", __FUNCTION__); - } - else { - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using normal storage\n", __FUNCTION__); - - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r200ChooseTextureFormat. - */ - _mesa_store_teximage2d(ctx, target, level, internalFormat, - width, height, border, format, type, pixels, - &ctx->Unpack, texObj, texImage); - - t->dirty_images[face] |= (1 << level); - } -} - - -static void r200TexSubImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage2D"); - return; - } - } - - _mesa_store_texsubimage2d(ctx, target, level, xoffset, yoffset, width, - height, format, type, pixels, packing, texObj, - texImage); - - t->dirty_images[face] |= (1 << level); -} - - -static void r200CompressedTexImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid *data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - if ( t != NULL ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexImage2D"); - return; - } - } - - texImage->IsClientData = GL_FALSE; -/* can't call this, different parameters. Would never evaluate to true anyway currently - if (r200ValidateClientStorage( ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) { - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using client storage\n", __FUNCTION__); - } - else */{ - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using normal storage\n", __FUNCTION__); - - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r200ChooseTextureFormat. - */ - _mesa_store_compressed_teximage2d(ctx, target, level, internalFormat, width, - height, border, imageSize, data, texObj, texImage); - - t->dirty_images[face] |= (1 << level); - } -} - - -static void r200CompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, - GLsizei imageSize, const GLvoid *data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexSubImage2D"); - return; - } - } - - _mesa_store_compressed_texsubimage2d(ctx, target, level, xoffset, yoffset, width, - height, format, imageSize, data, texObj, texImage); - - t->dirty_images[face] |= (1 << level); -} - - -#if ENABLE_HW_3D_TEXTURE -static void r200TexImage3D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLint border, - GLenum format, GLenum type, const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage3D"); - return; - } - } - - texImage->IsClientData = GL_FALSE; - -#if 0 - if (r200ValidateClientStorage( ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) { - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using client storage\n", __FUNCTION__); - } - else -#endif - { - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Using normal storage\n", __FUNCTION__); - - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r200ChooseTextureFormat. - */ - _mesa_store_teximage3d(ctx, target, level, internalFormat, - width, height, depth, border, - format, type, pixels, - &ctx->Unpack, texObj, texImage); - - t->dirty_images[0] |= (1 << level); - } -} -#endif - - -#if ENABLE_HW_3D_TEXTURE -static void -r200TexSubImage3D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - -/* fprintf(stderr, "%s\n", __FUNCTION__); */ - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) r200AllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage3D"); - return; - } - texObj->DriverData = t; - } - - _mesa_store_texsubimage3d(ctx, target, level, xoffset, yoffset, zoffset, - width, height, depth, - format, type, pixels, packing, texObj, texImage); - - t->dirty_images[0] |= (1 << level); -} -#endif @@ -1034,7 +355,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, struct gl_texture_object *texObj, GLenum pname, const GLfloat *params ) { - radeonTexObjPtr t = (radeonTexObjPtr) texObj->DriverData; + radeonTexObj* t = radeon_tex_obj(texObj); if ( R200_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { fprintf( stderr, "%s( %s )\n", __FUNCTION__, @@ -1081,46 +402,33 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, } - -static void r200BindTexture( GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj ) -{ - if ( R200_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { - fprintf( stderr, "%s( %p ) unit=%d\n", __FUNCTION__, (void *)texObj, - ctx->Texture.CurrentUnit ); - } - - if ( (target == GL_TEXTURE_1D) - || (target == GL_TEXTURE_2D) -#if ENABLE_HW_3D_TEXTURE - || (target == GL_TEXTURE_3D) -#endif - || (target == GL_TEXTURE_CUBE_MAP) - || (target == GL_TEXTURE_RECTANGLE_NV) ) { - assert( texObj->DriverData != NULL ); - } -} - - -static void r200DeleteTexture( GLcontext *ctx, - struct gl_texture_object *texObj ) +static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - driTextureObject * t = (driTextureObject *) texObj->DriverData; - - if ( R200_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { - fprintf( stderr, "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj, - _mesa_lookup_enum_by_nr( texObj->Target ) ); + radeonTexObj* t = radeon_tex_obj(texObj); + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + (void *)texObj, + _mesa_lookup_enum_by_nr(texObj->Target)); + } + + if (rmesa) { + int i; + R200_FIREVERTICES(rmesa); + for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { + if ( t == rmesa->state.texture.unit[i].texobj ) { + rmesa->state.texture.unit[i].texobj = NULL; + rmesa->hw.tex[i].dirty = GL_FALSE; + rmesa->hw.cube[i].dirty = GL_FALSE; + } + } } - - if ( t != NULL ) { - if ( rmesa ) { - R200_FIREVERTICES( rmesa ); - } - - driDestroyTextureObject( t ); + + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; } - /* Free mipmap images and the texture object itself */ _mesa_delete_texture_object(ctx, texObj); } @@ -1150,46 +458,57 @@ static void r200TexGen( GLcontext *ctx, * Called via ctx->Driver.NewTextureObject. * Note: this function will be called during context creation to * allocate the default texture objects. - * Note: we could use containment here to 'derive' the driver-specific - * texture object from the core mesa gl_texture_object. Not done at this time. * Fixup MaxAnisotropy according to user preference. */ -static struct gl_texture_object * -r200NewTextureObject( GLcontext *ctx, GLuint name, GLenum target ) +static struct gl_texture_object *r200NewTextureObject(GLcontext * ctx, + GLuint name, + GLenum target) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_texture_object *obj; - obj = _mesa_new_texture_object(ctx, name, target); - if (!obj) - return NULL; - obj->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; - r200AllocTexObj( obj ); - return obj; + radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); + + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + t, _mesa_lookup_enum_by_nr(target)); + } + + _mesa_initialize_texture_object(&t->base, name, target); + t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; + + /* Initialize hardware state */ + r200SetTexWrap( t, t->base.WrapS, t->base.WrapT, t->base.WrapR ); + r200SetTexMaxAnisotropy( t, t->base.MaxAnisotropy ); + r200SetTexFilter(t, t->base.MinFilter, t->base.MagFilter); + r200SetTexBorderColor(t, t->base._BorderChan); + + return &t->base; } + void r200InitTextureFuncs( struct dd_function_table *functions ) { /* Note: we only plug in the functions we implement in the driver * since _mesa_init_driver_functions() was already called. */ - functions->ChooseTextureFormat = r200ChooseTextureFormat; - functions->TexImage1D = r200TexImage1D; - functions->TexImage2D = r200TexImage2D; + functions->ChooseTextureFormat = radeonChooseTextureFormat; + functions->TexImage1D = radeonTexImage1D; + functions->TexImage2D = radeonTexImage2D; #if ENABLE_HW_3D_TEXTURE - functions->TexImage3D = r200TexImage3D; + functions->TexImage3D = radeonTexImage3D; #else functions->TexImage3D = _mesa_store_teximage3d; #endif - functions->TexSubImage1D = r200TexSubImage1D; - functions->TexSubImage2D = r200TexSubImage2D; + functions->TexSubImage1D = radeonTexSubImage1D; + functions->TexSubImage2D = radeonTexSubImage2D; #if ENABLE_HW_3D_TEXTURE - functions->TexSubImage3D = r200TexSubImage3D; + functions->TexSubImage3D = radeonTexSubImage3D; #else functions->TexSubImage3D = _mesa_store_texsubimage3d; #endif functions->NewTextureObject = r200NewTextureObject; - functions->BindTexture = r200BindTexture; + // functions->BindTexture = r200BindTexture; functions->DeleteTexture = r200DeleteTexture; functions->IsTextureResident = driIsTextureResident; @@ -1197,22 +516,16 @@ void r200InitTextureFuncs( struct dd_function_table *functions ) functions->TexParameter = r200TexParameter; functions->TexGen = r200TexGen; - functions->CompressedTexImage2D = r200CompressedTexImage2D; - functions->CompressedTexSubImage2D = r200CompressedTexSubImage2D; + functions->CompressedTexImage2D = radeonCompressedTexImage2D; + functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; + + functions->GenerateMipmap = radeon_generate_mipmap; + + functions->NewTextureImage = radeonNewTextureImage; + functions->FreeTexImageData = radeonFreeTexImageData; + functions->MapTexture = radeonMapTexture; + functions->UnmapTexture = radeonUnmapTexture; driInitTextureFormats(); -#if 000 - /* moved or obsolete code */ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - driInitTextureObjects( ctx, & rmesa->swapped, - DRI_TEXMGR_DO_TEXTURE_1D - | DRI_TEXMGR_DO_TEXTURE_2D ); - - /* Hack: r200NewTextureObject is not yet installed when the - * default textures are created. Therefore set MaxAnisotropy of the - * default 2D texture now. */ - ctx->Shared->Default2D->MaxAnisotropy = driQueryOptionf (&rmesa->optionCache, - "def_max_anisotropy"); -#endif } diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index 5a0922de215..a50786e2e78 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -49,7 +49,7 @@ SOFTWARE. #include /* for usleep() */ - +#if 0 /** * Destroy any device-dependent state associated with the texture. This may * include NULLing out hardware state that points to the texture. @@ -528,3 +528,4 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) return 0; } +#endif diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 02f79bf3f80..2a402e99c6f 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -40,6 +40,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/texobj.h" #include "main/enums.h" +#include "common_context.h" +#include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_state.h" #include "r200_ioctl.h" @@ -139,6 +141,8 @@ static const struct tx_table tx_table_le[] = #undef _ALPHA #undef _INVALID +#if 0 + /** * This function computes the number of bytes of storage needed for * the given texture object (all mipmap levels, all cube faces). @@ -180,7 +184,7 @@ static void r200SetTexImages( r200ContextPtr rmesa, } } - texelBytes = baseImage->TexFormat->TexelBytes; + /* Compute which mipmap levels we really want to send to the hardware. */ @@ -217,7 +221,7 @@ static void r200SetTexImages( r200ContextPtr rmesa, } } if (tObj->Target != GL_TEXTURE_RECTANGLE_NV) { - /* we can set macro tiling even for small textures, they will be untiled anyway */ + /* we can set macro tiling even for small textures, they will be untiled anyway */ t->tile_bits |= R200_TXO_MACRO_TILE; } } @@ -387,7 +391,7 @@ static void r200SetTexImages( r200ContextPtr rmesa, /* FYI: r200UploadTexImages( rmesa, t ) used to be called here */ } - +#endif /* ================================================================ @@ -1232,10 +1236,11 @@ static void import_tex_obj_state( r200ContextPtr rmesa, cmd[TEX_PP_TXOFFSET_OLDDRM] = texobj->pp_txoffset; } - if (texobj->base.tObj->Target == GL_TEXTURE_CUBE_MAP) { + if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) { GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; - GLuint bytesPerFace = texobj->base.totalSize / 6; - ASSERT(texobj->base.totalSize % 6 == 0); + // GLuint bytesPerFace = texobj->base.totalSize / 6; + // ASSERT(texobj->base.totalSize % 6 == 0); + GLuint bytesPerFace = 1; // TODO R200_STATECHANGE( rmesa, cube[unit] ); cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; @@ -1254,7 +1259,6 @@ static void import_tex_obj_state( r200ContextPtr rmesa, texobj->dirty_state &= ~(1<TexGenEnabled & R_BIT) { if (texUnit->GenModeR != mode) mixed_fallback = GL_TRUE; @@ -1513,52 +1516,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit ) return GL_TRUE; } - -static void disable_tex( GLcontext *ctx, int unit ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if (rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_0_ENABLE<state.texture.unit[unit].texobj != NULL ) { - /* The old texture is no longer bound to this texture unit. - * Mark it as such. - */ - - rmesa->state.texture.unit[unit].texobj->base.bound &= ~(1UL << unit); - rmesa->state.texture.unit[unit].texobj = NULL; - } - - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_0_ENABLE << unit); - - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); - - if (rmesa->radeon.TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<2 texunits. - */ - - { - GLuint tmp = rmesa->TexGenEnabled; - - rmesa->TexGenEnabled &= ~(R200_TEXGEN_TEXMAT_0_ENABLE<TexGenEnabled &= ~(R200_TEXMAT_0_ENABLE<TexGenNeedNormals[unit] = GL_FALSE; - rmesa->TexGenCompSel &= ~(R200_OUTPUT_TEX_0 << unit); - - if (tmp != rmesa->TexGenEnabled) { - rmesa->recheck_texgen[unit] = GL_TRUE; - rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - } - } -} - void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -1575,237 +1532,164 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d ) } } -static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - - /* Need to load the 2d images associated with this unit. - */ - if (t->pp_txformat & R200_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~R200_TXFORMAT_NON_POWER2; - t->base.dirty_images[0] = ~0; - } - - ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); - - if ( t->base.dirty_images[0] ) { - R200_FIREVERTICES( rmesa ); - r200SetTexImages( rmesa, tObj ); - r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock && !t->image_override ) - return GL_FALSE; - } - - set_re_cntl_d3d( ctx, unit, GL_FALSE ); - - return GL_TRUE; -} - -#if ENABLE_HW_3D_TEXTURE -static GLboolean enable_tex_3d( GLcontext *ctx, int unit ) +/** + * Compute the cached hardware register values for the given texture object. + * + * \param rmesa Context pointer + * \param t the r300 texture object + */ +static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - - /* Need to load the 3d images associated with this unit. - */ - if (t->pp_txformat & R200_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~R200_TXFORMAT_NON_POWER2; - t->base.dirty_images[0] = ~0; + const struct gl_texture_image *firstImage = + t->base.Image[0][t->mt->firstLevel]; + GLint log2Width, log2Height, log2Depth, texelBytes; + + log2Width = firstImage->WidthLog2; + log2Height = firstImage->HeightLog2; + log2Depth = firstImage->DepthLog2; + texelBytes = firstImage->TexFormat->TexelBytes; + + + if (!t->image_override) { + if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + const struct tx_table *table = _mesa_little_endian() ? tx_table_le : + tx_table_be; + + t->pp_txformat &= ~(R200_TXFORMAT_FORMAT_MASK | + R200_TXFORMAT_ALPHA_IN_MAP); + t->pp_txfilter &= ~R200_YUV_TO_RGB; + + t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + } else { + _mesa_problem(NULL, "unexpected texture format in %s", + __FUNCTION__); + return; + } } + + t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK; + t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << R200_MAX_MIP_LEVEL_SHIFT; + + t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK | + R200_TXFORMAT_HEIGHT_MASK | + R200_TXFORMAT_CUBIC_MAP_ENABLE | + R200_TXFORMAT_F5_WIDTH_MASK | + R200_TXFORMAT_F5_HEIGHT_MASK); + t->pp_txformat |= ((log2Width << R200_TXFORMAT_WIDTH_SHIFT) | + (log2Height << R200_TXFORMAT_HEIGHT_SHIFT)); + + t->tile_bits = 0; + + // if (t->base.Target == GL_TEXTURE_CUBE_MAP) + // t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP; + // if (t->base.Target == GL_TEXTURE_3D) + // t->pp_txformat |= R300_TX_FORMAT_3D; + + t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK); + if (t->base.Target == GL_TEXTURE_3D) { + t->pp_txformat_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT); + t->pp_txformat_x |= R200_TEXCOORD_VOLUME; - ASSERT(tObj->Target == GL_TEXTURE_3D); - - /* R100 & R200 do not support mipmaps for 3D textures. - */ - if ( (tObj->MinFilter != GL_NEAREST) && (tObj->MinFilter != GL_LINEAR) ) { - return GL_FALSE; } - - if ( t->base.dirty_images[0] ) { - R200_FIREVERTICES( rmesa ); - r200SetTexImages( rmesa, tObj ); - r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock ) - return GL_FALSE; + else if (t->base.Target == GL_TEXTURE_CUBE_MAP) { + ASSERT(log2Width == log2Height); + t->pp_txformat |= ((log2Width << R200_TXFORMAT_F5_WIDTH_SHIFT) | + (log2Height << R200_TXFORMAT_F5_HEIGHT_SHIFT) | + /* don't think we need this bit, if it exists at all - fglrx does not set it */ + (R200_TXFORMAT_CUBIC_MAP_ENABLE)); + t->pp_txformat_x |= R200_TEXCOORD_CUBIC_ENV; + t->pp_cubic_faces = ((log2Width << R200_FACE_WIDTH_1_SHIFT) | + (log2Height << R200_FACE_HEIGHT_1_SHIFT) | + (log2Width << R200_FACE_WIDTH_2_SHIFT) | + (log2Height << R200_FACE_HEIGHT_2_SHIFT) | + (log2Width << R200_FACE_WIDTH_3_SHIFT) | + (log2Height << R200_FACE_HEIGHT_3_SHIFT) | + (log2Width << R200_FACE_WIDTH_4_SHIFT) | + (log2Height << R200_FACE_HEIGHT_4_SHIFT)); } - - set_re_cntl_d3d( ctx, unit, GL_TRUE ); - - return GL_TRUE; -} -#endif - -static GLboolean enable_tex_cube( GLcontext *ctx, int unit ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - GLuint face; - - /* Need to load the 2d images associated with this unit. - */ - if (t->pp_txformat & R200_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~R200_TXFORMAT_NON_POWER2; - for (face = 0; face < 6; face++) - t->base.dirty_images[face] = ~0; + else { + /* If we don't in fact send enough texture coordinates, q will be 1, + * making TEXCOORD_PROJ act like TEXCOORD_NONPROJ (Right?) + */ + t->pp_txformat_x |= R200_TEXCOORD_PROJ; } - ASSERT(tObj->Target == GL_TEXTURE_CUBE_MAP); - - if ( t->base.dirty_images[0] || t->base.dirty_images[1] || - t->base.dirty_images[2] || t->base.dirty_images[3] || - t->base.dirty_images[4] || t->base.dirty_images[5] ) { - /* flush */ - R200_FIREVERTICES( rmesa ); - /* layout memory space, once for all faces */ - r200SetTexImages( rmesa, tObj ); - } + t->pp_txsize = (((firstImage->Width - 1) << R200_PP_TX_WIDTHMASK_SHIFT) + | ((firstImage->Height - 1) << R200_PP_TX_HEIGHTMASK_SHIFT)); - /* upload (per face) */ - for (face = 0; face < 6; face++) { - if (t->base.dirty_images[face]) { - r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, face ); - } - } - - if ( !t->base.memBlock ) { - /* texmem alloc failed, use s/w fallback */ - return GL_FALSE; + if ( !t->image_override ) { + if (firstImage->IsCompressed) + t->pp_txpitch = (firstImage->Width + 63) & ~(63); + else + t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63); + t->pp_txpitch -= 32; } - set_re_cntl_d3d( ctx, unit, GL_TRUE ); - - return GL_TRUE; -} - -static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - - if (!(t->pp_txformat & R200_TXFORMAT_NON_POWER2)) { + if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { t->pp_txformat |= R200_TXFORMAT_NON_POWER2; - t->base.dirty_images[0] = ~0; - } - - ASSERT(tObj->Target == GL_TEXTURE_RECTANGLE_NV); + // t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; - if ( t->base.dirty_images[0] ) { - R200_FIREVERTICES( rmesa ); - r200SetTexImages( rmesa, tObj ); - r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock && - !t->image_override && - !rmesa->prefer_gart_client_texturing ) - return GL_FALSE; } - - set_re_cntl_d3d( ctx, unit, GL_FALSE ); - - return GL_TRUE; + } - -static GLboolean update_tex_common( GLcontext *ctx, int unit ) +static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - - /* Fallback if there's a texture border */ - if ( tObj->Image[0][tObj->BaseLevel]->Border > 0 ) - return GL_FALSE; - - /* Update state if this is a different texture object to last - * time. - */ - if ( rmesa->state.texture.unit[unit].texobj != t ) { - if ( rmesa->state.texture.unit[unit].texobj != NULL ) { - /* The old texture is no longer bound to this texture unit. - * Mark it as such. - */ + radeonTexObj *t = radeon_tex_obj(texObj); - rmesa->state.texture.unit[unit].texobj->base.bound &= - ~(1UL << unit); - } - - rmesa->state.texture.unit[unit].texobj = t; - t->base.bound |= (1UL << unit); - t->dirty_state |= 1<hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_0_ENABLE<hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); - rmesa->recheck_texgen[unit] = GL_TRUE; - } + if (texObj->Target == GL_TEXTURE_RECTANGLE_NV || + texObj->Target == GL_TEXTURE_2D) + set_re_cntl_d3d( ctx, unit, GL_FALSE ); + else + set_re_cntl_d3d( ctx, unit, GL_TRUE ); + R200_STATECHANGE( rmesa, ctx ); + rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; + + R200_STATECHANGE( rmesa, vtx ); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); + rmesa->recheck_texgen[unit] = GL_TRUE; if (t->dirty_state & (1<recheck_texgen[unit]) { - GLboolean fallback = !r200_validate_texgen( ctx, unit ); - TCL_FALLBACK( ctx, (R200_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = 0; - rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - - FALLBACK( rmesa, R200_FALLBACK_BORDER_MODE, t->border_fallback ); - return !t->border_fallback; + t->dirty_state = R200_TEX_ALL; + + t->validated = GL_TRUE; + return GL_TRUE; } - - -static GLboolean r200UpdateTextureUnit( GLcontext *ctx, int unit ) +GLboolean r200UpdateTextureUnit(GLcontext *ctx, int unit) { r200ContextPtr rmesa = R200_CONTEXT(ctx); GLuint unitneeded = rmesa->state.texture.unit[unit].unitneeded; - if ( unitneeded & (TEXTURE_RECT_BIT) ) { - return (enable_tex_rect( ctx, unit ) && - update_tex_common( ctx, unit )); - } - else if ( unitneeded & (TEXTURE_1D_BIT | TEXTURE_2D_BIT) ) { - return (enable_tex_2d( ctx, unit ) && - update_tex_common( ctx, unit )); - } -#if ENABLE_HW_3D_TEXTURE - else if ( unitneeded & (TEXTURE_3D_BIT) ) { - return (enable_tex_3d( ctx, unit ) && - update_tex_common( ctx, unit )); - } -#endif - else if ( unitneeded & (TEXTURE_CUBE_BIT) ) { - return (enable_tex_cube( ctx, unit ) && - update_tex_common( ctx, unit )); - } - else if ( unitneeded ) { - return GL_FALSE; - } - else { - disable_tex( ctx, unit ); - return GL_TRUE; - } + if (!unitneeded) + return GL_TRUE; + + if (!r200_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) { + _mesa_warning(ctx, + "failed to validate texture for unit %d.\n", + unit); + rmesa->state.texture.unit[unit].texobj = NULL; + return GL_FALSE; + } + + rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); + return GL_TRUE; } @@ -1863,7 +1747,7 @@ void r200UpdateTextureState( GLcontext *ctx ) R200_STATECHANGE(rmesa, tex[1]); rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE; if (!(rmesa->hw.cst.cmd[CST_PP_CNTL_X] & R200_PPX_TEX_1_ENABLE)) - rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; + rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] |= R200_TXFORMAT_LOOKUP_DISABLE; } else if (!ctx->ATIFragmentShader._Enabled) { diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index e84d0acd6d8..eb8e481a18e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -245,6 +245,11 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes R300_WAIT_3D | R300_WAIT_3D_CLEAN)); } +static void r300_vtbl_flush_vertices(radeonContextPtr rmesa) +{ + R300_FIREVERTICES(((r300ContextPtr)rmesa)); +} + static void r300_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r300_get_lock; @@ -289,7 +294,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, */ driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r300"); - r300->initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); /* Init default driver functions then plug in our R300-specific functions @@ -309,10 +314,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, } /* Init r300 context data */ - r300->texture_depth = driQueryOptioni(&r300->radeon.optionCache, + r300->radeon.texture_depth = driQueryOptioni(&r300->radeon.optionCache, "texture_depth"); - if (r300->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - r300->texture_depth = (screen->cpp == 4) ? + if (r300->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) + r300->radeon.texture_depth = (screen->cpp == 4) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; /* Set the maximum texture size small enough that we can guarentee that diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 54844370ea1..8f67460e420 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -717,11 +717,6 @@ struct r300_context { /* Vertex buffers */ - GLuint NewGLState; - - int texture_depth; - float initialMaxAnisotropy; - GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index ea5d65542b2..5fbd5b93ff8 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2416,8 +2416,8 @@ void r300UpdateShaders(r300ContextPtr rmesa) ctx = rmesa->radeon.glCtx; - if (rmesa->NewGLState && hw_tcl_on) { - rmesa->NewGLState = 0; + if (rmesa->radeon.NewGLState && hw_tcl_on) { + rmesa->radeon.NewGLState = 0; for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { rmesa->temp_attrib[i] = @@ -2677,7 +2677,7 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) r300UpdateStateParameters(ctx, new_state); - r300->NewGLState |= new_state; + r300->radeon.NewGLState |= new_state; } /** diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 7363c045716..11e89ffd0f0 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -181,492 +181,6 @@ static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4]) t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); } -/* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *r300Choose8888TexFormat(GLenum srcFormat, - GLenum srcType) -{ - const GLuint ui = 1; - const GLubyte littleEndian = *((const GLubyte *)&ui); - - if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { - return &_mesa_texformat_rgba8888; - } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { - return &_mesa_texformat_rgba8888_rev; - } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8)) { - return &_mesa_texformat_argb8888_rev; - } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { - return &_mesa_texformat_argb8888; - } else - return _dri_texformat_argb8888; -} - -static const struct gl_texture_format *r300ChooseTextureFormat(GLcontext * ctx, - GLint - internalFormat, - GLenum format, - GLenum type) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - const GLboolean do32bpt = - (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32); - const GLboolean force16bpt = - (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16); - (void)format; - -#if 0 - fprintf(stderr, "InternalFormat=%s(%d) type=%s format=%s\n", - _mesa_lookup_enum_by_nr(internalFormat), internalFormat, - _mesa_lookup_enum_by_nr(type), _mesa_lookup_enum_by_nr(format)); - fprintf(stderr, "do32bpt=%d force16bpt=%d\n", do32bpt, force16bpt); -#endif - - switch (internalFormat) { - case 4: - case GL_RGBA: - case GL_COMPRESSED_RGBA: - switch (type) { - case GL_UNSIGNED_INT_10_10_10_2: - case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? _dri_texformat_argb8888 : - _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - default: - return do32bpt ? r300Choose8888TexFormat(format, type) : - _dri_texformat_argb4444; - } - - case 3: - case GL_RGB: - case GL_COMPRESSED_RGB: - switch (type) { - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_5_6_5: - case GL_UNSIGNED_SHORT_5_6_5_REV: - return _dri_texformat_rgb565; - default: - return do32bpt ? _dri_texformat_argb8888 : - _dri_texformat_rgb565; - } - - case GL_RGBA8: - case GL_RGB10_A2: - case GL_RGBA12: - case GL_RGBA16: - return !force16bpt ? - r300Choose8888TexFormat(format, - type) : _dri_texformat_argb4444; - - case GL_RGBA4: - case GL_RGBA2: - return _dri_texformat_argb4444; - - case GL_RGB5_A1: - return _dri_texformat_argb1555; - - case GL_RGB8: - case GL_RGB10: - case GL_RGB12: - case GL_RGB16: - return !force16bpt ? _dri_texformat_argb8888 : - _dri_texformat_rgb565; - - case GL_RGB5: - case GL_RGB4: - case GL_R3_G3_B2: - return _dri_texformat_rgb565; - - case GL_ALPHA: - case GL_ALPHA4: - case GL_ALPHA8: - case GL_ALPHA12: - case GL_ALPHA16: - case GL_COMPRESSED_ALPHA: - return _dri_texformat_a8; - - case 1: - case GL_LUMINANCE: - case GL_LUMINANCE4: - case GL_LUMINANCE8: - case GL_LUMINANCE12: - case GL_LUMINANCE16: - case GL_COMPRESSED_LUMINANCE: - return _dri_texformat_l8; - - case 2: - case GL_LUMINANCE_ALPHA: - case GL_LUMINANCE4_ALPHA4: - case GL_LUMINANCE6_ALPHA2: - case GL_LUMINANCE8_ALPHA8: - case GL_LUMINANCE12_ALPHA4: - case GL_LUMINANCE12_ALPHA12: - case GL_LUMINANCE16_ALPHA16: - case GL_COMPRESSED_LUMINANCE_ALPHA: - return _dri_texformat_al88; - - case GL_INTENSITY: - case GL_INTENSITY4: - case GL_INTENSITY8: - case GL_INTENSITY12: - case GL_INTENSITY16: - case GL_COMPRESSED_INTENSITY: - return _dri_texformat_i8; - - case GL_YCBCR_MESA: - if (type == GL_UNSIGNED_SHORT_8_8_APPLE || - type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; - else - return &_mesa_texformat_ycbcr_rev; - - case GL_RGB_S3TC: - case GL_RGB4_S3TC: - case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; - - case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; - - case GL_RGBA_S3TC: - case GL_RGBA4_S3TC: - case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; - - case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; - - case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; - case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; - case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; - case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; - case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; - case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; - case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; - case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; - case GL_RGB16F_ARB: - return &_mesa_texformat_rgba_float16; - case GL_RGB32F_ARB: - return &_mesa_texformat_rgba_float32; - case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; - case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; - - case GL_DEPTH_COMPONENT: - case GL_DEPTH_COMPONENT16: - case GL_DEPTH_COMPONENT24: - case GL_DEPTH_COMPONENT32: -#if 0 - switch (type) { - case GL_UNSIGNED_BYTE: - case GL_UNSIGNED_SHORT: - return &_mesa_texformat_z16; - case GL_UNSIGNED_INT: - return &_mesa_texformat_z32; - case GL_UNSIGNED_INT_24_8_EXT: - default: - return &_mesa_texformat_z24_s8; - } -#else - return &_mesa_texformat_z16; -#endif - - default: - _mesa_problem(ctx, - "unexpected internalFormat 0x%x in r300ChooseTextureFormat", - (int)internalFormat); - return NULL; - } - - return NULL; /* never get here */ -} - -/** - * All glTexImage calls go through this function. - */ -static void r300_teximage( - GLcontext *ctx, int dims, - GLint face, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLsizei imageSize, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage, - int compressed) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - radeonTexObj* t = radeon_tex_obj(texObj); - radeon_texture_image* image = get_radeon_texture_image(texImage); - - R300_FIREVERTICES(rmesa); - - t->validated = GL_FALSE; - - /* Choose and fill in the texture format for this image */ - texImage->TexFormat = r300ChooseTextureFormat(ctx, internalFormat, format, type); - _mesa_set_fetch_functions(texImage, dims); - - if (texImage->TexFormat->TexelBytes == 0) { - texImage->IsCompressed = GL_TRUE; - texImage->CompressedSize = - ctx->Driver.CompressedTextureSize(ctx, texImage->Width, - texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); - } else { - texImage->IsCompressed = GL_FALSE; - texImage->CompressedSize = 0; - } - - /* Allocate memory for image */ - radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ - - if (!t->mt) - radeon_try_alloc_miptree(&rmesa->radeon, t, texImage, face, level); - if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { - image->mt = t->mt; - image->mtlevel = level - t->mt->firstLevel; - image->mtface = face; - radeon_miptree_reference(t->mt); - } else { - int size; - if (texImage->IsCompressed) { - size = texImage->CompressedSize; - } else { - size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; - } - texImage->Data = _mesa_alloc_texmemory(size); - } - - /* Upload texture image; note that the spec allows pixels to be NULL */ - if (compressed) { - pixels = _mesa_validate_pbo_compressed_teximage( - ctx, imageSize, pixels, packing, "glCompressedTexImage"); - } else { - pixels = _mesa_validate_pbo_teximage( - ctx, dims, width, height, depth, - format, type, pixels, packing, "glTexImage"); - } - - if (pixels) { - radeon_teximage_map(image, GL_TRUE); - - if (compressed) { - memcpy(texImage->Data, pixels, imageSize); - } else { - GLuint dstRowStride; - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; - } - if (!texImage->TexFormat->StoreImage(ctx, dims, - texImage->_BaseFormat, - texImage->TexFormat, - texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */ - dstRowStride, - texImage->ImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); - } - - radeon_teximage_unmap(image); - } - - _mesa_unmap_teximage_pbo(ctx, packing); - - /* SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); - } -} - -static void r300TexImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - r300_teximage(ctx, 1, 0, level, internalFormat, width, 1, 1, - 0, format, type, pixels, packing, texObj, texImage, 0); -} - -static void r300TexImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - GLuint face = radeon_face_for_target(target); - - r300_teximage(ctx, 2, face, level, internalFormat, width, height, 1, - 0, format, type, pixels, packing, texObj, texImage, 0); -} - -static void r300CompressedTexImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - GLuint face = radeon_face_for_target(target); - - r300_teximage(ctx, 2, face, level, internalFormat, width, height, 1, - imageSize, 0, 0, data, 0, texObj, texImage, 1); -} - -static void r300TexImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - r300_teximage(ctx, 3, 0, level, internalFormat, width, height, depth, - 0, format, type, pixels, packing, texObj, texImage, 0); -} - -/** - * Update a subregion of the given texture image. - */ -static void r300_texsubimage(GLcontext* ctx, int dims, int level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage, - int compressed) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - radeon_texture_image* image = get_radeon_texture_image(texImage); - - R300_FIREVERTICES(rmesa); - - pixels = _mesa_validate_pbo_teximage(ctx, dims, - width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); - - if (pixels) { - GLint dstRowStride; - radeon_teximage_map(image, GL_TRUE); - - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; - } - - if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, - texImage->TexFormat, texImage->Data, - xoffset, yoffset, zoffset, - dstRowStride, - texImage->ImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); - - radeon_teximage_unmap(image); - } - - _mesa_unmap_teximage_pbo(ctx, packing); - - /* GL_SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); - } -} - -static void r300TexSubImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - r300_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, - format, type, pixels, packing, texObj, texImage, 0); -} - -static void r300TexSubImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - r300_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, - format, type, pixels, packing, texObj, texImage, 0); -} - -static void r300CompressedTexSubImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint xoffset, - GLint yoffset, GLsizei width, - GLsizei height, GLenum format, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - r300_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, - format, 0, data, 0, texObj, texImage, 1); -} - -static void -r300TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - r300_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, - format, type, pixels, packing, texObj, texImage, 0); -} - - - /** * Changes variables and flags for a state update, which will happen at the * next UpdateTextureState @@ -784,7 +298,7 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, } _mesa_initialize_texture_object(&t->base, name, target); - t->base.MaxAnisotropy = rmesa->initialMaxAnisotropy; + t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; /* Initialize hardware state */ r300UpdateTexWrap(t); @@ -804,21 +318,21 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->MapTexture = radeonMapTexture; functions->UnmapTexture = radeonUnmapTexture; - functions->ChooseTextureFormat = r300ChooseTextureFormat; - functions->TexImage1D = r300TexImage1D; - functions->TexImage2D = r300TexImage2D; - functions->TexImage3D = r300TexImage3D; - functions->TexSubImage1D = r300TexSubImage1D; - functions->TexSubImage2D = r300TexSubImage2D; - functions->TexSubImage3D = r300TexSubImage3D; + functions->ChooseTextureFormat = radeonChooseTextureFormat; + functions->TexImage1D = radeonTexImage1D; + functions->TexImage2D = radeonTexImage2D; + functions->TexImage3D = radeonTexImage3D; + functions->TexSubImage1D = radeonTexSubImage1D; + functions->TexSubImage2D = radeonTexSubImage2D; + functions->TexSubImage3D = radeonTexSubImage3D; functions->NewTextureObject = r300NewTextureObject; functions->DeleteTexture = r300DeleteTexture; functions->IsTextureResident = driIsTextureResident; functions->TexParameter = r300TexParameter; - functions->CompressedTexImage2D = r300CompressedTexImage2D; - functions->CompressedTexSubImage2D = r300CompressedTexSubImage2D; + functions->CompressedTexImage2D = radeonCompressedTexImage2D; + functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; functions->GenerateMipmap = radeon_generate_mipmap; diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 77d9a9b3bfb..68c7ca3d29f 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -242,81 +242,6 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) } } - -static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, - GLuint numrows, GLuint rowsize) -{ - assert(rowsize <= dststride); - assert(rowsize <= srcstride); - - if (rowsize == srcstride && rowsize == dststride) { - memcpy(dst, src, numrows*rowsize); - } else { - GLuint i; - for(i = 0; i < numrows; ++i) { - memcpy(dst, src, rowsize); - dst += dststride; - src += srcstride; - } - } -} - - -/** - * Ensure that the given image is stored in the given miptree from now on. - */ -static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level) -{ - radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; - unsigned char *dest; - - assert(image->mt != mt); - assert(dstlvl->width == image->base.Width); - assert(dstlvl->height == image->base.Height); - assert(dstlvl->depth == image->base.Depth); - - radeon_bo_map(mt->bo, GL_TRUE); - dest = mt->bo->ptr + dstlvl->faces[face].offset; - - if (image->mt) { - /* Format etc. should match, so we really just need a memcpy(). - * In fact, that memcpy() could be done by the hardware in many - * cases, provided that we have a proper memory manager. - */ - radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; - - assert(srclvl->size == dstlvl->size); - assert(srclvl->rowstride == dstlvl->rowstride); - - radeon_bo_map(image->mt->bo, GL_FALSE); - memcpy(dest, - image->mt->bo->ptr + srclvl->faces[face].offset, - dstlvl->size); - radeon_bo_unmap(image->mt->bo); - - radeon_miptree_unreference(image->mt); - } else { - uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; - - if (mt->tilebits) - WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); - - copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, - image->base.Height * image->base.Depth, srcrowstride); - - _mesa_free_texmemory(image->base.Data); - image->base.Data = 0; - } - - radeon_bo_unmap(mt->bo); - - image->mt = mt; - image->mtface = face; - image->mtlevel = level; - radeon_miptree_reference(image->mt); -} - - /** * Ensure the given texture is ready for rendering. * @@ -326,67 +251,10 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object { r300ContextPtr rmesa = R300_CONTEXT(ctx); radeonTexObj *t = radeon_tex_obj(texObj); - radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]); - int face, level; - - if (t->validated || t->image_override) - return GL_TRUE; - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj); - - if (baseimage->base.Border > 0) + if (!radeon_validate_texture_miptree(ctx, texObj)) return GL_FALSE; - /* Ensure a matching miptree exists. - * - * Differing mipmap trees can result when the app uses TexImage to - * change texture dimensions. - * - * Prefer to use base image's miptree if it - * exists, since that most likely contains more valid data (remember - * that the base level is usually significantly larger than the rest - * of the miptree, so cubemaps are the only possible exception). - */ - if (baseimage->mt && - baseimage->mt != t->mt && - radeon_miptree_matches_texture(baseimage->mt, &t->base)) { - radeon_miptree_unreference(t->mt); - t->mt = baseimage->mt; - radeon_miptree_reference(t->mt); - } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - } - - if (!t->mt) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, " Allocate new miptree\n"); - radeon_try_alloc_miptree(&rmesa->radeon, t, &baseimage->base, 0, texObj->BaseLevel); - if (!t->mt) { - _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree"); - return GL_FALSE; - } - } - - /* Ensure all images are stored in the single main miptree */ - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { - radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, " face %i, level %i... ", face, level); - if (t->mt == image->mt) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "OK\n"); - continue; - } - - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "migrating\n"); - migrate_image_to_miptree(t->mt, image, face, level); - } - } - /* Configure the hardware registers (more precisely, the cached version * of the hardware registers). */ setup_hardware_state(rmesa, t); @@ -431,7 +299,8 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - t->bo = NULL; + + t->bo = NULL; t->override_offset = offset; t->pp_txpitch &= (1 << 13) -1; pitch_val = pitch; @@ -463,7 +332,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) { struct gl_texture_unit *texUnit; struct gl_texture_object *texObj; - struct gl_texture_image *texImage; + struct gl_texture_image *texImage; struct radeon_renderbuffer *rb; radeon_texture_image *rImage; radeonContextPtr radeon; @@ -488,43 +357,43 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) return; } - radeon_update_renderbuffers(pDRICtx, dPriv); - /* back & depth buffer are useless free them right away */ - rb = (void*)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void*)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); + radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ + rb = (void*)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); rb->bo = NULL; - } - rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb->bo == NULL) { - /* Failed to BO for the buffer */ - return; - } - - _mesa_lock_texture(radeon->glCtx, texObj); - if (t->bo) { - t->bo = NULL; - } - if (t->mt) { - t->mt = NULL; - } - if (rImage->mt) { - radeon_miptree_unreference(rImage->mt); - rImage->mt = NULL; - } + } + rb = (void*)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; + } + + _mesa_lock_texture(radeon->glCtx, texObj); + if (t->bo) { + t->bo = NULL; + } + if (t->mt) { + t->mt = NULL; + } + if (rImage->mt) { + radeon_miptree_unreference(rImage->mt); + rImage->mt = NULL; + } fprintf(stderr,"settexbuf %dx%d@%d\n", rb->width, rb->height, rb->cpp); - _mesa_init_teximage_fields(radeon->glCtx, target, texImage, - rb->width, rb->height, 1, 0, rb->cpp); + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->width, rb->height, 1, 0, rb->cpp); texImage->TexFormat = &_mesa_texformat_rgba8888_rev; - rImage->bo = rb->bo; - - t->bo = rb->bo; - t->tile_bits = 0; + rImage->bo = rb->bo; + + t->bo = rb->bo; + t->tile_bits = 0; t->image_override = GL_TRUE; t->override_offset = 0; t->pp_txpitch &= (1 << 13) -1; @@ -553,6 +422,6 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; t->pp_txpitch |= pitch_val; t->validated = GL_TRUE; - _mesa_unlock_texture(radeon->glCtx, texObj); - return; + _mesa_unlock_texture(radeon->glCtx, texObj); + return; } diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 6cbcffd2830..09a53b00eae 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -404,6 +404,7 @@ struct radeon_context { void (*update_draw_buffer)(GLcontext *ctx); void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); void (*emit_state)(radeonContextPtr rmesa); + void (*flush_vertices)(radeonContextPtr rmesa); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 2d0fc3a0dd3..94d2e6c8764 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -36,6 +36,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include #include "main/glheader.h" #include "main/imports.h" +#include "main/context.h" #include "main/api_arrayelt.h" #include "main/enums.h" #include "main/colormac.h" @@ -47,6 +48,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/tnl.h" #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "main/mipmap.h" +#include "main/texformat.h" +#include "main/texstore.h" +#include "main/teximage.h" +#include "main/texobj.h" #include "drirenderbuffer.h" #include "vblank.h" @@ -1477,3 +1483,630 @@ void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_obj _mesa_generate_mipmap(ctx, target, texObj); radeon_teximage_unmap(baseimage); } + + +/* try to find a format which will only need a memcopy */ +static const struct gl_texture_format *radeonChoose8888TexFormat(GLenum srcFormat, + GLenum srcType) +{ + const GLuint ui = 1; + const GLubyte littleEndian = *((const GLubyte *)&ui); + + if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { + return &_mesa_texformat_rgba8888; + } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { + return &_mesa_texformat_rgba8888_rev; + } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8)) { + return &_mesa_texformat_argb8888_rev; + } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { + return &_mesa_texformat_argb8888; + } else + return _dri_texformat_argb8888; +} + +const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + const GLboolean do32bpt = + (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32); + const GLboolean force16bpt = + (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16); + (void)format; + +#if 0 + fprintf(stderr, "InternalFormat=%s(%d) type=%s format=%s\n", + _mesa_lookup_enum_by_nr(internalFormat), internalFormat, + _mesa_lookup_enum_by_nr(type), _mesa_lookup_enum_by_nr(format)); + fprintf(stderr, "do32bpt=%d force16bpt=%d\n", do32bpt, force16bpt); +#endif + + switch (internalFormat) { + case 4: + case GL_RGBA: + case GL_COMPRESSED_RGBA: + switch (type) { + case GL_UNSIGNED_INT_10_10_10_2: + case GL_UNSIGNED_INT_2_10_10_10_REV: + return do32bpt ? _dri_texformat_argb8888 : + _dri_texformat_argb1555; + case GL_UNSIGNED_SHORT_4_4_4_4: + case GL_UNSIGNED_SHORT_4_4_4_4_REV: + return _dri_texformat_argb4444; + case GL_UNSIGNED_SHORT_5_5_5_1: + case GL_UNSIGNED_SHORT_1_5_5_5_REV: + return _dri_texformat_argb1555; + default: + return do32bpt ? radeonChoose8888TexFormat(format, type) : + _dri_texformat_argb4444; + } + + case 3: + case GL_RGB: + case GL_COMPRESSED_RGB: + switch (type) { + case GL_UNSIGNED_SHORT_4_4_4_4: + case GL_UNSIGNED_SHORT_4_4_4_4_REV: + return _dri_texformat_argb4444; + case GL_UNSIGNED_SHORT_5_5_5_1: + case GL_UNSIGNED_SHORT_1_5_5_5_REV: + return _dri_texformat_argb1555; + case GL_UNSIGNED_SHORT_5_6_5: + case GL_UNSIGNED_SHORT_5_6_5_REV: + return _dri_texformat_rgb565; + default: + return do32bpt ? _dri_texformat_argb8888 : + _dri_texformat_rgb565; + } + + case GL_RGBA8: + case GL_RGB10_A2: + case GL_RGBA12: + case GL_RGBA16: + return !force16bpt ? + radeonChoose8888TexFormat(format, + type) : _dri_texformat_argb4444; + + case GL_RGBA4: + case GL_RGBA2: + return _dri_texformat_argb4444; + + case GL_RGB5_A1: + return _dri_texformat_argb1555; + + case GL_RGB8: + case GL_RGB10: + case GL_RGB12: + case GL_RGB16: + return !force16bpt ? _dri_texformat_argb8888 : + _dri_texformat_rgb565; + + case GL_RGB5: + case GL_RGB4: + case GL_R3_G3_B2: + return _dri_texformat_rgb565; + + case GL_ALPHA: + case GL_ALPHA4: + case GL_ALPHA8: + case GL_ALPHA12: + case GL_ALPHA16: + case GL_COMPRESSED_ALPHA: + return _dri_texformat_a8; + + case 1: + case GL_LUMINANCE: + case GL_LUMINANCE4: + case GL_LUMINANCE8: + case GL_LUMINANCE12: + case GL_LUMINANCE16: + case GL_COMPRESSED_LUMINANCE: + return _dri_texformat_l8; + + case 2: + case GL_LUMINANCE_ALPHA: + case GL_LUMINANCE4_ALPHA4: + case GL_LUMINANCE6_ALPHA2: + case GL_LUMINANCE8_ALPHA8: + case GL_LUMINANCE12_ALPHA4: + case GL_LUMINANCE12_ALPHA12: + case GL_LUMINANCE16_ALPHA16: + case GL_COMPRESSED_LUMINANCE_ALPHA: + return _dri_texformat_al88; + + case GL_INTENSITY: + case GL_INTENSITY4: + case GL_INTENSITY8: + case GL_INTENSITY12: + case GL_INTENSITY16: + case GL_COMPRESSED_INTENSITY: + return _dri_texformat_i8; + + case GL_YCBCR_MESA: + if (type == GL_UNSIGNED_SHORT_8_8_APPLE || + type == GL_UNSIGNED_BYTE) + return &_mesa_texformat_ycbcr; + else + return &_mesa_texformat_ycbcr_rev; + + case GL_RGB_S3TC: + case GL_RGB4_S3TC: + case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: + return &_mesa_texformat_rgb_dxt1; + + case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: + return &_mesa_texformat_rgba_dxt1; + + case GL_RGBA_S3TC: + case GL_RGBA4_S3TC: + case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: + return &_mesa_texformat_rgba_dxt3; + + case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: + return &_mesa_texformat_rgba_dxt5; + + case GL_ALPHA16F_ARB: + return &_mesa_texformat_alpha_float16; + case GL_ALPHA32F_ARB: + return &_mesa_texformat_alpha_float32; + case GL_LUMINANCE16F_ARB: + return &_mesa_texformat_luminance_float16; + case GL_LUMINANCE32F_ARB: + return &_mesa_texformat_luminance_float32; + case GL_LUMINANCE_ALPHA16F_ARB: + return &_mesa_texformat_luminance_alpha_float16; + case GL_LUMINANCE_ALPHA32F_ARB: + return &_mesa_texformat_luminance_alpha_float32; + case GL_INTENSITY16F_ARB: + return &_mesa_texformat_intensity_float16; + case GL_INTENSITY32F_ARB: + return &_mesa_texformat_intensity_float32; + case GL_RGB16F_ARB: + return &_mesa_texformat_rgba_float16; + case GL_RGB32F_ARB: + return &_mesa_texformat_rgba_float32; + case GL_RGBA16F_ARB: + return &_mesa_texformat_rgba_float16; + case GL_RGBA32F_ARB: + return &_mesa_texformat_rgba_float32; + + case GL_DEPTH_COMPONENT: + case GL_DEPTH_COMPONENT16: + case GL_DEPTH_COMPONENT24: + case GL_DEPTH_COMPONENT32: +#if 0 + switch (type) { + case GL_UNSIGNED_BYTE: + case GL_UNSIGNED_SHORT: + return &_mesa_texformat_z16; + case GL_UNSIGNED_INT: + return &_mesa_texformat_z32; + case GL_UNSIGNED_INT_24_8_EXT: + default: + return &_mesa_texformat_z24_s8; + } +#else + return &_mesa_texformat_z16; +#endif + + default: + _mesa_problem(ctx, + "unexpected internalFormat 0x%x in r300ChooseTextureFormat", + (int)internalFormat); + return NULL; + } + + return NULL; /* never get here */ +} + +/** + * All glTexImage calls go through this function. + */ +static void radeon_teximage( + GLcontext *ctx, int dims, + GLint face, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLsizei imageSize, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj* t = radeon_tex_obj(texObj); + radeon_texture_image* image = get_radeon_texture_image(texImage); + + rmesa->vtbl.flush_vertices(rmesa); + + t->validated = GL_FALSE; + + /* Choose and fill in the texture format for this image */ + texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type); + _mesa_set_fetch_functions(texImage, dims); + + if (texImage->TexFormat->TexelBytes == 0) { + texImage->IsCompressed = GL_TRUE; + texImage->CompressedSize = + ctx->Driver.CompressedTextureSize(ctx, texImage->Width, + texImage->Height, texImage->Depth, + texImage->TexFormat->MesaFormat); + } else { + texImage->IsCompressed = GL_FALSE; + texImage->CompressedSize = 0; + } + + /* Allocate memory for image */ + radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ + + if (!t->mt) + radeon_try_alloc_miptree(rmesa, t, texImage, face, level); + if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { + image->mt = t->mt; + image->mtlevel = level - t->mt->firstLevel; + image->mtface = face; + radeon_miptree_reference(t->mt); + } else { + int size; + if (texImage->IsCompressed) { + size = texImage->CompressedSize; + } else { + size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; + } + texImage->Data = _mesa_alloc_texmemory(size); + } + + /* Upload texture image; note that the spec allows pixels to be NULL */ + if (compressed) { + pixels = _mesa_validate_pbo_compressed_teximage( + ctx, imageSize, pixels, packing, "glCompressedTexImage"); + } else { + pixels = _mesa_validate_pbo_teximage( + ctx, dims, width, height, depth, + format, type, pixels, packing, "glTexImage"); + } + + if (pixels) { + radeon_teximage_map(image, GL_TRUE); + + if (compressed) { + memcpy(texImage->Data, pixels, imageSize); + } else { + GLuint dstRowStride; + if (image->mt) { + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; + } + if (!texImage->TexFormat->StoreImage(ctx, dims, + texImage->_BaseFormat, + texImage->TexFormat, + texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */ + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); + } + + radeon_teximage_unmap(image); + } + + _mesa_unmap_teximage_pbo(ctx, packing); + + /* SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); + } +} + +void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_teximage(ctx, 1, 0, level, internalFormat, width, 1, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); +} + +void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) + +{ + GLuint face = radeon_face_for_target(target); + + radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); +} + +void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint internalFormat, + GLint width, GLint height, GLint border, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + GLuint face = radeon_face_for_target(target); + + radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, + imageSize, 0, 0, data, 0, texObj, texImage, 1); +} + +void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_teximage(ctx, 3, 0, level, internalFormat, width, height, depth, + 0, format, type, pixels, packing, texObj, texImage, 0); +} + +/** + * Update a subregion of the given texture image. + */ +static void radeon_texsubimage(GLcontext* ctx, int dims, int level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeon_texture_image* image = get_radeon_texture_image(texImage); + + rmesa->vtbl.flush_vertices(rmesa); + + pixels = _mesa_validate_pbo_teximage(ctx, dims, + width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); + + if (pixels) { + GLint dstRowStride; + radeon_teximage_map(image, GL_TRUE); + + if (image->mt) { + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; + } + + if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, + texImage->TexFormat, texImage->Data, + xoffset, yoffset, zoffset, + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); + + radeon_teximage_unmap(image); + } + + _mesa_unmap_teximage_pbo(ctx, packing); + + /* GL_SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); + } +} + +void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, + GLsizei width, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, + format, type, pixels, packing, texObj, texImage, 0); +} + +void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, + 1, format, type, pixels, packing, texObj, texImage, + 0); +} + +void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint xoffset, + GLint yoffset, GLsizei width, + GLsizei height, GLenum format, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, + format, 0, data, 0, texObj, texImage, 1); +} + + +void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, + format, type, pixels, packing, texObj, texImage, 0); +} + +static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, + GLuint numrows, GLuint rowsize) +{ + assert(rowsize <= dststride); + assert(rowsize <= srcstride); + + if (rowsize == srcstride && rowsize == dststride) { + memcpy(dst, src, numrows*rowsize); + } else { + GLuint i; + for(i = 0; i < numrows; ++i) { + memcpy(dst, src, rowsize); + dst += dststride; + src += srcstride; + } + } +} + + +/** + * Ensure that the given image is stored in the given miptree from now on. + */ +static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level) +{ + radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; + unsigned char *dest; + + assert(image->mt != mt); + assert(dstlvl->width == image->base.Width); + assert(dstlvl->height == image->base.Height); + assert(dstlvl->depth == image->base.Depth); + + radeon_bo_map(mt->bo, GL_TRUE); + dest = mt->bo->ptr + dstlvl->faces[face].offset; + + if (image->mt) { + /* Format etc. should match, so we really just need a memcpy(). + * In fact, that memcpy() could be done by the hardware in many + * cases, provided that we have a proper memory manager. + */ + radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; + + assert(srclvl->size == dstlvl->size); + assert(srclvl->rowstride == dstlvl->rowstride); + + radeon_bo_map(image->mt->bo, GL_FALSE); + memcpy(dest, + image->mt->bo->ptr + srclvl->faces[face].offset, + dstlvl->size); + radeon_bo_unmap(image->mt->bo); + + radeon_miptree_unreference(image->mt); + } else { + uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; + +// if (mt->tilebits) +// WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); + + copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, + image->base.Height * image->base.Depth, srcrowstride); + + _mesa_free_texmemory(image->base.Data); + image->base.Data = 0; + } + + radeon_bo_unmap(mt->bo); + + image->mt = mt; + image->mtface = face; + image->mtlevel = level; + radeon_miptree_reference(image->mt); +} + +int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj *t = radeon_tex_obj(texObj); + radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]); + int face, level; + + if (t->validated || t->image_override) + return GL_TRUE; + + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj); + + if (baseimage->base.Border > 0) + return GL_FALSE; + + /* Ensure a matching miptree exists. + * + * Differing mipmap trees can result when the app uses TexImage to + * change texture dimensions. + * + * Prefer to use base image's miptree if it + * exists, since that most likely contains more valid data (remember + * that the base level is usually significantly larger than the rest + * of the miptree, so cubemaps are the only possible exception). + */ + if (baseimage->mt && + baseimage->mt != t->mt && + radeon_miptree_matches_texture(baseimage->mt, &t->base)) { + radeon_miptree_unreference(t->mt); + t->mt = baseimage->mt; + radeon_miptree_reference(t->mt); + } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + } + + if (!t->mt) { + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, " Allocate new miptree\n"); + radeon_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel); + if (!t->mt) { + _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree"); + return GL_FALSE; + } + } + + /* Ensure all images are stored in the single main miptree */ + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { + radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, " face %i, level %i... ", face, level); + if (t->mt == image->mt) { + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "OK\n"); + continue; + } + + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "migrating\n"); + migrate_image_to_miptree(t->mt, image, face, level); + } + } + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 828fb85b38b..470a3fd5a72 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -42,5 +42,73 @@ void radeon_teximage_unmap(radeon_texture_image *image); void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); +int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); GLuint radeon_face_for_target(GLenum target); +const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type); + +void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint internalFormat, + GLint width, GLint height, GLint border, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, + GLsizei width, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint xoffset, + GLint yoffset, GLsizei width, + GLsizei height, GLenum format, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); + +void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); + + #endif -- cgit v1.2.3 From 674b204ba7c4854fec92a0c939de5012fecb6d87 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 01:17:31 +1000 Subject: r200: fix cubemaps --- src/mesa/drivers/dri/r200/r200_state_init.c | 26 ++++++++++++++++++++++++++ src/mesa/drivers/dri/r200/r200_texstate.c | 9 --------- 2 files changed, 26 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 249f4eb4ce6..26d89432bf0 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -382,6 +382,29 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } +static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r200->state.texture.unit[i].texobj; + GLuint size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, 3); + + fprintf(stderr,"total size is %d\n", t->mt->totalsize); + if (t && !t->image_override) { + size = t->mt->totalsize / 6; + OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + END_BATCH(); +} /* Initialize the context's hardware state. */ @@ -533,6 +556,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); + for (i = 0; i < 5; i++) + rmesa->hw.cube[i].emit = cube_emit; } else { ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); @@ -542,6 +567,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); } + if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) { ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 2a402e99c6f..f8641d18f8d 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1581,11 +1581,6 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) t->tile_bits = 0; - // if (t->base.Target == GL_TEXTURE_CUBE_MAP) - // t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP; - // if (t->base.Target == GL_TEXTURE_3D) - // t->pp_txformat |= R300_TX_FORMAT_3D; - t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK); if (t->base.Target == GL_TEXTURE_3D) { t->pp_txformat_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT); @@ -1628,8 +1623,6 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { t->pp_txformat |= R200_TXFORMAT_NON_POWER2; - // t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; - } } @@ -1647,8 +1640,6 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object * of the hardware registers). */ setup_hardware_state(rmesa, t); - - if (texObj->Target == GL_TEXTURE_RECTANGLE_NV || texObj->Target == GL_TEXTURE_2D) set_re_cntl_d3d( ctx, unit, GL_FALSE ); -- cgit v1.2.3 From 909aeb005f6e5b35889aa9b4fc5e68786bdad047 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 01:24:50 +1000 Subject: radeon: fix 1D textures --- src/mesa/drivers/dri/r200/r200_texstate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index f8641d18f8d..7dcb86d00f4 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1641,7 +1641,8 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object setup_hardware_state(rmesa, t); if (texObj->Target == GL_TEXTURE_RECTANGLE_NV || - texObj->Target == GL_TEXTURE_2D) + texObj->Target == GL_TEXTURE_2D || + texObj->Target == GL_TEXTURE_1D) set_re_cntl_d3d( ctx, unit, GL_FALSE ); else set_re_cntl_d3d( ctx, unit, GL_TRUE ); -- cgit v1.2.3 From 0788e424713a2b71cceee60bcd21c79a2896b3bd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 02:38:00 +1000 Subject: r200: remove indexed verts --- src/mesa/drivers/dri/r200/r200_context.h | 2 -- src/mesa/drivers/dri/r200/r200_swtcl.c | 2 -- src/mesa/drivers/dri/r200/r200_swtcl.h | 4 ---- src/mesa/drivers/dri/r200/r200_tcl.c | 4 ---- 4 files changed, 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 5ecf7979994..2725dc495f6 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -544,7 +544,6 @@ struct r200_tcl_info { GLuint *Elts; - struct radeon_dma_region indexed_verts; struct radeon_dma_region vertex_data[15]; }; @@ -603,7 +602,6 @@ struct r200_swtcl_info { struct radeon_bo *bo; void (*flush) (r200ContextPtr); - struct radeon_dma_region indexed_verts; }; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 0be772d0158..7275886f846 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -954,6 +954,4 @@ void r200DestroySwtcl( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - // if (rmesa->swtcl.indexed_verts.buf) - // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index 0c25d8bc83d..91c7c0ff8fc 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -52,10 +52,6 @@ extern void r200BuildVertices( GLcontext *ctx, GLuint start, GLuint count, extern void r200PrintSetupFlags(char *msg, GLuint flags ); -extern void r200_emit_indexed_verts( GLcontext *ctx, - GLuint start, - GLuint count ); - extern void r200_translate_vertex( GLcontext *ctx, const radeonVertex *src, SWvertex *dst ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 226bf1620c4..0f15fd457e5 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -570,10 +570,6 @@ static void transition_to_hwtnl( GLcontext *ctx ) rmesa->dma.flush = NULL; - // if (rmesa->swtcl.indexed_verts.buf) - // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - // __FUNCTION__ ); - R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_FORCE_W_TO_ONE; -- cgit v1.2.3 From eda2284961e46002c7b2bd4e4ae2785d7b0a2191 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 02:53:30 +1000 Subject: r200r300: start merging span code --- src/mesa/drivers/dri/r200/r200_span.c | 141 +++-------------- src/mesa/drivers/dri/r200/r200_texstate.c | 253 ------------------------------ src/mesa/drivers/dri/r300/radeon_span.c | 217 ------------------------- src/mesa/drivers/dri/radeon/common_misc.c | 211 +++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 9 +- 5 files changed, 241 insertions(+), 590 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index df0172f64ed..17c651395b9 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -52,21 +52,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * information. */ #define LOCAL_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ + const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ - GLubyte *buf = (GLubyte *) drb->flippedData \ - + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \ GLuint p; \ (void) p; #define LOCAL_DEPTH_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ + const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; \ - GLubyte *buf = (GLubyte *) drb->Base.Data; + GLuint yo = dPriv->y; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -89,7 +86,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) +#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -99,7 +96,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) +#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) #include "spantmp2.h" @@ -116,70 +113,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * are set up correctly. It is not quite enough to get it working with hyperz too... */ -/* extract bit 'b' of x, result is zero or one */ -#define BIT(x,b) ((x & (1<>b) - -static GLuint -r200_mba_z32( driRenderbuffer *drb, GLint x, GLint y ) -{ - GLuint pitch = drb->pitch; - if (drb->depthHasSurface) { - return 4 * (x + y * pitch); - } - else { - GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x7FF) >> 5); - GLuint a = - (BIT(x,0) << 2) | - (BIT(y,0) << 3) | - (BIT(x,1) << 4) | - (BIT(y,1) << 5) | - (BIT(x,3) << 6) | - (BIT(x,4) << 7) | - (BIT(x,2) << 8) | - (BIT(y,2) << 9) | - (BIT(y,3) << 10) | - (((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) | - ((b >> 1) << 12); - return a; - } -} - -static GLuint -r200_mba_z16( driRenderbuffer *drb, GLint x, GLint y ) -{ - GLuint pitch = drb->pitch; - if (drb->depthHasSurface) { - return 2 * (x + y * pitch); - } - else { - GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x7FF) >> 6); - GLuint a = - (BIT(x,0) << 1) | - (BIT(y,0) << 2) | - (BIT(x,1) << 3) | - (BIT(y,1) << 4) | - (BIT(x,2) << 5) | - (BIT(x,4) << 6) | - (BIT(x,5) << 7) | - (BIT(x,3) << 8) | - (BIT(y,2) << 9) | - (BIT(y,3) << 10) | - (((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) | - ((b >> 1) << 12); - return a; - } -} - - /* 16-bit depth buffer functions */ #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo )) = d; + *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo )); + d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -191,16 +133,17 @@ r200_mba_z16( driRenderbuffer *drb, GLint x, GLint y ) #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = r200_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + r200_mba_z32( drb, _x + xo, \ - _y + yo )) & 0x00ffffff; + do { \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \ + }while(0) #define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" @@ -214,17 +157,17 @@ do { \ */ #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = r200_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = r200_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ d = tmp >> 24; \ } while (0) @@ -233,51 +176,11 @@ do { \ #include "stenciltmp.h" -/* Move locking out to get reasonable span performance (10x better - * than doing this in HW_LOCK above). WaitForIdle() is the main - * culprit. - */ - -static void r200SpanRenderStart( GLcontext *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - - R200_FIREVERTICES( rmesa ); - LOCK_HARDWARE( &rmesa->radeon ); - radeonWaitForIdleLocked( &rmesa->radeon ); - - /* Read & rewrite the first pixel in the frame buffer. This should - * be a noop, right? In fact without this conform fails as reading - * from the framebuffer sometimes produces old results -- the - * on-card read cache gets mixed up and doesn't notice that the - * framebuffer has been updated. - * - * In the worst case this is buggy too as p might get the wrong - * value first time, so really need a hidden pixel somewhere for this. - */ - { - int p; - driRenderbuffer *drb = - (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0]; - volatile int *buf = - (volatile int *)(rmesa->radeon.dri.screen->pFB + drb->offset); - p = *buf; - *buf = p; - } -} - -static void r200SpanRenderFinish( GLcontext *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - _swrast_flush( ctx ); - UNLOCK_HARDWARE( &rmesa->radeon ); -} - void r200InitSpanFuncs( GLcontext *ctx ) { struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx); - swdd->SpanRenderStart = r200SpanRenderStart; - swdd->SpanRenderFinish = r200SpanRenderFinish; + swdd->SpanRenderStart = radeonSpanRenderStart; + swdd->SpanRenderFinish = radeonSpanRenderFinish; } diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 7dcb86d00f4..12b828846f4 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -141,259 +141,6 @@ static const struct tx_table tx_table_le[] = #undef _ALPHA #undef _INVALID -#if 0 - -/** - * This function computes the number of bytes of storage needed for - * the given texture object (all mipmap levels, all cube faces). - * The \c image[face][level].x/y/width/height parameters for upload/blitting - * are computed here. \c pp_txfilter, \c pp_txformat, etc. will be set here - * too. - * - * \param rmesa Context pointer - * \param tObj GL texture object whose images are to be posted to - * hardware state. - */ -static void r200SetTexImages( r200ContextPtr rmesa, - struct gl_texture_object *tObj ) -{ - radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData; - const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; - GLint curOffset, blitWidth; - GLint i, texelBytes; - GLint numLevels; - GLint log2Width, log2Height, log2Depth; - - /* Set the hardware texture format - */ - if ( !t->image_override ) { - if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) { - const struct tx_table *table = _mesa_little_endian() ? tx_table_le : - tx_table_be; - - t->pp_txformat &= ~(R200_TXFORMAT_FORMAT_MASK | - R200_TXFORMAT_ALPHA_IN_MAP); - t->pp_txfilter &= ~R200_YUV_TO_RGB; - - t->pp_txformat |= table[ baseImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= table[ baseImage->TexFormat->MesaFormat ].filter; - } - else { - _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; - } - } - - - - /* Compute which mipmap levels we really want to send to the hardware. - */ - - driCalculateTextureFirstLastLevel( (driTextureObject *) t ); - log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2; - log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2; - log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2; - - numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); - - /* Calculate mipmap offsets and dimensions for blitting (uploading) - * The idea is that we lay out the mipmap levels within a block of - * memory organized as a rectangle of width BLIT_WIDTH_BYTES. - */ - curOffset = 0; - blitWidth = BLIT_WIDTH_BYTES; - t->tile_bits = 0; - - /* figure out if this texture is suitable for tiling. */ - if (texelBytes) { - if (rmesa->texmicrotile && (tObj->Target != GL_TEXTURE_RECTANGLE_NV) && - /* texrect might be able to use micro tiling too in theory? */ - (baseImage->Height > 1)) { - /* allow 32 (bytes) x 1 mip (which will use two times the space - the non-tiled version would use) max if base texture is large enough */ - if ((numLevels == 1) || - (((baseImage->Width * texelBytes / baseImage->Height) <= 32) && - (baseImage->Width * texelBytes > 64)) || - ((baseImage->Width * texelBytes / baseImage->Height) <= 16)) { - t->tile_bits |= R200_TXO_MICRO_TILE; - } - } - if (tObj->Target != GL_TEXTURE_RECTANGLE_NV) { - /* we can set macro tiling even for small textures, they will be untiled anyway */ - t->tile_bits |= R200_TXO_MACRO_TILE; - } - } - - for (i = 0; i < numLevels; i++) { - const struct gl_texture_image *texImage; - GLuint size; - - texImage = tObj->Image[0][i + t->base.firstLevel]; - if ( !texImage ) - break; - - /* find image size in bytes */ - if (texImage->IsCompressed) { - /* need to calculate the size AFTER padding even though the texture is - submitted without padding. - Only handle pot textures currently - don't know if npot is even possible, - size calculation would certainly need (trivial) adjustments. - Align (and later pad) to 32byte, not sure what that 64byte blit width is - good for? */ - if ((t->pp_txformat & R200_TXFORMAT_FORMAT_MASK) == R200_TXFORMAT_DXT1) { - /* RGB_DXT1/RGBA_DXT1, 8 bytes per block */ - if ((texImage->Width + 3) < 8) /* width one block */ - size = texImage->CompressedSize * 4; - else if ((texImage->Width + 3) < 16) - size = texImage->CompressedSize * 2; - else size = texImage->CompressedSize; - } - else /* DXT3/5, 16 bytes per block */ - if ((texImage->Width + 3) < 8) - size = texImage->CompressedSize * 2; - else size = texImage->CompressedSize; - } - else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - size = ((texImage->Width * texelBytes + 63) & ~63) * texImage->Height; - } - else if (t->tile_bits & R200_TXO_MICRO_TILE) { - /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, - though the actual offset may be different (if texture is less than - 32 bytes width) to the untiled case */ - int w = (texImage->Width * texelBytes * 2 + 31) & ~31; - size = (w * ((texImage->Height + 1) / 2)) * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - } - else { - int w = (texImage->Width * texelBytes + 31) & ~31; - size = w * texImage->Height * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - } - assert(size > 0); - - /* Align to 32-byte offset. It is faster to do this unconditionally - * (no branch penalty). - */ - - curOffset = (curOffset + 0x1f) & ~0x1f; - - if (texelBytes) { - t->image[0][i].x = curOffset; /* fix x and y coords up later together with offset */ - t->image[0][i].y = 0; - t->image[0][i].width = MIN2(size / texelBytes, blitWidth); - t->image[0][i].height = (size / texelBytes) / t->image[0][i].width; - } - else { - t->image[0][i].x = curOffset % BLIT_WIDTH_BYTES; - t->image[0][i].y = curOffset / BLIT_WIDTH_BYTES; - t->image[0][i].width = MIN2(size, BLIT_WIDTH_BYTES); - t->image[0][i].height = size / t->image[0][i].width; - } - -#if 0 - /* for debugging only and only applicable to non-rectangle targets */ - assert(size % t->image[0][i].width == 0); - assert(t->image[0][i].x == 0 - || (size < BLIT_WIDTH_BYTES && t->image[0][i].height == 1)); -#endif - - if (0) - fprintf(stderr, - "level %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n", - i, texImage->Width, texImage->Height, - t->image[0][i].x, t->image[0][i].y, - t->image[0][i].width, t->image[0][i].height, size, curOffset); - - curOffset += size; - - } - - /* Align the total size of texture memory block. - */ - t->base.totalSize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; - - /* Setup remaining cube face blits, if needed */ - if (tObj->Target == GL_TEXTURE_CUBE_MAP) { - const GLuint faceSize = t->base.totalSize; - GLuint face; - /* reuse face 0 x/y/width/height - just update the offset when uploading */ - for (face = 1; face < 6; face++) { - for (i = 0; i < numLevels; i++) { - t->image[face][i].x = t->image[0][i].x; - t->image[face][i].y = t->image[0][i].y; - t->image[face][i].width = t->image[0][i].width; - t->image[face][i].height = t->image[0][i].height; - } - } - t->base.totalSize = 6 * faceSize; /* total texmem needed */ - } - - - /* Hardware state: - */ - t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK; - t->pp_txfilter |= (numLevels - 1) << R200_MAX_MIP_LEVEL_SHIFT; - - t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK | - R200_TXFORMAT_HEIGHT_MASK | - R200_TXFORMAT_CUBIC_MAP_ENABLE | - R200_TXFORMAT_F5_WIDTH_MASK | - R200_TXFORMAT_F5_HEIGHT_MASK); - t->pp_txformat |= ((log2Width << R200_TXFORMAT_WIDTH_SHIFT) | - (log2Height << R200_TXFORMAT_HEIGHT_SHIFT)); - - t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK); - if (tObj->Target == GL_TEXTURE_3D) { - t->pp_txformat_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT); - t->pp_txformat_x |= R200_TEXCOORD_VOLUME; - } - else if (tObj->Target == GL_TEXTURE_CUBE_MAP) { - ASSERT(log2Width == log2Height); - t->pp_txformat |= ((log2Width << R200_TXFORMAT_F5_WIDTH_SHIFT) | - (log2Height << R200_TXFORMAT_F5_HEIGHT_SHIFT) | -/* don't think we need this bit, if it exists at all - fglrx does not set it */ - (R200_TXFORMAT_CUBIC_MAP_ENABLE)); - t->pp_txformat_x |= R200_TEXCOORD_CUBIC_ENV; - t->pp_cubic_faces = ((log2Width << R200_FACE_WIDTH_1_SHIFT) | - (log2Height << R200_FACE_HEIGHT_1_SHIFT) | - (log2Width << R200_FACE_WIDTH_2_SHIFT) | - (log2Height << R200_FACE_HEIGHT_2_SHIFT) | - (log2Width << R200_FACE_WIDTH_3_SHIFT) | - (log2Height << R200_FACE_HEIGHT_3_SHIFT) | - (log2Width << R200_FACE_WIDTH_4_SHIFT) | - (log2Height << R200_FACE_HEIGHT_4_SHIFT)); - } - else { - /* If we don't in fact send enough texture coordinates, q will be 1, - * making TEXCOORD_PROJ act like TEXCOORD_NONPROJ (Right?) - */ - t->pp_txformat_x |= R200_TEXCOORD_PROJ; - } - - t->pp_txsize = (((tObj->Image[0][t->base.firstLevel]->Width - 1) << 0) | - ((tObj->Image[0][t->base.firstLevel]->Height - 1) << 16)); - - /* Only need to round to nearest 32 for textures, but the blitter - * requires 64-byte aligned pitches, and we may/may not need the - * blitter. NPOT only! - */ - if ( !t->image_override ) { - if (baseImage->IsCompressed) - t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); - else - t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63); - t->pp_txpitch -= 32; - } - - t->dirty_state = R200_TEX_ALL; - - /* FYI: r200UploadTexImages( rmesa, t ) used to be called here */ -} -#endif - - /* ================================================================ * Texture combine functions */ diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c index 30dde809948..5019ee44322 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -79,133 +79,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define HW_UNLOCK() -static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - GLint nmacroblkpl; - GLint nmicroblkpl; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - nmacroblkpl = rrb->pitch >> 5; - offset += ((y >> 4) * nmacroblkpl) << 11; - offset += ((y & 15) >> 1) << 8; - offset += (y & 1) << 4; - offset += (x >> 5) << 11; - offset += ((x & 31) >> 2) << 5; - offset += (x & 3) << 2; - } else { - nmacroblkpl = rrb->pitch >> 6; - offset += ((y >> 3) * nmacroblkpl) << 11; - offset += (y & 7) << 8; - offset += (x >> 6) << 11; - offset += ((x & 63) >> 3) << 5; - offset += (x & 7) << 2; - } - } else { - nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; - offset += (y * nmicroblkpl) << 5; - offset += (x >> 3) << 5; - offset += (x & 7) << 2; - } - } - return &ptr[offset]; -} - -static GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - GLint nmacroblkpl; - GLint nmicroblkpl; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - nmacroblkpl = rrb->pitch >> 6; - offset += ((y >> 4) * nmacroblkpl) << 11; - offset += ((y & 15) >> 1) << 8; - offset += (y & 1) << 4; - offset += (x >> 6) << 11; - offset += ((x & 63) >> 3) << 5; - offset += (x & 7) << 1; - } else { - nmacroblkpl = rrb->pitch >> 7; - offset += ((y >> 3) * nmacroblkpl) << 11; - offset += (y & 7) << 8; - offset += (x >> 7) << 11; - offset += ((x & 127) >> 4) << 5; - offset += (x & 15) << 2; - } - } else { - nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; - offset += (y * nmicroblkpl) << 5; - offset += (x >> 4) << 5; - offset += (x & 15) << 2; - } - } - return &ptr[offset]; -} - -static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - GLint microblkxs; - GLint macroblkxs; - GLint nmacroblkpl; - GLint nmicroblkpl; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - microblkxs = 16 / rrb->cpp; - macroblkxs = 128 / rrb->cpp; - nmacroblkpl = rrb->pitch / macroblkxs; - offset += ((y >> 4) * nmacroblkpl) << 11; - offset += ((y & 15) >> 1) << 8; - offset += (y & 1) << 4; - offset += (x / macroblkxs) << 11; - offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; - offset += (x & (microblkxs - 1)) * rrb->cpp; - } else { - microblkxs = 32 / rrb->cpp; - macroblkxs = 256 / rrb->cpp; - nmacroblkpl = rrb->pitch / macroblkxs; - offset += ((y >> 3) * nmacroblkpl) << 11; - offset += (y & 7) << 8; - offset += (x / macroblkxs) << 11; - offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; - offset += (x & (microblkxs - 1)) * rrb->cpp; - } - } else { - microblkxs = 32 / rrb->cpp; - nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; - offset += (y * nmicroblkpl) << 5; - offset += (x / microblkxs) << 5; - offset += (x & (microblkxs - 1)) * rrb->cpp; - } - } - return &ptr[offset]; -} - /* ================================================================ * Color buffer */ @@ -345,96 +218,6 @@ do { \ #define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" -static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) -{ - struct radeon_renderbuffer *rrb = (void*)rb; - int r; - - if (rrb->bo) { - r = radeon_bo_map(rrb->bo, write); - if (r) { - fprintf(stderr, "(%s) error(%d) mapping buffer.\n", - __FUNCTION__, r); - } - } -} - -static void unmap_buffer(struct gl_renderbuffer *rb) -{ - struct radeon_renderbuffer *rrb = (void*)rb; - - if (rrb->bo) { - radeon_bo_unmap(rrb->bo); - } -} - -/* Move locking out to get reasonable span performance (10x better - * than doing this in HW_LOCK above). WaitForIdle() is the main - * culprit. - */ - -static void radeonSpanRenderStart(GLcontext * ctx) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - int i; -#ifdef COMPILE_R300 - r300ContextPtr r300 = (r300ContextPtr) rmesa; - R300_FIREVERTICES(r300); -#else - RADEON_FIREVERTICES(rmesa); -#endif - - for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) - ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); - } - - /* color draw buffers */ - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { - map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); - } - - map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); - - if (ctx->DrawBuffer->_DepthBuffer) { - map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); - } - if (ctx->DrawBuffer->_StencilBuffer) - map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); - - /* The locking and wait for idle should really only be needed in classic mode. - * In a future memory manager based implementation, this should become - * unnecessary due to the fact that mapping our buffers, textures, etc. - * should implicitly wait for any previous rendering commands that must - * be waited on. */ - LOCK_HARDWARE(rmesa); - radeonWaitForIdleLocked(rmesa); -} - -static void radeonSpanRenderFinish(GLcontext * ctx) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - int i; - _swrast_flush(ctx); - UNLOCK_HARDWARE(rmesa); - - for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) - ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); - } - - /* color draw buffers */ - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) - unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); - - unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); - - if (ctx->DrawBuffer->_DepthBuffer) - unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); - if (ctx->DrawBuffer->_StencilBuffer) - unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); -} - void radeonInitSpanFuncs(GLcontext * ctx) { struct swrast_device_driver *swdd = diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 94d2e6c8764..99ca936dae3 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2110,3 +2110,214 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t return GL_TRUE; } + + +GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + nmacroblkpl = rrb->pitch >> 5; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x >> 5) << 11; + offset += ((x & 31) >> 2) << 5; + offset += (x & 3) << 2; + } else { + nmacroblkpl = rrb->pitch >> 6; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x >> 6) << 11; + offset += ((x & 63) >> 3) << 5; + offset += (x & 7) << 2; + } + } else { + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x >> 3) << 5; + offset += (x & 7) << 2; + } + } + return &ptr[offset]; +} + +GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + nmacroblkpl = rrb->pitch >> 6; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x >> 6) << 11; + offset += ((x & 63) >> 3) << 5; + offset += (x & 7) << 1; + } else { + nmacroblkpl = rrb->pitch >> 7; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x >> 7) << 11; + offset += ((x & 127) >> 4) << 5; + offset += (x & 15) << 2; + } + } else { + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x >> 4) << 5; + offset += (x & 15) << 2; + } + } + return &ptr[offset]; +} + +GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint microblkxs; + GLint macroblkxs; + GLint nmacroblkpl; + GLint nmicroblkpl; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + microblkxs = 16 / rrb->cpp; + macroblkxs = 128 / rrb->cpp; + nmacroblkpl = rrb->pitch / macroblkxs; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x / macroblkxs) << 11; + offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } else { + microblkxs = 32 / rrb->cpp; + macroblkxs = 256 / rrb->cpp; + nmacroblkpl = rrb->pitch / macroblkxs; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x / macroblkxs) << 11; + offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } + } else { + microblkxs = 32 / rrb->cpp; + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } + } + return &ptr[offset]; +} + + +static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) +{ + struct radeon_renderbuffer *rrb = (void*)rb; + int r; + + if (rrb->bo) { + r = radeon_bo_map(rrb->bo, write); + if (r) { + fprintf(stderr, "(%s) error(%d) mapping buffer.\n", + __FUNCTION__, r); + } + } +} + +static void unmap_buffer(struct gl_renderbuffer *rb) +{ + struct radeon_renderbuffer *rrb = (void*)rb; + + if (rrb->bo) { + radeon_bo_unmap(rrb->bo); + } +} + +void radeonSpanRenderStart(GLcontext * ctx) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + int i; + + rmesa->vtbl.flush_vertices(rmesa); + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + + /* color draw buffers */ + for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { + map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); + } + + map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); + + if (ctx->DrawBuffer->_DepthBuffer) { + map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); + } + if (ctx->DrawBuffer->_StencilBuffer) + map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); + + /* The locking and wait for idle should really only be needed in classic mode. + * In a future memory manager based implementation, this should become + * unnecessary due to the fact that mapping our buffers, textures, etc. + * should implicitly wait for any previous rendering commands that must + * be waited on. */ + LOCK_HARDWARE(rmesa); + radeonWaitForIdleLocked(rmesa); +} + +void radeonSpanRenderFinish(GLcontext * ctx) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + int i; + _swrast_flush(ctx); + UNLOCK_HARDWARE(rmesa); + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + + /* color draw buffers */ + for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) + unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); + + unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); + + if (ctx->DrawBuffer->_DepthBuffer) + unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); + if (ctx->DrawBuffer->_StencilBuffer) + unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); +} + diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 470a3fd5a72..aeff52a66e1 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -110,5 +110,12 @@ void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage); - +void radeonSpanRenderStart(GLcontext * ctx); +void radeonSpanRenderFinish(GLcontext * ctx); +GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, + GLint x, GLint y); +GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, + GLint x, GLint y); +GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, + GLint x, GLint y); #endif -- cgit v1.2.3 From 7d01cb37d94b8966fa089106b902325dbef33a58 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 00:17:38 +1000 Subject: r200: emit elts into a separate ELT bo --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 209 ++++++++------------------ src/mesa/drivers/dri/r200/r200_context.h | 7 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 249 +------------------------------ src/mesa/drivers/dri/r200/r200_ioctl.h | 3 +- src/mesa/drivers/dri/r200/r200_pixel.c | 10 +- src/mesa/drivers/dri/r200/r200_tcl.c | 19 ++- 6 files changed, 89 insertions(+), 408 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 6d421f5d5ec..5768f39e5c1 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -238,40 +238,61 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); END_BATCH(); -#if 0 - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ, - __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2; - cmd[2].i = (primitive | - R200_VF_PRIM_WALK_LIST | - R200_VF_COLOR_ORDER_RGBA | - (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); -#endif } +static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) +{ + BATCH_LOCALS(&rmesa->radeon); + + if (vertex_count > 0) { + BEGIN_BATCH(8); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0); + OUT_BATCH(R200_VF_PRIM_WALK_IND | + ((vertex_count + 0) << 16) | + type); + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); + OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); + OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset, + rmesa->tcl.elt_dma_bo, + rmesa->tcl.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(vertex_count/2); + } else { + OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); + OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); + OUT_BATCH(rmesa->tcl.elt_dma_offset); + OUT_BATCH(vertex_count/2); + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0, 0); + } + END_BATCH(); + } +} -void r200FlushElts( GLcontext *ctx ) +void r200FlushElts( r200ContextPtr rmesa ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start); int dwords; - int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2; + int nr, elt_used = rmesa->tcl.elt_used; if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); + fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used); - assert( rmesa->dma.flush == r200FlushElts ); - rmesa->dma.flush = NULL; + assert( rmesa->tcl.flush == r200FlushElts ); + rmesa->tcl.flush = NULL; - /* Cope with odd number of elts: - */ - rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; - dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; + elt_used = (elt_used + 2) & ~2; - cmd[1] |= (dwords - 3) << 16; - cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT; + nr = elt_used / 2; + + radeon_bo_unmap(rmesa->tcl.elt_dma_bo); + + r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); + + radeon_bo_unref(rmesa->tcl.elt_dma_bo); + rmesa->tcl.elt_dma_bo = NULL; if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); @@ -284,7 +305,6 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, GLuint min_nr ) { - drm_radeon_cmd_header_t *cmd; GLushort *retval; if (R200_DEBUG & DEBUG_IOCTL) @@ -293,29 +313,24 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, assert((primitive & R200_VF_PRIM_WALK_IND)); r200EmitState( rmesa ); - - // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), - // __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2; - cmd[2].i = (primitive | - R200_VF_PRIM_WALK_IND | - R200_VF_COLOR_ORDER_RGBA); + rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, R200_ELT_BUF_SZ, 4, + RADEON_GEM_DOMAIN_GTT, 0); + rmesa->tcl.elt_dma_offset = 0; + rmesa->tcl.elt_used = min_nr * 2; + + radeon_bo_map(rmesa->tcl.elt_dma_bo, 1); + retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; - retval = (GLushort *)(cmd+3); if (R200_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: header 0x%x prim %x \n", - __FUNCTION__, - cmd[1].i, primitive); + fprintf(stderr, "%s: header prim %x \n", + __FUNCTION__, primitive); - assert(!rmesa->dma.flush); + assert(!rmesa->tcl.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = r200FlushElts; - - rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; + rmesa->tcl.flush = r200FlushElts; return retval; } @@ -439,112 +454,14 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) } END_BATCH(); } - -#if 0 -void r200EmitAOS( r200ContextPtr rmesa, - struct radeon_dma_region **component, - GLuint nr, - GLuint offset ) -{ - drm_radeon_cmd_header_t *cmd; - int sz = AOS_BUFSZ(nr); - int i; - int *tmp; - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr); - - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz, __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (((sz / sizeof(int)) - 3) << 16); - cmd[2].i = nr; - tmp = &cmd[0].i; - cmd += 3; - - for (i = 0 ; i < nr ; i++) { - if (i & 1) { - cmd[0].i |= ((component[i]->aos_stride << 24) | - (component[i]->aos_size << 16)); - cmd[2].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - cmd += 3; - } - else { - cmd[0].i = ((component[i]->aos_stride << 8) | - (component[i]->aos_size << 0)); - cmd[1].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - } - } - - if (R200_DEBUG & DEBUG_VERTS) { - fprintf(stderr, "%s:\n", __FUNCTION__); - for (i = 0 ; i < sz ; i++) - fprintf(stderr, " %d: %x\n", i, tmp[i]); - } -} -#endif - -void r200EmitBlit( r200ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, - GLuint w, GLuint h ) +void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type) { - drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n", - __FUNCTION__, - src_pitch, src_offset, srcx, srcy, - dst_pitch, dst_offset, dstx, dsty, - w, h); - - assert( (src_pitch & 63) == 0 ); - assert( (dst_pitch & 63) == 0 ); - assert( (src_offset & 1023) == 0 ); - assert( (dst_offset & 1023) == 0 ); - assert( w < (1<<16) ); - assert( h < (1<<16) ); - - // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), - // __FUNCTION__ ); - - - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16); - cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); - - cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10); - cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10); - cmd[5].i = (srcx << 16) | srcy; - cmd[6].i = (dstx << 16) | dsty; /* dst */ - cmd[7].i = (w << 16) | h; + BEGIN_BATCH(3); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type); + END_BATCH(); } - -void r200EmitWait( r200ContextPtr rmesa, GLuint flags ) -{ - drm_radeon_cmd_header_t *cmd; - - assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); - - // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), - // __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].wait.cmd_type = RADEON_CMD_WAIT; - cmd[0].wait.flags = flags; -} diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 2725dc495f6..607997fafc9 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -531,7 +531,7 @@ struct r200_state { #define R200_CMD_BUF_SZ (16*1024) - +#define R200_ELT_BUF_SZ (16*1024) /* r200_tcl.c */ struct r200_tcl_info { @@ -544,6 +544,11 @@ struct r200_tcl_info { GLuint *Elts; + struct radeon_bo *elt_dma_bo; + int elt_dma_offset; /** Offset into this buffer object, in bytes */ + int elt_used; + + void (*flush) (r200ContextPtr); struct radeon_dma_region vertex_data[15]; }; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 1fbbbfbb569..65786be96cb 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -85,252 +85,6 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) rmesa->store = saved_store; } -#if 0 -int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) -{ - int ret, i; - drm_radeon_cmd_buffer_t cmd; - - if (rmesa->radeon.lost_context) - r200BackUpAndEmitLostStateLocked( rmesa ); - - if (R200_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (0 & R200_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < rmesa->store.cmd_used ; i += 4 ) - fprintf(stderr, "%d: %x\n", i/4, - *(int *)(&rmesa->store.cmd_buf[i])); - } - - if (R200_DEBUG & DEBUG_DMA) - fprintf(stderr, "%s: Releasing %d buffers\n", __FUNCTION__, - rmesa->dma.nr_released_bufs); - - - if (R200_DEBUG & DEBUG_SANITY) { - if (rmesa->radeon.state.scissor.enabled) - ret = r200SanityCmdBuffer( rmesa, - rmesa->radeon.state.scissor.numClipRects, - rmesa->radeon.state.scissor.pClipRects); - else - ret = r200SanityCmdBuffer( rmesa, - rmesa->radeon.numClipRects, - rmesa->radeon.pClipRects); - if (ret) { - fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); - goto out; - } - } - - - if (R200_DEBUG & DEBUG_MEMORY) { - if (! driValidateTextureHeaps( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, - & rmesa->radeon.swapped ) ) { - fprintf( stderr, "%s: texture memory is inconsistent - expect " - "mangled textures\n", __FUNCTION__ ); - } - } - - - cmd.bufsz = rmesa->store.cmd_used; - cmd.buf = rmesa->store.cmd_buf; - - if (rmesa->radeon.state.scissor.enabled) { - cmd.nbox = rmesa->radeon.state.scissor.numClipRects; - cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.state.scissor.pClipRects; - } else { - cmd.nbox = rmesa->radeon.numClipRects; - cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects; - } - - ret = drmCommandWrite( rmesa->radeon.dri.fd, - DRM_RADEON_CMDBUF, - &cmd, sizeof(cmd) ); - - if (ret) - fprintf(stderr, "drmCommandWrite: %d\n", ret); - - if (R200_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__); - radeonWaitForIdleLocked( &rmesa->radeon ); - } - - - out: - rmesa->store.primnr = 0; - rmesa->store.statenr = 0; - rmesa->store.cmd_used = 0; - rmesa->dma.nr_released_bufs = 0; - rmesa->save_on_next_emit = 1; - - return ret; -} - -/* Note: does not emit any commands to avoid recursion on - * r200AllocCmdBuf. - */ -void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) -{ - int ret; - - LOCK_HARDWARE( &rmesa->radeon ); - - ret = rcommonFlushCmdBufLocked( rmesa, caller ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if (ret) { - fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret); - exit(ret); - } -} -#endif - - -/* ============================================================= - * Hardware vertex buffer handling - */ - -#if 0 -void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) -{ - struct radeon_dma_buffer *dmabuf; - int fd = rmesa->radeon.dri.fd; - int index = 0; - int size = 0; - drmDMAReq dma; - int ret; - - if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) { - rmesa->dma.flush( rmesa->radeon.glCtx ); - } - - if (rmesa->dma.current.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - - if (rmesa->dma.nr_released_bufs > 4) - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - - dma.context = rmesa->radeon.dri.hwContext; - dma.send_count = 0; - dma.send_list = NULL; - dma.send_sizes = NULL; - dma.flags = 0; - dma.request_count = 1; - dma.request_size = RADEON_BUFFER_SIZE; - dma.request_list = &index; - dma.request_sizes = &size; - dma.granted_count = 0; - - LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ - - while (1) { - ret = drmDMA( fd, &dma ); - if (ret == 0) - break; - - if (rmesa->dma.nr_released_bufs) { - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - } - - if (rmesa->radeon.do_usleeps) { - UNLOCK_HARDWARE( &rmesa->radeon ); - DO_USLEEP( 1 ); - LOCK_HARDWARE( &rmesa->radeon ); - } - } - - UNLOCK_HARDWARE(&rmesa->radeon); - - if (R200_DEBUG & DEBUG_DMA) - fprintf(stderr, "Allocated buffer %d\n", index); - - dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); - dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index]; - dmabuf->refcount = 1; - - rmesa->dma.current.buf = dmabuf; - rmesa->dma.current.address = dmabuf->buf->address; - rmesa->dma.current.end = dmabuf->buf->total; - rmesa->dma.current.start = 0; - rmesa->dma.current.ptr = 0; -} - -void r200ReleaseDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ) -{ - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (!region->buf) - return; - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); - - if (--region->buf->refcount == 0) { - drm_radeon_cmd_header_t *cmd; - - if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, - region->buf->buf->idx); - - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sizeof(*cmd), - __FUNCTION__ ); - cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD; - cmd->dma.buf_idx = region->buf->buf->idx; - FREE(region->buf); - rmesa->dma.nr_released_bufs++; - } - - region->buf = NULL; - region->start = 0; -} - -/* Allocates a region from rmesa->dma.current. If there isn't enough - * space in current, grab a new buffer (and discard what was left of current) - */ -void r200AllocDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - int bytes, - int alignment ) -{ - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); - - if (region->buf) - r200ReleaseDmaRegion( rmesa, region, __FUNCTION__ ); - - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; - - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - r200RefillCurrentDmaRegion( rmesa ); - - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; - region->address = rmesa->dma.current.address; - region->buf = rmesa->dma.current.buf; - region->buf->refcount++; - - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; - - assert( rmesa->dma.current.ptr <= rmesa->dma.current.end ); -} -#endif - /* ================================================================ * Buffer clear */ @@ -526,6 +280,9 @@ void r200Flush( GLcontext *ctx ) if (rmesa->dma.flush) rmesa->dma.flush( ctx ); + if (rmesa->tcl.flush) + rmesa->tcl.flush( rmesa ); + r200EmitState( rmesa ); if (rmesa->radeon.cmdbuf.cs->cdw) diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 1ae0dd114b5..e3f0b66514d 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -53,7 +53,8 @@ extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ); -extern void r200FlushElts(GLcontext *ctx); +extern void r200FlushElts(r200ContextPtr rmesa); + extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 930d797f45c..eefa2a1e11a 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -156,6 +156,8 @@ r200TryReadPixels( GLcontext *ctx, GLuint cpp = rmesa->radeon.radeonScreen->cpp; GLint size = width * height * cpp; + return GL_FALSE; +#if 0 if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -165,7 +167,6 @@ r200TryReadPixels( GLcontext *ctx, pitch * height * rmesa->radeon.radeonScreen->cpp ) ) { if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: dest not GART\n", __FUNCTION__); - return GL_FALSE; } /* Need GL_PACK_INVERT_MESA to cope with upsidedown results from @@ -262,7 +263,7 @@ r200TryReadPixels( GLcontext *ctx, UNLOCK_HARDWARE( &rmesa->radeon ); r200Finish( ctx ); /* required by GL */ - +#endif return GL_TRUE; } @@ -305,7 +306,7 @@ static void do_draw_pix( GLcontext *ctx, if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); - +#if 0 switch ( rmesa->radeon.radeonScreen->cpp ) { case 2: blit_format = R200_CP_COLOR_FORMAT_RGB565; @@ -366,6 +367,7 @@ static void do_draw_pix( GLcontext *ctx, rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */ UNLOCK_HARDWARE( &rmesa->radeon ); +#endif } @@ -431,7 +433,7 @@ r200TryDrawPixels( GLcontext *ctx, return GL_FALSE; } - if ( r200IsGartMemory(rmesa, pixels, size) ) + if (0)// r200IsGartMemory(rmesa, pixels, size) ) { do_draw_pix( ctx, x, y, width, height, pitch, pixels, planemask ); return GL_TRUE; diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 0f15fd457e5..891a942e387 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,23 +142,22 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { - fprintf(stderr,"alloc elts\n"); - if (rmesa->dma.flush == r200FlushElts && - rmesa->store.cmd_used + nr*2 < R200_CMD_BUF_SZ) { + fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); + if (rmesa->tcl.flush == r200FlushElts && + rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - GLushort *dest = (GLushort *)(rmesa->store.cmd_buf + - rmesa->store.cmd_used); + GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + + rmesa->tcl.elt_used); - rmesa->store.cmd_used += nr*2; + rmesa->tcl.elt_used += nr*2; return dest; } else { - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if (rmesa->tcl.flush) + rmesa->tcl.flush( rmesa ); - rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); + rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, 0 ); -- cgit v1.2.3 From 4ca76586c23200b66cb4f85afb21ea02853779ea Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 00:23:10 +1000 Subject: r200: disable some debug --- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 7f7ae2ba792..bcdc4336abd 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -223,7 +223,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) GLuint count = VB->Count; GLuint i, emitsize; - fprintf(stderr,"emit arrays\n"); + // fprintf(stderr,"emit arrays\n"); for ( i = 0; i < 15; i++ ) { GLubyte attrib = vimap_rev[i]; if (attrib != 255) { diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 891a942e387..10c0dacd30e 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,7 +142,7 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { - fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); + // fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); if (rmesa->tcl.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { @@ -187,7 +187,7 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); + // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + VBUF_BUFSZ ); -- cgit v1.2.3 From 014c52eb6bc2fc0edb69d1ef063eb6c9735b3833 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 02:47:15 +1000 Subject: radeon: add r100/r200 workarounds for legacy aging --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 19 +++++++++++-------- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 10 +++++++++- 2 files changed, 20 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index e378b118e0e..32b452d6363 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -163,14 +163,17 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml) drm_radeon_getparam_t gp; int r; - gp.param = RADEON_PARAM_LAST_CLEAR; - gp.value = (int *)&boml->current_age; - r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp)); - if (r) { - fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); - exit(1); - } + if (IS_R300_CLASS(boml->screen)) { + gp.param = RADEON_PARAM_LAST_CLEAR; + gp.value = (int *)&boml->current_age; + r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (r) { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); + exit(1); + } + } else + boml->current_age = boml->screen->scratch[3]; } static int legacy_is_pending(struct radeon_bo *bo) diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index af9ee4df472..3a3a245d798 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -317,12 +317,20 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } - dump_cmdbuf(cs); + // dump_cmdbuf(cs); r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { return r; } + if (!IS_R300_CLASS(csm->ctx->radeonScreen)) { + drm_radeon_irq_emit_t emit_cmd; + emit_cmd.irq_seq = &csm->pending_age; + r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd)); + if (r) { + return r; + } + } cs_set_age(cs); return 0; } -- cgit v1.2.3 From 11995807f1d83e29e4517c6ae5449cd702f33835 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:12:54 +1000 Subject: radeon: fix counting for cfree handles in an inline --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 32b452d6363..c4026be9712 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -93,6 +93,13 @@ static void bo_legacy_tobj_destroy(void *data, driTextureObject *t) bo_legacy->validated = 0; } +static void inline clean_handles(struct bo_manager_legacy *bom) +{ + while (bom->cfree_handles > 0 && + !bom->free_handles[bom->cfree_handles - 1]) + bom->cfree_handles--; + +} static int legacy_new_handle(struct bo_manager_legacy *bom, uint32_t *handle) { uint32_t tmp; @@ -103,12 +110,7 @@ static int legacy_new_handle(struct bo_manager_legacy *bom, uint32_t *handle) } if (bom->cfree_handles > 0) { tmp = bom->free_handles[--bom->cfree_handles]; - while (!bom->free_handles[bom->cfree_handles - 1]) { - bom->cfree_handles--; - if (bom->cfree_handles <= 0) { - bom->cfree_handles = 0; - } - } + clean_handles(bom); } else { bom->cfree_handles = 0; tmp = bom->nhandle++; @@ -135,12 +137,7 @@ static int legacy_free_handle(struct bo_manager_legacy *bom, uint32_t handle) bom->free_handles[i] = 0; } } - while (!bom->free_handles[bom->cfree_handles - 1]) { - bom->cfree_handles--; - if (bom->cfree_handles <= 0) { - bom->cfree_handles = 0; - } - } + clean_handles(bom); return 0; } if (bom->cfree_handles < bom->nfree_handles) { -- cgit v1.2.3 From a5b54eb3c99aedf92197c834a6645127a231b382 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:19:56 +1000 Subject: radeon: cleanup bo unref codepath in pending code assert for bad case hopefully --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index c4026be9712..353f00100a0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -190,10 +190,14 @@ static int legacy_is_pending(struct radeon_bo *bo) if (bo_legacy->pnext) { bo_legacy->pnext->pprev = bo_legacy->pprev; } + assert(bo_legacy->is_pending <= bo->cref); while (bo_legacy->is_pending--) { - radeon_bo_unref(bo); + bo = radeon_bo_unref(bo); + if (!bo) + break; } - bo_legacy->is_pending = 0; + if (bo) + bo_legacy->is_pending = 0; boml->cpendings--; return 0; } @@ -580,7 +584,7 @@ void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending) struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; bo_legacy->pending = pending; - bo_legacy->is_pending += 1; + bo_legacy->is_pending++; /* add to pending list */ radeon_bo_ref(bo); if (bo_legacy->is_pending > 1) { -- cgit v1.2.3 From bb7756eaed7b6c51a2da2ed9905b79172be91881 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:29:22 +1000 Subject: radeon: free indices caught with valgrind --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 3a3a245d798..0d0ea364028 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -337,6 +337,7 @@ static int cs_emit(struct radeon_cs *cs) static int cs_destroy(struct radeon_cs *cs) { + free(cs->relocs->indices); free(cs->relocs); free(cs->packets); free(cs); -- cgit v1.2.3 From c66e38d24fa8ffa2ac759ce118cb779fbce117d4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:31:06 +1000 Subject: radeon: fix reloc free harder --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 0d0ea364028..ef59dd1f5c8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -337,7 +337,9 @@ static int cs_emit(struct radeon_cs *cs) static int cs_destroy(struct radeon_cs *cs) { - free(cs->relocs->indices); + struct cs_reloc_legacy *relocs; + relocs = cs->relocs; + free(relocs->indices); free(cs->relocs); free(cs->packets); free(cs); -- cgit v1.2.3 From 2c8b55b351c84cda4e620a5aba3e67c110890567 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:35:58 +1000 Subject: radeon: fix relocs even more --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index ef59dd1f5c8..f09031e83bb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -335,11 +335,15 @@ static int cs_emit(struct radeon_cs *cs) return 0; } +static void inline cs_free_reloc(void *relocs_p) +{ + struct cs_reloc_legacy *relocs = relocs_p; + free(relocs->indices); +} + static int cs_destroy(struct radeon_cs *cs) { - struct cs_reloc_legacy *relocs; - relocs = cs->relocs; - free(relocs->indices); + cs_free_reloc(cs->relocs); free(cs->relocs); free(cs->packets); free(cs); @@ -348,6 +352,7 @@ static int cs_destroy(struct radeon_cs *cs) static int cs_erase(struct radeon_cs *cs) { + cs_free_reloc(cs->relocs); free(cs->relocs); cs->relocs_total_size = 0; cs->relocs = NULL; -- cgit v1.2.3 From 02952a41eb0e47ab77a984922c1c3202aeb45b50 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:38:35 +1000 Subject: radeon: check relocs before deref --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index f09031e83bb..b9751248280 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -337,8 +337,9 @@ static int cs_emit(struct radeon_cs *cs) static void inline cs_free_reloc(void *relocs_p) { - struct cs_reloc_legacy *relocs = relocs_p; - free(relocs->indices); + struct cs_reloc_legacy *relocs = relocs_p; + if (relocs) + free(relocs->indices); } static int cs_destroy(struct radeon_cs *cs) -- cgit v1.2.3 From 860d0cc656ee0eb724b2d82596c09a9eee9a8d19 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:47:38 +1000 Subject: radeon: free all relocs in array --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index b9751248280..1f07c1c6c4f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -135,7 +135,7 @@ static int cs_write_reloc(struct radeon_cs *cs, relocs[i].base.read_domain |= read_domain; relocs[i].base.write_domain |= write_domain; /* save indice */ - relocs[i].cindices += 1; + relocs[i].cindices++; indices = (uint32_t*)realloc(relocs[i].indices, relocs[i].cindices * 4); if (indices == NULL) { @@ -335,16 +335,21 @@ static int cs_emit(struct radeon_cs *cs) return 0; } -static void inline cs_free_reloc(void *relocs_p) +static void inline cs_free_reloc(void *relocs_p, int crelocs) { struct cs_reloc_legacy *relocs = relocs_p; - if (relocs) - free(relocs->indices); + int i; + + for (i = 0; i < crelocs; i++) { + struct cs_reloc_legacy *ptr = relocs[i]; + if (ptr) + free(ptr->indices); + } } static int cs_destroy(struct radeon_cs *cs) { - cs_free_reloc(cs->relocs); + cs_free_reloc(cs->relocs, cs->crelocs); free(cs->relocs); free(cs->packets); free(cs); @@ -353,7 +358,7 @@ static int cs_destroy(struct radeon_cs *cs) static int cs_erase(struct radeon_cs *cs) { - cs_free_reloc(cs->relocs); + cs_free_reloc(cs->relocs, cs->crelocs); free(cs->relocs); cs->relocs_total_size = 0; cs->relocs = NULL; -- cgit v1.2.3 From 8b56a86385f3411f0d1ba64423f32bff6c60416d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 21:49:58 +1000 Subject: radeon: better free of array --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 1f07c1c6c4f..f542ee041f8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -339,11 +339,10 @@ static void inline cs_free_reloc(void *relocs_p, int crelocs) { struct cs_reloc_legacy *relocs = relocs_p; int i; - + if (relocs_p) + return; for (i = 0; i < crelocs; i++) { - struct cs_reloc_legacy *ptr = relocs[i]; - if (ptr) - free(ptr->indices); + free(relocs[i].indices); } } -- cgit v1.2.3 From 9780127449c6b32cc16ee1a1589c1e28eae1d7bb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 07:34:45 +1000 Subject: radeon: remove some debugging --- src/mesa/drivers/dri/r200/r200_state_init.c | 7 ------- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 2 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 2 -- 3 files changed, 1 insertion(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 26d89432bf0..864fe344b27 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -363,15 +363,8 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) radeonTexObj *t = r200->state.texture.unit[i].texobj; BEGIN_BATCH_NO_AUTOSTATE(dwords); - fprintf(stderr,"atom state is %x, %x %x %x %x %x\n", atom->cmd[0], - atom->cmd[1], - atom->cmd[2], - atom->cmd[3], - atom->cmd[4], - atom->cmd[5]); OUT_BATCH_TABLE(atom->cmd, 10); if (t && !t->image_override) { - fprintf(stderr,"emitting reloc for %d\n", i); OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index d6fa50a0290..e5d524f104a 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -50,7 +50,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, */ #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ do { \ - if (offset) {\ + if (0 && offset) {\ fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ __FILE__, __FUNCTION__, __LINE__, offset);\ }\ diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index f542ee041f8..714d2628124 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -234,8 +234,6 @@ static int cs_process_relocs(struct radeon_cs *cs) relocs[i].base.bo, soffset, eoffset); return r; } - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", - relocs[i].base.bo, soffset, eoffset); cs->packets[relocs[i].indices[j]] += soffset; if (cs->packets[relocs[i].indices[j]] >= eoffset) { radeon_bo_debug(relocs[i].base.bo, 12); -- cgit v1.2.3 From d93dc4338279c03b8fa2b0adec01dedae4fe4895 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 08:08:34 +1000 Subject: radeon: plug memory leak running gears --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 714d2628124..a95d27c05e6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -337,11 +337,10 @@ static void inline cs_free_reloc(void *relocs_p, int crelocs) { struct cs_reloc_legacy *relocs = relocs_p; int i; - if (relocs_p) + if (!relocs_p) return; - for (i = 0; i < crelocs; i++) { + for (i = 0; i < crelocs; i++) free(relocs[i].indices); - } } static int cs_destroy(struct radeon_cs *cs) -- cgit v1.2.3 From f69e2f42d53337702ce52173a58a49e53bfdee56 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 22:49:16 +1000 Subject: r200: fix up swtcl/tcl flushes --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 3 ++- src/mesa/drivers/dri/r200/r200_context.h | 4 ++-- src/mesa/drivers/dri/r200/r200_ioctl.c | 6 +++--- src/mesa/drivers/dri/r200/r200_ioctl.h | 9 ++++----- src/mesa/drivers/dri/r200/r200_swtcl.c | 6 +----- src/mesa/drivers/dri/r200/r200_tcl.c | 8 ++++---- 6 files changed, 16 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 5768f39e5c1..fb8dddad3fa 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -272,8 +272,9 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) } } -void r200FlushElts( r200ContextPtr rmesa ) +void r200FlushElts(GLcontext *ctx) { + r200ContextPtr rmesa = R200_CONTEXT(ctx); int dwords; int nr, elt_used = rmesa->tcl.elt_used; diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 607997fafc9..62847be522e 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -548,7 +548,7 @@ struct r200_tcl_info { int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; - void (*flush) (r200ContextPtr); + void (*flush) (GLcontext *ctx); struct radeon_dma_region vertex_data[15]; }; @@ -606,7 +606,7 @@ struct r200_swtcl_info { GLboolean needproj; struct radeon_bo *bo; - void (*flush) (r200ContextPtr); + void (*flush) (GLcontext *ctx); }; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 65786be96cb..744a2d8a4fd 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -277,11 +277,11 @@ void r200Flush( GLcontext *ctx ) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->dma.flush) - rmesa->dma.flush( ctx ); + if (rmesa->swtcl.flush) + rmesa->swtcl.flush( ctx ); if (rmesa->tcl.flush) - rmesa->tcl.flush( rmesa ); + rmesa->tcl.flush( ctx ); r200EmitState( rmesa ); diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index e3f0b66514d..ccc15c5b49d 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -53,8 +53,7 @@ extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ); -extern void r200FlushElts(r200ContextPtr rmesa); - +extern void r200FlushElts(GLcontext *ctx); extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, @@ -113,8 +112,8 @@ void r200SetUpAtomList( r200ContextPtr rmesa ); */ #define R200_NEWPRIM( rmesa ) \ do { \ - if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa->radeon.glCtx ); \ + if ( rmesa->swtcl.flush ) \ + rmesa->swtcl.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -154,7 +153,7 @@ static INLINE int R200_DB_STATECHANGE( */ #define R200_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->store.cmd_used || rmesa->dma.flush ) { \ + if ( rmesa->swtcl.flush || rmesa->tcl.flush ) { \ r200Flush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 7275886f846..663e4ae0bc6 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -210,10 +210,6 @@ static void r200RenderStart( GLcontext *ctx ) r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200SetVertexFormat( ctx ); - - if (rmesa->dma.flush != 0 && - rmesa->dma.flush != flush_last_swtcl_prim) - rmesa->dma.flush( ctx ); } @@ -283,7 +279,7 @@ static void flush_last_swtcl_prim(GLcontext *ctx) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - rmesa->dma.flush = NULL; + rmesa->swtcl.flush = NULL; radeon_bo_unmap(rmesa->swtcl.bo); rcommonEnsureCmdBufSpace(rmesa, diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 10c0dacd30e..9562c8b315f 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -155,7 +155,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) } else { if (rmesa->tcl.flush) - rmesa->tcl.flush( rmesa ); + rmesa->tcl.flush( rmesa->radeon.glCtx ); rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); @@ -564,10 +564,10 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; - if ( rmesa->dma.flush ) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if ( rmesa->swtcl.flush ) + rmesa->swtcl.flush( rmesa->radeon.glCtx ); - rmesa->dma.flush = NULL; + rmesa->swtcl.flush = NULL; R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; -- cgit v1.2.3 From ab6edc9dce3ee0c63037c155a40d97a868c19341 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:01:21 +1000 Subject: radeon: add repeated register packet one --- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index e5d524f104a..b4ed153d263 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -16,6 +16,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, #define CP_PACKET2 (2 << 30) #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) +#define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) #define CP_PACKET3( pkt, n ) \ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) -- cgit v1.2.3 From 31a112e6e81246944bc96b8d095960dd0f96c83c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:01:41 +1000 Subject: r200: avoid setting variable on kernel mm setup --- src/mesa/drivers/dri/r200/r200_context.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index d8e28cd7531..9f1edd39d3d 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -365,7 +365,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, } - rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; + if (!rmesa->radeon.radeonScreen->kernel_mm) + rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); make_empty_list( & rmesa->radeon.swapped ); -- cgit v1.2.3 From 474d282a1d5435e7b5de40538d65f54e32ce4713 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:02:43 +1000 Subject: r200: re-write state handlers for new CS mechanism --- src/mesa/drivers/dri/r200/r200_reg.h | 3 + src/mesa/drivers/dri/r200/r200_state_init.c | 384 ++++++++++++++++++++++------ 2 files changed, 302 insertions(+), 85 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h index a8b0ae7e29d..526a624b697 100644 --- a/src/mesa/drivers/dri/r200/r200_reg.h +++ b/src/mesa/drivers/dri/r200/r200_reg.h @@ -463,8 +463,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_VSC_UPDATE_USER_COLOR_1_ENABLE 0x00020000 /* gap */ #define R200_SE_TCL_VECTOR_INDX_REG 0x2200 +# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 +# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 #define R200_SE_TCL_VECTOR_DATA_REG 0x2204 #define R200_SE_TCL_SCALAR_INDX_REG 0x2208 +# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 #define R200_SE_TCL_SCALAR_DATA_REG 0x220c /* gap */ #define R200_SE_TCL_MATRIX_SEL_0 0x2230 diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 864fe344b27..1e904ea4321 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -185,12 +185,17 @@ void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) fprintf(stderr, "\n"); } -static int cmdpkt( int id ) +static int cmdpkt( r200ContextPtr rmesa, int id ) { drm_radeon_cmd_header_t h; - h.i = 0; - h.packet.cmd_type = RADEON_CMD_PACKET; - h.packet.packet_id = id; + + if (rmesa->radeon.radeonScreen->kernel_mm) { + return CP_PACKET0(packet[id].start, packet[id].len - 1); + } else { + h.i = 0; + h.packet.cmd_type = RADEON_CMD_PACKET; + h.packet.packet_id = id; + } return h.i; } @@ -292,6 +297,117 @@ VP_CHECK( tcl_vp, GL_TRUE ) VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 ) VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 ) +#define OUT_VEC(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + h.i = hdr; \ + OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ + OUT_BATCH(0); \ + OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ + OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ + OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ + OUT_BATCH_TABLE((data), h.vectors.count); \ + } while(0) + +#define OUT_VECLINEAR(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ + uint32_t _sz = h.veclinear.count * 4; \ + h.i = hdr; \ + OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ + OUT_BATCH(0); \ + OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ + OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ + OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \ + OUT_BATCH_TABLE((data), _sz); \ + } while(0) + +#define OUT_SCL(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + h.i = hdr; \ + OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ + OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ + OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ + OUT_BATCH_TABLE((data), h.scalars.count); \ + } while(0) + +#define OUT_SCL2(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + h.i = hdr; \ + OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ + OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ + OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ + OUT_BATCH_TABLE((data), h.scalars.count); \ + } while(0) + +static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); + OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); + END_BATCH(); +} + +static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); + OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); + END_BATCH(); +} + +static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); + OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); + END_BATCH(); +} + +static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); + END_BATCH(); +} + +static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_SCL(atom->cmd[0], atom->cmd+1); + END_BATCH(); +} + + +static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VEC(atom->cmd[0], atom->cmd+1); + END_BATCH(); +} static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) { @@ -309,8 +425,8 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) rrb = r200->radeon.state.depth.rrb; if (!rrb) { - OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]); - OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]); + OUT_BATCH(0); + OUT_BATCH(0); } else { zbpitch = (rrb->pitch / rrb->cpp); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); @@ -351,7 +467,74 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH_TABLE((atom->cmd + 14), 4); END_BATCH(); - +} + +static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + struct radeon_renderbuffer *rrb, *drb; + uint32_t cbpitch = 0; + uint32_t zbpitch = 0; + uint32_t dwords = atom->cmd_size; + GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; + + rrb = r200->radeon.state.color.rrb; + if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (rrb) { + assert(rrb->bo != NULL); + cbpitch = (rrb->pitch / rrb->cpp); + if (r200->radeon.sarea->tiling_enabled) + cbpitch |= R200_COLOR_TILE_ENABLE; + } + + drb = r200->radeon.state.depth.rrb; + if (drb) + zbpitch = (drb->pitch / drb->cpp); + + /* output the first 7 bytes of context */ + BEGIN_BATCH_NO_AUTOSTATE(dwords); + + /* In the CS case we need to split this up */ + OUT_BATCH(CP_PACKET0(packet[0].start, 3)); + OUT_BATCH_TABLE((atom->cmd + 1), 4); + + if (drb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); + OUT_BATCH(zbpitch); + } + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); + OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); + OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); + OUT_BATCH(atom->cmd[CTX_PP_CNTL]); + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + + + if (rrb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + } + + if (rrb) { + if (rrb->cpp == 4) + ; + else + ; + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); + OUT_BATCH(cbpitch); + } + + if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { + OUT_BATCH_TABLE((atom->cmd + 14), 4); + } + + END_BATCH(); } static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) @@ -488,7 +671,10 @@ void r200InitState( r200ContextPtr rmesa ) else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); - rmesa->hw.ctx.emit = ctx_emit; + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.ctx.emit = ctx_emit_cs; + else + rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); @@ -633,87 +819,115 @@ void r200InitState( r200ContextPtr rmesa ) /* Fill in the packet headers: */ - rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); - rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); - rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); + rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); + rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); + rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) - rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR); - rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); - rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); - rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK); - rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE); - rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL); - rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC); - rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(R200_EMIT_PP_CNTL_X); - rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET); - rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL); - rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0); - rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS); - rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(R200_EMIT_RE_POINTSIZE); - rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); - rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3); - rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0); + rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR); + rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); + rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); + rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); + rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); + rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); + rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); + rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X); + rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET); + rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL); + rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0); + rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS); + rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE); + rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); + rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3); + rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0); if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { - rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR); - rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0); - rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0); - rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_1); - rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1); - rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_2); - rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2); - rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_3); - rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3); - rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_4); - rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4); - rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_5); - rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5); + rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR); + rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0); + rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); + rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1); + rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); + rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2); + rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); + rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3); + rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); + rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4); + rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); + rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5); + rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); } else { - rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_0); - rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0); - rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1); - rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1); - rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2); - rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2); - rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3); - rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3); - rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4); - rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4); - rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5); - rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5); + rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0); + rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); + rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1); + rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); + rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2); + rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); + rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3); + rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); + rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4); + rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); + rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5); + rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); + } + rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0); + rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1); + rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL); + rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0); + rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0); + rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1); + rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1); + rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2); + rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2); + rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3); + rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3); + rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4); + rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4); + rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5); + rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5); + rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0); + rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1); + rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2); + rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3); + rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4); + rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5); + rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); + rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0); + rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL); + rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2); + rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0); + rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL); + rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0); + rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL); + rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL); + rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL); + rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL); + rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); + if (rmesa->radeon.radeonScreen->kernel_mm) { + rmesa->hw.mtl[0].emit = mtl_emit; + rmesa->hw.mtl[1].emit = mtl_emit; + + rmesa->hw.vpi[0].emit = veclinear_emit; + rmesa->hw.vpi[1].emit = veclinear_emit; + rmesa->hw.vpp[0].emit = veclinear_emit; + rmesa->hw.vpp[1].emit = veclinear_emit; + + rmesa->hw.grd.emit = scl_emit; + rmesa->hw.fog.emit = vec_emit; + rmesa->hw.glt.emit = vec_emit; + rmesa->hw.eye.emit = vec_emit; + + for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) + rmesa->hw.mat[i].emit = vec_emit; + + for (i = 0; i < 8; i++) + rmesa->hw.lit[i].emit = lit_emit; + + for (i = 0; i < 6; i++) + rmesa->hw.ucp[i].emit = vec_emit; + + rmesa->hw.ptp.emit = ptp_emit; } - rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_0); - rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_1); - rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(R200_EMIT_VAP_PVS_CNTL); - rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0); - rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0); - rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1); - rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1); - rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2); - rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2); - rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3); - rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3); - rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4); - rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4); - rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5); - rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5); - rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0); - rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1); - rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2); - rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3); - rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4); - rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5); - rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR); - rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0); - rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL); - rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2); - rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(R200_EMIT_MATRIX_SELECT_0); - rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(R200_EMIT_VAP_CTL); - rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(R200_EMIT_VTX_FMT_0); - rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL); - rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL); - rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL); - rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL); - rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL); + + + rmesa->hw.mtl[0].cmd[MTL_CMD_0] = cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); rmesa->hw.mtl[0].cmd[MTL_CMD_1] = -- cgit v1.2.3 From b13746b558200862a5d7e7196555f5df38eccd5a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:03:21 +1000 Subject: r300: fix some whitespace --- src/mesa/drivers/dri/r300/r300_ioctl.c | 56 +++++++++++++++++----------------- 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index eb500379118..d12fde175bc 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -159,41 +159,41 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, R300_S_FRONT_ZFAIL_OP_SHIFT); } - OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); + OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); OUT_BATCH(t1); OUT_BATCH(t2); OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << R300_STENCILWRITEMASK_SHIFT) | (ctx->Stencil.Clear & R300_STENCILREF_MASK)); - END_BATCH(); + END_BATCH(); } - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(9); - OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR)); - OUT_BATCH_FLOAT32(dPriv->w / 2.0); - OUT_BATCH_FLOAT32(dPriv->h / 2.0); - OUT_BATCH_FLOAT32(ctx->Depth.Clear); - OUT_BATCH_FLOAT32(1.0); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); - END_BATCH(); - } else { - OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); - OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | - (1 << R300_PRIM_NUM_VERTICES_SHIFT)); - OUT_BATCH_FLOAT32(dPriv->w / 2.0); - OUT_BATCH_FLOAT32(dPriv->h / 2.0); - OUT_BATCH_FLOAT32(ctx->Depth.Clear); - OUT_BATCH_FLOAT32(1.0); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); - OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); - } - + if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(9); + OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR)); + OUT_BATCH_FLOAT32(dPriv->w / 2.0); + OUT_BATCH_FLOAT32(dPriv->h / 2.0); + OUT_BATCH_FLOAT32(ctx->Depth.Clear); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); + END_BATCH(); + } else { + OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); + OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | + (1 << R300_PRIM_NUM_VERTICES_SHIFT)); + OUT_BATCH_FLOAT32(dPriv->w / 2.0); + OUT_BATCH_FLOAT32(dPriv->h / 2.0); + OUT_BATCH_FLOAT32(ctx->Depth.Clear); + OUT_BATCH_FLOAT32(1.0); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); + OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); + } + r300EmitCacheFlush(rmesa); cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); -- cgit v1.2.3 From 5fbb00a11e6c113503399c8acf06196eea64fac4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:03:34 +1000 Subject: r200: unref swtcl buffer correctly --- src/mesa/drivers/dri/r200/r200_swtcl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 663e4ae0bc6..3142f8b6c94 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -297,6 +297,7 @@ static void flush_last_swtcl_prim(GLcontext *ctx) rmesa->swtcl.hw_primitive, rmesa->swtcl.numverts); + radeon_bo_unref(rmesa->swtcl.bo); // COMMIT_BATCH(); rmesa->swtcl.numverts = 0; } -- cgit v1.2.3 From 682ebc79d55ae6aede3369e344dbcb320be1f39f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:03:47 +1000 Subject: r200: start work on userspace clear for r200 --- src/mesa/drivers/dri/r200/r200_ioctl.c | 163 +++++++++++++++++++-------------- 1 file changed, 94 insertions(+), 69 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 744a2d8a4fd..cb2f50d5d87 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -85,85 +85,29 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) rmesa->store = saved_store; } -/* ================================================================ - * Buffer clear - */ -static void r200Clear( GLcontext *ctx, GLbitfield mask ) +static void r200UserClear(GLcontext *ctx, GLuint flags) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - GLuint flags = 0; - GLuint color_mask = 0; - GLint ret, i; - GLint cx, cy, cw, ch; - - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "r200Clear\n"); - } - - { - LOCK_HARDWARE( &rmesa->radeon ); - UNLOCK_HARDWARE( &rmesa->radeon ); - if ( dPriv->numClipRects == 0 ) - return; - } + if (flags & (RADEON_FRONT | RADEON_BACK)) { - r200Flush( ctx ); - - if ( mask & BUFFER_BIT_FRONT_LEFT ) { - flags |= RADEON_FRONT; - color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; - mask &= ~BUFFER_BIT_FRONT_LEFT; - } - - if ( mask & BUFFER_BIT_BACK_LEFT ) { - flags |= RADEON_BACK; - color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; - mask &= ~BUFFER_BIT_BACK_LEFT; - } - - if ( mask & BUFFER_BIT_DEPTH ) { - flags |= RADEON_DEPTH; - mask &= ~BUFFER_BIT_DEPTH; - } - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { - flags |= RADEON_STENCIL; - mask &= ~BUFFER_BIT_STENCIL; } + + if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) + && (flags & RADEON_CLEAR_FASTZ)) { - if ( mask ) { - if (R200_DEBUG & DEBUG_FALLBACKS) - fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); - _swrast_Clear( ctx, mask ); } - if ( !flags ) - return; +} - if (rmesa->using_hyperz) { - flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) - flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->radeon.state.stencil.hwBuffer) || - ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && - ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { - flags |= RADEON_CLEAR_FASTZ; - } - } +static void r200KernelClear(GLcontext *ctx, GLuint flags) +{ + r200ContextPtr rmesa = R200_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + GLint cx, cy, cw, ch, ret; + GLuint i; LOCK_HARDWARE( &rmesa->radeon ); - /* compute region after locking: */ - cx = ctx->DrawBuffer->_Xmin; - cy = ctx->DrawBuffer->_Ymin; - cw = ctx->DrawBuffer->_Xmax - cx; - ch = ctx->DrawBuffer->_Ymax - cy; - - /* Flip top to bottom */ - cx += dPriv->x; - cy = dPriv->y + dPriv->h - cy - ch; - /* Throttle the number of clear ioctls we do. */ while ( 1 ) { @@ -197,6 +141,16 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) /* Send current state to the hardware */ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); + + /* compute region after locking: */ + cx = ctx->DrawBuffer->_Xmin; + cy = ctx->DrawBuffer->_Ymin; + cw = ctx->DrawBuffer->_Xmax - cx; + ch = ctx->DrawBuffer->_Ymax - cy; + + /* Flip top to bottom */ + cx += dPriv->x; + cy = dPriv->y + dPriv->h - cy - ch; for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); drm_clip_rect_t *box = dPriv->pClipRects; @@ -264,8 +218,79 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) exit( 1 ); } } - UNLOCK_HARDWARE( &rmesa->radeon ); +} +/* ================================================================ + * Buffer clear + */ +static void r200Clear( GLcontext *ctx, GLbitfield mask ) +{ + r200ContextPtr rmesa = R200_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + GLuint flags = 0; + GLuint color_mask = 0; + GLint ret; + + if ( R200_DEBUG & DEBUG_IOCTL ) { + fprintf( stderr, "r200Clear\n"); + } + + { + LOCK_HARDWARE( &rmesa->radeon ); + UNLOCK_HARDWARE( &rmesa->radeon ); + if ( dPriv->numClipRects == 0 ) + return; + } + + r200Flush( ctx ); + + if ( mask & BUFFER_BIT_FRONT_LEFT ) { + flags |= RADEON_FRONT; + color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; + mask &= ~BUFFER_BIT_FRONT_LEFT; + } + + if ( mask & BUFFER_BIT_BACK_LEFT ) { + flags |= RADEON_BACK; + color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; + mask &= ~BUFFER_BIT_BACK_LEFT; + } + + if ( mask & BUFFER_BIT_DEPTH ) { + flags |= RADEON_DEPTH; + mask &= ~BUFFER_BIT_DEPTH; + } + + if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { + flags |= RADEON_STENCIL; + mask &= ~BUFFER_BIT_STENCIL; + } + + if ( mask ) { + if (R200_DEBUG & DEBUG_FALLBACKS) + fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); + _swrast_Clear( ctx, mask ); + } + + if ( !flags ) + return; + + if (rmesa->using_hyperz) { + flags |= RADEON_USE_COMP_ZBUF; +/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) + flags |= RADEON_USE_HIERZ; */ + if (!(rmesa->radeon.state.stencil.hwBuffer) || + ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && + ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { + flags |= RADEON_CLEAR_FASTZ; + } + } + + if (rmesa->radeon.radeonScreen->kernel_mm) + r200UserClear(ctx, flags); + else + r200KernelClear(ctx, flags); + rmesa->hw.all_dirty = GL_TRUE; } -- cgit v1.2.3 From 5ba92a5b0543b4ff2c7db6101029ba36cb9843fa Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 16:47:37 +1000 Subject: radeon/r200/r300: bring back old style DMA buffer on top of BOs. this gets back a lot of the lots speed in gears on r500 at least I also fixed the legacy bufmgr to deal when the dma space fills up --- src/mesa/drivers/dri/r200/Makefile | 1 - src/mesa/drivers/dri/r200/r200_context.c | 7 +- src/mesa/drivers/dri/r200/r200_context.h | 4 - src/mesa/drivers/dri/r200/r200_maos_arrays.c | 104 ----- src/mesa/drivers/dri/r200/r200_texmem.c | 531 ------------------------- src/mesa/drivers/dri/r300/r300_context.c | 1 + src/mesa/drivers/dri/r300/r300_context.h | 1 - src/mesa/drivers/dri/r300/r300_emit.c | 52 +-- src/mesa/drivers/dri/r300/r300_ioctl.c | 10 +- src/mesa/drivers/dri/r300/r300_render.c | 6 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 89 +++-- src/mesa/drivers/dri/radeon/common_context.h | 33 +- src/mesa/drivers/dri/radeon/common_misc.c | 85 +++- src/mesa/drivers/dri/radeon/common_misc.h | 4 + src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 34 +- src/mesa/drivers/dri/radeon/radeon_context.c | 6 +- src/mesa/drivers/dri/radeon/radeon_context.h | 1 - src/mesa/drivers/dri/radeon/radeon_ioctl.c | 14 +- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 16 +- 19 files changed, 244 insertions(+), 755 deletions(-) delete mode 100644 src/mesa/drivers/dri/r200/r200_texmem.c (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 5f1cfc889ee..d96999f7bbb 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -18,7 +18,6 @@ DRIVER_SOURCES = r200_context.c \ r200_cmdbuf.c \ r200_pixel.c \ r200_tex.c \ - r200_texmem.c \ r200_texstate.c \ r200_tcl.c \ r200_swtcl.c \ diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 9f1edd39d3d..53c64eb5a38 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -365,9 +365,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, } - if (!rmesa->radeon.radeonScreen->kernel_mm) - rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; - (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); make_empty_list( & rmesa->radeon.swapped ); @@ -587,8 +584,8 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200DestroySwtcl( rmesa->radeon.glCtx ); r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); - if (rmesa->dma.current.buf) { - // r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); + if (rmesa->dma.current) { + radeonReleaseDmaRegion(rmesa); rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 62847be522e..80981135ac6 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -525,10 +525,6 @@ struct r200_state { GLuint envneeded; }; -#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ - (rvb)->address - rmesa->dma.buf0_address + \ - (rvb)->start) - #define R200_CMD_BUF_SZ (16*1024) #define R200_ELT_BUF_SZ (16*1024) diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index bcdc4336abd..278e00442c8 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -50,110 +50,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_maos.h" #include "r200_tcl.h" - -#if 0 -/* Usage: - * - from r200_tcl_render - * - call r200EmitArrays to ensure uptodate arrays in dma - * - emit primitives (new type?) which reference the data - * -- need to use elts for lineloop, quads, quadstrip/flat - * -- other primitives are all well-formed (need tristrip-1,fake-poly) - * - */ -static void emit_ubyte_rgba3( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - r200_color_t *out = (r200_color_t *)(rvb->start + rvb->address); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p\n", - __FUNCTION__, count, stride, (void *)out); - - for (i = 0; i < count; i++) { - out->red = *data; - out->green = *(data+1); - out->blue = *(data+2); - out->alpha = 0xFF; - out++; - data += stride; - } -} - -static void emit_ubyte_rgba4( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 4) { - for (i = 0; i < count; i++) - ((int *)out)[i] = LE32_TO_CPU(((int *)data)[i]); - } else { - for (i = 0; i < count; i++) { - *(int *)out++ = LE32_TO_CPU(*(int *)data); - data += stride; - } - } -} - - -static void emit_ubyte_rgba( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int size, - int stride, - int count ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if (R200_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size); - - assert (!rvb->buf); - - if (stride == 0) { - // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); - count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = 1; - } - else { - // r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 1; - rvb->aos_size = 1; - } - - /* Emit the data - */ - switch (size) { - case 3: - emit_ubyte_rgba3( ctx, rvb, data, stride, count ); - break; - case 4: - emit_ubyte_rgba4( ctx, rvb, data, stride, count ); - break; - default: - assert(0); - exit(1); - break; - } -} -#endif - - #if defined(USE_X86_ASM) #define COPY_DWORDS( dst, src, nr ) \ do { \ diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c deleted file mode 100644 index a50786e2e78..00000000000 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ /dev/null @@ -1,531 +0,0 @@ -/************************************************************************** - -Copyright (C) Tungsten Graphics 2002. All Rights Reserved. -The Weather Channel, Inc. funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 -license. This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation on the rights to use, copy, modify, merge, publish, -distribute, sub license, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR -SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR -IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Kevin E. Martin - * Gareth Hughes - * - */ - -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/colormac.h" -#include "main/macros.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_tex.h" -#include "radeon_reg.h" - -#include /* for usleep() */ - -#if 0 -/** - * Destroy any device-dependent state associated with the texture. This may - * include NULLing out hardware state that points to the texture. - */ -void -r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t ) -{ - if ( R200_DEBUG & DEBUG_TEXTURE ) { - fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, - (void *)t, (void *)t->base.tObj ); - } - - if ( rmesa != NULL ) { - unsigned i; - - - for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { - if ( t == rmesa->state.texture.unit[i].texobj ) { - rmesa->state.texture.unit[i].texobj = NULL; - rmesa->hw.tex[i].dirty = GL_FALSE; - rmesa->hw.cube[i].dirty = GL_FALSE; - } - } - } -} - - -/* ------------------------------------------------------------ - * Texture image conversions - */ - - -static void r200UploadGARTClientSubImage( r200ContextPtr rmesa, - radeonTexObjPtr t, - struct gl_texture_image *texImage, - GLint hwlevel, - GLint x, GLint y, - GLint width, GLint height ) -{ - const struct gl_texture_format *texFormat = texImage->TexFormat; - GLuint srcPitch, dstPitch; - int blit_format; - int srcOffset; - - /* - * XXX it appears that we always upload the full image, not a subimage. - * I.e. x==0, y==0, width=texWidth, height=texWidth. If this is ever - * changed, the src pitch will have to change. - */ - switch ( texFormat->TexelBytes ) { - case 1: - blit_format = R200_CP_COLOR_FORMAT_CI8; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - case 2: - blit_format = R200_CP_COLOR_FORMAT_RGB565; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - case 4: - blit_format = R200_CP_COLOR_FORMAT_ARGB8888; - srcPitch = t->image[0][0].width * texFormat->TexelBytes; - dstPitch = t->image[0][0].width * texFormat->TexelBytes; - break; - default: - return; - } - - t->image[0][hwlevel].data = texImage->Data; - srcOffset = r200GartOffsetFromVirtual( rmesa, texImage->Data ); - - assert( srcOffset != ~0 ); - - /* Don't currently need to cope with small pitches? - */ - width = texImage->Width; - height = texImage->Height; - - r200EmitWait( rmesa, RADEON_WAIT_3D ); - - r200EmitBlit( rmesa, blit_format, - srcPitch, - srcOffset, - dstPitch, - t->bufAddr, - x, - y, - t->image[0][hwlevel].x + x, - t->image[0][hwlevel].y + y, - width, - height ); - - r200EmitWait( rmesa, RADEON_WAIT_2D ); -} - -static void r200UploadRectSubImage( r200ContextPtr rmesa, - radeonTexObjPtr t, - struct gl_texture_image *texImage, - GLint x, GLint y, - GLint width, GLint height ) -{ - const struct gl_texture_format *texFormat = texImage->TexFormat; - int blit_format, dstPitch, done; - - switch ( texFormat->TexelBytes ) { - case 1: - blit_format = R200_CP_COLOR_FORMAT_CI8; - break; - case 2: - blit_format = R200_CP_COLOR_FORMAT_RGB565; - break; - case 4: - blit_format = R200_CP_COLOR_FORMAT_ARGB8888; - break; - default: - return; - } - - t->image[0][0].data = texImage->Data; - - /* Currently don't need to cope with small pitches. - */ - width = texImage->Width; - height = texImage->Height; - dstPitch = t->pp_txpitch + 32; - - if (rmesa->prefer_gart_client_texturing && texImage->IsClientData) { - /* In this case, could also use GART texturing. This is - * currently disabled, but has been tested & works. - */ - if ( !t->image_override ) - t->pp_txoffset = r200GartOffsetFromVirtual( rmesa, texImage->Data ); - t->pp_txpitch = texImage->RowStride * texFormat->TexelBytes - 32; - - if (R200_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, - "Using GART texturing for rectangular client texture\n"); - - /* Release FB memory allocated for this image: - */ - /* FIXME This may not be correct as driSwapOutTextureObject sets - * FIXME dirty_images. It may be fine, though. - */ - if ( t->base.memBlock ) { - driSwapOutTextureObject( (driTextureObject *) t ); - } - } - else if (texImage->IsClientData) { - /* Data already in GART memory, with usable pitch. - */ - GLuint srcPitch; - srcPitch = texImage->RowStride * texFormat->TexelBytes; - r200EmitBlit( rmesa, - blit_format, - srcPitch, - r200GartOffsetFromVirtual( rmesa, texImage->Data ), - dstPitch, t->bufAddr, - 0, 0, - 0, 0, - width, height ); - } - else { - /* Data not in GART memory, or bad pitch. - */ - for (done = 0; done < height ; ) { - struct radeon_dma_region region; - int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch ); - int src_pitch; - char *tex; - - src_pitch = texImage->RowStride * texFormat->TexelBytes; - - tex = (char *)texImage->Data + done * src_pitch; - - memset(®ion, 0, sizeof(region)); - // r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); - - /* Copy texdata to dma: - */ - if (0) - fprintf(stderr, "%s: src_pitch %d dst_pitch %d\n", - __FUNCTION__, src_pitch, dstPitch); - - if (src_pitch == dstPitch) { - memcpy( region.address + region.start, tex, lines * src_pitch ); - } - else { - char *buf = region.address + region.start; - int i; - for (i = 0 ; i < lines ; i++) { - memcpy( buf, tex, src_pitch ); - buf += dstPitch; - tex += src_pitch; - } - } - - r200EmitWait( rmesa, RADEON_WAIT_3D ); - - /* Blit to framebuffer - */ - r200EmitBlit( rmesa, - blit_format, - dstPitch, GET_START( ®ion ), - dstPitch | (t->tile_bits >> 16), - t->bufAddr, - 0, 0, - 0, done, - width, lines ); - - r200EmitWait( rmesa, RADEON_WAIT_2D ); - - // r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); - done += lines; - } - } -} - - -/** - * Upload the texture image associated with texture \a t at the specified - * level at the address relative to \a start. - */ -static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t, - GLint hwlevel, - GLint x, GLint y, GLint width, GLint height, - GLuint face ) -{ - struct gl_texture_image *texImage = NULL; - GLuint offset; - GLint imageWidth, imageHeight; - GLint ret; - drm_radeon_texture_t tex; - drm_radeon_tex_image_t tmp; - const int level = hwlevel + t->base.firstLevel; - - if ( R200_DEBUG & DEBUG_TEXTURE ) { - fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n", - __FUNCTION__, (void *)t, (void *)t->base.tObj, - level, width, height, face ); - } - - ASSERT(face < 6); - - /* Ensure we have a valid texture to upload */ - if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) { - _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); - return; - } - - texImage = t->base.tObj->Image[face][level]; - - if ( !texImage ) { - if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level ); - return; - } - if ( !texImage->Data ) { - if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ ); - return; - } - - - if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - assert(level == 0); - assert(hwlevel == 0); - if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__); - r200UploadRectSubImage( rmesa, t, texImage, x, y, width, height ); - return; - } - else if (texImage->IsClientData) { - if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: image data is in GART client storage\n", - __FUNCTION__); - r200UploadGARTClientSubImage( rmesa, t, texImage, hwlevel, - x, y, width, height ); - return; - } - else if ( R200_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: image data is in normal memory\n", - __FUNCTION__); - - - imageWidth = texImage->Width; - imageHeight = texImage->Height; - - offset = t->bufAddr + t->base.totalSize / 6 * face; - - if ( R200_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { - GLint imageX = 0; - GLint imageY = 0; - GLint blitX = t->image[face][hwlevel].x; - GLint blitY = t->image[face][hwlevel].y; - GLint blitWidth = t->image[face][hwlevel].width; - GLint blitHeight = t->image[face][hwlevel].height; - fprintf( stderr, " upload image: %d,%d at %d,%d\n", - imageWidth, imageHeight, imageX, imageY ); - fprintf( stderr, " upload blit: %d,%d at %d,%d\n", - blitWidth, blitHeight, blitX, blitY ); - fprintf( stderr, " blit ofs: 0x%07x level: %d/%d\n", - (GLuint)offset, hwlevel, level ); - } - - t->image[face][hwlevel].data = texImage->Data; - - /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct. - * NOTE: we're always use a 1KB-wide blit and I8 texture format. - * We used to use 1, 2 and 4-byte texels and used to use the texture - * width to dictate the blit width - but that won't work for compressed - * textures. (Brian) - * NOTE: can't do that with texture tiling. (sroland) - */ - tex.offset = offset; - tex.image = &tmp; - /* copy (x,y,width,height,data) */ - memcpy( &tmp, &t->image[face][hwlevel], sizeof(tmp) ); - - if (texImage->TexFormat->TexelBytes) { - /* use multi-byte upload scheme */ - tex.height = imageHeight; - tex.width = imageWidth; - tex.format = t->pp_txformat & R200_TXFORMAT_FORMAT_MASK; - if (tex.format == R200_TXFORMAT_ABGR8888) { - /* drm will refuse abgr8888 textures. */ - tex.format = R200_TXFORMAT_ARGB8888; - } - tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1); - tex.offset += tmp.x & ~1023; - tmp.x = tmp.x % 1024; - if (t->tile_bits & R200_TXO_MICRO_TILE) { - /* need something like "tiled coordinates" ? */ - tmp.y = tmp.x / (tex.pitch * 128) * 2; - tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes; - tex.pitch |= RADEON_DST_TILE_MICRO >> 22; - } - else { - tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1); - } - if ((t->tile_bits & R200_TXO_MACRO_TILE) && - (texImage->Width * texImage->TexFormat->TexelBytes >= 256) && - ((!(t->tile_bits & R200_TXO_MICRO_TILE) && (texImage->Height >= 8)) || - (texImage->Height >= 16))) { - /* weird: R200 disables macro tiling if mip width is smaller than 256 bytes, - OR if height is smaller than 8 automatically, but if micro tiling is active - the limit is height 16 instead ? */ - tex.pitch |= RADEON_DST_TILE_MACRO >> 22; - } - } - else { - /* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is - needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */ - /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed - so the kernel module reads the right amount of data. */ - tex.format = R200_TXFORMAT_I8; /* any 1-byte texel format */ - tex.pitch = (BLIT_WIDTH_BYTES / 64); - tex.height = (imageHeight + 3) / 4; - tex.width = (imageWidth + 3) / 4; - switch (t->pp_txformat & R200_TXFORMAT_FORMAT_MASK) { - case R200_TXFORMAT_DXT1: - tex.width *= 8; - break; - case R200_TXFORMAT_DXT23: - case R200_TXFORMAT_DXT45: - tex.width *= 16; - break; - default: - fprintf(stderr, "unknown compressed tex format in uploadSubImage\n"); - } - } - - LOCK_HARDWARE( &rmesa->radeon ); - do { - ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE, - &tex, sizeof(drm_radeon_texture_t) ); - if (ret) { - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n"); - usleep(1); - } - } while ( ret == -EAGAIN ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret ); - fprintf( stderr, " offset=0x%08x\n", - offset ); - fprintf( stderr, " image width=%d height=%d\n", - imageWidth, imageHeight ); - fprintf( stderr, " blit width=%d height=%d data=%p\n", - t->image[face][hwlevel].width, t->image[face][hwlevel].height, - t->image[face][hwlevel].data ); - exit( 1 ); - } -} - - -/** - * Upload the texture images associated with texture \a t. This might - * require the allocation of texture memory. - * - * \param rmesa Context pointer - * \param t Texture to be uploaded - * \param face Cube map face to be uploaded. Zero for non-cube maps. - */ - -int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) -{ - const int numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - if ( R200_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { - fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__, - (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize, - t->base.firstLevel, t->base.lastLevel ); - } - - if ( !t || t->base.totalSize == 0 || t->image_override ) - return 0; - - if (R200_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - r200Finish( rmesa->radeon.glCtx ); - } - - LOCK_HARDWARE( &rmesa->radeon ); - - if ( t->base.memBlock == NULL ) { - int heap; - - heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, - (driTextureObject *) t ); - if ( heap == -1 ) { - UNLOCK_HARDWARE( &rmesa->radeon ); - return -1; - } - - /* Set the base offset of the texture image */ - t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] - + t->base.memBlock->ofs; - t->pp_txoffset = t->bufAddr; - - if (!(t->base.tObj->Image[0][0]->IsClientData)) { - /* hope it's safe to add that here... */ - t->pp_txoffset |= t->tile_bits; - } - - /* Mark this texobj as dirty on all units: - */ - t->dirty_state = R200_TEX_ALL; - } - - /* Let the world know we've used this memory recently. - */ - driUpdateTextureLRU( (driTextureObject *) t ); - UNLOCK_HARDWARE( &rmesa->radeon ); - - /* Upload any images that are new */ - if (t->base.dirty_images[face]) { - int i; - for ( i = 0 ; i < numLevels ; i++ ) { - if ( (t->base.dirty_images[face] & (1 << (i+t->base.firstLevel))) != 0 ) { - uploadSubImage( rmesa, t, i, 0, 0, t->image[face][i].width, - t->image[face][i].height, face ); - } - } - t->base.dirty_images[face] = 0; - } - - - if (R200_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - r200Finish( rmesa->radeon.glCtx ); - } - - return 0; -} -#endif diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index eb8e481a18e..f57952d8780 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -259,6 +259,7 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; radeon->vtbl.emit_state = r300_vtbl_emit_state; + radeon->vtbl.flush_vertices = r300_vtbl_flush_vertices; } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 8f67460e420..155529a8a67 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -699,7 +699,6 @@ struct r300_swtcl_info { GLuint specoffset; struct radeon_bo *bo; - void (*flush) (r300ContextPtr); }; diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index e2d90a843ef..c47f19ea11e 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -301,28 +301,28 @@ int r300EmitArrays(GLcontext * ctx) } /* Setup INPUT_ROUTE. */ - if (rmesa->radeon.radeonScreen->kernel_mm) { - R300_STATECHANGE(rmesa, vir[0]); - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= - (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], - vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; - R300_STATECHANGE(rmesa, vir[1]); - rmesa->hw.vir[1].cmd[0] |= - (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, - nr) & 0x3FFF) << 16; - } else { - R300_STATECHANGE(rmesa, vir[0]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = - r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], - vb->AttribPtr, inputs, tab, nr); - R300_STATECHANGE(rmesa, vir[1]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = - r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, - nr); - } - + if (rmesa->radeon.radeonScreen->kernel_mm) { + R300_STATECHANGE(rmesa, vir[0]); + rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[0].cmd[0] |= + (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; + R300_STATECHANGE(rmesa, vir[1]); + rmesa->hw.vir[1].cmd[0] |= + (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + nr) & 0x3FFF) << 16; + } else { + R300_STATECHANGE(rmesa, vir[0]); + ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = + r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + vb->AttribPtr, inputs, tab, nr); + R300_STATECHANGE(rmesa, vir[1]); + ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = + r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + nr); + } + /* Setup INPUT_CNTL. */ R300_STATECHANGE(rmesa, vic); rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); @@ -337,6 +337,8 @@ int r300EmitArrays(GLcontext * ctx) rmesa->state.aos_count = nr; + radeon_bo_unmap(rmesa->radeon.dma.current); + return R300_FALLBACK_NONE; } @@ -347,13 +349,15 @@ void r300ReleaseArrays(GLcontext * ctx) if (rmesa->state.elt_dma_bo) { radeon_bo_unref(rmesa->state.elt_dma_bo); - rmesa->state.elt_dma_bo = 0; + rmesa->state.elt_dma_bo = NULL; } for (i = 0; i < rmesa->state.aos_count; i++) { if (rmesa->state.aos[i].bo) { - rmesa->state.aos[i].bo = radeon_bo_unref(rmesa->state.aos[i].bo); + radeon_bo_unref(rmesa->state.aos[i].bo); + rmesa->state.aos[i].bo = NULL; } } + radeonReleaseDmaRegion(&rmesa->radeon); } void r300EmitCacheFlush(r300ContextPtr rmesa) diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index d12fde175bc..b0a579bf840 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -393,7 +393,7 @@ static void r300EmitClearState(GLcontext * ctx) R300_STATECHANGE(r300, fp); R300_STATECHANGE(r300, r500fp); - BEGIN_BATCH(14); + BEGIN_BATCH(7); OUT_BATCH_REGSEQ(R500_US_CONFIG, 2); OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_BATCH(0x0); @@ -619,10 +619,10 @@ void r300Flush(GLcontext * ctx) if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->swtcl.flush) { - rmesa->swtcl.flush(rmesa); - } - + if (rmesa->radeon.dma.flush) { + rmesa->radeon.dma.flush(ctx); + } + if (rmesa->radeon.cmdbuf.cs->cdw) { rcommonFlushCmdBuf(&rmesa->radeon, __FUNCTION__); } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index ef3671eadbd..57249c46ef8 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -177,10 +177,8 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) r300ContextPtr rmesa = R300_CONTEXT(ctx); void *out; - rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, n_elts * 4, 4, - RADEON_GEM_DOMAIN_GTT, 0); - rmesa->state.elt_dma_offset = 0; + radeonAllocDmaRegion(&rmesa->radeon, &rmesa->state.elt_dma_bo, + &rmesa->state.elt_dma_offset, n_elts * 4, 4); radeon_bo_map(rmesa->state.elt_dma_bo, 1); out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; memcpy(out, elts, n_elts * 4); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index eb86bd3bdd6..1ce51b21f3a 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -57,7 +57,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "r300_emit.h" -static void flush_last_swtcl_prim( r300ContextPtr rmesa ); +static void flush_last_swtcl_prim( GLcontext *ctx); void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset); @@ -241,26 +241,45 @@ static void r300SetVertexFormat( GLcontext *ctx ) /* Flush vertices in the current dma region. */ -static void flush_last_swtcl_prim( r300ContextPtr rmesa ) +static void flush_last_swtcl_prim( GLcontext *ctx ) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); + struct radeon_dma *dma = &rmesa->radeon.dma; + + if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - rmesa->swtcl.flush = NULL; - radeon_bo_unmap(rmesa->swtcl.bo); - rcommonEnsureCmdBufSpace(rmesa, - rmesa->hw.max_state_size + (12*sizeof(int)), - __FUNCTION__); - r300EmitState(rmesa); - r300EmitVertexAOS(rmesa, - rmesa->swtcl.vertex_size, - rmesa->swtcl.bo, - 0); - r300EmitVbufPrim(rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - r300EmitCacheFlush(rmesa); - COMMIT_BATCH(); - rmesa->swtcl.numverts = 0; + dma->flush = NULL; + + if (dma->current) { + GLuint current_offset = dma->current_used; + + assert (dma->current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + dma->current_vertexptr); + + radeon_bo_unmap(dma->current); + if (dma->current_used != dma->current_vertexptr) { + dma->current_used = dma->current_vertexptr; + + rcommonEnsureCmdBufSpace(rmesa, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); + r300EmitState(rmesa); + r300EmitVertexAOS(rmesa, + rmesa->swtcl.vertex_size, + dma->current, + current_offset); + + r300EmitVbufPrim(rmesa, + rmesa->swtcl.hw_primitive, + rmesa->swtcl.numverts); + r300EmitCacheFlush(rmesa); + COMMIT_BATCH(); + } + radeonReleaseDmaRegion(&rmesa->radeon); + rmesa->swtcl.numverts = 0; + } } /* Alloc space in the current dma region. @@ -269,15 +288,29 @@ static void * r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; + void *head; - rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); - radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->swtcl.flush == NULL) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->swtcl.flush = flush_last_swtcl_prim; + if (!rmesa->radeon.dma.current || rmesa->radeon.dma.current_vertexptr + bytes > rmesa->radeon.dma.current->size) { + radeonRefillCurrentDmaRegion( &rmesa->radeon, bytes); } - return rmesa->swtcl.bo->ptr; + + if (!rmesa->radeon.dma.flush) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->radeon.dma.flush = flush_last_swtcl_prim; + } + + ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); + ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); + ASSERT( rmesa->radeon.dma.current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + rmesa->dma.current_vertexptr ); + +// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, +// rmesa->radeon.dma.current_vertexptr); + head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr); + rmesa->radeon.dma.current_vertexptr += bytes; + rmesa->swtcl.numverts += nverts; + return head; } static GLuint reduced_prim[] = { @@ -550,9 +583,9 @@ static void r300RenderStart(GLcontext *ctx) r300UpdateShaderStates(rmesa); r300EmitCacheFlush(rmesa); - if (rmesa->swtcl.flush != NULL) { - rmesa->swtcl.flush(rmesa); - } + if (rmesa->radeon.dma.flush != NULL) { + rmesa->radeon.dma.flush(ctx); + } } static void r300RenderFinish(GLcontext *ctx) diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 09a53b00eae..471e7cdfb17 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -225,16 +225,26 @@ struct radeon_aos { }; struct radeon_dma { - /* Active dma region. Allocations for vertices and retained - * regions come from here. Also used for emitting random vertices, - * these may be flushed by calling flush_current(); - */ - struct radeon_dma_region current; - - void (*flush)( GLcontext *ctx ); - - char *buf0_address; /* start of buf[0], for index calcs */ - GLuint nr_released_bufs; /* flush after so many buffers released */ + /* Active dma region. Allocations for vertices and retained + * regions come from here. Also used for emitting random vertices, + * these may be flushed by calling flush_current(); + */ + struct radeon_bo *current; /** Buffer that DMA memory is allocated from */ + int current_used; /** Number of bytes allocated and forgotten about */ + int current_vertexptr; /** End of active vertex region */ + + /** + * If current_vertexptr != current_used then flush must be non-zero. + * flush must be called before non-active vertex allocations can be + * performed. + */ + void (*flush) (GLcontext *); + + /* Number of "in-flight" DMA buffers, i.e. the number of buffers + * for which a DISCARD command is currently queued in the command buffer +. + */ + GLuint nr_released_bufs; }; struct radeon_ioctl { @@ -266,6 +276,8 @@ static INLINE GLuint radeonPackColor(GLuint cpp, #define MAX_CMD_BUF_SZ (16*1024) +#define MAX_DMA_BUF_SZ (64*1024) + struct radeon_store { GLuint statenr; GLuint primnr; @@ -354,6 +366,7 @@ struct radeon_context { int texture_depth; float initialMaxAnisotropy; + struct radeon_dma dma; /* Rasterization and vertex state: */ GLuint TclFallback; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 99ca936dae3..3ed58815d33 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1316,22 +1316,19 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, uint32_t *out; uint32_t bo_size; - memset(aos, 0, sizeof(struct radeon_aos)); if (stride == 0) { - bo_size = size * 4; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); count = 1; aos->stride = 0; } else { - bo_size = size * count * 4; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); aos->stride = size; } - aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); - aos->offset = 0; + aos->components = size; aos->count = count; - radeon_bo_map(aos->bo, 1); +// radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: radeonEmitVec4(out, data, stride, count); break; @@ -1342,7 +1339,7 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, assert(0); break; } - radeon_bo_unmap(aos->bo); +// radeon_bo_unmap(aos->bo); } @@ -2321,3 +2318,75 @@ void radeonSpanRenderFinish(GLcontext * ctx) unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); } +void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) +{ + size = MAX2(size, MAX_DMA_BUF_SZ * 16); + + if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (rmesa->dma.flush) { + radeon_bo_unmap(rmesa->dma.current); + rmesa->dma.flush(rmesa->glCtx); + } + + + + if (rmesa->dma.nr_released_bufs > 4) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + rmesa->dma.nr_released_bufs = 0; + } + + if (rmesa->dma.current) { + radeon_bo_unref(rmesa->dma.current); + rmesa->dma.current = 0; + } + + rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom, + 0, size, 4, RADEON_GEM_DOMAIN_GTT, + 0); + + rmesa->dma.current_used = 0; + rmesa->dma.current_vertexptr = 0; + radeon_bo_map(rmesa->dma.current, 1); +} + +/* Allocates a region from rmesa->dma.current. If there isn't enough + * space in current, grab a new buffer (and discard what was left of current) + */ +void radeonAllocDmaRegion(radeonContextPtr rmesa, + struct radeon_bo **pbo, int *poffset, + int bytes, int alignment) +{ + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); + + if (rmesa->dma.flush) + rmesa->dma.flush(rmesa->glCtx); + + assert(rmesa->dma.current_used == rmesa->dma.current_vertexptr); + + alignment--; + rmesa->dma.current_used = (rmesa->dma.current_used + alignment) & ~alignment; + + if (!rmesa->dma.current || rmesa->dma.current_used + bytes > rmesa->dma.current->size) + radeonRefillCurrentDmaRegion(rmesa, (bytes + 15) & ~15); + + *poffset = rmesa->dma.current_used; + *pbo = rmesa->dma.current; + radeon_bo_ref(*pbo); + + /* Always align to at least 16 bytes */ + rmesa->dma.current_used = (rmesa->dma.current_used + bytes + 15) & ~15; + rmesa->dma.current_vertexptr = rmesa->dma.current_used; + + assert(rmesa->dma.current_used <= rmesa->dma.current->size); +} + +void radeonReleaseDmaRegion(radeonContextPtr rmesa) +{ + rmesa->dma.nr_released_bufs++; + radeon_bo_unref(rmesa->dma.current); + rmesa->dma.current = NULL; +} + diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index aeff52a66e1..d17d1607db1 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -118,4 +118,8 @@ GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, GLint x, GLint y); GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, GLint x, GLint y); +void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size); +void radeonAllocDmaRegion(radeonContextPtr rmesa, + struct radeon_bo **pbo, int *poffset, + int bytes, int alignment); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 353f00100a0..bd126c026cc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -77,6 +77,7 @@ struct bo_manager_legacy { uint32_t fb_location; uint32_t texture_offset; unsigned dma_alloc_size; + uint32_t dma_buf_count; unsigned cpendings; driTextureObject texture_swapped; driTexHeap *texture_heap; @@ -221,7 +222,7 @@ static int legacy_wait_pending(struct radeon_bo *bo) return 0; } -static void legacy_track_pending(struct bo_manager_legacy *boml) +static void legacy_track_pending(struct bo_manager_legacy *boml, int debug) { struct bo_legacy *bo_legacy; struct bo_legacy *next; @@ -229,6 +230,9 @@ static void legacy_track_pending(struct bo_manager_legacy *boml) legacy_get_current_age(boml); bo_legacy = boml->pending_bos.pnext; while (bo_legacy) { + if (debug) + fprintf(stderr,"pending %p %d %d %d\n", bo_legacy, bo_legacy->base.size, + boml->current_age, bo_legacy->pending); next = bo_legacy->pnext; if (legacy_is_pending(&(bo_legacy->base))) { } @@ -236,6 +240,19 @@ static void legacy_track_pending(struct bo_manager_legacy *boml) } } +static int legacy_wait_any_pending(struct bo_manager_legacy *boml) +{ + struct bo_legacy *bo_legacy; + struct bo_legacy *next; + + legacy_get_current_age(boml); + bo_legacy = boml->pending_bos.pnext; + if (!bo_legacy) + return -1; + legacy_wait_pending(&bo_legacy->base); + return 0; +} + static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, uint32_t size, uint32_t alignment, @@ -292,13 +309,13 @@ static int bo_dma_alloc(struct radeon_bo *bo) if (r) { /* ptr is set to NULL if dma allocation failed */ bo_legacy->ptr = NULL; - exit(0); return r; } bo_legacy->ptr = boml->screen->gartTextures.map + base_offset; bo_legacy->offset = boml->screen->gart_texture_offset + base_offset; bo->size = size; boml->dma_alloc_size += size; + boml->dma_buf_count++; return 0; } @@ -328,6 +345,7 @@ static int bo_dma_free(struct radeon_bo *bo) return r; } boml->dma_alloc_size -= bo_legacy->base.size; + boml->dma_buf_count--; return 0; } @@ -388,15 +406,20 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, return NULL; } if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) { - legacy_track_pending(boml); + retry: + legacy_track_pending(boml, 0); /* dma buffers */ + r = bo_dma_alloc(&(bo_legacy->base)); if (r) { - fprintf(stderr, "Ran out of GART memory (for %d)!\n", size); + if (legacy_wait_any_pending(boml) == -1) { + fprintf(stderr, "Ran out of GART memory (for %d)!\n", size); fprintf(stderr, "Please consider adjusting GARTSize option.\n"); bo_free(bo_legacy); exit(-1); - return NULL; + } + goto retry; + return NULL; } } else { bo_legacy->ptr = malloc(bo_legacy->base.size); @@ -460,7 +483,6 @@ static int bo_map(struct radeon_bo *bo, int write) volatile int *buf = (int*)boml->screen->driScreen->pFB; p = *buf; } - return 0; } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index b87275c56b8..a6a3b1178c6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -318,7 +318,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, screen->sarea_priv_offset); - rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; + //rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); make_empty_list( & rmesa->radeon.swapped ); @@ -522,8 +522,8 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) radeonDestroySwtcl( rmesa->radeon.glCtx ); radeonReleaseArrays( rmesa->radeon.glCtx, ~0 ); - if (rmesa->dma.current.buf) { - radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); + if (rmesa->radeon.dma.current) { + radeonReleaseDmaRegion( rmesa, &rmesa->radeon.dma.current, __FUNCTION__ ); radeonFlushCmdBuf( rmesa, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index dedc3626040..ba5c57f1210 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -425,7 +425,6 @@ struct r100_context { /* Vertex buffers */ struct radeon_ioctl ioctl; - struct radeon_dma dma; struct radeon_store store; /* A full state emit as of the first state emit in the main store, in case * the context is lost. diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index cd0f90d748b..5ab19b2a8c2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -117,12 +117,12 @@ static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa ) rmesa->radeon.lost_context = GL_FALSE; - nr_released_bufs = rmesa->dma.nr_released_bufs; + nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; saved_store = rmesa->store; - rmesa->dma.nr_released_bufs = 0; + rmesa->radeon.dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); - rmesa->dma.nr_released_bufs = nr_released_bufs; + rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } @@ -308,8 +308,8 @@ void radeonFlushElts( GLcontext *ctx ) if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - assert( rmesa->dma.flush == radeonFlushElts ); - rmesa->dma.flush = NULL; + assert( rmesa->radeon.dma.flush == radeonFlushElts ); + rmesa->radeon.dma.flush = NULL; /* Cope with odd number of elts: */ @@ -381,9 +381,9 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, __FUNCTION__, cmd[1].i, vertex_format, primitive); - assert(!rmesa->dma.flush); + assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = radeonFlushElts; + rmesa->radeon.dma.flush = radeonFlushElts; rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index d11feb58043..b4bc9b11441 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -76,16 +76,6 @@ extern void radeonEmitBlit( r100ContextPtr rmesa, extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ); extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * ); -extern void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ); - -extern void radeonAllocDmaRegion( r100ContextPtr rmesa, - struct radeon_dma_region *region, - int bytes, - int alignment ); - -extern void radeonReleaseDmaRegion( r100ContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ); extern void radeonFlush( GLcontext *ctx ); extern void radeonFinish( GLcontext *ctx ); @@ -101,8 +91,8 @@ extern void radeonSetUpAtomList( r100ContextPtr rmesa ); */ #define RADEON_NEWPRIM( rmesa ) \ do { \ - if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa->radeon.glCtx ); \ + if ( rmesa->radeon.dma.flush ) \ + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -142,7 +132,7 @@ static INLINE int RADEON_DB_STATECHANGE( */ #define RADEON_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->store.cmd_used || rmesa->dma.flush ) { \ + if ( rmesa->store.cmd_used || rmesa->radeon.dma.flush ) { \ radeonFlush( rmesa->radeon.glCtx ); \ } \ } while (0) -- cgit v1.2.3 From 59b183ce0fc8fd8ab73b9321e609fdb3c29bb078 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 19:11:31 +1000 Subject: radeon: remove even more common code --- src/mesa/drivers/dri/radeon/Makefile | 1 - src/mesa/drivers/dri/radeon/radeon_context.c | 49 +-- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 2 +- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 246 +----------- src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 100 ----- src/mesa/drivers/dri/radeon/radeon_tex.c | 485 ++--------------------- 6 files changed, 55 insertions(+), 828 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 9c76abccd36..2ef3640e1d0 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -15,7 +15,6 @@ DRIVER_SOURCES = \ radeon_state.c \ radeon_state_init.c \ radeon_tex.c \ - radeon_texmem.c \ radeon_texstate.c \ radeon_tcl.c \ radeon_swtcl.c \ diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index a6a3b1178c6..6b91bdce9cf 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -225,6 +225,15 @@ static void r100_vtbl_set_all_dirty(GLcontext *ctx) rmesa->hw.all_dirty = GL_TRUE; } +static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) +{ +} + +static void r100_vtbl_emit_state(radeonContextPtr rmesa) +{ + radeonEmitState((r100ContextPtr)rmesa); +} + static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; @@ -232,6 +241,8 @@ static void r100_init_vtbl(radeonContextPtr radeon) radeon->vtbl.flush = r100_vtbl_flush; radeon->vtbl.set_all_dirty = r100_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; + radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; + radeon->vtbl.emit_state = r100_vtbl_emit_state; } /* Create the device specific context. @@ -290,35 +301,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, radeonInitDriverFuncs( &functions ); radeonInitTextureFuncs( &functions ); - /* Allocate the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx; - else - shareCtx = NULL; - rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx, - &functions, (void *) rmesa); - if (!rmesa->radeon.glCtx) { - FREE(rmesa); - return GL_FALSE; + if (!radeonInitContext(&rmesa->radeon, &functions, + glVisual, driContextPriv, + sharedContextPrivate)) { + FREE(rmesa); + return GL_FALSE; } - driContextPriv->driverPrivate = rmesa; - - /* Init radeon context data */ - rmesa->radeon.dri.context = driContextPriv; - rmesa->radeon.dri.screen = sPriv; - rmesa->radeon.dri.drawable = NULL; - rmesa->radeon.dri.readable = NULL; - rmesa->radeon.dri.hwContext = driContextPriv->hHWContext; - rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock; - rmesa->radeon.dri.fd = sPriv->fd; - rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor; - - rmesa->radeon.radeonScreen = screen; - rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + - screen->sarea_priv_offset); - - - //rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); make_empty_list( & rmesa->radeon.swapped ); @@ -523,11 +511,10 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) radeonDestroySwtcl( rmesa->radeon.glCtx ); radeonReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->radeon.dma.current) { - radeonReleaseDmaRegion( rmesa, &rmesa->radeon.dma.current, __FUNCTION__ ); - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); + radeonReleaseDmaRegion( &rmesa->radeon ); + radeonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } - radeonCleanupContext(&rmesa->radeon); _mesa_vector4f_free( &rmesa->tcl.ObjClean ); if (rmesa->radeon.state.scissor.pClipRects) { diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index a95d27c05e6..8997187d62b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -315,7 +315,7 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } - // dump_cmdbuf(cs); + dump_cmdbuf(cs); r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 5ab19b2a8c2..b101668f778 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -538,248 +538,6 @@ void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ) cmd[0].wait.flags = flags; } - -static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, - const char * caller ) -{ - int ret, i; - drm_radeon_cmd_buffer_t cmd; - - if (rmesa->radeon.lost_context) - radeonBackUpAndEmitLostStateLocked(rmesa); - - if (RADEON_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (RADEON_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < rmesa->store.cmd_used ; i += 4 ) - fprintf(stderr, "%d: %x\n", i/4, - *(int *)(&rmesa->store.cmd_buf[i])); - } - - if (RADEON_DEBUG & DEBUG_DMA) - fprintf(stderr, "%s: Releasing %d buffers\n", __FUNCTION__, - rmesa->dma.nr_released_bufs); - - - if (RADEON_DEBUG & DEBUG_SANITY) { - if (rmesa->radeon.state.scissor.enabled) - ret = radeonSanityCmdBuffer( rmesa, - rmesa->radeon.state.scissor.numClipRects, - rmesa->radeon.state.scissor.pClipRects); - else - ret = radeonSanityCmdBuffer( rmesa, - rmesa->radeon.numClipRects, - rmesa->radeon.pClipRects); - if (ret) { - fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); - goto out; - } - } - - - cmd.bufsz = rmesa->store.cmd_used; - cmd.buf = rmesa->store.cmd_buf; - - if (rmesa->radeon.state.scissor.enabled) { - cmd.nbox = rmesa->radeon.state.scissor.numClipRects; - cmd.boxes = rmesa->radeon.state.scissor.pClipRects; - } else { - cmd.nbox = rmesa->radeon.numClipRects; - cmd.boxes = rmesa->radeon.pClipRects; - } - - ret = drmCommandWrite( rmesa->radeon.dri.fd, - DRM_RADEON_CMDBUF, - &cmd, sizeof(cmd) ); - - if (ret) - fprintf(stderr, "drmCommandWrite: %d\n", ret); - - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__); - radeonWaitForIdleLocked( &rmesa->radeon ); - } - - out: - rmesa->store.primnr = 0; - rmesa->store.statenr = 0; - rmesa->store.cmd_used = 0; - rmesa->dma.nr_released_bufs = 0; - rmesa->save_on_next_emit = 1; - - return ret; -} - - -/* Note: does not emit any commands to avoid recursion on - * radeonAllocCmdBuf. - */ -void radeonFlushCmdBuf( r100ContextPtr rmesa, const char *caller ) -{ - int ret; - - - LOCK_HARDWARE( &rmesa->radeon ); - - ret = radeonFlushCmdBufLocked( rmesa, caller ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if (ret) { - fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret); - exit(ret); - } -} - -/* ============================================================= - * Hardware vertex buffer handling - */ - - -void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa ) -{ - struct radeon_dma_buffer *dmabuf; - int fd = rmesa->radeon.dri.fd; - int index = 0; - int size = 0; - drmDMAReq dma; - int ret; - - if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) { - rmesa->dma.flush( rmesa->radeon.glCtx ); - } - - if (rmesa->dma.current.buf) - radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - - if (rmesa->dma.nr_released_bufs > 4) - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); - - dma.context = rmesa->radeon.dri.hwContext; - dma.send_count = 0; - dma.send_list = NULL; - dma.send_sizes = NULL; - dma.flags = 0; - dma.request_count = 1; - dma.request_size = RADEON_BUFFER_SIZE; - dma.request_list = &index; - dma.request_sizes = &size; - dma.granted_count = 0; - - LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ - - ret = drmDMA( fd, &dma ); - - if (ret != 0) { - /* Free some up this way? - */ - if (rmesa->dma.nr_released_bufs) { - radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); - } - - if (RADEON_DEBUG & DEBUG_DMA) - fprintf(stderr, "Waiting for buffers\n"); - - radeonWaitForIdleLocked( &rmesa->radeon ); - ret = drmDMA( fd, &dma ); - - if ( ret != 0 ) { - UNLOCK_HARDWARE( &rmesa->radeon ); - fprintf( stderr, "Error: Could not get dma buffer... exiting\n" ); - exit( -1 ); - } - } - - UNLOCK_HARDWARE(&rmesa->radeon); - - if (RADEON_DEBUG & DEBUG_DMA) - fprintf(stderr, "Allocated buffer %d\n", index); - - dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); - dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index]; - dmabuf->refcount = 1; - - rmesa->dma.current.buf = dmabuf; - rmesa->dma.current.address = dmabuf->buf->address; - rmesa->dma.current.end = dmabuf->buf->total; - rmesa->dma.current.start = 0; - rmesa->dma.current.ptr = 0; - - rmesa->c_vertexBuffers++; -} - -void radeonReleaseDmaRegion( r100ContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (!region->buf) - return; - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); - - if (--region->buf->refcount == 0) { - drm_radeon_cmd_header_t *cmd; - - if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, - region->buf->buf->idx); - - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd), - __FUNCTION__ ); - cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD; - cmd->dma.buf_idx = region->buf->buf->idx; - FREE(region->buf); - rmesa->dma.nr_released_bufs++; - } - - region->buf = NULL; - region->start = 0; -} - -/* Allocates a region from rmesa->dma.current. If there isn't enough - * space in current, grab a new buffer (and discard what was left of current) - */ -void radeonAllocDmaRegion( r100ContextPtr rmesa, - struct radeon_dma_region *region, - int bytes, - int alignment ) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); - - if (region->buf) - radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ ); - - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; - - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - radeonRefillCurrentDmaRegion( rmesa ); - - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; - region->address = rmesa->dma.current.address; - region->buf = rmesa->dma.current.buf; - region->buf->refcount++; - - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; -} - /* ================================================================ * Buffer clear */ @@ -972,8 +730,8 @@ void radeonFlush( GLcontext *ctx ) if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); radeonEmitState( rmesa ); diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index de3c3a15a7f..471583ab6d1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -49,106 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_maos.h" #include "radeon_tcl.h" -#if 0 -/* Usage: - * - from radeon_tcl_render - * - call radeonEmitArrays to ensure uptodate arrays in dma - * - emit primitives (new type?) which reference the data - * -- need to use elts for lineloop, quads, quadstrip/flat - * -- other primitives are all well-formed (need tristrip-1,fake-poly) - * - */ -static void emit_ubyte_rgba3( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - radeon_color_t *out = (radeon_color_t *)(rvb->start + rvb->address); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p\n", - __FUNCTION__, count, stride, (void *)out); - - for (i = 0; i < count; i++) { - out->red = *data; - out->green = *(data+1); - out->blue = *(data+2); - out->alpha = 0xFF; - out++; - data += stride; - } -} - -static void emit_ubyte_rgba4( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 4) - COPY_DWORDS( out, data, count ); - else - for (i = 0; i < count; i++) { - *out++ = LE32_TO_CPU(*(int *)data); - data += stride; - } -} - - -static void emit_ubyte_rgba( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int size, - int stride, - int count ) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size); - - assert (!rvb->buf); - - if (stride == 0) { - radeonAllocDmaRegion( rmesa, rvb, 4, 4 ); - count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = 1; - } - else { - radeonAllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 1; - rvb->aos_size = 1; - } - - /* Emit the data - */ - switch (size) { - case 3: - emit_ubyte_rgba3( ctx, rvb, data, stride, count ); - break; - case 4: - emit_ubyte_rgba4( ctx, rvb, data, stride, count ); - break; - default: - assert(0); - exit(1); - break; - } -} -#endif - #if defined(USE_X86_ASM) #define COPY_DWORDS( dst, src, nr ) \ do { \ diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index e4829aaeaba..c6a911abef6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -173,7 +173,7 @@ static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK); /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */ - if ( t->base.tObj->Target == GL_TEXTURE_CUBE_MAP ) { + if ( t->base.Target == GL_TEXTURE_CUBE_MAP ) { switch ( minf ) { case GL_NEAREST: case GL_NEAREST_MIPMAP_NEAREST: @@ -244,426 +244,6 @@ static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] ) t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); } - -/** - * Allocate space for and load the mesa images into the texture memory block. - * This will happen before drawing with a new texture, or drawing with a - * texture after it was swapped out or teximaged again. - */ - -static radeonTexObjPtr radeonAllocTexObj( struct gl_texture_object *texObj ) -{ - radeonTexObjPtr t; - - t = CALLOC_STRUCT( radeon_tex_obj ); - texObj->DriverData = t; - if ( t != NULL ) { - if ( RADEON_DEBUG & DEBUG_TEXTURE ) { - fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)texObj, (void *)t ); - } - - /* Initialize non-image-dependent parts of the state: - */ - t->base.tObj = texObj; - t->border_fallback = GL_FALSE; - - t->pp_txfilter = RADEON_BORDER_MODE_OGL; - t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP | - RADEON_TXFORMAT_PERSPECTIVE_ENABLE); - - make_empty_list( & t->base ); - - radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT ); - radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy ); - radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - radeonSetTexBorderColor( t, texObj->_BorderChan ); - } - - return t; -} - - -static const struct gl_texture_format * -radeonChooseTextureFormat( GLcontext *ctx, GLint internalFormat, - GLenum format, GLenum type ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - const GLboolean do32bpt = - ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_32 ); - const GLboolean force16bpt = - ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 ); - (void) format; - - switch ( internalFormat ) { - case 4: - case GL_RGBA: - case GL_COMPRESSED_RGBA: - switch ( type ) { - case GL_UNSIGNED_INT_10_10_10_2: - case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - default: - return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_argb4444; - } - - case 3: - case GL_RGB: - case GL_COMPRESSED_RGB: - switch ( type ) { - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_5_6_5: - case GL_UNSIGNED_SHORT_5_6_5_REV: - return _dri_texformat_rgb565; - default: - return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_rgb565; - } - - case GL_RGBA8: - case GL_RGB10_A2: - case GL_RGBA12: - case GL_RGBA16: - return !force16bpt ? - _dri_texformat_argb8888 : _dri_texformat_argb4444; - - case GL_RGBA4: - case GL_RGBA2: - return _dri_texformat_argb4444; - - case GL_RGB5_A1: - return _dri_texformat_argb1555; - - case GL_RGB8: - case GL_RGB10: - case GL_RGB12: - case GL_RGB16: - return !force16bpt ? _dri_texformat_argb8888 : _dri_texformat_rgb565; - - case GL_RGB5: - case GL_RGB4: - case GL_R3_G3_B2: - return _dri_texformat_rgb565; - - case GL_ALPHA: - case GL_ALPHA4: - case GL_ALPHA8: - case GL_ALPHA12: - case GL_ALPHA16: - case GL_COMPRESSED_ALPHA: - return _dri_texformat_a8; - - case 1: - case GL_LUMINANCE: - case GL_LUMINANCE4: - case GL_LUMINANCE8: - case GL_LUMINANCE12: - case GL_LUMINANCE16: - case GL_COMPRESSED_LUMINANCE: - return _dri_texformat_l8; - - case 2: - case GL_LUMINANCE_ALPHA: - case GL_LUMINANCE4_ALPHA4: - case GL_LUMINANCE6_ALPHA2: - case GL_LUMINANCE8_ALPHA8: - case GL_LUMINANCE12_ALPHA4: - case GL_LUMINANCE12_ALPHA12: - case GL_LUMINANCE16_ALPHA16: - case GL_COMPRESSED_LUMINANCE_ALPHA: - return _dri_texformat_al88; - - case GL_INTENSITY: - case GL_INTENSITY4: - case GL_INTENSITY8: - case GL_INTENSITY12: - case GL_INTENSITY16: - case GL_COMPRESSED_INTENSITY: - return _dri_texformat_i8; - - case GL_YCBCR_MESA: - if (type == GL_UNSIGNED_SHORT_8_8_APPLE || - type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; - else - return &_mesa_texformat_ycbcr_rev; - - case GL_RGB_S3TC: - case GL_RGB4_S3TC: - case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; - - case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; - - case GL_RGBA_S3TC: - case GL_RGBA4_S3TC: - case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; - - case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; - - default: - _mesa_problem(ctx, "unexpected texture format in %s", __FUNCTION__); - return NULL; - } - - return NULL; /* never get here */ -} - - -static void radeonTexImage1D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) radeonAllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D"); - return; - } - } - - /* Note, this will call ChooseTextureFormat */ - _mesa_store_teximage1d(ctx, target, level, internalFormat, - width, border, format, type, pixels, - &ctx->Unpack, texObj, texImage); - - t->dirty_images[0] |= (1 << level); -} - - -static void radeonTexSubImage1D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) radeonAllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage1D"); - return; - } - } - - _mesa_store_texsubimage1d(ctx, target, level, xoffset, width, - format, type, pixels, packing, texObj, - texImage); - - t->dirty_images[0] |= (1 << level); -} - - -static void radeonTexImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - if ( t != NULL ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) radeonAllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D"); - return; - } - } - - /* Note, this will call ChooseTextureFormat */ - _mesa_store_teximage2d(ctx, target, level, internalFormat, - width, height, border, format, type, pixels, - &ctx->Unpack, texObj, texImage); - - t->dirty_images[face] |= (1 << level); -} - - -static void radeonTexSubImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) radeonAllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage2D"); - return; - } - } - - _mesa_store_texsubimage2d(ctx, target, level, xoffset, yoffset, width, - height, format, type, pixels, packing, texObj, - texImage); - - t->dirty_images[face] |= (1 << level); -} - -static void radeonCompressedTexImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid *data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - if ( t != NULL ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) radeonAllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexImage2D"); - return; - } - } - - /* Note, this will call ChooseTextureFormat */ - _mesa_store_compressed_teximage2d(ctx, target, level, internalFormat, width, - height, border, imageSize, data, texObj, texImage); - - t->dirty_images[face] |= (1 << level); -} - - -static void radeonCompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, - GLsizei imageSize, const GLvoid *data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage ) -{ - driTextureObject * t = (driTextureObject *) texObj->DriverData; - GLuint face; - - - /* which cube face or ordinary 2D image */ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - assert( t ); /* this _should_ be true */ - if ( t ) { - driSwapOutTextureObject( t ); - } - else { - t = (driTextureObject *) radeonAllocTexObj( texObj ); - if (!t) { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexSubImage2D"); - return; - } - } - - _mesa_store_compressed_texsubimage2d(ctx, target, level, xoffset, yoffset, width, - height, format, imageSize, data, texObj, texImage); - - t->dirty_images[face] |= (1 << level); -} - #define SCALED_FLOAT_TO_BYTE( x, scale ) \ (((GLuint)((255.0F / scale) * (x))) / 2) @@ -779,40 +359,26 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, t->dirty_state = R100_TEX_ALL; } - -static void radeonBindTexture( GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj ) -{ - if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { - fprintf( stderr, "%s( %p ) unit=%d\n", __FUNCTION__, (void *)texObj, - ctx->Texture.CurrentUnit ); - } - - assert( (target != GL_TEXTURE_1D && target != GL_TEXTURE_2D && - target != GL_TEXTURE_RECTANGLE_NV && target != GL_TEXTURE_CUBE_MAP) || - (texObj->DriverData != NULL) ); -} - - static void radeonDeleteTexture( GLcontext *ctx, struct gl_texture_object *texObj ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - driTextureObject * t = (driTextureObject *) texObj->DriverData; + radeonTexObj* t = radeon_tex_obj(texObj); if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { fprintf( stderr, "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj, _mesa_lookup_enum_by_nr( texObj->Target ) ); } - if ( t != NULL ) { - if ( rmesa ) { - RADEON_FIREVERTICES( rmesa ); - } - - driDestroyTextureObject( t ); + if ( rmesa ) { + RADEON_FIREVERTICES( rmesa ); + } + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + } /* Free mipmap images and the texture object itself */ _mesa_delete_texture_object(ctx, texObj); } @@ -847,16 +413,26 @@ static struct gl_texture_object * radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_texture_object *obj; - obj = _mesa_new_texture_object(ctx, name, target); - if (!obj) - return NULL; - obj->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; - radeonAllocTexObj( obj ); - return obj; + radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); + + _mesa_initialize_texture_object(&t->base, name, target); + t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; + + t->border_fallback = GL_FALSE; + + t->pp_txfilter = RADEON_BORDER_MODE_OGL; + t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP | + RADEON_TXFORMAT_PERSPECTIVE_ENABLE); + + radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT ); + radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy ); + radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter ); + radeonSetTexBorderColor( t, t->base._BorderChan ); + return &t->base; } + void radeonInitTextureFuncs( struct dd_function_table *functions ) { functions->ChooseTextureFormat = radeonChooseTextureFormat; @@ -866,7 +442,7 @@ void radeonInitTextureFuncs( struct dd_function_table *functions ) functions->TexSubImage2D = radeonTexSubImage2D; functions->NewTextureObject = radeonNewTextureObject; - functions->BindTexture = radeonBindTexture; + // functions->BindTexture = radeonBindTexture; functions->DeleteTexture = radeonDeleteTexture; functions->IsTextureResident = driIsTextureResident; @@ -877,5 +453,12 @@ void radeonInitTextureFuncs( struct dd_function_table *functions ) functions->CompressedTexImage2D = radeonCompressedTexImage2D; functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; + functions->GenerateMipmap = radeon_generate_mipmap; + + functions->NewTextureImage = radeonNewTextureImage; + functions->FreeTexImageData = radeonFreeTexImageData; + functions->MapTexture = radeonMapTexture; + functions->UnmapTexture = radeonUnmapTexture; + driInitTextureFormats(); } -- cgit v1.2.3 From c9bb5cd20e5468168d54fe461c853926072fa813 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 20:33:07 +1000 Subject: r200: bring back single dma flush --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 8 ++++---- src/mesa/drivers/dri/r200/r200_context.c | 4 ++-- src/mesa/drivers/dri/r200/r200_context.h | 3 --- src/mesa/drivers/dri/r200/r200_ioctl.c | 13 +++++-------- src/mesa/drivers/dri/r200/r200_ioctl.h | 6 +++--- src/mesa/drivers/dri/r200/r200_swtcl.c | 6 +++--- src/mesa/drivers/dri/r200/r200_tcl.c | 15 ++++++++------- 7 files changed, 25 insertions(+), 30 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index fb8dddad3fa..eba5d6e0198 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -281,8 +281,8 @@ void r200FlushElts(GLcontext *ctx) if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used); - assert( rmesa->tcl.flush == r200FlushElts ); - rmesa->tcl.flush = NULL; + assert( rmesa->radeon.dma.flush == r200FlushElts ); + rmesa->radeon.dma.flush = NULL; elt_used = (elt_used + 2) & ~2; @@ -329,9 +329,9 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, fprintf(stderr, "%s: header prim %x \n", __FUNCTION__, primitive); - assert(!rmesa->tcl.flush); + assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->tcl.flush = r200FlushElts; + rmesa->radeon.dma.flush = r200FlushElts; return retval; } diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 53c64eb5a38..c2b269880c6 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -584,8 +584,8 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200DestroySwtcl( rmesa->radeon.glCtx ); r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); - if (rmesa->dma.current) { - radeonReleaseDmaRegion(rmesa); + if (rmesa->radeon.dma.current) { + radeonReleaseDmaRegion(&rmesa->radeon); rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 80981135ac6..2df0ca12729 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -544,7 +544,6 @@ struct r200_tcl_info { int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; - void (*flush) (GLcontext *ctx); struct radeon_dma_region vertex_data[15]; }; @@ -602,7 +601,6 @@ struct r200_swtcl_info { GLboolean needproj; struct radeon_bo *bo; - void (*flush) (GLcontext *ctx); }; @@ -633,7 +631,6 @@ struct r200_context { /* Vertex buffers */ struct radeon_ioctl ioctl; - struct radeon_dma dma; struct radeon_store store; /* A full state emit as of the first state emit in the main store, in case * the context is lost. diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index cb2f50d5d87..0b7f6644573 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -76,12 +76,12 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) rmesa->radeon.lost_context = GL_FALSE; - nr_released_bufs = rmesa->dma.nr_released_bufs; + nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; saved_store = rmesa->store; - rmesa->dma.nr_released_bufs = 0; + rmesa->radeon.dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); - rmesa->dma.nr_released_bufs = nr_released_bufs; + rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } @@ -302,11 +302,8 @@ void r200Flush( GLcontext *ctx ) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->swtcl.flush) - rmesa->swtcl.flush( ctx ); - - if (rmesa->tcl.flush) - rmesa->tcl.flush( ctx ); + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( ctx ); r200EmitState( rmesa ); diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index ccc15c5b49d..0410fdf3c31 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -112,8 +112,8 @@ void r200SetUpAtomList( r200ContextPtr rmesa ); */ #define R200_NEWPRIM( rmesa ) \ do { \ - if ( rmesa->swtcl.flush ) \ - rmesa->swtcl.flush( rmesa->radeon.glCtx ); \ + if ( rmesa->radeon.dma.flush ) \ + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -153,7 +153,7 @@ static INLINE int R200_DB_STATECHANGE( */ #define R200_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->swtcl.flush || rmesa->tcl.flush ) { \ + if ( rmesa->radeon.dma.flush ) { \ r200Flush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 3142f8b6c94..2a22bd297a4 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -279,7 +279,7 @@ static void flush_last_swtcl_prim(GLcontext *ctx) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - rmesa->swtcl.flush = NULL; + rmesa->radeon.dma.flush = NULL; radeon_bo_unmap(rmesa->swtcl.bo); rcommonEnsureCmdBufSpace(rmesa, @@ -313,9 +313,9 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->swtcl.flush == NULL) { + if (rmesa->radeon.dma.flush == NULL) { rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->swtcl.flush = flush_last_swtcl_prim; + rmesa->radeon.dma.flush = flush_last_swtcl_prim; } return rmesa->swtcl.bo->ptr; diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 9562c8b315f..5bb25bc53a6 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -143,7 +143,7 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { // fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); - if (rmesa->tcl.flush == r200FlushElts && + if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + @@ -154,8 +154,8 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) return dest; } else { - if (rmesa->tcl.flush) - rmesa->tcl.flush( rmesa->radeon.glCtx ); + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); @@ -188,7 +188,8 @@ static void r200EmitPrim( GLcontext *ctx, r200TclPrimitive( ctx, prim, hwprim ); // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); - rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rcommonEnsureCmdBufSpace( &rmesa->radeon, + AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + VBUF_BUFSZ ); r200EmitAOS( rmesa, @@ -564,10 +565,10 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; - if ( rmesa->swtcl.flush ) - rmesa->swtcl.flush( rmesa->radeon.glCtx ); + if ( rmesa->radeon.dma.flush ) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rmesa->swtcl.flush = NULL; + rmesa->radeon.dma.flush = NULL; R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; -- cgit v1.2.3 From 70661f678edcc9b6dd5005016e3355ec4546e716 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 20:46:31 +1000 Subject: WIP comit --- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 22 ++++++ src/mesa/drivers/dri/radeon/common_context.h | 14 ++++ src/mesa/drivers/dri/radeon/common_misc.c | 62 +++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_tcl.c | 7 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 92 ++++++++++++++++++++++++- src/mesa/drivers/dri/radeon/server/radeon_reg.h | 3 + 7 files changed, 195 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 1ce51b21f3a..6ae5868a52c 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -303,7 +303,7 @@ r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); ASSERT( rmesa->radeon.dma.current_used + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current_vertexptr ); + rmesa->radeon.dma.current_vertexptr ); // fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, // rmesa->radeon.dma.current_vertexptr); diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index b4ed153d263..d5dece63551 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -14,6 +14,28 @@ void rcommonBeginBatch(radeonContextPtr rmesa, const char *function, int line); +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + #define CP_PACKET2 (2 << 30) #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 471e7cdfb17..1ed33e2aec5 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -247,6 +247,19 @@ struct radeon_dma { GLuint nr_released_bufs; }; +/* radeon_swtcl.c + */ +struct radeon_swtcl_info { + struct radeon_bo *bo; + + /* Fallback rasterization functions + */ + GLuint hw_primitive; + GLenum render_primitive; + GLuint numverts; + +}; + struct radeon_ioctl { GLuint vertex_offset; GLuint vertex_size; @@ -403,6 +416,7 @@ struct radeon_context { /* Derived state - for r300 only */ struct radeon_state state; + struct radeon_swtcl swtcl; /* Configuration cache */ driOptionCache optionCache; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 3ed58815d33..19294487f64 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2389,4 +2389,66 @@ void radeonReleaseDmaRegion(radeonContextPtr rmesa) radeon_bo_unref(rmesa->dma.current); rmesa->dma.current = NULL; } + +void rcommonEmitVertexAOS(radeonContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) +{ + BATCH_LOCALS(rmesa); + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", + __FUNCTION__, vertex_size, offset); + + BEGIN_BATCH(5); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); + OUT_BATCH(1); + OUT_BATCH(vertex_size | (vertex_size << 8)); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); +} + +void rcommonEmitVbufPrim(radeonContextPtr rmesa, GLuint primitive, GLuint vertex_nr) +{ + BATCH_LOCALS(rmesa); + int type, num_verts; + + type = r300PrimitiveType(rmesa, primitive); + num_verts = r300NumVerts(rmesa, vertex_nr, primitive); + + BEGIN_BATCH(3); + OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); + END_BATCH(); +} + + +/* Alloc space in the current dma region. + */ +static void * +rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) +{ + GLuint bytes = vsize * nverts; + void *head; + + if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) { + radeonRefillCurrentDmaRegion( rmesa, bytes); + } + + if (!rmesa->dma.flush) { + rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->dma.flush = flush_last_swtcl_prim; + } + + ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); + ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); + ASSERT( rmesa->radeon.dma.current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + rmesa->radeon.dma.current_vertexptr ); + +// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, +// rmesa->radeon.dma.current_vertexptr); + head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr); + rmesa->radeon.dma.current_vertexptr += bytes; + rmesa->swtcl.numverts += nverts; + return head; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index b59685790c1..81c0c84257c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -177,18 +177,17 @@ static void radeonEmitPrim( GLcontext *ctx, r100ContextPtr rmesa = R100_CONTEXT( ctx ); radeonTclPrimitive( ctx, prim, hwprim ); - radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rcommonEnsureCmdBufSpace( &rmesa->radeon, + AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rmesa->hw.max_state_size + VBUF_BUFSZ ); radeonEmitAOS( rmesa, - rmesa->tcl.aos_components, rmesa->tcl.nr_aos_components, start ); /* Why couldn't this packet have taken an offset param? */ radeonEmitVbufPrim( rmesa, - rmesa->tcl.vertex_format, rmesa->tcl.hw_primitive, count - start ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 911a0b3a0c5..9ede92b8313 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -122,6 +122,7 @@ tx_table[] = * \param tObj GL texture object whose images are to be posted to * hardware state. */ +#if 0 static void radeonSetTexImages( r100ContextPtr rmesa, struct gl_texture_object *tObj ) { @@ -354,7 +355,7 @@ static void radeonSetTexImages( r100ContextPtr rmesa, /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */ } - +#endif /* ================================================================ @@ -1100,7 +1101,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) return GL_TRUE; } - +#if 0 static void disable_tex( GLcontext *ctx, int unit ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); @@ -1332,9 +1333,89 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit ) FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); return !t->border_fallback; } +#endif + +/** + * Compute the cached hardware register values for the given texture object. + * + * \param rmesa Context pointer + * \param t the r300 texture object + */ +static void setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t) +{ + const struct gl_texture_image *firstImage = + t->base.Image[0][t->mt->firstLevel]; + GLint log2Width, log2Height, log2Depth, texelBytes; + + log2Width = firstImage->WidthLog2; + log2Height = firstImage->HeightLog2; + log2Depth = firstImage->DepthLog2; + texelBytes = firstImage->TexFormat->TexelBytes; + + if (!t->image_override) { + if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + const struct tx_table *table = _mesa_little_endian() ? tx_table_le : + tx_table_be; + + t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | + RADEON_TXFORMAT_ALPHA_IN_MAP); + t->pp_txfilter &= ~RADEON_YUV_TO_RGB; + + // t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; + // t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + } else { + _mesa_problem(NULL, "unexpected texture format in %s", + __FUNCTION__); + return; + } + } + + t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; + t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << RADEON_MAX_MIP_LEVEL_SHIFT; + + t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK | + RADEON_TXFORMAT_HEIGHT_MASK | + RADEON_TXFORMAT_CUBIC_MAP_ENABLE | + RADEON_TXFORMAT_F5_WIDTH_MASK | + RADEON_TXFORMAT_F5_HEIGHT_MASK); + t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) | + (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT)); + + t->tile_bits = 0; + + if (t->base.Target == GL_TEXTURE_CUBE_MAP) { + ASSERT(log2Width == log2Height); + t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) | + (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) | + /* don't think we need this bit, if it exists at all - fglrx does not set it */ + (RADEON_TXFORMAT_CUBIC_MAP_ENABLE)); + t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) | + (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) | + (log2Width << RADEON_FACE_WIDTH_2_SHIFT) | + (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) | + (log2Width << RADEON_FACE_WIDTH_3_SHIFT) | + (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) | + (log2Width << RADEON_FACE_WIDTH_4_SHIFT) | + (log2Height << RADEON_FACE_HEIGHT_4_SHIFT)); + } + t->pp_txsize = (((firstImage->Width - 1) << RADEON_PP_TX_WIDTHMASK_SHIFT) + | ((firstImage->Height - 1) << RADEON_PP_TX_HEIGHTMASK_SHIFT)); + if ( !t->image_override ) { + if (firstImage->IsCompressed) + t->pp_txpitch = (firstImage->Width + 63) & ~(63); + else + t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63); + t->pp_txpitch -= 32; + } + if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { + t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; + } + +} +#if 0 static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) { struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; @@ -1359,6 +1440,13 @@ static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) return GL_TRUE; } } +#endif + +static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) +{ + struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; + +} void radeonUpdateTextureState( GLcontext *ctx ) { diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h index 596a8aa7157..0df634b84db 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h +++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h @@ -2031,6 +2031,9 @@ #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400 +#define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500 +#define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 -- cgit v1.2.3 From 08bb7eedfbba839676ab63fb20dd22e4f27722cb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 23:19:11 +1000 Subject: r200: fix swtcl - slow but works --- src/mesa/drivers/dri/r200/r200_swtcl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 2a22bd297a4..ef725a0efb6 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -310,6 +310,9 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; + if (rmesa->swtcl.flush) + rmesa->swtcl.flush(rmesa->radeon.glCtx); + rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); radeon_bo_map(rmesa->swtcl.bo, 1); @@ -317,6 +320,7 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->radeon.dma.flush = flush_last_swtcl_prim; } + rmesa->swtcl.numverts = nverts; return rmesa->swtcl.bo->ptr; -- cgit v1.2.3 From e45213d89bf26c68c9f4c9074eaec9ab3311de7d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 31 Jan 2009 01:59:57 +1000 Subject: r200/r300: add aperture space checks --- src/mesa/drivers/dri/r200/r200_ioctl.h | 2 + src/mesa/drivers/dri/r200/r200_state.c | 71 ++++++++++++++++- src/mesa/drivers/dri/r200/r200_state.h | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 3 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 8 +- src/mesa/drivers/dri/r300/r300_render.c | 3 + src/mesa/drivers/dri/r300/r300_state.c | 1 - src/mesa/drivers/dri/r300/r300_swtcl.c | 2 + src/mesa/drivers/dri/r300/r300_tex.h | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 53 ++++++++++++- src/mesa/drivers/dri/radeon/common_misc.c | 49 ++++++++++-- src/mesa/drivers/dri/radeon/common_misc.h | 33 ++++++++ src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 65 +++++++++------- src/mesa/drivers/dri/radeon/radeon_bo_legacy.h | 1 + src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 104 ++++++++++++++++++++++++- 15 files changed, 345 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 0410fdf3c31..3e39a9124d2 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -43,6 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" +#include "common_cmdbuf.h" + extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index f2e62d1bf78..f3d809d62cb 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -48,6 +48,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_buffer.h" +#include "radeon_cs.h" +#include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -2347,9 +2349,66 @@ r200UpdateDrawBuffer(GLcontext *ctx) #endif } +static GLboolean r200ValidateBuffers(GLcontext *ctx) +{ + r200ContextPtr rmesa = R200_CONTEXT(ctx); + struct radeon_cs_space_check bos[8]; + struct radeon_renderbuffer *rrb; + int num_bo = 0; + int i; + int flushed = 0, ret; +again: + num_bo = 0; + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + + if (!ctx->Texture.Unit[i]._ReallyEnabled) + continue; + + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + bos[num_bo].bo = t->mt->bo; + bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].write_domain = 0; + bos[num_bo].new_accounted = 0; + num_bo++; + } + + ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) + return GL_FALSE; + if (ret == RADEON_CS_SPACE_FLUSH) { + r200Flush(ctx); + if (flushed) + return GL_FALSE; + flushed = 1; + goto again; + } + return GL_TRUE; +} - -void r200ValidateState( GLcontext *ctx ) +GLboolean r200ValidateState( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); GLuint new_state = rmesa->radeon.NewGLState; @@ -2364,6 +2423,10 @@ void r200ValidateState( GLcontext *ctx ) r200UpdateLocalViewer( ctx ); } + /* we need to do a space check here */ + if (!r200ValidateBuffers(ctx)) + return GL_FALSE; + /* FIXME: don't really need most of these when vertex progs are enabled */ /* Need an event driven matrix update? @@ -2408,6 +2471,7 @@ void r200ValidateState( GLcontext *ctx ) } rmesa->radeon.NewGLState = 0; + return GL_TRUE; } @@ -2452,7 +2516,8 @@ static void r200WrapRunPipeline( GLcontext *ctx ) /* Validate state: */ if (rmesa->radeon.NewGLState) - r200ValidateState( ctx ); + if (!r200ValidateState( ctx )) + FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE); has_material = !ctx->VertexProgram._Enabled && ctx->Light.Enabled && check_material( ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h index 741bf88e9c2..1dddbfdbfed 100644 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ b/src/mesa/drivers/dri/r200/r200_state.h @@ -47,7 +47,7 @@ extern void r200UpdateViewportOffset( GLcontext *ctx ); extern void r200UpdateWindow( GLcontext *ctx ); extern void r200UpdateDrawBuffer(GLcontext *ctx); -extern void r200ValidateState( GLcontext *ctx ); +extern GLboolean r200ValidateState( GLcontext *ctx ); extern void r200PrintDirty( r200ContextPtr rmesa, const char *msg ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 5bb25bc53a6..3c19e330f5c 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -406,7 +406,8 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Validate state: */ if (rmesa->radeon.NewGLState) - r200ValidateState( ctx ); + if (!r200ValidateState( ctx )) + return GL_TRUE; /* fallback to sw t&l */ if (!ctx->VertexProgram._Enabled) { /* NOTE: inputs != tnl->render_inputs - these are the untransformed diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 04bb76bb301..90989316022 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -296,12 +296,8 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; - GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate; - rrb = r300->radeon.state.color.rrb; - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } + rrb = radeon_get_colorbuffer(&r300->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; @@ -331,7 +327,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) struct radeon_renderbuffer *rrb; uint32_t zbpitch; - rrb = r300->radeon.state.depth.rrb; + rrb = radeon_get_depthbuffer(&r300->radeon); if (!rrb) return; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 57249c46ef8..3b00de2b562 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -501,6 +501,9 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, return GL_TRUE; } + if (!r300ValidateTextures(ctx)) + return GL_TRUE; + r300UpdateShaders(rmesa); vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 5fbd5b93ff8..e5939afeeb3 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2632,7 +2632,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) GLcontext *ctx; ctx = rmesa->radeon.glCtx; - r300ValidateTextures(ctx); r300SetEarlyZState(ctx); GLuint fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 6ae5868a52c..ef65fbb127a 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -579,6 +579,8 @@ static void r300RenderStart(GLcontext *ctx) r300ChooseRenderState(ctx); r300SetVertexFormat(ctx); + r300ValidateTextures(ctx); + r300UpdateShaders(rmesa); r300UpdateShaderStates(rmesa); diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h index 358b927828c..a293ccf02ca 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ b/src/mesa/drivers/dri/r300/r300_tex.h @@ -41,7 +41,7 @@ extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); -extern void r300ValidateTextures(GLcontext * ctx); +extern GLboolean r300ValidateTextures(GLcontext * ctx); extern void r300InitTextureFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 68c7ca3d29f..7ffc15fe39d 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -49,6 +49,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "radeon_ioctl.h" #include "radeon_mipmap_tree.h" +#include "radeon_cs.h" #include "r300_tex.h" #include "r300_reg.h" #include "radeon_buffer.h" @@ -265,13 +266,43 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object /** - * Ensure all enabled and complete textures are uploaded. + * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ -void r300ValidateTextures(GLcontext * ctx) +GLboolean r300ValidateBuffers(GLcontext * ctx) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); + struct radeon_cs_space_check bos[16]; + struct radeon_renderbuffer *rrb; + int num_bo = 0; int i; + int flushed = 0, ret; +again: + num_bo = 0; + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; @@ -280,7 +311,25 @@ void r300ValidateTextures(GLcontext * ctx) "failed to validate texture for unit %d.\n", i); } + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + bos[num_bo].bo = t->mt->bo; + bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].write_domain = 0; + bos[num_bo].new_accounted = 0; + num_bo++; } + + ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) + return GL_FALSE; + if (ret == RADEON_CS_SPACE_FLUSH) { + r300Flush(ctx); + if (flushed) + return GL_FALSE; + flushed = 1; + goto again; + } + return GL_TRUE; } void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 19294487f64..1adcefb19a1 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -685,6 +685,14 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) assert(rmesa->cmdbuf.cs != NULL); rmesa->cmdbuf.size = size; + if (!rmesa->radeonScreen->kernel_mm) { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } else { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } + } /** * Destroy the command buffer @@ -907,7 +915,7 @@ void radeonCleanupContext(radeonContextPtr radeon) } } -void +static void radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, GLframebuffer *draw) { @@ -1314,7 +1322,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); uint32_t *out; - uint32_t bo_size; if (stride == 0) { radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); @@ -1328,7 +1335,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, aos->components = size; aos->count = count; -// radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: radeonEmitVec4(out, data, stride, count); break; @@ -1339,7 +1345,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, assert(0); break; } -// radeon_bo_unmap(aos->bo); } @@ -2320,6 +2325,9 @@ void radeonSpanRenderFinish(GLcontext * ctx) void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) { + struct radeon_cs_space_check bos[1]; + int flushed, ret; + size = MAX2(size, MAX_DMA_BUF_SZ * 16); if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) @@ -2330,8 +2338,6 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) rmesa->dma.flush(rmesa->glCtx); } - - if (rmesa->dma.nr_released_bufs > 4) { rcommonFlushCmdBuf(rmesa, __FUNCTION__); rmesa->dma.nr_released_bufs = 0; @@ -2341,13 +2347,42 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) radeon_bo_unref(rmesa->dma.current); rmesa->dma.current = 0; } - + +again_alloc: rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom, 0, size, 4, RADEON_GEM_DOMAIN_GTT, 0); + if (!rmesa->dma.current) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + rmesa->dma.nr_released_bufs = 0; + goto again_alloc; + } + rmesa->dma.current_used = 0; rmesa->dma.current_vertexptr = 0; + + bos[0].bo = rmesa->dma.current; + bos[0].read_domains = RADEON_GEM_DOMAIN_GTT; + bos[0].write_domain =0 ; + bos[0].new_accounted = 0; + +again: + ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) { + fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen"); + assert(0); + } else if (ret == RADEON_CS_SPACE_FLUSH) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + if (flushed) { + fprintf(stderr,"flushed but still no space\n"); + assert(0); + } + flushed = 1; + goto again; + } + + radeon_bo_map(rmesa->dma.current, 1); } diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index d17d1607db1..44e464eb139 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -2,6 +2,7 @@ #define COMMON_MISC_H #include "common_context.h" +#include "radeon_buffer.h" void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); @@ -122,4 +123,36 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size); void radeonAllocDmaRegion(radeonContextPtr rmesa, struct radeon_bo **pbo, int *poffset, int bytes, int alignment); +void radeonReleaseDmaRegion(radeonContextPtr rmesa); + +void rcommon_flush_last_swtcl_prim(GLcontext *ctx); + +void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); + + +static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; + rrb = rmesa->state.depth.rrb; + if (!rrb) + return NULL; + + return rrb; +} + +static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; + GLframebuffer *fb = rmesa->dri.drawable->driverPrivate; + + rrb = rmesa->state.color.rrb; + if (rmesa->radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb) + return NULL; + return rrb; +} + + #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index bd126c026cc..f782d96900c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -413,10 +413,8 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, r = bo_dma_alloc(&(bo_legacy->base)); if (r) { if (legacy_wait_any_pending(boml) == -1) { - fprintf(stderr, "Ran out of GART memory (for %d)!\n", size); - fprintf(stderr, "Please consider adjusting GARTSize option.\n"); bo_free(bo_legacy); - exit(-1); + return NULL; } goto retry; return NULL; @@ -639,6 +637,24 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom) free(boml); } +static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy *bom, + int size, uint32_t offset) +{ + struct bo_legacy *bo; + + bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); + if (bo == NULL) + return NULL; + bo->static_bo = 1; + bo->offset = offset + bom->fb_location; + bo->base.handle = bo->offset; + bo->ptr = bom->screen->driScreen->pFB + offset; + if (bo->base.handle > bom->nhandle) { + bom->nhandle = bo->base.handle + 1; + } + return bo; +} + struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *scrn) { struct bo_manager_legacy *bom; @@ -682,41 +698,30 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc /* biggest framebuffer size */ size = 4096*4096*4; + /* allocate front */ - bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); - if (bo == NULL) { + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset); + if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } if (scrn->sarea->tiling_enabled) { bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; } - bo->static_bo = 1; - bo->offset = bom->screen->frontOffset + bom->fb_location; - bo->base.handle = bo->offset; - bo->ptr = scrn->driScreen->pFB + bom->screen->frontOffset; - if (bo->base.handle > bom->nhandle) { - bom->nhandle = bo->base.handle + 1; - } + /* allocate back */ - bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); - if (bo == NULL) { + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset); + if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } if (scrn->sarea->tiling_enabled) { bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; } - bo->static_bo = 1; - bo->offset = bom->screen->backOffset + bom->fb_location; - bo->base.handle = bo->offset; - bo->ptr = scrn->driScreen->pFB + bom->screen->backOffset; - if (bo->base.handle > bom->nhandle) { - bom->nhandle = bo->base.handle + 1; - } + /* allocate depth */ - bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); - if (bo == NULL) { + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset); + if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } @@ -725,13 +730,6 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc bo->base.flags |= RADEON_BO_FLAGS_MACRO_TILE; bo->base.flags |= RADEON_BO_FLAGS_MICRO_TILE; } - bo->static_bo = 1; - bo->offset = bom->screen->depthOffset + bom->fb_location; - bo->base.handle = bo->offset; - bo->ptr = scrn->driScreen->pFB + bom->screen->depthOffset; - if (bo->base.handle > bom->nhandle) { - bom->nhandle = bo->base.handle + 1; - } return (struct radeon_bo_manager*)bom; } @@ -750,3 +748,10 @@ unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo) } return bo->size; } + +int radeon_legacy_bo_is_static(struct radeon_bo *bo) +{ + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + return bo_legacy->static_bo; +} + diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h index 208171e3720..575979cbecc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h @@ -44,4 +44,5 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom); void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom); unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo); +int radeon_legacy_bo_is_static(struct radeon_bo *bo); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 8997187d62b..171818db37c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -315,7 +315,7 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } - dump_cmdbuf(cs); + // dump_cmdbuf(cs); r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { @@ -330,6 +330,10 @@ static int cs_emit(struct radeon_cs *cs) } } cs_set_age(cs); + + cs->csm->read_used = 0; + cs->csm->vram_write_used = 0; + cs->csm->gart_write_used = 0; return 0; } @@ -374,6 +378,101 @@ static void cs_print(struct radeon_cs *cs, FILE *file) { } +static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo) +{ + struct radeon_cs_manager *csm = cs->csm; + int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0; + uint32_t read_domains, write_domain; + int i; + struct radeon_bo *bo; + + /* check the totals for this operation */ + + if (num_bo == 0) + return 0; + + /* prepare */ + for (i = 0; i < num_bo; i++) { + bo = bos[i].bo; + + bos[i].new_accounted = 0; + read_domains = bos[i].read_domains; + write_domain = bos[i].write_domain; + + /* pinned bos don't count */ + if (radeon_legacy_bo_is_static(bo)) + continue; + + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) + continue; + + if (read_domains && ((read_domains << 16) == bo->space_accounted)) + continue; + + if (bo->space_accounted == 0) { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + this_op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + this_op_gart_write += bo->size; + else + this_op_read += bo->size; + bos[i].new_accounted = (read_domains << 16) | write_domain; + } else { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) { + bos[i].new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) { + this_op_read -= bo->size; + this_op_vram_write += bo->size; + } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) { + this_op_read -= bo->size; + this_op_gart_write += bo->size; + } + } else if (read_domains & old_write) { + bos[i].new_accounted = bo->space_accounted & 0xffff; + } else { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } + } + + if (this_op_read < 0) + this_op_read = 0; + + /* check sizes - operation first */ + if ((this_op_read + this_op_gart_write > csm->gart_limit) || + (this_op_vram_write > csm->vram_limit)) { + return RADEON_CS_SPACE_OP_TO_BIG; + } + + if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) || + ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) { + return RADEON_CS_SPACE_FLUSH; + } + + csm->gart_write_used += this_op_gart_write; + csm->vram_write_used += this_op_vram_write; + csm->read_used += this_op_read; + /* commit */ + for (i = 0; i < num_bo; i++) { + bo = bos[i].bo; + bo->space_accounted = bos[i].new_accounted; + } + + return RADEON_CS_SPACE_OK; +} + static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_create, cs_write_dword, @@ -384,7 +483,8 @@ static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_destroy, cs_erase, cs_need_flush, - cs_print + cs_print, + cs_check_space }; struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) -- cgit v1.2.3 From f68a61d88398fe8eb3eb41b929dcb4483354a81e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 31 Jan 2009 02:00:12 +1000 Subject: r200/r300: swtcl fixups to use old dma buffers on top of BOs --- src/mesa/drivers/dri/r200/r200_context.c | 3 +- src/mesa/drivers/dri/r200/r200_context.h | 30 ----- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 19 ++- src/mesa/drivers/dri/r200/r200_swtcl.c | 113 ++++++------------ src/mesa/drivers/dri/r200/r200_swtcl.h | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 4 +- src/mesa/drivers/dri/r300/r300_context.c | 1 + src/mesa/drivers/dri/r300/r300_context.h | 34 +----- src/mesa/drivers/dri/r300/r300_swtcl.c | 157 ++++++++----------------- src/mesa/drivers/dri/r300/r300_swtcl.h | 1 + src/mesa/drivers/dri/radeon/common_context.h | 38 +++--- src/mesa/drivers/dri/radeon/common_misc.c | 68 +++++------ src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 3 + src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + 14 files changed, 163 insertions(+), 311 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index c2b269880c6..c2b5afc3850 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -297,6 +297,7 @@ static void r200_init_vtbl(radeonContextPtr radeon) radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; radeon->vtbl.emit_state = r200_vtbl_emit_state; + radeon->vtbl.swtcl_flush = r200_swtcl_flush; } @@ -389,7 +390,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->hw.all_dirty = 1; /* Set the maximum texture size small enough that we can guarentee that diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 2df0ca12729..4b7ce5d1efa 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -551,40 +551,12 @@ struct r200_tcl_info { /* r200_swtcl.c */ struct r200_swtcl_info { - GLuint RenderIndex; - - /** - * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is - * installed in the Mesa state vector. - */ - GLuint vertex_size; - - /** - * Attributes instructing the Mesa TCL pipeline where / how to put vertex - * data in the hardware buffer. - */ - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - - /** - * Number of elements of \c ::vertex_attrs that are actually used. - */ - GLuint vertex_attr_count; - /** - * Cached pointer to the buffer where Mesa will store vertex data. - */ - GLubyte *verts; - /* Fallback rasterization functions - */ radeon_point_func draw_point; radeon_line_func draw_line; radeon_tri_func draw_tri; - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - /** * Offset of the 4UB color data within a hardware (swtcl) vertex. */ @@ -599,8 +571,6 @@ struct r200_swtcl_info { * Should Mesa project vertex data or will the hardware do it? */ GLboolean needproj; - - struct radeon_bo *bo; }; diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 278e00442c8..1bf7ef33f8e 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -75,37 +75,29 @@ static void r200_emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); uint32_t *out; - uint32_t bo_size; int i; int size = 1; - memset(aos, 0, sizeof(struct radeon_aos)); if (stride == 0) { - bo_size = size * 4; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); count = 1; aos->stride = 0; } else { - bo_size = size * count * 4; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); aos->stride = size; } - aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); - aos->offset = 0; + aos->components = size; aos->count = count; - radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); for (i = 0; i < count; i++) { out[0] = r200ComputeFogBlendFactor( ctx, *(GLfloat *)data ); out++; data += stride; } - radeon_bo_unmap(aos->bo); } - - /* Emit any changed arrays to new GART memory, re-emit a packet to * update the arrays. */ @@ -230,6 +222,7 @@ after_emit: rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1; } + radeon_bo_unmap(rmesa->radeon.dma.current); rmesa->tcl.nr_aos_components = nr; } @@ -240,7 +233,9 @@ void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) int i; for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { if (rmesa->tcl.aos[i].bo) { - rmesa->tcl.aos[i].bo = radeon_bo_unref(rmesa->tcl.aos[i].bo); + radeon_bo_unref(rmesa->tcl.aos[i].bo); + rmesa->tcl.aos[i].bo = NULL; } } + radeonReleaseDmaRegion(&rmesa->radeon); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index ef725a0efb6..a39072d1d2b 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -56,27 +56,24 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_tcl.h" -static void flush_last_swtcl_prim( GLcontext *ctx ); - - /*********************************************************************** * Initialization ***********************************************************************/ #define EMIT_ATTR( ATTR, STYLE, F0 ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ fmt_0 |= F0; \ } while (0) #define EMIT_PAD( N ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) static void r200SetVertexFormat( GLcontext *ctx ) @@ -101,7 +98,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - rmesa->swtcl.vertex_attr_count = 0; + rmesa->radeon.swtcl.vertex_attr_count = 0; /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. @@ -194,12 +191,12 @@ static void r200SetVertexFormat( GLcontext *ctx ) rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = fmt_0; rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = fmt_1; - rmesa->swtcl.vertex_size = + rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->swtcl.vertex_attrs, - rmesa->swtcl.vertex_attr_count, + rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); - rmesa->swtcl.vertex_size /= 4; + rmesa->radeon.swtcl.vertex_size /= 4; RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset ); } } @@ -270,63 +267,27 @@ void r200ChooseVertexState( GLcontext *ctx ) } } - -/* Flush vertices in the current dma region. - */ -static void flush_last_swtcl_prim(GLcontext *ctx) +void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->radeon.dma.flush = NULL; - - radeon_bo_unmap(rmesa->swtcl.bo); - rcommonEnsureCmdBufSpace(rmesa, + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size + (12*sizeof(int)), __FUNCTION__); r200EmitState(rmesa); r200EmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - rmesa->swtcl.bo, 0); + rmesa->radeon.swtcl.vertex_size, + rmesa->radeon.dma.current, + current_offset); r200EmitVbufPrim( rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); + rmesa->radeon.swtcl.hw_primitive, + rmesa->radeon.swtcl.numverts); - radeon_bo_unref(rmesa->swtcl.bo); - // COMMIT_BATCH(); - rmesa->swtcl.numverts = 0; } - -/* Alloc space in the current dma region. - */ -static INLINE void * -r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) -{ - GLuint bytes = vsize * nverts; - - if (rmesa->swtcl.flush) - rmesa->swtcl.flush(rmesa->radeon.glCtx); - - rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); - radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->radeon.dma.flush == NULL) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->radeon.dma.flush = flush_last_swtcl_prim; - } - rmesa->swtcl.numverts = nverts; - return rmesa->swtcl.bo->ptr; - - -} - - /**************************************************************************/ @@ -374,11 +335,11 @@ static void r200ResetLineStipple( GLcontext *ctx ); #undef LOCAL_VARS #undef ALLOC_VERTS #define CTX_ARG r200ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size -#define ALLOC_VERTS( n, size ) r200AllocDmaLowVerts( rmesa, n, size * 4 ) +#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size +#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ) #define LOCAL_VARS \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - const char *r200verts = (char *)rmesa->swtcl.verts; + const char *r200verts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int))) #define VERTEX radeonVertex #define DO_DEBUG_VERTS (1 && (R200_DEBUG & DEBUG_VERTS)) @@ -438,7 +399,7 @@ static struct { #define VERT_Y(_v) _v->v.y #define VERT_Z(_v) _v->v.z #define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->swtcl.verts + (e*rmesa->swtcl.vertex_size*sizeof(int))) +#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) #define VERT_SET_RGBA( v, c ) \ do { \ @@ -495,7 +456,7 @@ do { \ ***********************************************************************/ #define RASTERIZE(x) r200RasterPrimitive( ctx, reduced_hw_prim(ctx, x) ) -#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive +#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive #undef TAG #define TAG(x) x #include "tnl_dd/t_dd_unfilled.h" @@ -551,8 +512,8 @@ static void init_rast_tab( void ) #undef LOCAL_VARS #define LOCAL_VARS \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->swtcl.vertex_size; \ - const char *r200verts = (char *)rmesa->swtcl.verts; \ + const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ + const char *r200verts = (char *)rmesa->radeon.swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; @@ -587,7 +548,7 @@ void r200ChooseRenderState( GLcontext *ctx ) if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R200_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= R200_UNFILLED_BIT; - if (index != rmesa->swtcl.RenderIndex) { + if (index != rmesa->radeon.swtcl.RenderIndex) { tnl->Driver.Render.Points = rast_tab[index].points; tnl->Driver.Render.Line = rast_tab[index].line; tnl->Driver.Render.ClippedLine = rast_tab[index].line; @@ -604,7 +565,7 @@ void r200ChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; } - rmesa->swtcl.RenderIndex = index; + rmesa->radeon.swtcl.RenderIndex = index; } } @@ -618,7 +579,7 @@ static void r200RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (rmesa->swtcl.hw_primitive != hwprim) { + if (rmesa->radeon.swtcl.hw_primitive != hwprim) { /* need to disable perspective-correct texturing for point sprites */ if ((hwprim & 0xf) == R200_VF_PRIM_POINT_SPRITES && ctx->Point.PointSprite) { if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) { @@ -631,14 +592,14 @@ static void r200RasterPrimitive( GLcontext *ctx, GLuint hwprim ) rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE; } R200_NEWPRIM( rmesa ); - rmesa->swtcl.hw_primitive = hwprim; + rmesa->radeon.swtcl.hw_primitive = hwprim; } } static void r200RenderPrimitive( GLcontext *ctx, GLenum prim ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - rmesa->swtcl.render_primitive = prim; + rmesa->radeon.swtcl.render_primitive = prim; if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) r200RasterPrimitive( ctx, reduced_hw_prim(ctx, prim) ); } @@ -691,7 +652,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) R200_FIREVERTICES( rmesa ); TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); - rmesa->swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.RenderIndex = ~0; if (R200_DEBUG & DEBUG_FALLBACKS) { fprintf(stderr, "R200 begin rasterization fallback: 0x%x %s\n", bit, getFallbackString(bit)); @@ -776,7 +737,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, vte |= R200_VTX_W0_FMT; vap &= ~R200_VAP_FORCE_W_TO_ONE; - rmesa->swtcl.vertex_size = 5; + rmesa->radeon.swtcl.vertex_size = 5; if ( (rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) || (rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) { @@ -944,10 +905,10 @@ void r200InitSwtcl( GLcontext *ctx ) _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 36 * sizeof(GLfloat) ); - rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->swtcl.RenderIndex = ~0; - rmesa->swtcl.render_primitive = GL_TRIANGLES; - rmesa->swtcl.hw_primitive = 0; + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; + rmesa->radeon.swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; + rmesa->radeon.swtcl.hw_primitive = 0; } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index 91c7c0ff8fc..a4051a4b768 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -66,5 +66,5 @@ extern void r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, const struct gl_pixelstore_attrib *unpack, const GLubyte *bitmap ); - +void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset); #endif diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 3c19e330f5c..494a8f3d7be 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -157,7 +157,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); + rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, 0 ); @@ -190,7 +190,7 @@ static void r200EmitPrim( GLcontext *ctx, // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index f57952d8780..7e707a38b39 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -260,6 +260,7 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; radeon->vtbl.emit_state = r300_vtbl_emit_state; radeon->vtbl.flush_vertices = r300_vtbl_flush_vertices; + radeon->vtbl.swtcl_flush = r300_swtcl_flush; } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 155529a8a67..9e97a136e39 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -658,37 +658,7 @@ struct r300_state { /* r300_swtcl.c */ struct r300_swtcl_info { - GLuint RenderIndex; - - /** - * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is - * installed in the Mesa state vector. - */ - GLuint vertex_size; - - /** - * Attributes instructing the Mesa TCL pipeline where / how to put vertex - * data in the hardware buffer. - */ - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - - /** - * Number of elements of \c ::vertex_attrs that are actually used. - */ - GLuint vertex_attr_count; - - /** - * Cached pointer to the buffer where Mesa will store vertex data. - */ - GLubyte *verts; - - /* Fallback rasterization functions - */ - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - - /** + /* * Offset of the 4UB color data within a hardware (swtcl) vertex. */ GLuint coloroffset; @@ -697,8 +667,6 @@ struct r300_swtcl_info { * Offset of the 3UB specular color data within a hardware (swtcl) vertex. */ GLuint specoffset; - - struct radeon_bo *bo; }; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index ef65fbb127a..73e3c51b9a7 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -57,24 +57,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "r300_emit.h" -static void flush_last_swtcl_prim( GLcontext *ctx); - - void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset); void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr); #define EMIT_ATTR( ATTR, STYLE ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) #define EMIT_PAD( N ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) static void r300SetVertexFormat( GLcontext *ctx ) @@ -112,7 +109,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - rmesa->swtcl.vertex_attr_count = 0; + rmesa->radeon.swtcl.vertex_attr_count = 0; /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. @@ -222,95 +219,20 @@ static void r300SetVertexFormat( GLcontext *ctx ) rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_fmt_1; - rmesa->swtcl.vertex_size = + rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->swtcl.vertex_attrs, - rmesa->swtcl.vertex_attr_count, + rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); - rmesa->swtcl.vertex_size /= 4; + rmesa->radeon.swtcl.vertex_size /= 4; RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset ); R300_STATECHANGE(rmesa, vte); rmesa->hw.vte.cmd[1] = vte; - rmesa->hw.vte.cmd[2] = rmesa->swtcl.vertex_size; -} - - -/* Flush vertices in the current dma region. - */ -static void flush_last_swtcl_prim( GLcontext *ctx ) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct radeon_dma *dma = &rmesa->radeon.dma; - - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - dma->flush = NULL; - - if (dma->current) { - GLuint current_offset = dma->current_used; - - assert (dma->current_used + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - dma->current_vertexptr); - - radeon_bo_unmap(dma->current); - if (dma->current_used != dma->current_vertexptr) { - dma->current_used = dma->current_vertexptr; - - rcommonEnsureCmdBufSpace(rmesa, - rmesa->hw.max_state_size + (12*sizeof(int)), - __FUNCTION__); - r300EmitState(rmesa); - r300EmitVertexAOS(rmesa, - rmesa->swtcl.vertex_size, - dma->current, - current_offset); - - r300EmitVbufPrim(rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - r300EmitCacheFlush(rmesa); - COMMIT_BATCH(); - } - radeonReleaseDmaRegion(&rmesa->radeon); - rmesa->swtcl.numverts = 0; - } -} - -/* Alloc space in the current dma region. - */ -static void * -r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) -{ - GLuint bytes = vsize * nverts; - void *head; - - if (!rmesa->radeon.dma.current || rmesa->radeon.dma.current_vertexptr + bytes > rmesa->radeon.dma.current->size) { - radeonRefillCurrentDmaRegion( &rmesa->radeon, bytes); - } - - if (!rmesa->radeon.dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->radeon.dma.flush = flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->radeon.dma.current_used + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->radeon.dma.current_vertexptr ); - -// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, -// rmesa->radeon.dma.current_vertexptr); - head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr); - rmesa->radeon.dma.current_vertexptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; + rmesa->hw.vte.cmd[2] = rmesa->radeon.swtcl.vertex_size; } static GLuint reduced_prim[] = { @@ -350,11 +272,11 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); #undef LOCAL_VARS #undef ALLOC_VERTS #define CTX_ARG r300ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size -#define ALLOC_VERTS( n, size ) r300AllocDmaLowVerts( rmesa, n, size * 4 ) +#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size +#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ) #define LOCAL_VARS \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const char *r300verts = (char *)rmesa->swtcl.verts; + const char *r300verts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int))) #define VERTEX r300Vertex #define DO_DEBUG_VERTS (1 && (RADEON_DEBUG & DEBUG_VERTS)) @@ -413,7 +335,7 @@ static struct { #define VERT_Y(_v) _v->v.y #define VERT_Z(_v) _v->v.z #define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->swtcl.verts + (e*rmesa->swtcl.vertex_size*sizeof(int))) +#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) /* Only used to pull back colors into vertices (ie, we know color is * floating point). @@ -459,7 +381,7 @@ do { \ ***********************************************************************/ #define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] ) -#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive +#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive #undef TAG #define TAG(x) x #include "tnl_dd/t_dd_unfilled.h" @@ -516,8 +438,8 @@ static void init_rast_tab( void ) #undef LOCAL_VARS #define LOCAL_VARS \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->swtcl.vertex_size; \ - const char *r300verts = (char *)rmesa->swtcl.verts; \ + const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ + const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; @@ -549,7 +471,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT; - if (index != rmesa->swtcl.RenderIndex) { + if (index != rmesa->radeon.swtcl.RenderIndex) { tnl->Driver.Render.Points = rast_tab[index].points; tnl->Driver.Render.Line = rast_tab[index].line; tnl->Driver.Render.ClippedLine = rast_tab[index].line; @@ -566,7 +488,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; } - rmesa->swtcl.RenderIndex = index; + rmesa->radeon.swtcl.RenderIndex = index; } } @@ -598,9 +520,9 @@ static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - if (rmesa->swtcl.hw_primitive != hwprim) { + if (rmesa->radeon.swtcl.hw_primitive != hwprim) { R300_NEWPRIM( rmesa ); - rmesa->swtcl.hw_primitive = hwprim; + rmesa->radeon.swtcl.hw_primitive = hwprim; } } @@ -608,7 +530,7 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - rmesa->swtcl.render_primitive = prim; + rmesa->radeon.swtcl.render_primitive = prim; if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED)) return; @@ -647,10 +569,10 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 48 * sizeof(GLfloat) ); - rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->swtcl.RenderIndex = ~0; - rmesa->swtcl.render_primitive = GL_TRIANGLES; - rmesa->swtcl.hw_primitive = 0; + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; + rmesa->radeon.swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; + rmesa->radeon.swtcl.hw_primitive = 0; _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); @@ -698,3 +620,24 @@ void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); END_BATCH(); } + +void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) +{ + r300ContextPtr rmesa = R300_CONTEXT(ctx); + + rcommonEnsureCmdBufSpace(&rmesa->radeon, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); + r300EmitState(rmesa); + r300EmitVertexAOS(rmesa, + rmesa->radeon.swtcl.vertex_size, + rmesa->radeon.dma.current, + current_offset); + + r300EmitVbufPrim(rmesa, + rmesa->radeon.swtcl.hw_primitive, + rmesa->radeon.swtcl.numverts); + r300EmitCacheFlush(rmesa); + COMMIT_BATCH(); + +} diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index 55df53c1adf..23b4ce34698 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -42,4 +42,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r300InitSwtcl( GLcontext *ctx ); extern void r300DestroySwtcl( GLcontext *ctx ); +extern void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset); #endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 1ed33e2aec5..90abca0bc10 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -11,6 +11,7 @@ #include "radeon_screen.h" #include "radeon_drm.h" #include "dri_util.h" +#include "tnl/t_vertex.h" /* This union is used to avoid warnings/miscompilation with float to uint32_t casts due to strict-aliasing */ @@ -250,13 +251,19 @@ struct radeon_dma { /* radeon_swtcl.c */ struct radeon_swtcl_info { - struct radeon_bo *bo; - /* Fallback rasterization functions - */ - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; + GLuint RenderIndex; + GLuint vertex_size; + GLubyte *verts; + + /* Fallback rasterization functions + */ + GLuint hw_primitive; + GLenum render_primitive; + GLuint numverts; + + struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; + GLuint vertex_attr_count; }; @@ -416,7 +423,7 @@ struct radeon_context { /* Derived state - for r300 only */ struct radeon_state state; - struct radeon_swtcl swtcl; + struct radeon_swtcl_info swtcl; /* Configuration cache */ driOptionCache optionCache; @@ -424,14 +431,15 @@ struct radeon_context { struct radeon_cmdbuf cmdbuf; struct { - void (*get_lock)(radeonContextPtr radeon); - void (*update_viewport_offset)(GLcontext *ctx); - void (*flush)(GLcontext *ctx); - void (*set_all_dirty)(GLcontext *ctx); - void (*update_draw_buffer)(GLcontext *ctx); - void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); - void (*emit_state)(radeonContextPtr rmesa); - void (*flush_vertices)(radeonContextPtr rmesa); + void (*get_lock)(radeonContextPtr radeon); + void (*update_viewport_offset)(GLcontext *ctx); + void (*flush)(GLcontext *ctx); + void (*set_all_dirty)(GLcontext *ctx); + void (*update_draw_buffer)(GLcontext *ctx); + void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); + void (*emit_state)(radeonContextPtr rmesa); + void (*flush_vertices)(radeonContextPtr rmesa); + void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 1adcefb19a1..9044967ac05 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2420,46 +2420,46 @@ void radeonAllocDmaRegion(radeonContextPtr rmesa, void radeonReleaseDmaRegion(radeonContextPtr rmesa) { - rmesa->dma.nr_released_bufs++; - radeon_bo_unref(rmesa->dma.current); + if (rmesa->dma.current) { + rmesa->dma.nr_released_bufs++; + radeon_bo_unref(rmesa->dma.current); + } rmesa->dma.current = NULL; } -void rcommonEmitVertexAOS(radeonContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) + +/* Flush vertices in the current dma region. + */ +void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) { - BATCH_LOCALS(rmesa); + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + struct radeon_dma *dma = &rmesa->dma; + - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", - __FUNCTION__, vertex_size, offset); + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s\n", __FUNCTION__); + dma->flush = NULL; - BEGIN_BATCH(5); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); - OUT_BATCH(1); - OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); -} + if (dma->current) { + GLuint current_offset = dma->current_used; -void rcommonEmitVbufPrim(radeonContextPtr rmesa, GLuint primitive, GLuint vertex_nr) -{ - BATCH_LOCALS(rmesa); - int type, num_verts; + assert (dma->current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + dma->current_vertexptr); - type = r300PrimitiveType(rmesa, primitive); - num_verts = r300NumVerts(rmesa, vertex_nr, primitive); + radeon_bo_unmap(dma->current); + if (dma->current_used != dma->current_vertexptr) { + dma->current_used = dma->current_vertexptr; - BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); - END_BATCH(); + rmesa->vtbl.swtcl_flush(ctx, current_offset); + } + radeonReleaseDmaRegion(rmesa); + rmesa->swtcl.numverts = 0; + } } - - - /* Alloc space in the current dma region. */ -static void * +void * rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; @@ -2471,19 +2471,19 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) if (!rmesa->dma.flush) { rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; + rmesa->dma.flush = rcommon_flush_last_swtcl_prim; } ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->radeon.dma.current_used + + ASSERT( rmesa->dma.flush == rcommon_flush_last_swtcl_prim ); + ASSERT( rmesa->dma.current_used + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->radeon.dma.current_vertexptr ); + rmesa->dma.current_vertexptr ); // fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, // rmesa->radeon.dma.current_vertexptr); - head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr); - rmesa->radeon.dma.current_vertexptr += bytes; + head = (rmesa->dma.current->ptr + rmesa->dma.current_vertexptr); + rmesa->dma.current_vertexptr += bytes; rmesa->swtcl.numverts += nverts; return head; } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 171818db37c..5c6d93f573b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -44,6 +44,8 @@ struct cs_manager_legacy { /* hack for scratch stuff */ uint32_t pending_age; uint32_t pending_count; + + }; struct cs_reloc_legacy { @@ -507,3 +509,4 @@ void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm) { free(csm); } + diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 320bf9244b0..4ff4267348b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1015,6 +1015,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) free(screen); return NULL; } + return screen; } -- cgit v1.2.3 From f4dfafd50acdff994b16946773cbfbefdc172f3e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 2 Feb 2009 12:26:04 +1000 Subject: r300: rename validate textures to validate buffers --- src/mesa/drivers/dri/r300/r300_render.c | 2 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/r300/r300_tex.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 3b00de2b562..8db22b777f1 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -501,7 +501,7 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, return GL_TRUE; } - if (!r300ValidateTextures(ctx)) + if (!r300ValidateBuffers(ctx)) return GL_TRUE; r300UpdateShaders(rmesa); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 73e3c51b9a7..98208cd77e6 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -501,7 +501,7 @@ static void r300RenderStart(GLcontext *ctx) r300ChooseRenderState(ctx); r300SetVertexFormat(ctx); - r300ValidateTextures(ctx); + r300ValidateBuffers(ctx); r300UpdateShaders(rmesa); r300UpdateShaderStates(rmesa); diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h index a293ccf02ca..c4f42ee621c 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ b/src/mesa/drivers/dri/r300/r300_tex.h @@ -41,7 +41,7 @@ extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); -extern GLboolean r300ValidateTextures(GLcontext * ctx); +extern GLboolean r300ValidateBuffers(GLcontext * ctx); extern void r300InitTextureFuncs(struct dd_function_table *functions); -- cgit v1.2.3 From 75762a8219d7db0f7990eab73f953a6a4f9ee130 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 2 Feb 2009 12:26:22 +1000 Subject: radeon: this code forgot to add dPriv x/y back to spans --- src/mesa/drivers/dri/radeon/common_misc.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 9044967ac05..bc84b67f001 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -199,7 +199,7 @@ void radeonUpdateScissor( GLcontext *ctx ) if ( rmesa->dri.drawable ) { __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; - + int x = ctx->Scissor.X; int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; int w = ctx->Scissor.X + ctx->Scissor.Width - 1; @@ -2118,11 +2118,15 @@ GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { GLubyte *ptr = rrb->bo->ptr; + const __DRIdrawablePrivate *dPriv = rrb->dPriv; uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; GLint offset; GLint nmacroblkpl; GLint nmicroblkpl; + x += dPriv->x; + y += dPriv->y; + if (rrb->has_surface || !(rrb->bo->flags & mask)) { offset = x * rrb->cpp + y * rrb->pitch; } else { @@ -2158,11 +2162,15 @@ GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { GLubyte *ptr = rrb->bo->ptr; + const __DRIdrawablePrivate *dPriv = rrb->dPriv; uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; GLint offset; GLint nmacroblkpl; GLint nmicroblkpl; + x += dPriv->x; + y += dPriv->y; + if (rrb->has_surface || !(rrb->bo->flags & mask)) { offset = x * rrb->cpp + y * rrb->pitch; } else { @@ -2198,6 +2206,7 @@ GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { GLubyte *ptr = rrb->bo->ptr; + const __DRIdrawablePrivate *dPriv = rrb->dPriv; uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; GLint offset; GLint microblkxs; @@ -2205,6 +2214,9 @@ GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, GLint nmacroblkpl; GLint nmicroblkpl; + x += dPriv->x; + y += dPriv->y; + if (rrb->has_surface || !(rrb->bo->flags & mask)) { offset = x * rrb->cpp + y * rrb->pitch; } else { -- cgit v1.2.3 From dbf72bdd3dda73384381a9ae8a94b522b7f786c2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Feb 2009 09:48:27 +1000 Subject: radeon_bo: align size of bo to page size. This is really required for the VRAM allocator upload function. --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index f782d96900c..07af01fc402 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -260,6 +260,9 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, uint32_t flags) { struct bo_legacy *bo_legacy; + uint32_t pgsize = getpagesize() - 1; + + size = (size + pgsize) & ~pgsize; bo_legacy = (struct bo_legacy*)calloc(1, sizeof(struct bo_legacy)); if (bo_legacy == NULL) { -- cgit v1.2.3 From d9cf1319252e053a894dd49583064e4cd063d119 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Feb 2009 09:49:45 +1000 Subject: r300: fixup mipmap + texsubimage issues This fixes a few regression in piglit, and adds some debug to the mipmap code --- src/mesa/drivers/dri/r300/r300_tex.c | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 5 +- src/mesa/drivers/dri/radeon/common_misc.c | 60 +++++++++++++++++++----- src/mesa/drivers/dri/radeon/common_misc.h | 2 +- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 5 ++ 5 files changed, 58 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 11e89ffd0f0..989aa462aea 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -334,7 +334,7 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->CompressedTexImage2D = radeonCompressedTexImage2D; functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; - functions->GenerateMipmap = radeon_generate_mipmap; + functions->GenerateMipmap = radeonGenerateMipmap; driInitTextureFormats(); } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 7ffc15fe39d..6e2b1309c5d 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -225,8 +225,9 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) t->pp_txformat |= R300_TX_FORMAT_3D; t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) - | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)) - | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT); + | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT) + | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT) + | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT)); if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { unsigned int align = (64 / t->mt->bpp) - 1; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index bc84b67f001..162057ca9e9 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1476,13 +1476,42 @@ GLuint radeon_face_for_target(GLenum target) * This relies on internal details of _mesa_generate_mipmap, in particular * the fact that the memory for recreated texture images is always freed. */ -void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) +void radeon_generate_mipmap(GLcontext *ctx, GLenum target, + struct gl_texture_object *texObj) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; + int i, face; + + + _mesa_generate_mipmap(ctx, target, texObj); + + for (face = 0; face < nr_faces; face++) { + for (i = texObj->BaseLevel + 1; i < texObj->MaxLevel; i++) { + radeon_texture_image *image; + + image = get_radeon_texture_image(texObj->Image[face][i]); + + if (image == NULL) + break; + + image->mtlevel = i; + image->mtface = face; + + radeon_miptree_unreference(image->mt); + image->mt = NULL; + } + } + +} + +void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) { GLuint face = radeon_face_for_target(target); radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); radeon_teximage_map(baseimage, GL_FALSE); - _mesa_generate_mipmap(ctx, target, texObj); + radeon_generate_mipmap(ctx, target, texObj); radeon_teximage_unmap(baseimage); } @@ -1803,15 +1832,17 @@ static void radeon_teximage( _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); } - radeon_teximage_unmap(image); } - _mesa_unmap_teximage_pbo(ctx, packing); - /* SGIS_generate_mipmap */ if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); + radeon_generate_mipmap(ctx, texObj->Target, texObj); } + radeon_teximage_unmap(image); + + _mesa_unmap_teximage_pbo(ctx, packing); + + } void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, @@ -1878,13 +1909,15 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, const struct gl_pixelstore_attrib *packing, struct gl_texture_object *texObj, struct gl_texture_image *texImage, - int compressed) + int compressed) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); rmesa->vtbl.flush_vertices(rmesa); + t->validated = GL_FALSE; pixels = _mesa_validate_pbo_teximage(ctx, dims, width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); @@ -1896,7 +1929,7 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { - dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; + dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes; } if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, @@ -1908,15 +1941,18 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, format, type, pixels, packing)) _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); - radeon_teximage_unmap(image); - } - _mesa_unmap_teximage_pbo(ctx, packing); + } /* GL_SGIS_generate_mipmap */ if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj); + radeon_generate_mipmap(ctx, texObj->Target, texObj); } + radeon_teximage_unmap(image); + + _mesa_unmap_teximage_pbo(ctx, packing); + + } void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 44e464eb139..9bb1d03a097 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -42,7 +42,7 @@ void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable); void radeon_teximage_unmap(radeon_texture_image *image); void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); -void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); +void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); GLuint radeon_face_for_target(GLenum target); const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 955d4b71ed5..323726c5749 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -101,6 +101,11 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, *curOffset = (*curOffset + 0x1f) & ~0x1f; lvl->faces[face].offset = *curOffset; *curOffset += lvl->size; + + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, + "level %d, face %d: rs:%d %dx%d at %d\n", + level, face, lvl->rowstride, lvl->width, lvl->height, lvl->faces[face].offset); } static GLuint minify(GLuint size, GLuint levels) -- cgit v1.2.3 From 4c078cfbad82126108081350b9326228aa2da46d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Feb 2009 12:38:31 +1000 Subject: radeon: add a reference to the static buffers so they don't get deleted --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 07af01fc402..71fe27609b3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -655,6 +655,7 @@ static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy if (bo->base.handle > bom->nhandle) { bom->nhandle = bo->base.handle + 1; } + radeon_bo_ref(&(bo->base)); return bo; } -- cgit v1.2.3 From e8f575d657c5a363a4bf090b3b4fd219cce218ae Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 11:13:54 +1000 Subject: radeon_cs: move to inline cs_write_dword this gets back some of the CPU this was wasting --- src/mesa/drivers/dri/r300/r300_context.c | 34 ++++++++++++------------- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 35 +++++++++++--------------- 2 files changed, 31 insertions(+), 38 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 7e707a38b39..ba784e8c903 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -214,34 +214,32 @@ static void r300_vtbl_emit_state(radeonContextPtr rmesa) r300EmitState((r300ContextPtr)rmesa); } -extern int cs_write_dword(struct radeon_cs *cs, uint32_t dword); - static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { /* please flush pipe do all pending work */ - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_SC_SCREENDOOR, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, 0x0); + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_SC_SCREENDOOR, 1)); - cs_write_dword(cs, 0x00FFFFFF); - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, 0x00FFFFFF); + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_SC_HYPERZ, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, 0x0); + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_US_CONFIG, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, 0x0); + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_ZB_CNTL, 1)); - cs_write_dword(cs, 0x0); - cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D)); - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, 0x0); + radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D)); + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1)); - cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, + radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, R300_ZB_ZCACHE_CTLSTAT, 1)); - cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); - cs_write_dword(cs, cmdwait(rmesa->radeonScreen, + radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); + radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D | R300_WAIT_3D_CLEAN)); } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 5c6d93f573b..fe4f90e0b1c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -75,25 +75,6 @@ static struct radeon_cs *cs_create(struct radeon_cs_manager *csm, return cs; } -int cs_write_dword(struct radeon_cs *cs, uint32_t dword) -{ - if (cs->cdw >= cs->ndw) { - uint32_t tmp, *ptr; - tmp = (cs->cdw + 1 + 0x3FF) & (~0x3FF); - ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); - if (ptr == NULL) { - return -ENOMEM; - } - cs->packets = ptr; - cs->ndw = tmp; - } - cs->packets[cs->cdw++] = dword; - if (cs->section) { - cs->section_cdw++; - } - return 0; -} - static int cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, @@ -192,6 +173,21 @@ static int cs_begin(struct radeon_cs *cs, cs->section_file = file; cs->section_func = func; cs->section_line = line; + + + if (cs->cdw + ndw > cs->ndw) { + uint32_t tmp, *ptr; + int num = (ndw > 0x3FF) ? ndw : 0x3FF; + + tmp = (cs->cdw + 1 + num) & (~num); + ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); + if (ptr == NULL) { + return -ENOMEM; + } + cs->packets = ptr; + cs->ndw = tmp; + } + return 0; } @@ -477,7 +473,6 @@ static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bo static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_create, - cs_write_dword, cs_write_reloc, cs_begin, cs_end, -- cgit v1.2.3 From c85a3851b6519c24780e94dea570a72418621189 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 11:14:38 +1000 Subject: radeon: only do the fb read if we are mapping a VRAM object this makes writing the DMA buffers got a lot better --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 71fe27609b3..993bac81243 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -479,7 +479,7 @@ static int bo_map(struct radeon_bo *bo, int write) * framebuffer, but I've found this to be unnecessary. * -- Nicolai Hähnle, June 2008 */ - { + if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) { int p; volatile int *buf = (int*)boml->screen->driScreen->pFB; p = *buf; -- cgit v1.2.3 From 3f59bee43862519e84a52d371fc370cac32ae350 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 11:17:37 +1000 Subject: r200: move to new mipmap interface --- src/mesa/drivers/dri/r200/r200_tex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 7c433cc6b71..52edf7ed0c1 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -519,7 +519,7 @@ void r200InitTextureFuncs( struct dd_function_table *functions ) functions->CompressedTexImage2D = radeonCompressedTexImage2D; functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; - functions->GenerateMipmap = radeon_generate_mipmap; + functions->GenerateMipmap = radeonGenerateMipmap; functions->NewTextureImage = radeonNewTextureImage; functions->FreeTexImageData = radeonFreeTexImageData; -- cgit v1.2.3 From 55c8a79a339668dd661bb8adb615fbcb8075f51a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 11:19:26 +1000 Subject: radeon: add support for stencil buffers + misc debug changes this adds the stencil rb setup, along with misc changes to formatting and debug --- src/mesa/drivers/dri/radeon/common_misc.c | 54 +++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 162057ca9e9..0779feea97f 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -923,7 +923,6 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, struct radeon_renderbuffer *rb; if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->frontOffset, @@ -959,6 +958,18 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; } + if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } } static void @@ -1014,6 +1025,19 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; } + if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } } @@ -1027,6 +1051,9 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) int i, count; GLframebuffer *draw; radeonContextPtr radeon; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); draw = drawable->driverPrivate; screen = context->driScreenPriv; @@ -1168,19 +1195,19 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; radeon->state.depth.rrb = (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + } else { + radeon_make_renderbuffer_current(radeon, dfb); } if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); + fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, dfb, rfb); driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); if (driReadPriv != driDrawPriv) driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeon_make_renderbuffer_current(radeon, dfb); - } + _mesa_make_current(radeon->glCtx, dfb, rfb); @@ -1387,12 +1414,17 @@ void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) radeon_bo_unref(image->bo); image->bo = NULL; } + if (timage->Data) { + _mesa_free_texmemory(timage->Data); + timage->Data = NULL; + } } /* Set Data pointer and additional data for mapped texture image */ static void teximage_set_map_data(radeon_texture_image *image) { radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; image->base.RowStride = lvl->rowstride / image->mt->bpp; } @@ -1430,7 +1462,7 @@ void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeonTexObj* t = radeon_tex_obj(texObj); int face, level; - assert(texObj->_Complete); + // assert(texObj->_Complete); assert(t->mt); radeon_bo_map(t->mt->bo, GL_FALSE); @@ -1445,7 +1477,7 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeonTexObj* t = radeon_tex_obj(texObj); int face, level; - assert(texObj->_Complete); + // assert(texObj->_Complete); assert(t->mt); for(face = 0; face < t->mt->faces; ++face) { @@ -1838,7 +1870,9 @@ static void radeon_teximage( if (level == texObj->BaseLevel && texObj->GenerateMipmap) { radeon_generate_mipmap(ctx, texObj->Target, texObj); } - radeon_teximage_unmap(image); + + if (pixels) + radeon_teximage_unmap(image); _mesa_unmap_teximage_pbo(ctx, packing); @@ -2040,6 +2074,7 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag assert(dstlvl->height == image->base.Height); assert(dstlvl->depth == image->base.Depth); + radeon_bo_map(mt->bo, GL_TRUE); dest = mt->bo->ptr + dstlvl->faces[face].offset; @@ -2054,6 +2089,7 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag assert(srclvl->rowstride == dstlvl->rowstride); radeon_bo_map(image->mt->bo, GL_FALSE); + memcpy(dest, image->mt->bo->ptr + srclvl->faces[face].offset, dstlvl->size); @@ -2133,7 +2169,7 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, " face %i, level %i... ", face, level); + fprintf(stderr, " face %i, level %i... %p vs %p ", face, level, t->mt, image->mt); if (t->mt == image->mt) { if (RADEON_DEBUG & DEBUG_TEXTURE) fprintf(stderr, "OK\n"); -- cgit v1.2.3 From 711cbf30a1ce72338ca9f1c0f71bd530754a4bd9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 13:16:03 +1000 Subject: r300: make dma buffer reuse much more sensible --- src/mesa/drivers/dri/r300/r300_emit.c | 3 --- src/mesa/drivers/dri/radeon/common_misc.c | 8 ++++++-- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index c47f19ea11e..a8592440da5 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -337,8 +337,6 @@ int r300EmitArrays(GLcontext * ctx) rmesa->state.aos_count = nr; - radeon_bo_unmap(rmesa->radeon.dma.current); - return R300_FALLBACK_NONE; } @@ -357,7 +355,6 @@ void r300ReleaseArrays(GLcontext * ctx) rmesa->state.aos[i].bo = NULL; } } - radeonReleaseDmaRegion(&rmesa->radeon); } void r300EmitCacheFlush(r300ContextPtr rmesa) diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 0779feea97f..62650e28929 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -621,6 +621,8 @@ int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller) { int ret; + radeonReleaseDmaRegion(rmesa); + LOCK_HARDWARE(rmesa); ret = rcommonFlushCmdBufLocked(rmesa, caller); UNLOCK_HARDWARE(rmesa); @@ -2418,7 +2420,6 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) fprintf(stderr, "%s\n", __FUNCTION__); if (rmesa->dma.flush) { - radeon_bo_unmap(rmesa->dma.current); rmesa->dma.flush(rmesa->glCtx); } @@ -2504,9 +2505,12 @@ void radeonAllocDmaRegion(radeonContextPtr rmesa, void radeonReleaseDmaRegion(radeonContextPtr rmesa) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %p\n", __FUNCTION__, rmesa->dma.current); if (rmesa->dma.current) { rmesa->dma.nr_released_bufs++; - radeon_bo_unref(rmesa->dma.current); + radeon_bo_unmap(rmesa->dma.current); + radeon_bo_unref(rmesa->dma.current); } rmesa->dma.current = NULL; } -- cgit v1.2.3 From e44effcfcba4591a622e47ee1b4807ddf5789d51 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 13:16:41 +1000 Subject: radeon: call getpagesize once and store in a static --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 993bac81243..a716f1059b9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -260,7 +260,10 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, uint32_t flags) { struct bo_legacy *bo_legacy; - uint32_t pgsize = getpagesize() - 1; + static int pgsize; + + if (pgsize == 0) + pgsize = getpagesize() - 1; size = (size + pgsize) & ~pgsize; -- cgit v1.2.3 From c1a42f5cdc68d8ec2ccae2cd93a1615f5d4ca924 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 23:40:41 +1000 Subject: r200: fixup DMA region stuff --- src/mesa/drivers/dri/r200/r200_context.c | 1 - src/mesa/drivers/dri/r200/r200_maos_arrays.c | 2 -- 2 files changed, 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index c2b5afc3850..7a8c596ecf9 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -586,7 +586,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->radeon.dma.current) { - radeonReleaseDmaRegion(&rmesa->radeon); rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 1bf7ef33f8e..716f9037dd9 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -222,7 +222,6 @@ after_emit: rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1; } - radeon_bo_unmap(rmesa->radeon.dma.current); rmesa->tcl.nr_aos_components = nr; } @@ -237,5 +236,4 @@ void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) rmesa->tcl.aos[i].bo = NULL; } } - radeonReleaseDmaRegion(&rmesa->radeon); } -- cgit v1.2.3 From 0bcac04100f01bb79edacb29384fb535c37413f1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 13:40:48 +1000 Subject: r300: fix swtcl --- src/mesa/drivers/dri/radeon/common_misc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 62650e28929..c87c6f1a648 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2535,13 +2535,11 @@ void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == dma->current_vertexptr); - radeon_bo_unmap(dma->current); if (dma->current_used != dma->current_vertexptr) { dma->current_used = dma->current_vertexptr; rmesa->vtbl.swtcl_flush(ctx, current_offset); } - radeonReleaseDmaRegion(rmesa); rmesa->swtcl.numverts = 0; } } @@ -2554,7 +2552,7 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) void *head; if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) { - radeonRefillCurrentDmaRegion( rmesa, bytes); + radeonRefillCurrentDmaRegion(rmesa, bytes); } if (!rmesa->dma.flush) { -- cgit v1.2.3 From c370776b02806c6c98d1354e3d60d06311dcfb80 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 13:41:05 +1000 Subject: radeon: make generate_mipmap static --- src/mesa/drivers/dri/radeon/common_misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index c87c6f1a648..f2b1213cb42 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1510,8 +1510,8 @@ GLuint radeon_face_for_target(GLenum target) * This relies on internal details of _mesa_generate_mipmap, in particular * the fact that the memory for recreated texture images is always freed. */ -void radeon_generate_mipmap(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj) +static void radeon_generate_mipmap(GLcontext *ctx, GLenum target, + struct gl_texture_object *texObj) { radeonTexObj* t = radeon_tex_obj(texObj); GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; -- cgit v1.2.3 From 88a409fa8e85a45eb71f99e5926340a5fe6a8071 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 15:12:16 +1000 Subject: r300: fix up CS for modesetting - gears under kms works --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 105 ++++++++++++++++-------------- src/mesa/drivers/dri/r300/r300_emit.h | 4 +- src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_render.c | 21 ++++-- src/mesa/drivers/dri/radeon/common_misc.c | 15 +++-- 5 files changed, 82 insertions(+), 67 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 90989316022..779307f5eba 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -185,38 +185,41 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(&r300->radeon); drm_r300_cmd_header_t cmd; - uint32_t addr, ndw, i; - - if (!r300->radeon.radeonScreen->kernel_mm) { - uint32_t dwords; - dwords = (*atom->check) (ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - return; - } - - cmd.u = atom->cmd[0]; - addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; + uint32_t addr, ndw, i; + + if (!r300->radeon.radeonScreen->kernel_mm) { + uint32_t dwords; + dwords = (*atom->check) (ctx, atom); + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + return; + } + + cmd.u = atom->cmd[0]; + addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; ndw = cmd.vpu.count * 4; - if (ndw) { - /* flush processing vertices */ - OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); - OUT_BATCH(0x0); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH((1 << 15) | (1 << 28)); - OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); - OUT_BATCH(0x00FFFFFF); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); - OUT_BATCH(1); - /* write vpu */ - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0)); - OUT_BATCH(addr); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); - for (i = 0; i < ndw; i++) { - OUT_BATCH(atom->cmd[i+1]); - } - } + if (ndw) { + BEGIN_BATCH_NO_AUTOSTATE(11 + ndw); + + /* flush processing vertices */ + OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); + OUT_BATCH(0x0); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH((1 << 15) | (1 << 28)); + OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); + OUT_BATCH(0x00FFFFFF); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); + OUT_BATCH(1); + /* write vpu */ + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0)); + OUT_BATCH(addr); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); + for (i = 0; i < ndw; i++) { + OUT_BATCH(atom->cmd[i+1]); + } + END_BATCH(); + } } void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) @@ -250,12 +253,14 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) ndw = sz * stride; if (ndw) { + BEGIN_BATCH_NO_AUTOSTATE(3 + ndw); OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0)); OUT_BATCH(addr); OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR); for (i = 0; i < ndw; i++) { OUT_BATCH(atom->cmd[i+1]); } + END_BATCH(); } } @@ -269,23 +274,23 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) int i; for(i = 0; i < numtmus; ++i) { - BEGIN_BATCH(2); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - radeonTexObj *t = r300->hw.textures[i]; - if (t && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!t) { - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); - } else { - if (t->bo) { - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - OUT_BATCH(t->override_offset); - } - } - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); + radeonTexObj *t = r300->hw.textures[i]; + if (t && !t->image_override) { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else if (!t) { + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + } else { + if (t->bo) { + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH(t->override_offset); + } + } + END_BATCH(); } } } @@ -312,7 +317,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R300_COLOR_TILE_ENABLE; - BEGIN_BATCH(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); @@ -339,7 +344,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) zbpitch |= R300_DEPTHMICROTILE_TILED; } - BEGIN_BATCH(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index d6df2e9edf0..94b0a7ebe80 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -136,10 +136,10 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ R300_CMD_PACKET3_RAW)); \ - }\ + } else b_l_rmesa->cmdbuf.cs->section_cdw++;\ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } while(0) diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index b0a579bf840..f07252fbe24 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -99,7 +99,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, if (flags & CLEARBUFFER_COLOR) { assert(rrb != 0); - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); @@ -115,7 +115,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ cbpitch |= R300_DEPTHMICROTILE_TILED; } - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 8db22b777f1..7af9691cdee 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -229,12 +229,12 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); - BEGIN_BATCH(sz+2); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); - OUT_BATCH(nr); - if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH(sz+2); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->state.aos[i].components << 0) | (rmesa->state.aos[i].stride << 8) | @@ -246,10 +246,10 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH_RELOC(voffset, rmesa->state.aos[i].bo, voffset, - RADEON_GEM_DOMAIN_GTT, + RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + offset * 4 * rmesa->state.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, rmesa->state.aos[i+1].bo, voffset, @@ -268,7 +268,13 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) RADEON_GEM_DOMAIN_GTT, 0, 0); } + END_BATCH(); } else { + + BEGIN_BATCH(sz+2+(nr * 2)); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->state.aos[i].components << 0) | (rmesa->state.aos[i].stride << 8) | @@ -312,8 +318,9 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) RADEON_GEM_DOMAIN_GTT, 0, 0); } + END_BATCH(); } - END_BATCH(); + } static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index f2b1213cb42..ec530071222 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -691,8 +691,13 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); } else { - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + struct drm_radeon_gem_info mminfo; + + if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) + { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_size); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size); + } } } @@ -2412,7 +2417,7 @@ void radeonSpanRenderFinish(GLcontext * ctx) void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) { struct radeon_cs_space_check bos[1]; - int flushed, ret; + int flushed = 0, ret; size = MAX2(size, MAX_DMA_BUF_SZ * 16); @@ -2464,10 +2469,8 @@ again: assert(0); } flushed = 1; - goto again; + goto again_alloc; } - - radeon_bo_map(rmesa->dma.current, 1); } -- cgit v1.2.3 From b584b0728d3a001a142f76dde22f9e8ed7d2dd16 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 15:58:08 +1000 Subject: radeon: make compile again. Not tested but ripped out lots of stuff unneeded anymore time to test later --- src/mesa/drivers/dri/radeon/radeon_context.c | 6 +- src/mesa/drivers/dri/radeon/radeon_context.h | 19 +-- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 2 +- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 109 +++++---------- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 55 ++++---- src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 10 +- src/mesa/drivers/dri/radeon/radeon_span.c | 136 ++++--------------- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 168 ++++++++---------------- src/mesa/drivers/dri/radeon/radeon_swtcl.h | 2 +- src/mesa/drivers/dri/radeon/radeon_tcl.c | 24 ++-- src/mesa/drivers/dri/radeon/radeon_tex.c | 3 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 21 +-- 12 files changed, 181 insertions(+), 374 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 6b91bdce9cf..aa1cd5e300d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -54,6 +54,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" #include "radeon_context.h" +#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_span.h" @@ -243,6 +244,7 @@ static void r100_init_vtbl(radeonContextPtr radeon) radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; radeon->vtbl.emit_state = r100_vtbl_emit_state; + radeon->vtbl.swtcl_flush = r100_swtcl_flush; } /* Create the device specific context. @@ -332,7 +334,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->hw.all_dirty = GL_TRUE; /* Set the maximum texture size small enough that we can guarentee that @@ -512,7 +514,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) radeonReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->radeon.dma.current) { radeonReleaseDmaRegion( &rmesa->radeon ); - radeonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } _mesa_vector4f_free( &rmesa->tcl.ObjClean ); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index ba5c57f1210..6edbaf69107 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -340,7 +340,7 @@ struct r100_state { #define RADEON_CMD_BUF_SZ (8*1024) - +#define R200_ELT_BUF_SZ (8*1024) /* radeon_tcl.c */ struct radeon_tcl_info { @@ -364,18 +364,17 @@ struct radeon_tcl_info { struct radeon_dma_region fog; struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; struct radeon_dma_region norm; + + struct radeon_bo *elt_dma_bo; + int elt_dma_offset; /** Offset into this buffer object, in bytes */ + int elt_used; }; /* radeon_swtcl.c */ -struct radeon_swtcl_info { - GLuint RenderIndex; - GLuint vertex_size; +struct r100_swtcl_info { GLuint vertex_format; - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - GLuint vertex_attr_count; - GLubyte *verts; /* Fallback rasterization functions @@ -384,10 +383,6 @@ struct radeon_swtcl_info { radeon_line_func draw_line; radeon_tri_func draw_tri; - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - /** * Offset of the 4UB color data within a hardware (swtcl) vertex. */ @@ -448,7 +443,7 @@ struct r100_context { /* radeon_swtcl.c */ - struct radeon_swtcl_info swtcl; + struct r100_swtcl_info swtcl; GLboolean using_hyperz; GLboolean texmicrotile; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index fe4f90e0b1c..1c885c1612b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -313,7 +313,7 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } - // dump_cmdbuf(cs); + //dump_cmdbuf(cs); r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index b101668f778..a823c79d6cc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -43,6 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "radeon_context.h" +#include "common_cmdbuf.h" +#include "radeon_cs.h" #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_tcl.h" @@ -186,7 +188,7 @@ void radeonEmitState( r100ContextPtr rmesa ) * for enough space for the case of emitting all state, and inline the * radeonAllocCmdBuf code here without all the checks. */ - radeonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size); + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); dest = rmesa->store.cmd_buf + rmesa->store.cmd_used; /* We always always emit zbs, this is due to a bug found by keithw in @@ -243,8 +245,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ) { - drm_radeon_cmd_header_t *cmd; - + BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); @@ -254,43 +255,16 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, fprintf(stderr, "%s cmd_used/4: %d\n", __FUNCTION__, rmesa->store.cmd_used/4); - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, VBUF_BUFSZ, - __FUNCTION__ ); -#if RADEON_OLD_PACKETS - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM | (3 << 16); - cmd[2].i = rmesa->ioctl.vertex_offset; - cmd[3].i = vertex_nr; - cmd[4].i = vertex_format; - cmd[5].i = (primitive | - RADEON_CP_VC_CNTL_PRIM_WALK_LIST | - RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | - (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); - - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: header 0x%x offt 0x%x vfmt 0x%x vfcntl %x \n", - __FUNCTION__, - cmd[1].i, cmd[2].i, cmd[4].i, cmd[5].i); -#else - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = RADEON_CP_PACKET3_3D_DRAW_VBUF | (1 << 16); - cmd[2].i = vertex_format; - cmd[3].i = (primitive | - RADEON_CP_VC_CNTL_PRIM_WALK_LIST | - RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | - RADEON_CP_VC_CNTL_MAOS_ENABLE | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | - (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); - - - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: header 0x%x vfmt 0x%x vfcntl %x \n", - __FUNCTION__, - cmd[1].i, cmd[2].i, cmd[3].i); -#endif + BEGIN_BATCH(3); + OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 0); + OUT_BATCH(vertex_format); + OUT_BATCH(primitive | + RADEON_CP_VC_CNTL_PRIM_WALK_LIST | + RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | + RADEON_CP_VC_CNTL_MAOS_ENABLE | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | + (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); + END_BATCH(); } @@ -346,35 +320,14 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, radeonEmitState( rmesa ); - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, - ELTS_BUFSZ(min_nr), - __FUNCTION__ ); -#if RADEON_OLD_PACKETS - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM; - cmd[2].i = rmesa->ioctl.vertex_offset; - cmd[3].i = 0xffff; - cmd[4].i = vertex_format; - cmd[5].i = (primitive | - RADEON_CP_VC_CNTL_PRIM_WALK_IND | - RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); - - retval = (GLushort *)(cmd+6); -#else - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = RADEON_CP_PACKET3_3D_DRAW_INDX; - cmd[2].i = vertex_format; - cmd[3].i = (primitive | - RADEON_CP_VC_CNTL_PRIM_WALK_IND | - RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | - RADEON_CP_VC_CNTL_MAOS_ENABLE | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); - - retval = (GLushort *)(cmd+4); -#endif + rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, R200_ELT_BUF_SZ, 4, + RADEON_GEM_DOMAIN_GTT, 0); + rmesa->tcl.elt_dma_offset = 0; + rmesa->tcl.elt_used = min_nr * 2; + + radeon_bo_map(rmesa->tcl.elt_dma_bo, 1); + retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s: header 0x%x vfmt 0x%x prim %x \n", @@ -400,21 +353,19 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa, rmesa->ioctl.vertex_size = vertex_size; rmesa->ioctl.vertex_offset = offset; #else - drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL)) fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", __FUNCTION__, vertex_size, offset); - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, VERT_AOS_BUFSZ, - __FUNCTION__ ); - - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = RADEON_CP_PACKET3_3D_LOAD_VBPNTR | (2 << 16); - cmd[2].i = 1; - cmd[3].i = vertex_size | (vertex_size << 8); - cmd[4].i = offset; + BEGIN_BATCH(5); + OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2); + OUT_BATCH(1); + OUT_BATCH(vertex_size | (vertex_size << 8)); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); +} #endif } diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index b4bc9b11441..87d64fb728f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -153,36 +153,37 @@ do { \ #define VBUF_BUFSZ (4 * sizeof(int)) #endif -/* Ensure that a minimum amount of space is available in the command buffer. - * This is used to ensure atomicity of state updates with the rendering requests - * that rely on them. - * - * An alternative would be to implement a "soft lock" such that when the buffer - * wraps at an inopportune time, we grab the lock, flush the current buffer, - * and hang on to the lock until the critical section is finished and we flush - * the buffer again and unlock. - */ -static INLINE void radeonEnsureCmdBufSpace( r100ContextPtr rmesa, - int bytes ) -{ - if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ) - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); - assert( bytes <= RADEON_CMD_BUF_SZ ); -} -/* Alloc space in the command buffer - */ -static INLINE char *radeonAllocCmdBuf( r100ContextPtr rmesa, - int bytes, const char *where ) +static inline uint32_t cmdpacket3(int cmd_type) { - if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ) - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = cmd_type; + + return (uint32_t)cmd.i; - { - char *head = rmesa->store.cmd_buf + rmesa->store.cmd_used; - rmesa->store.cmd_used += bytes; - return head; - } } +#define OUT_BATCH_PACKET3(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3)); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + +#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP)); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + + #endif /* __RADEON_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 2abf644ef2d..5a0bbaacc9b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -380,8 +380,8 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (rmesa->tcl.indexed_verts.buf) radeonReleaseArrays( ctx, ~0 ); - radeonAllocDmaRegion( rmesa, - &rmesa->tcl.indexed_verts, + radeonAllocDmaRegion( &rmesa->radeon, + 0, &rmesa->tcl.indexed_verts, VB->Count * setup_tab[i].vertex_size * 4, 4); @@ -425,7 +425,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) rmesa->tcl.indexed_verts.start ); rmesa->tcl.vertex_format = setup_tab[i].vertex_format; - rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts ); + // rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts ); rmesa->tcl.indexed_verts.aos_size = setup_tab[i].vertex_size; rmesa->tcl.indexed_verts.aos_stride = setup_tab[i].vertex_size; @@ -444,6 +444,6 @@ void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) _tnl_print_vert_flags( __FUNCTION__, newinputs ); #endif - if (newinputs) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ ); + /// if (newinputs) + /// radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index a850baea296..332a0ca69b1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -59,21 +59,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * information. */ #define LOCAL_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ + const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ - GLubyte *buf = (GLubyte *) drb->flippedData \ - + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \ GLuint p; \ - (void) p; + (void) p; #define LOCAL_DEPTH_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ + const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; \ - GLubyte *buf = (GLubyte *) drb->Base.Data; + GLuint yo = dPriv->y; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -94,7 +91,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) +#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -104,82 +101,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) +#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) #include "spantmp2.h" -/* ================================================================ - * Depth buffer - */ - -/* The Radeon family has depth tiling on all the time, so we have to convert - * the x,y coordinates into the memory bus address (mba) in the same - * manner as the engine. In each case, the linear block address (ba) - * is calculated, and then wired with x and y to produce the final - * memory address. - * The chip will do address translation on its own if the surface registers - * are set up correctly. It is not quite enough to get it working with hyperz - * too... - */ - -static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y) -{ - GLuint pitch = drb->pitch; - if (drb->depthHasSurface) { - return 4 * (x + y * pitch); - } else { - GLuint ba, address = 0; /* a[0..1] = 0 */ - -#ifdef COMPILE_R300 - ba = (y / 8) * (pitch / 8) + (x / 8); -#else - ba = (y / 16) * (pitch / 16) + (x / 16); -#endif - - address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */ - address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */ - address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */ - address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ - - return address; - } -} - -static INLINE GLuint -radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) -{ - GLuint pitch = drb->pitch; - if (drb->depthHasSurface) { - return 2 * (x + y * pitch); - } else { - GLuint ba, address = 0; /* a[0] = 0 */ - - ba = (y / 16) * (pitch / 32) + (x / 32); - - address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */ - address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */ - address |= (x & 0x8) << 4; /* a[7] = x[3] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */ - address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ - - return address; - } -} - /* 16-bit depth buffer functions */ #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d; + *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )); + d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -203,24 +136,25 @@ do { \ #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #endif #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ - do { \ + do { \ d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ _y + yo )) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ - _y + yo )) & 0x00ffffff; + do { \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \ + } while (0) #endif #define TAG(x) radeon##x##_z24_s8 @@ -244,11 +178,11 @@ do { \ #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #endif @@ -262,8 +196,8 @@ do { \ #else #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint tmp = *_ptr; \ d = (tmp & 0xff000000) >> 24; \ } while (0) #endif @@ -271,32 +205,6 @@ do { \ #define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" -/* Move locking out to get reasonable span performance (10x better - * than doing this in HW_LOCK above). WaitForIdle() is the main - * culprit. - */ - -static void radeonSpanRenderStart(GLcontext * ctx) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); -#ifdef COMPILE_R300 - r300ContextPtr r300 = (r300ContextPtr) rmesa; - R300_FIREVERTICES(r300); -#else - r100ContextPtr r100 = (r100ContextPtr) rmesa; - RADEON_FIREVERTICES(r100); -#endif - LOCK_HARDWARE(rmesa); - radeonWaitForIdleLocked(rmesa); -} - -static void radeonSpanRenderFinish(GLcontext * ctx) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - _swrast_flush(ctx); - UNLOCK_HARDWARE(rmesa); -} - void radeonInitSpanFuncs(GLcontext * ctx) { struct swrast_device_driver *swdd = diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index ef89d73bdda..4b49c141a0f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -52,8 +52,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_tcl.h" -static void flush_last_swtcl_prim(GLcontext *ctx); - /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */ /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */ #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */ @@ -64,18 +62,18 @@ static void flush_last_swtcl_prim(GLcontext *ctx); #define EMIT_ATTR( ATTR, STYLE, F0 ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ fmt_0 |= F0; \ } while (0) #define EMIT_PAD( N ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) static GLuint radeon_cp_vc_frmts[3][2] = @@ -106,7 +104,7 @@ static void radeonSetVertexFormat( GLcontext *ctx ) } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - rmesa->swtcl.vertex_attr_count = 0; + rmesa->radeon.swtcl.vertex_attr_count = 0; /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. @@ -208,16 +206,16 @@ static void radeonSetVertexFormat( GLcontext *ctx ) fmt_0 != rmesa->swtcl.vertex_format) { RADEON_NEWPRIM(rmesa); rmesa->swtcl.vertex_format = fmt_0; - rmesa->swtcl.vertex_size = + rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->swtcl.vertex_attrs, - rmesa->swtcl.vertex_attr_count, + rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); - rmesa->swtcl.vertex_size /= 4; + rmesa->radeon.swtcl.vertex_size /= 4; RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset ); if (RADEON_DEBUG & DEBUG_VERTS) fprintf( stderr, "%s: vertex_size= %d floats\n", - __FUNCTION__, rmesa->swtcl.vertex_size); + __FUNCTION__, rmesa->radeon.swtcl.vertex_size); } } @@ -228,9 +226,9 @@ static void radeonRenderStart( GLcontext *ctx ) radeonSetVertexFormat( ctx ); - if (rmesa->dma.flush != 0 && - rmesa->dma.flush != flush_last_swtcl_prim) - rmesa->dma.flush( ctx ); + if (rmesa->radeon.dma.flush != 0 && + rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim) + rmesa->radeon.dma.flush( ctx ); } @@ -281,81 +279,29 @@ void radeonChooseVertexState( GLcontext *ctx ) } } - -/* Flush vertices in the current dma region. - */ -static void flush_last_swtcl_prim(GLcontext *ctx) +void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->dma.flush = NULL; - - if (rmesa->dma.current.buf) { - struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset + - current->buf->buf->idx * RADEON_BUFFER_SIZE + - current->start); - - assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - - assert (current->start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - current->ptr); - - if (rmesa->dma.current.start != rmesa->dma.current.ptr) { - radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ + - rmesa->hw.max_state_size + VBUF_BUFSZ ); - - radeonEmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - current_offset); - - radeonEmitVbufPrim( rmesa, - rmesa->swtcl.vertex_format, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - } - - rmesa->swtcl.numverts = 0; - current->start = current->ptr; - } -} - - -/* Alloc space in the current dma region. - */ -static INLINE void * -radeonAllocDmaLowVerts( r100ContextPtr rmesa, int nverts, int vsize ) -{ - GLuint bytes = vsize * nverts; - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - radeonRefillCurrentDmaRegion( rmesa ); + rcommonEnsureCmdBufSpace(&rmesa->radeon, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); - if (!rmesa->dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; - } - - assert( vsize == rmesa->swtcl.vertex_size * 4 ); - assert( rmesa->dma.flush == flush_last_swtcl_prim ); - assert (rmesa->dma.current.start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current.ptr); + radeonEmitState(rmesa); + radeonEmitVertexAOS( rmesa, + rmesa->radeon.swtcl.vertex_size, + // rmesa->radeon.dma.current, + current_offset); - { - GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr); - rmesa->dma.current.ptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; - } + + radeonEmitVbufPrim( rmesa, + rmesa->swtcl.vertex_format, + rmesa->radeon.swtcl.hw_primitive, + rmesa->radeon.swtcl.numverts); } - /* * Render unclipped vertex buffers by emitting vertices directly to * dma buffers. Use strip/fan hardware primitives where possible. @@ -391,19 +337,19 @@ static INLINE void radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim ) { RADEON_NEWPRIM( rmesa ); - rmesa->swtcl.hw_primitive = hw_prim[prim]; - assert(rmesa->dma.current.ptr == rmesa->dma.current.start); + rmesa->radeon.swtcl.hw_primitive = hw_prim[prim]; + // assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start); } #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx) #define INIT( prim ) radeonDmaPrimitive( rmesa, prim ) #define FLUSH() RADEON_NEWPRIM( rmesa ) -#define GET_CURRENT_VB_MAX_VERTS() \ - (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4)) +#define GET_CURRENT_VB_MAX_VERTS() 10\ +// (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4)) #define GET_SUBSEQUENT_VB_MAX_VERTS() \ - ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4)) + ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4)) #define ALLOC_VERTS( nr ) \ - radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 ) + rcommonAllocDmaLowVerts( &rmesa->radeon, nr, rmesa->radeon.swtcl.vertex_size * 4 ) #define EMIT_VERTS( ctx, j, nr, buf ) \ _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf) @@ -428,7 +374,7 @@ static GLboolean radeon_run_render( GLcontext *ctx, if (rmesa->swtcl.indexed_verts.buf) RELEASE_ELT_VERTS(); - if (rmesa->swtcl.RenderIndex != 0 || + if (rmesa->radeon.swtcl.RenderIndex != 0 || !radeon_dma_validate_render( ctx, VB )) return GL_TRUE; @@ -498,12 +444,12 @@ static void radeonResetLineStipple( GLcontext *ctx ); #undef LOCAL_VARS #undef ALLOC_VERTS #define CTX_ARG r100ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size -#define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 ) +#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size +#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, (size) * 4 ) #undef LOCAL_VARS #define LOCAL_VARS \ r100ContextPtr rmesa = R100_CONTEXT(ctx); \ - const char *radeonverts = (char *)rmesa->swtcl.verts; + const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int))) #define VERTEX radeonVertex #undef TAG @@ -561,7 +507,7 @@ static struct { #define VERT_Y(_v) _v->v.y #define VERT_Z(_v) _v->v.z #define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int))) +#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int))) #define VERT_SET_RGBA( v, c ) \ do { \ @@ -618,7 +564,7 @@ do { \ ***********************************************************************/ #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] ) -#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive +#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive #undef TAG #define TAG(x) x #include "tnl_dd/t_dd_unfilled.h" @@ -675,8 +621,8 @@ static void init_rast_tab( void ) #undef LOCAL_VARS #define LOCAL_VARS \ r100ContextPtr rmesa = R100_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->swtcl.vertex_size; \ - const char *radeonverts = (char *)rmesa->swtcl.verts; \ + const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ + const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; @@ -711,7 +657,7 @@ void radeonChooseRenderState( GLcontext *ctx ) if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT; - if (index != rmesa->swtcl.RenderIndex) { + if (index != rmesa->radeon.swtcl.RenderIndex) { tnl->Driver.Render.Points = rast_tab[index].points; tnl->Driver.Render.Line = rast_tab[index].line; tnl->Driver.Render.ClippedLine = rast_tab[index].line; @@ -728,7 +674,7 @@ void radeonChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; } - rmesa->swtcl.RenderIndex = index; + rmesa->radeon.swtcl.RenderIndex = index; } } @@ -742,16 +688,16 @@ static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - if (rmesa->swtcl.hw_primitive != hwprim) { + if (rmesa->radeon.swtcl.hw_primitive != hwprim) { RADEON_NEWPRIM( rmesa ); - rmesa->swtcl.hw_primitive = hwprim; + rmesa->radeon.swtcl.hw_primitive = hwprim; } } static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - rmesa->swtcl.render_primitive = prim; + rmesa->radeon.swtcl.render_primitive = prim; if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) radeonRasterPrimitive( ctx, reduced_hw_prim[prim] ); } @@ -806,7 +752,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) RADEON_FIREVERTICES( rmesa ); TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); - rmesa->swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.RenderIndex = ~0; if (RADEON_DEBUG & DEBUG_FALLBACKS) { fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n", bit, getFallbackString(bit)); @@ -873,10 +819,10 @@ void radeonInitSwtcl( GLcontext *ctx ) _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, RADEON_MAX_TNL_VERTEX_SIZE); - rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->swtcl.RenderIndex = ~0; - rmesa->swtcl.render_primitive = GL_TRIANGLES; - rmesa->swtcl.hw_primitive = 0; + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; + rmesa->radeon.swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; + rmesa->radeon.swtcl.hw_primitive = 0; } @@ -884,7 +830,7 @@ void radeonDestroySwtcl( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - if (rmesa->swtcl.indexed_verts.buf) - radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + // __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.h b/src/mesa/drivers/dri/radeon/radeon_swtcl.h index e485052ad77..3ada9890b37 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.h +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.h @@ -63,5 +63,5 @@ extern void radeon_translate_vertex( GLcontext *ctx, extern void radeon_print_vertex( GLcontext *ctx, const radeonVertex *v ); - +extern void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 81c0c84257c..a54e471065c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -145,15 +145,15 @@ static GLboolean discrete_prim[0x10] = { static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) { - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr)); radeonEmitAOS( rmesa, - rmesa->tcl.aos_components, - rmesa->tcl.nr_aos_components, 0 ); + rmesa->tcl.aos_components, + rmesa->tcl.nr_aos_components, 0 ); return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, @@ -182,12 +182,14 @@ static void radeonEmitPrim( GLcontext *ctx, rmesa->hw.max_state_size + VBUF_BUFSZ ); radeonEmitAOS( rmesa, + rmesa->tcl.aos_components, rmesa->tcl.nr_aos_components, start ); /* Why couldn't this packet have taken an offset param? */ radeonEmitVbufPrim( rmesa, + 0, rmesa->tcl.hw_primitive, count - start ); } @@ -508,15 +510,15 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial; - if ( rmesa->dma.flush ) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if ( rmesa->radeon.dma.flush ) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rmesa->dma.flush = NULL; + rmesa->radeon.dma.flush = NULL; rmesa->swtcl.vertex_format = 0; - if (rmesa->swtcl.indexed_verts.buf) - radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + // __FUNCTION__ ); if (RADEON_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "Radeon end tcl fallback\n"); diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index c6a911abef6..9ef08fbe68a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/texobj.h" #include "radeon_context.h" +#include "radeon_mipmap_tree.h" #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_swtcl.h" @@ -453,7 +454,7 @@ void radeonInitTextureFuncs( struct dd_function_table *functions ) functions->CompressedTexImage2D = radeonCompressedTexImage2D; functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; - functions->GenerateMipmap = radeon_generate_mipmap; + functions->GenerateMipmap = radeonGenerateMipmap; functions->NewTextureImage = radeonNewTextureImage; functions->FreeTexImageData = radeonFreeTexImageData; diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 9ede92b8313..3c28d70e376 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "radeon_context.h" +#include "radeon_mipmap_tree.h" #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_swtcl.h" @@ -75,10 +76,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \ && (tx_table[f].format != 0xffffffff) ) -static const struct { +struct tx_table { GLuint format, filter; -} -tx_table[] = +}; + +static const struct tx_table tx_table[] = { _ALPHA(RGBA8888), _ALPHA_REV(RGBA8888), @@ -901,13 +903,13 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \ RADEON_TXFORMAT_NON_POWER2) - +#if 0 static void import_tex_obj_state( r100ContextPtr rmesa, int unit, radeonTexObjPtr texobj ) { /* do not use RADEON_DB_STATE to avoid stale texture caches */ - int *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; + uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; RADEON_STATECHANGE( rmesa, tex[unit] ); @@ -955,7 +957,7 @@ static void import_tex_obj_state( r100ContextPtr rmesa, texobj->dirty_state &= ~(1<image_override) { if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { - const struct tx_table *table = _mesa_little_endian() ? tx_table_le : - tx_table_be; + const struct tx_table *table = tx_table; t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | RADEON_TXFORMAT_ALPHA_IN_MAP); @@ -1399,8 +1400,8 @@ static void setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t) (log2Height << RADEON_FACE_HEIGHT_4_SHIFT)); } - t->pp_txsize = (((firstImage->Width - 1) << RADEON_PP_TX_WIDTHMASK_SHIFT) - | ((firstImage->Height - 1) << RADEON_PP_TX_HEIGHTMASK_SHIFT)); + t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT) + | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT)); if ( !t->image_override ) { if (firstImage->IsCompressed) -- cgit v1.2.3 From 8fe61fc5ba70be29b9d7dbdfab45c5434be587fc Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 16:01:41 +1000 Subject: radeon/r200 remove more unused code --- src/mesa/drivers/dri/r200/r200_ioctl.h | 34 ------------------------------ src/mesa/drivers/dri/radeon/radeon_ioctl.c | 15 ++++++------- 2 files changed, 7 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 3e39a9124d2..30b089658d5 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -169,40 +169,6 @@ do { \ #define ELTS_BUFSZ(nr) (12 + nr * 2) #define VBUF_BUFSZ (3 * sizeof(int)) -/* Ensure that a minimum amount of space is available in the command buffer. - * This is used to ensure atomicity of state updates with the rendering requests - * that rely on them. - * - * An alternative would be to implement a "soft lock" such that when the buffer - * wraps at an inopportune time, we grab the lock, flush the current buffer, - * and hang on to the lock until the critical section is finished and we flush - * the buffer again and unlock. - */ -#if 0 -static INLINE void r200EnsureCmdBufSpace( r200ContextPtr rmesa, int bytes ) -{ - if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - rcommonFlushCmdBuf( rmesa, __FUNCTION__ ); - assert( bytes <= R200_CMD_BUF_SZ ); -} - -/* Alloc space in the command buffer - */ -static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa, - int bytes, const char *where ) -{ - char * head; - - if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - r200FlushCmdBuf( rmesa, where ); - - head = rmesa->store.cmd_buf + rmesa->store.cmd_used; - rmesa->store.cmd_used += bytes; - assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); - return head; -} -#endif - static inline uint32_t cmdpacket3(int cmd_type) { drm_radeon_cmd_header_t cmd; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index a823c79d6cc..94e930a1f44 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -60,8 +60,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_IDLE_RETRY 16 -static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, - const char * caller ); static void print_state_atom( struct radeon_state_atom *state ) { @@ -123,7 +121,7 @@ static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa ) saved_store = rmesa->store; rmesa->radeon.dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; - radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } @@ -310,7 +308,6 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint primitive, GLuint min_nr ) { - drm_radeon_cmd_header_t *cmd; GLushort *retval; if (RADEON_DEBUG & DEBUG_IOCTL) @@ -330,15 +327,15 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: header 0x%x vfmt 0x%x prim %x \n", + fprintf(stderr, "%s: header vfmt 0x%x prim %x \n", __FUNCTION__, - cmd[1].i, vertex_format, primitive); + vertex_format, primitive); assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->radeon.dma.flush = radeonFlushElts; - rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; + // rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; return retval; } @@ -424,6 +421,8 @@ void radeonEmitAOS( r100ContextPtr rmesa, #endif } + + /* using already shifted color_fmt! */ void radeonEmitBlit( r100ContextPtr rmesa, /* FIXME: which drmMinor is required? */ GLuint color_fmt, @@ -600,7 +599,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } /* Send current state to the hardware */ - radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); -- cgit v1.2.3 From 0a43603c1c714b4a87b3a282bdf1295ecda31713 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Feb 2009 09:18:15 +1000 Subject: r300: fix some autostate batch setups --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 16 +++++++++++----- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_emit.h | 10 +++++----- src/mesa/drivers/dri/r300/r300_render.c | 4 ++-- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 23 +++++++++++------------ 5 files changed, 30 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 779307f5eba..bbc71575950 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -274,23 +274,29 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) int i; for(i = 0; i < numtmus; ++i) { - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); radeonTexObj *t = r300->hw.textures[i]; if (t && !t->image_override) { + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); + END_BATCH(); } else if (!t) { - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + assert(0); } else { if (t->bo) { + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { + END_BATCH(); + } else if (!r300->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH(t->override_offset); + END_BATCH(); } } - END_BATCH(); } } } diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index a8592440da5..4a18397aa8f 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -361,7 +361,7 @@ void r300EmitCacheFlush(r300ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); - BEGIN_BATCH(4); + BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 94b0a7ebe80..290bd614c52 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -151,9 +151,9 @@ void static INLINE end_3d(r300ContextPtr rmesa) BATCH_LOCALS(&rmesa->radeon); if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH(1); - OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); + END_BATCH(); } } @@ -162,8 +162,8 @@ void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) BATCH_LOCALS(&rmesa->radeon); if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); END_BATCH(); } } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 7af9691cdee..23d068c3399 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -190,7 +190,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) BATCH_LOCALS(&rmesa->radeon); if (vertex_count > 0) { - BEGIN_BATCH(8); + BEGIN_BATCH(10); OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | ((vertex_count + 0) << 16) | @@ -231,7 +231,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH(sz+2); + BEGIN_BATCH(sz+2+(nr * 2)); OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index d5dece63551..071e29ee023 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -71,18 +71,17 @@ void rcommonBeginBatch(radeonContextPtr rmesa, /** * Write a relocated dword to the command buffer. */ -#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ - do { \ - if (0 && offset) {\ - fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ - __FILE__, __FUNCTION__, __LINE__, offset);\ - }\ - radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset);\ - radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ - bo, \ - rd, \ - wd, \ - flags);\ +#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ + do { \ + if (0 && offset) { \ + fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ + __FILE__, __FUNCTION__, __LINE__, offset); \ + } \ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ + radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ + bo, rd, wd, flags); \ + if (!b_l_rmesa->radeonScreen->kernel_mm) \ + b_l_rmesa->cmdbuf.cs->section_cdw += 2; \ } while(0) -- cgit v1.2.3 From 16f4b10170da7f1cae3561cdd2a0b2e3d86cf8de Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Feb 2009 19:36:39 +1000 Subject: radeon: remove unused texmem --- src/mesa/drivers/dri/radeon/radeon_texmem.c | 404 ---------------------------- 1 file changed, 404 deletions(-) delete mode 100644 src/mesa/drivers/dri/radeon/radeon_texmem.c (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c deleted file mode 100644 index 0cf5badf4f4..00000000000 --- a/src/mesa/drivers/dri/radeon/radeon_texmem.c +++ /dev/null @@ -1,404 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation on the rights to use, copy, modify, merge, publish, -distribute, sub license, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR -SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR -IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Kevin E. Martin - * Gareth Hughes - * - */ -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/macros.h" - -#include "radeon_context.h" -#include "radeon_ioctl.h" -#include "radeon_tex.h" - -#include /* for usleep() */ - - -/** - * Destroy any device-dependent state associated with the texture. This may - * include NULLing out hardware state that points to the texture. - */ -void -radeonDestroyTexObj( r100ContextPtr rmesa, radeonTexObjPtr t ) -{ - if ( RADEON_DEBUG & DEBUG_TEXTURE ) { - fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj ); - } - - if ( rmesa != NULL ) { - unsigned i; - - - for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { - if ( t == rmesa->state.texture.unit[i].texobj ) { - rmesa->state.texture.unit[i].texobj = NULL; - } - } - } -} - - -/* ------------------------------------------------------------ - * Texture image conversions - */ - - -static void radeonUploadRectSubImage( r100ContextPtr rmesa, - radeonTexObjPtr t, - struct gl_texture_image *texImage, - GLint x, GLint y, - GLint width, GLint height ) -{ - const struct gl_texture_format *texFormat = texImage->TexFormat; - int blit_format, dstPitch, done; - - switch ( texFormat->TexelBytes ) { - case 1: - blit_format = RADEON_GMC_DST_8BPP_CI; - break; - case 2: - blit_format = RADEON_GMC_DST_16BPP; - break; - case 4: - blit_format = RADEON_GMC_DST_32BPP; - break; - default: - fprintf( stderr, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n", - texFormat->TexelBytes); - return; - } - - t->image[0][0].data = texImage->Data; - - /* Currently don't need to cope with small pitches. - */ - width = texImage->Width; - height = texImage->Height; - dstPitch = t->pp_txpitch + 32; - - { /* FIXME: prefer GART-texturing if possible */ - /* Data not in GART memory, or bad pitch. - */ - for (done = 0; done < height ; ) { - struct radeon_dma_region region; - int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch ); - int src_pitch; - char *tex; - - src_pitch = texImage->RowStride * texFormat->TexelBytes; - - tex = (char *)texImage->Data + done * src_pitch; - - memset(®ion, 0, sizeof(region)); - radeonAllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); - - /* Copy texdata to dma: - */ - if (0) - fprintf(stderr, "%s: src_pitch %d dst_pitch %d\n", - __FUNCTION__, src_pitch, dstPitch); - - if (src_pitch == dstPitch) { - memcpy( region.address + region.start, tex, lines * src_pitch ); - } - else { - char *buf = region.address + region.start; - int i; - for (i = 0 ; i < lines ; i++) { - memcpy( buf, tex, src_pitch ); - buf += dstPitch; - tex += src_pitch; - } - } - - radeonEmitWait( rmesa, RADEON_WAIT_3D ); - - - - /* Blit to framebuffer - */ - radeonEmitBlit( rmesa, - blit_format, - dstPitch, GET_START( ®ion ), - dstPitch, t->bufAddr, - 0, 0, - 0, done, - width, lines ); - - radeonEmitWait( rmesa, RADEON_WAIT_2D ); - - radeonReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); - done += lines; - } - } -} - - -/** - * Upload the texture image associated with texture \a t at the specified - * level at the address relative to \a start. - */ -static void uploadSubImage( r100ContextPtr rmesa, radeonTexObjPtr t, - GLint hwlevel, - GLint x, GLint y, GLint width, GLint height, - GLuint face ) -{ - struct gl_texture_image *texImage = NULL; - GLuint offset; - GLint imageWidth, imageHeight; - GLint ret; - drm_radeon_texture_t tex; - drm_radeon_tex_image_t tmp; - const int level = hwlevel + t->base.firstLevel; - - if ( RADEON_DEBUG & DEBUG_TEXTURE ) { - fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n", - __FUNCTION__, (void *)t, (void *)t->base.tObj, level, width, height, face ); - } - - ASSERT(face < 6); - - /* Ensure we have a valid texture to upload */ - if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) { - _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); - return; - } - - texImage = t->base.tObj->Image[face][level]; - - if ( !texImage ) { - if ( RADEON_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level ); - return; - } - if ( !texImage->Data ) { - if ( RADEON_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ ); - return; - } - - - if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - assert(level == 0); - assert(hwlevel == 0); - if ( RADEON_DEBUG & DEBUG_TEXTURE ) - fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__); - radeonUploadRectSubImage( rmesa, t, texImage, x, y, width, height ); - return; - } - - imageWidth = texImage->Width; - imageHeight = texImage->Height; - - offset = t->bufAddr + t->base.totalSize * face / 6; - - if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { - GLint imageX = 0; - GLint imageY = 0; - GLint blitX = t->image[face][hwlevel].x; - GLint blitY = t->image[face][hwlevel].y; - GLint blitWidth = t->image[face][hwlevel].width; - GLint blitHeight = t->image[face][hwlevel].height; - fprintf( stderr, " upload image: %d,%d at %d,%d\n", - imageWidth, imageHeight, imageX, imageY ); - fprintf( stderr, " upload blit: %d,%d at %d,%d\n", - blitWidth, blitHeight, blitX, blitY ); - fprintf( stderr, " blit ofs: 0x%07x level: %d/%d\n", - (GLuint)offset, hwlevel, level ); - } - - t->image[face][hwlevel].data = texImage->Data; - - /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct. - * NOTE: we're always use a 1KB-wide blit and I8 texture format. - * We used to use 1, 2 and 4-byte texels and used to use the texture - * width to dictate the blit width - but that won't work for compressed - * textures. (Brian) - * NOTE: can't do that with texture tiling. (sroland) - */ - tex.offset = offset; - tex.image = &tmp; - /* copy (x,y,width,height,data) */ - memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) ); - - if (texImage->TexFormat->TexelBytes) { - /* use multi-byte upload scheme */ - tex.height = imageHeight; - tex.width = imageWidth; - tex.format = t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK; - tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1); - tex.offset += tmp.x & ~1023; - tmp.x = tmp.x % 1024; - if (t->tile_bits & RADEON_TXO_MICRO_TILE_X2) { - /* need something like "tiled coordinates" ? */ - tmp.y = tmp.x / (tex.pitch * 128) * 2; - tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes; - tex.pitch |= RADEON_DST_TILE_MICRO >> 22; - } - else { - tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1); - } - if ((t->tile_bits & RADEON_TXO_MACRO_TILE) && - (texImage->Width * texImage->TexFormat->TexelBytes >= 256)) { - /* radeon switches off macro tiling for small textures/mipmaps it seems */ - tex.pitch |= RADEON_DST_TILE_MACRO >> 22; - } - } - else { - /* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is - needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */ - /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed - so the kernel module reads the right amount of data. */ - tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */ - tex.pitch = (BLIT_WIDTH_BYTES / 64); - tex.height = (imageHeight + 3) / 4; - tex.width = (imageWidth + 3) / 4; - switch (t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK) { - case RADEON_TXFORMAT_DXT1: - tex.width *= 8; - break; - case RADEON_TXFORMAT_DXT23: - case RADEON_TXFORMAT_DXT45: - tex.width *= 16; - break; - } - } - - LOCK_HARDWARE( &rmesa->radeon ); - do { - ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE, - &tex, sizeof(drm_radeon_texture_t) ); - } while ( ret == -EAGAIN ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret ); - fprintf( stderr, " offset=0x%08x\n", - offset ); - fprintf( stderr, " image width=%d height=%d\n", - imageWidth, imageHeight ); - fprintf( stderr, " blit width=%d height=%d data=%p\n", - t->image[face][hwlevel].width, t->image[face][hwlevel].height, - t->image[face][hwlevel].data ); - exit( 1 ); - } -} - - -/** - * Upload the texture images associated with texture \a t. This might - * require the allocation of texture memory. - * - * \param rmesa Context pointer - * \param t Texture to be uploaded - * \param face Cube map face to be uploaded. Zero for non-cube maps. - */ - -int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face ) -{ - int numLevels; - - if ( !t || t->base.totalSize == 0 || t->image_override ) - return 0; - - if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { - fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__, - (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize, - t->base.firstLevel, t->base.lastLevel ); - } - - numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - radeonFinish( rmesa->radeon.glCtx ); - } - - LOCK_HARDWARE( &rmesa->radeon ); - - if ( t->base.memBlock == NULL ) { - int heap; - - heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, - (driTextureObject *) t ); - if ( heap == -1 ) { - UNLOCK_HARDWARE( &rmesa->radeon ); - return -1; - } - - /* Set the base offset of the texture image */ - t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] - + t->base.memBlock->ofs; - t->pp_txoffset = t->bufAddr; - - if (!(t->base.tObj->Image[0][0]->IsClientData)) { - /* hope it's safe to add that here... */ - t->pp_txoffset |= t->tile_bits; - } - - /* Mark this texobj as dirty on all units: - */ - t->dirty_state = R100_TEX_ALL; - } - - - /* Let the world know we've used this memory recently. - */ - driUpdateTextureLRU( (driTextureObject *) t ); - UNLOCK_HARDWARE( &rmesa->radeon ); - - - /* Upload any images that are new */ - if (t->base.dirty_images[face]) { - int i; - for ( i = 0 ; i < numLevels ; i++ ) { - if ( (t->base.dirty_images[face] & (1 << (i+t->base.firstLevel))) != 0 ) { - uploadSubImage( rmesa, t, i, 0, 0, t->image[face][i].width, - t->image[face][i].height, face ); - } - } - t->base.dirty_images[face] = 0; - } - - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "%s: Syncing\n", __FUNCTION__ ); - radeonFinish( rmesa->radeon.glCtx ); - } - - return 0; -} -- cgit v1.2.3 From 36d3f3e74a809ad346e981805a2f61710d3a380b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Feb 2009 19:57:55 +1000 Subject: r100: fixup radeon so gears seems to work --- src/mesa/drivers/dri/radeon/Makefile | 3 +- src/mesa/drivers/dri/radeon/common_misc.c | 6 +- src/mesa/drivers/dri/radeon/radeon_context.c | 11 ++- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 104 ++++++++++++------------ src/mesa/drivers/dri/radeon/radeon_state.c | 33 +++----- src/mesa/drivers/dri/radeon/radeon_state_init.c | 2 + 6 files changed, 81 insertions(+), 78 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 2ef3640e1d0..2d00f521a60 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -24,7 +24,8 @@ DRIVER_SOURCES = \ common_lock.c \ common_misc.c \ radeon_bo_legacy.c \ - radeon_cs_legacy.c + radeon_cs_legacy.c \ + radeon_mipmap_tree.c C_SOURCES = \ $(COMMON_SOURCES) \ diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index ec530071222..fbabed19f19 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -752,12 +752,12 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) radeon->radeonScreen->AGPMode; const char* chipname; - - if (IS_R300_CLASS(radeon->radeonScreen)) chipname = "R300"; - else + else if (IS_R200_CLASS(radeon->radeonScreen)) chipname = "R200"; + else + chipname = "R100"; offset = driGetRendererString(buffer, chipname, DRIVER_DATE, agp_mode); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index aa1cd5e300d..1d756bd868b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -235,6 +235,12 @@ static void r100_vtbl_emit_state(radeonContextPtr rmesa) radeonEmitState((r100ContextPtr)rmesa); } +static void r100_vtbl_flush_vertices(radeonContextPtr rmesa) +{ + RADEON_FIREVERTICES(((r100ContextPtr)rmesa)); +} + + static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; @@ -245,6 +251,7 @@ static void r100_init_vtbl(radeonContextPtr radeon) radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; radeon->vtbl.emit_state = r100_vtbl_emit_state; radeon->vtbl.swtcl_flush = r100_swtcl_flush; + radeon->vtbl.flush_vertices = r100_vtbl_flush_vertices; } /* Create the device specific context. @@ -258,7 +265,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r100ContextPtr rmesa; - GLcontext *ctx, *shareCtx; + GLcontext *ctx; int i; int tcl_mode, fthrottle_mode; @@ -313,6 +320,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); make_empty_list( & rmesa->radeon.swapped ); +#if 0 rmesa->radeon.nr_heaps = screen->numTexHeaps; for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa, @@ -328,6 +336,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i], & rmesa->c_textureSwaps ); } +#endif rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, "texture_depth"); if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 94e930a1f44..4ab297c5cee 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -59,19 +59,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_TIMEOUT 512 #define RADEON_IDLE_RETRY 16 - - -static void print_state_atom( struct radeon_state_atom *state ) -{ - int i; - - fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); - - if (RADEON_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < state->cmd_size ; i++) - fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); - -} +#define DEBUG_CMDBUF 0 static void radeonSaveHwState( r100ContextPtr rmesa ) { @@ -90,7 +78,7 @@ static void radeonSaveHwState( r100ContextPtr rmesa ) dest += size; rmesa->backup_store.cmd_used += size; if (RADEON_DEBUG & DEBUG_STATE) - print_state_atom( atom ); + radeon_print_state_atom( atom ); } } @@ -166,6 +154,40 @@ void radeonSetUpAtomList( r100ContextPtr rmesa ) insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt); } +static INLINE void radeonEmitAtoms(r100ContextPtr r100, GLboolean dirty) +{ + BATCH_LOCALS(&r100->radeon); + struct radeon_state_atom *atom; + int dwords; + + /* Emit actual atoms */ + foreach(atom, &r100->hw.atomlist) { + if ((atom->dirty || r100->hw.all_dirty) == dirty) { + dwords = (*atom->check) (r100->radeon.glCtx, atom); + if (dwords) { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + radeon_print_state_atom(atom); + } + if (atom->emit) { + (*atom->emit)(r100->radeon.glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } + } + } + } + + COMMIT_BATCH(); +} + void radeonEmitState( r100ContextPtr rmesa ) { struct radeon_state_atom *atom; @@ -180,6 +202,9 @@ void radeonEmitState( r100ContextPtr rmesa ) rmesa->save_on_next_emit = GL_FALSE; } + if (rmesa->radeon.cmdbuf.cs->cdw) + return; + /* this code used to return here but now it emits zbs */ /* To avoid going across the entire set of states multiple times, just check @@ -195,44 +220,20 @@ void radeonEmitState( r100ContextPtr rmesa ) you get tcl lockups on at least M7/7500 class of chips - airlied */ rmesa->hw.zbs.dirty=1; - if (RADEON_DEBUG & DEBUG_STATE) { - foreach(atom, &rmesa->hw.atomlist) { - if (atom->dirty || rmesa->hw.all_dirty) { - if (atom->check(rmesa->radeon.glCtx, 0)) - print_state_atom(atom); - else - fprintf(stderr, "skip state %s\n", atom->name); - } - } + if (!rmesa->radeon.cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + radeonEmitAtoms(rmesa, GL_FALSE); } - foreach(atom, &rmesa->hw.atomlist) { - if (rmesa->hw.all_dirty) - atom->dirty = GL_TRUE; - if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) && - atom->is_tcl) - atom->dirty = GL_FALSE; - if (atom->dirty) { - dwords = atom->check(rmesa->radeon.glCtx, atom); - if (dwords) { - int size = atom->cmd_size * 4; - - if (atom->emit) { - (*atom->emit)(rmesa->radeon.glCtx, atom); - } else { - memcpy(dest, atom->cmd, size); - dest += size; - rmesa->store.cmd_used += size; - } - atom->dirty = GL_FALSE; - } - } - } + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); - assert(rmesa->store.cmd_used <= RADEON_CMD_BUF_SZ); - + radeonEmitAtoms(rmesa, GL_TRUE); rmesa->hw.is_dirty = GL_FALSE; rmesa->hw.all_dirty = GL_FALSE; + } /* Fire a section of the retained (indexed_verts) buffer as a regular @@ -422,7 +423,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, } - +#if 0 /* using already shifted color_fmt! */ void radeonEmitBlit( r100ContextPtr rmesa, /* FIXME: which drmMinor is required? */ GLuint color_fmt, @@ -487,6 +488,7 @@ void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ) cmd[0].wait.cmd_type = RADEON_CMD_WAIT; cmd[0].wait.flags = flags; } +#endif /* ================================================================ * Buffer clear @@ -681,12 +683,12 @@ void radeonFlush( GLcontext *ctx ) fprintf(stderr, "%s\n", __FUNCTION__); if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); + rmesa->radeon.dma.flush( ctx ); radeonEmitState( rmesa ); - if (rmesa->store.cmd_used) - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); + if (rmesa->radeon.cmdbuf.cs->cdw) + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } /* Make sure all commands have been sent to the hardware and have diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 0c9fb14857c..1d683e5b3aa 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2091,34 +2091,23 @@ radeonUpdateDrawBuffer(GLcontext *ctx) { r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - driRenderbuffer *drb; + struct radeon_renderbuffer *rrb; if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } - else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } - else { - /* drawing to multiple buffers, or none */ - return; + /* draw to front */ + rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { + /* draw to back */ + rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } else { + /* drawing to multiple buffers, or none */ + return; } - assert(drb); - assert(drb->flippedPitch); + assert(rrb); + assert(rrb->pitch); RADEON_STATECHANGE( rmesa, ctx ); - - /* Note: we used the (possibly) page-flipped values */ - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) - & RADEON_COLOROFFSET_MASK); - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; - } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index f39fae8186c..02ea616a59e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -614,4 +614,6 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; rmesa->hw.all_dirty = GL_TRUE; + + rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); } -- cgit v1.2.3 From e223b7c312a1211966f47d36724ffceaec32a3f3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Feb 2009 20:30:03 +1000 Subject: radeon: port over arrays code even though not in use yet --- src/mesa/drivers/dri/radeon/common_misc.c | 4 +- src/mesa/drivers/dri/radeon/common_misc.h | 3 + src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 283 ++++------------------- 3 files changed, 52 insertions(+), 238 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index fbabed19f19..82cead1a25a 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1290,7 +1290,7 @@ static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count) } } -static void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) +void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) { int i; @@ -1309,7 +1309,7 @@ static void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) } } -static void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count) +void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count) { int i; diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 9bb1d03a097..80b34aa6bd3 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -31,6 +31,9 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv); +void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count); +void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count); + void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, GLvoid * data, int size, int stride, int count); void radeon_print_state_atom( struct radeon_state_atom *state ); diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index 471583ab6d1..fa3d0335fc2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -49,26 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_maos.h" #include "radeon_tcl.h" -#if defined(USE_X86_ASM) -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int __tmp; \ - __asm__ __volatile__( "rep ; movsl" \ - : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ - : "0" (nr), \ - "D" ((long)dst), \ - "S" ((long)src) ); \ -} while (0) -#else -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int j; \ - for ( j = 0 ; j < nr ; j++ ) \ - dst[j] = ((int *)src)[j]; \ - dst += nr; \ -} while (0) -#endif - static void emit_vecfog( GLcontext *ctx, struct radeon_dma_region *rvb, char *data, @@ -87,22 +67,22 @@ static void emit_vecfog( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - radeonAllocDmaRegion( rmesa, rvb, 4, 4 ); + radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = 1; + aos->stride = 0; } else { - radeonAllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 1; - rvb->aos_size = 1; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); + aos->stride = size; } + aos->components = size; + aos->count = count; + + /* Emit the data */ - out = (GLfloat *)(rvb->address + rvb->start); + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); for (i = 0; i < count; i++) { out[0] = radeonComputeFogBlendFactor( ctx, *(GLfloat *)data ); out++; @@ -110,169 +90,9 @@ static void emit_vecfog( GLcontext *ctx, } } -static void emit_vec4( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 4) - COPY_DWORDS( out, data, count ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out++; - data += stride; - } -} - - -static void emit_vec8( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 8) - COPY_DWORDS( out, data, count*2 ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data+4); - out += 2; - data += stride; - } -} - -static void emit_vec12( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 12) - COPY_DWORDS( out, data, count*3 ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data+4); - out[2] = *(int *)(data+8); - out += 3; - data += stride; - } -} - -static void emit_vec16( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) -{ - int i; - int *out = (int *)(rvb->address + rvb->start); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); - - if (stride == 16) - COPY_DWORDS( out, data, count*4 ); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data+4); - out[2] = *(int *)(data+8); - out[3] = *(int *)(data+12); - out += 4; - data += stride; - } -} - - -static void emit_vector( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int size, - int stride, - int count ) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d size %d stride %d\n", - __FUNCTION__, count, size, stride); - - assert (!rvb->buf); - - if (stride == 0) { - radeonAllocDmaRegion( rmesa, rvb, size * 4, 4 ); - count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = size; - } - else { - radeonAllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = size; - rvb->aos_size = size; - } - - /* Emit the data - */ - switch (size) { - case 1: - emit_vec4( ctx, rvb, data, stride, count ); - break; - case 2: - emit_vec8( ctx, rvb, data, stride, count ); - break; - case 3: - emit_vec12( ctx, rvb, data, stride, count ); - break; - case 4: - emit_vec16( ctx, rvb, data, stride, count ); - break; - default: - assert(0); - exit(1); - break; - } - -} - - - -static void emit_s0_vec( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) +static void emit_s0_vec(uint32_t *out, GLvoid *data, int stride, int count) { int i; - int *out = (int *)(rvb->address + rvb->start); - if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d\n", __FUNCTION__, count, stride); @@ -285,14 +105,9 @@ static void emit_s0_vec( GLcontext *ctx, } } -static void emit_stq_vec( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) +static void emit_stq_vec(uint32_t *out, GLvoid *data, int stride, int count) { int i; - int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d\n", @@ -311,8 +126,8 @@ static void emit_stq_vec( GLcontext *ctx, static void emit_tex_vector( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, + struct radeon_aos *aos, + GLvoid *data, int size, int stride, int count ) @@ -323,8 +138,6 @@ static void emit_tex_vector( GLcontext *ctx, if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size); - assert (!rvb->buf); - switch (size) { case 4: emitsize = 3; break; case 3: emitsize = 3; break; @@ -333,34 +146,32 @@ static void emit_tex_vector( GLcontext *ctx, if (stride == 0) { - radeonAllocDmaRegion( rmesa, rvb, 4 * emitsize, 4 ); + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * 4, 32); count = 1; - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = 0; - rvb->aos_size = emitsize; + aos->stride = 0; } else { - radeonAllocDmaRegion( rmesa, rvb, 4 * emitsize * count, 4 ); - rvb->aos_start = GET_START(rvb); - rvb->aos_stride = emitsize; - rvb->aos_size = emitsize; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * count * 4, 32); + aos->stride = emitsize; } + aos->components = emitsize; + aos->count = count; /* Emit the data */ switch (size) { case 1: - emit_s0_vec( ctx, rvb, data, stride, count ); + emit_s0_vec( out, data, stride, count ); break; case 2: - emit_vec8( ctx, rvb, data, stride, count ); + radeonEmitVec8( out, data, stride, count ); break; case 3: - emit_vec12( ctx, rvb, data, stride, count ); + radeonEmitVec12( out, data, stride, count ); break; case 4: - emit_stq_vec( ctx, rvb, data, stride, count ); + emit_stq_vec( out, data, stride, count ); break; default: assert(0); @@ -392,12 +203,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (1) { if (!rmesa->tcl.obj.buf) - emit_vector( ctx, - &rmesa->tcl.obj, - (char *)VB->ObjPtr->data, - VB->ObjPtr->size, - VB->ObjPtr->stride, - count); + rcommon_emit_vector( ctx, + &rmesa->tcl.obj, + (char *)VB->ObjPtr->data, + VB->ObjPtr->size, + VB->ObjPtr->stride, + count); switch( VB->ObjPtr->size ) { case 4: vfmt |= RADEON_CP_VC_FRMT_W0; @@ -412,12 +223,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (inputs & VERT_BIT_NORMAL) { if (!rmesa->tcl.norm.buf) - emit_vector( ctx, - &(rmesa->tcl.norm), - (char *)VB->NormalPtr->data, - 3, - VB->NormalPtr->stride, - count); + rcommon_emit_vector( ctx, + &(rmesa->tcl.norm), + (char *)VB->NormalPtr->data, + 3, + VB->NormalPtr->stride, + count); vfmt |= RADEON_CP_VC_FRMT_N0; component[nr++] = &rmesa->tcl.norm; @@ -438,12 +249,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) } if (!rmesa->tcl.rgba.buf) - emit_vector( ctx, - &(rmesa->tcl.rgba), - (char *)VB->ColorPtr[0]->data, - emitsize, - VB->ColorPtr[0]->stride, - count); + rcommon_emit_vector( ctx, + &(rmesa->tcl.rgba), + (char *)VB->ColorPtr[0]->data, + emitsize, + VB->ColorPtr[0]->stride, + count); component[nr++] = &rmesa->tcl.rgba; @@ -453,12 +264,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (inputs & VERT_BIT_COLOR1) { if (!rmesa->tcl.spec.buf) { - emit_vector( ctx, - &rmesa->tcl.spec, - (char *)VB->SecondaryColorPtr[0]->data, - 3, - VB->SecondaryColorPtr[0]->stride, - count); + rcommon_emit_vector( ctx, + &rmesa->tcl.spec, + (char *)VB->SecondaryColorPtr[0]->data, + 3, + VB->SecondaryColorPtr[0]->stride, + count); } vfmt |= RADEON_CP_VC_FRMT_FPSPEC; -- cgit v1.2.3 From abdf1f65d2bafbad8020f1444a01eb18ae9f7159 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Feb 2009 03:50:07 +1000 Subject: r200: cleanup some bits that aren't used --- src/mesa/drivers/dri/r200/r200_context.h | 2 -- src/mesa/drivers/dri/r200/r200_ioctl.h | 26 -------------------------- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 6 ++---- src/mesa/drivers/dri/r200/r200_tcl.c | 1 - 4 files changed, 2 insertions(+), 33 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 4b7ce5d1efa..862751bd404 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -535,7 +535,6 @@ struct r200_tcl_info { /* hw can handle 12 components max */ struct radeon_aos aos[12]; - // struct radeon_dma_region *aos_components[12]; GLuint nr_aos_components; GLuint *Elts; @@ -544,7 +543,6 @@ struct r200_tcl_info { int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; - struct radeon_dma_region vertex_data[15]; }; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 30b089658d5..6b9e4be30a0 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -63,32 +63,6 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); -extern void r200EmitBlit( r200ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, - GLuint w, GLuint h ); - -extern void r200EmitWait( r200ContextPtr rmesa, GLuint flags ); - -//extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); -//extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); - -extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ); - -extern void r200AllocDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - int bytes, - int alignment ); - -extern void r200ReleaseDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ); - extern void r200Flush( GLcontext *ctx ); extern void r200Finish( GLcontext *ctx ); extern void r200InitIoctlFuncs( struct dd_function_table *functions ); diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 716f9037dd9..5dbc202330b 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -105,7 +105,6 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - // struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt0 = 0, vfmt1 = 0; GLuint count = VB->Count; @@ -143,7 +142,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) case 3: /* special handling to fix up fog. Will get us into trouble with vbos...*/ assert(attrib == VERT_ATTRIB_FOG); - if (!rmesa->tcl.vertex_data[i].buf) { + if (!rmesa->tcl.aos[i].bo) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), @@ -200,7 +199,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) default: assert(0); } - if (!rmesa->tcl.vertex_data[i].buf) { + if (!rmesa->tcl.aos[nr].bo) { rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, @@ -211,7 +210,6 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) after_emit: assert(nr < 12); nr++; - // component[nr++] = &rmesa->tcl.vertex_data[i]; } } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 494a8f3d7be..4c4df14ef82 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,7 +142,6 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { - // fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { -- cgit v1.2.3 From 3fafaf8959681cc41c988607bb6e387bab4fe1b5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Feb 2009 03:50:38 +1000 Subject: radeon: make more r100 work --- src/mesa/drivers/dri/radeon/common_context.h | 1 + src/mesa/drivers/dri/radeon/radeon_context.h | 15 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 2 +- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 278 +++++++++++----- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 3 +- src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 84 ++--- src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 29 +- src/mesa/drivers/dri/radeon/radeon_state_init.c | 383 +++++++++++++++++++++-- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 3 +- src/mesa/drivers/dri/radeon/radeon_tcl.c | 38 ++- src/mesa/drivers/dri/radeon/radeon_tex.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 46 ++- 12 files changed, 670 insertions(+), 214 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 90abca0bc10..618e74d4583 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -269,6 +269,7 @@ struct radeon_swtcl_info { struct radeon_ioctl { GLuint vertex_offset; + struct radeon_bo *bo; GLuint vertex_size; }; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 6edbaf69107..358095a2b9d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -334,11 +334,6 @@ struct r100_state { struct radeon_texture_state texture; }; -#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ - (rvb)->address - rmesa->dma.buf0_address + \ - (rvb)->start) - - #define RADEON_CMD_BUF_SZ (8*1024) #define R200_ELT_BUF_SZ (8*1024) /* radeon_tcl.c @@ -352,12 +347,14 @@ struct radeon_tcl_info { */ GLvector4f ObjClean; - struct radeon_dma_region *aos_components[8]; + struct radeon_aos aos[8]; GLuint nr_aos_components; GLuint *Elts; - struct radeon_dma_region indexed_verts; + struct radeon_bo *indexed_bo; + +// struct radeon_dma_region indexed_verts; struct radeon_dma_region obj; struct radeon_dma_region rgba; struct radeon_dma_region spec; @@ -365,8 +362,8 @@ struct radeon_tcl_info { struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; struct radeon_dma_region norm; - struct radeon_bo *elt_dma_bo; - int elt_dma_offset; /** Offset into this buffer object, in bytes */ + int elt_cmd_offset; /** Offset into the cmdbuf */ + int elt_cmd_start; int elt_used; }; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 1c885c1612b..fbb93a8ba1e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -313,7 +313,7 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } - //dump_cmdbuf(cs); + //dump_cmdbuf(cs); r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 4ab297c5cee..1a33595884e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -59,7 +59,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_TIMEOUT 512 #define RADEON_IDLE_RETRY 16 -#define DEBUG_CMDBUF 0 +#define DEBUG_CMDBUF 1 static void radeonSaveHwState( r100ContextPtr rmesa ) { @@ -190,10 +190,6 @@ static INLINE void radeonEmitAtoms(r100ContextPtr r100, GLboolean dirty) void radeonEmitState( r100ContextPtr rmesa ) { - struct radeon_state_atom *atom; - char *dest; - uint32_t dwords; - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) fprintf(stderr, "%s\n", __FUNCTION__); @@ -212,7 +208,6 @@ void radeonEmitState( r100ContextPtr rmesa ) * radeonAllocCmdBuf code here without all the checks. */ rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - dest = rmesa->store.cmd_buf + rmesa->store.cmd_used; /* We always always emit zbs, this is due to a bug found by keithw in the hardware and rediscovered after Erics changes by me. @@ -250,12 +245,26 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, radeonEmitState( rmesa ); - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s cmd_used/4: %d\n", __FUNCTION__, - rmesa->store.cmd_used/4); + // if (RADEON_DEBUG & DEBUG_IOCTL) + // fprintf(stderr, "%s cmd_used/4: %d\n", __FUNCTION__, + // rmesa->store.cmd_used/4); + + +#if RADEON_OLD_PACKETS + BEGIN_BATCH(6); + OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); + OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(vertex_nr); + OUT_BATCH(vertex_format); + OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | + RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | + (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); + END_BATCH(); - BEGIN_BATCH(3); - OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 0); +#else + BEGIN_BATCH(4); + OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 1); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | @@ -264,45 +273,89 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); END_BATCH(); +#endif } +static void radeonFireEB(r100ContextPtr rmesa, int vertex_count, int vertex_format, int type) +{ + BATCH_LOCALS(&rmesa->radeon); + + if (vertex_count > 0) { + BEGIN_BATCH(8); + OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_DRAW_INDX, 0); + OUT_BATCH(vertex_format); + OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_IND | + ((vertex_count + 0) << 16) | + type); + + assert(0); // RADEON HAS NO INDX_BUFFERs +#if 0 + + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); + OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); + OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset, + rmesa->tcl.elt_dma_bo, + rmesa->tcl.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(vertex_count/2); + } else { + OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); + OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); + OUT_BATCH(rmesa->tcl.elt_dma_offset); + OUT_BATCH(vertex_count/2); + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0, 0); + } +#endif + END_BATCH(); + } +} void radeonFlushElts( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start); + BATCH_LOCALS(&rmesa->radeon); int dwords; -#if RADEON_OLD_PACKETS - int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 24)) / 2; -#else - int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 16)) / 2; -#endif - + uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start); + int nr = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw) * 2; + if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); assert( rmesa->radeon.dma.flush == radeonFlushElts ); rmesa->radeon.dma.flush = NULL; + /* Cope with odd number of elts: */ - rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; - dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; + // rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; + // dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; + dwords = nr / 2; + + rmesa->radeon.cmdbuf.cs->cdw += dwords; #if RADEON_OLD_PACKETS - cmd[1] |= (dwords - 3) << 16; + cmd[1] |= (dwords + 3) << 16; cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #else - cmd[1] |= (dwords - 3) << 16; + cmd[1] |= (dwords) << 16; cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #endif + fprintf(stderr,"nr is %d cmd1 is %08x\n", nr, cmd[1]); + + rmesa->radeon.cmdbuf.cs->section_cdw += dwords; + END_BATCH(); + if (RADEON_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); radeonFinish( rmesa->radeon.glCtx ); } -} +} GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint vertex_format, @@ -310,46 +363,65 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint min_nr ) { GLushort *retval; - + BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, min_nr); + fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); radeonEmitState( rmesa ); - rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, R200_ELT_BUF_SZ, 4, - RADEON_GEM_DOMAIN_GTT, 0); - rmesa->tcl.elt_dma_offset = 0; + rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; + +#if RADEON_OLD_PACKETS + BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(min_nr)/4); + OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0); + OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(0xffff); + OUT_BATCH(vertex_format); + OUT_BATCH(primitive | + RADEON_CP_VC_CNTL_PRIM_WALK_IND | + RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); + +#else + BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(min_nr)/4); + OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); + OUT_BATCH(vertex_format); + OUT_BATCH(primitive | + RADEON_CP_VC_CNTL_PRIM_WALK_IND | + RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | + RADEON_CP_VC_CNTL_MAOS_ENABLE | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); +#endif + + + rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; rmesa->tcl.elt_used = min_nr * 2; - radeon_bo_map(rmesa->tcl.elt_dma_bo, 1); - retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; + retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); + + fprintf(stderr," %d elt start %d offset %d\n", min_nr, rmesa->tcl.elt_cmd_start, rmesa->tcl.elt_cmd_offset); if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: header vfmt 0x%x prim %x \n", - __FUNCTION__, - vertex_format, primitive); + fprintf(stderr, "%s: header prim %x \n", + __FUNCTION__, primitive); assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->radeon.dma.flush = radeonFlushElts; - // rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; - return retval; } - - void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, + struct radeon_bo *bo, GLuint offset ) { #if RADEON_OLD_PACKETS - rmesa->ioctl.vertex_size = vertex_size; rmesa->ioctl.vertex_offset = offset; + rmesa->ioctl.bo = bo; #else BATCH_LOCALS(&rmesa->radeon); @@ -357,68 +429,124 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa, fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", __FUNCTION__, vertex_size, offset); - BEGIN_BATCH(5); + BEGIN_BATCH(7); OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); -} + #endif } void radeonEmitAOS( r100ContextPtr rmesa, - struct radeon_dma_region **component, GLuint nr, GLuint offset ) { #if RADEON_OLD_PACKETS assert( nr == 1 ); - assert( component[0]->aos_size == component[0]->aos_stride ); - rmesa->ioctl.vertex_size = component[0]->aos_size; + // assert( rmesa->radeon.aos[0]->aos_size == component[0]->aos_stride ); + // rmesa->ioctl.vertex_offset = + // (component[0]->aos_start + offset * component[0]->aos_stride * 4); + rmesa->ioctl.bo = rmesa->tcl.aos[0].bo; rmesa->ioctl.vertex_offset = - (component[0]->aos_start + offset * component[0]->aos_stride * 4); + (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4); #else - drm_radeon_cmd_header_t *cmd; - int sz = AOS_BUFSZ(nr); + BATCH_LOCALS(&rmesa->radeon); + uint32_t voffset; + // int sz = AOS_BUFSZ(nr); + int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; - int *tmp; if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sz, - __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = RADEON_CP_PACKET3_3D_LOAD_VBPNTR | (((sz / sizeof(int))-3) << 16); - cmd[2].i = nr; - tmp = &cmd[0].i; - cmd += 3; - - for (i = 0 ; i < nr ; i++) { - if (i & 1) { - cmd[0].i |= ((component[i]->aos_stride << 24) | - (component[i]->aos_size << 16)); - cmd[2].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - cmd += 3; + BEGIN_BATCH(sz+2+(nr * 2)); + OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH(voffset); } - else { - cmd[0].i = ((component[i]->aos_stride << 8) | - (component[i]->aos_size << 0)); - cmd[1].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); + for (i = 0; i + 1 < nr; i += 2) { + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+0].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + if (nr & 1) { + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[nr-1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); } } + END_BATCH(); - if (RADEON_DEBUG & DEBUG_VERTS) { - fprintf(stderr, "%s:\n", __FUNCTION__); - for (i = 0 ; i < sz ; i++) - fprintf(stderr, " %d: %x\n", i, tmp[i]); - } #endif } diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index 87d64fb728f..b7f07294946 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void radeonEmitState( r100ContextPtr rmesa ); extern void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, + struct radeon_bo *bo, GLuint offset ); extern void radeonEmitVbufPrim( r100ContextPtr rmesa, @@ -58,8 +59,8 @@ extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint primitive, GLuint min_nr ); + extern void radeonEmitAOS( r100ContextPtr rmesa, - struct radeon_dma_region **regions, GLuint n, GLuint offset ); diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index fa3d0335fc2..7f5da16b03d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "math/m_translate.h" #include "tnl/tnl.h" -#include "tnl/tcontext.h" #include "radeon_context.h" #include "radeon_ioctl.h" @@ -49,23 +48,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_maos.h" #include "radeon_tcl.h" -static void emit_vecfog( GLcontext *ctx, - struct radeon_dma_region *rvb, - char *data, - int stride, - int count ) +static void emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, + GLvoid *data, int stride, int count) { int i; - GLfloat *out; - + uint32_t *out; + int size = 1; radeonContextPtr rmesa = RADEON_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s count %d stride %d\n", __FUNCTION__, count, stride); - assert (!rvb->buf); - if (stride == 0) { radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); count = 1; @@ -125,15 +119,12 @@ static void emit_stq_vec(uint32_t *out, GLvoid *data, int stride, int count) -static void emit_tex_vector( GLcontext *ctx, - struct radeon_aos *aos, - GLvoid *data, - int size, - int stride, - int count ) +static void emit_tex_vector(GLcontext *ctx, struct radeon_aos *aos, + GLvoid *data, int size, int stride, int count) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); int emitsize; + uint32_t *out; if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size); @@ -160,6 +151,7 @@ static void emit_tex_vector( GLcontext *ctx, /* Emit the data */ + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: emit_s0_vec( out, data, stride, count ); @@ -188,9 +180,8 @@ static void emit_tex_vector( GLcontext *ctx, */ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt = 0; GLuint count = VB->Count; @@ -204,7 +195,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (1) { if (!rmesa->tcl.obj.buf) rcommon_emit_vector( ctx, - &rmesa->tcl.obj, + &(rmesa->tcl.aos[nr]), (char *)VB->ObjPtr->data, VB->ObjPtr->size, VB->ObjPtr->stride, @@ -217,21 +208,21 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) default: break; } - component[nr++] = &rmesa->tcl.obj; + nr++; } if (inputs & VERT_BIT_NORMAL) { if (!rmesa->tcl.norm.buf) rcommon_emit_vector( ctx, - &(rmesa->tcl.norm), + &(rmesa->tcl.aos[nr]), (char *)VB->NormalPtr->data, 3, VB->NormalPtr->stride, count); vfmt |= RADEON_CP_VC_FRMT_N0; - component[nr++] = &rmesa->tcl.norm; + nr++; } if (inputs & VERT_BIT_COLOR0) { @@ -250,14 +241,13 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.rgba.buf) rcommon_emit_vector( ctx, - &(rmesa->tcl.rgba), + &(rmesa->tcl.aos[nr]), (char *)VB->ColorPtr[0]->data, emitsize, VB->ColorPtr[0]->stride, count); - - component[nr++] = &rmesa->tcl.rgba; + nr++; } @@ -265,7 +255,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.spec.buf) { rcommon_emit_vector( ctx, - &rmesa->tcl.spec, + &(rmesa->tcl.aos[nr]), (char *)VB->SecondaryColorPtr[0]->data, 3, VB->SecondaryColorPtr[0]->stride, @@ -273,7 +263,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) } vfmt |= RADEON_CP_VC_FRMT_FPSPEC; - component[nr++] = &rmesa->tcl.spec; + nr++; } /* FIXME: not sure if this is correct. May need to stitch this together with @@ -282,13 +272,13 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (inputs & VERT_BIT_FOG) { if (!rmesa->tcl.fog.buf) emit_vecfog( ctx, - &(rmesa->tcl.fog), + &(rmesa->tcl.aos[nr]), (char *)VB->FogCoordPtr->data, VB->FogCoordPtr->stride, count); vfmt |= RADEON_CP_VC_FRMT_FPFOG; - component[nr++] = &rmesa->tcl.fog; + nr++; } @@ -299,11 +289,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (inputs & VERT_BIT_TEX(unit)) { if (!rmesa->tcl.tex[unit].buf) emit_tex_vector( ctx, - &(rmesa->tcl.tex[unit]), + &(rmesa->tcl.aos[nr]), (char *)VB->TexCoordPtr[unit]->data, VB->TexCoordPtr[unit]->size, VB->TexCoordPtr[unit]->stride, count ); + nr++; vfmt |= RADEON_ST_BIT(unit); /* assume we need the 3rd coord if texgen is active for r/q OR at least @@ -321,7 +312,6 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; } - component[nr++] = &rmesa->tcl.tex[unit]; } } @@ -337,31 +327,13 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) { - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); - GLuint unit; - -#if 0 - if (RADEON_DEBUG & DEBUG_VERTS) - _tnl_print_vert_flags( __FUNCTION__, newinputs ); -#endif - - if (newinputs & VERT_BIT_POS) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.obj, __FUNCTION__ ); - - if (newinputs & VERT_BIT_NORMAL) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.norm, __FUNCTION__ ); - - if (newinputs & VERT_BIT_COLOR0) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.rgba, __FUNCTION__ ); - - if (newinputs & VERT_BIT_COLOR1) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.spec, __FUNCTION__ ); - - if (newinputs & VERT_BIT_FOG) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.fog, __FUNCTION__ ); + r100ContextPtr rmesa = R100_CONTEXT( ctx ); + int i; - for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { - if (newinputs & VERT_BIT_TEX(unit)) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[unit], __FUNCTION__ ); + for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { + if (rmesa->tcl.aos[i].bo) { + radeon_bo_unref(rmesa->tcl.aos[i].bo); + rmesa->tcl.aos[i].bo = NULL; + } } } diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 5a0bbaacc9b..bb90a7b1117 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -374,14 +374,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) break; if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && - rmesa->tcl.indexed_verts.buf) + rmesa->tcl.aos[0].bo) return; - if (rmesa->tcl.indexed_verts.buf) + if (rmesa->tcl.aos[0].bo) radeonReleaseArrays( ctx, ~0 ); radeonAllocDmaRegion( &rmesa->radeon, - 0, &rmesa->tcl.indexed_verts, + &rmesa->tcl.aos[0].bo, + &rmesa->tcl.aos[0].offset, VB->Count * setup_tab[i].vertex_size * 4, 4); @@ -421,15 +422,11 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) setup_tab[i].emit( ctx, 0, VB->Count, - rmesa->tcl.indexed_verts.address + - rmesa->tcl.indexed_verts.start ); + rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset); + // rmesa->tcl.aos[0].size = setup_tab[i].vertex_size; + rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size; rmesa->tcl.vertex_format = setup_tab[i].vertex_format; - // rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts ); - rmesa->tcl.indexed_verts.aos_size = setup_tab[i].vertex_size; - rmesa->tcl.indexed_verts.aos_stride = setup_tab[i].vertex_size; - - rmesa->tcl.aos_components[0] = &rmesa->tcl.indexed_verts; rmesa->tcl.nr_aos_components = 1; } @@ -438,12 +435,10 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) { r100ContextPtr rmesa = R100_CONTEXT( ctx ); + int i; -#if 0 - if (RADEON_DEBUG & DEBUG_VERTS) - _tnl_print_vert_flags( __FUNCTION__, newinputs ); -#endif - - /// if (newinputs) - /// radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ ); + for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { + radeon_bo_unref(rmesa->tcl.aos[i].bo); + rmesa->tcl.aos[i].bo = NULL; + } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 02ea616a59e..0a9e8141911 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -38,14 +38,128 @@ #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" +#include "common_cmdbuf.h" +#include "radeon_cs.h" +#include "radeon_mipmap_tree.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_tcl.h" #include "radeon_tex.h" #include "radeon_swtcl.h" +#include "../r200/r200_reg.h" + #include "xmlpool.h" +/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in + * 1.3 cmdbuffers allow all previous state to be updated as well as + * the tcl scalar and vector areas. + */ +static struct { + int start; + int len; + const char *name; +} packet[RADEON_MAX_STATE_PACKETS] = { + {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, + {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, + {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, + {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, + {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, + {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, + {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, + {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, + {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, + {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, + {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, + {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, + {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, + {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, + {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, + {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, + {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, + {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, + {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, + {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, + {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, + "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, + {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, + {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, + {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, + {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, + {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, + {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, + {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, + {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, + {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, + {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, + {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, + {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, + {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, + {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, + {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, + {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, + {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, + {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, + {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, + {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, + {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, + {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, + {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, + {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, + {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, + {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, + {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, + {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, + {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, + "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, + {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, + {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, + {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, + {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, + {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, + {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, + {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, + {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, + {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, + {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, + {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, + "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, + {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ + {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ + {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, + {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, + {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, + {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, + {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, + {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, + {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, + {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, + {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, + {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, + {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, + {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, + {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, + {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, + {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, + {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, + {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, + {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, + {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, + {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, + {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ + {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, + {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, + {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, + {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, + {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, + {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, + {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, + {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, + {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, +}; + /* ============================================================= * State initialization */ @@ -65,12 +179,17 @@ void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) fprintf(stderr, "\n"); } -static int cmdpkt( int id ) +static int cmdpkt( r100ContextPtr rmesa, int id ) { drm_radeon_cmd_header_t h; - h.i = 0; - h.packet.cmd_type = RADEON_CMD_PACKET; - h.packet.packet_id = id; + + if (rmesa->radeon.radeonScreen->kernel_mm) { + return CP_PACKET0(packet[id].start, packet[id].len - 1); + } else { + h.i = 0; + h.packet.cmd_type = RADEON_CMD_PACKET; + h.packet.packet_id = id; + } return h.i; } @@ -146,7 +265,200 @@ CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) +#define OUT_VEC(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + h.i = hdr; \ + OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ + OUT_BATCH(0); \ + OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ + OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ + OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ + OUT_BATCH_TABLE((data), h.vectors.count); \ + } while(0) + +#define OUT_SCL(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + h.i = hdr; \ + OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ + OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ + OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ + OUT_BATCH_TABLE((data), h.scalars.count); \ + } while(0) + +static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_SCL(atom->cmd[0], atom->cmd+1); + END_BATCH(); +} + + +static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = atom->cmd_size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VEC(atom->cmd[0], atom->cmd+1); + END_BATCH(); +} + +static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; + uint32_t zbpitch; + uint32_t dwords = atom->cmd_size; + GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate; + + /* output the first 7 bytes of context */ + BEGIN_BATCH_NO_AUTOSTATE(dwords + 4); + OUT_BATCH_TABLE(atom->cmd, 5); + + rrb = r100->radeon.state.depth.rrb; + if (!rrb) { + OUT_BATCH(0); + OUT_BATCH(0); + } else { + zbpitch = (rrb->pitch / rrb->cpp); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH(zbpitch); + } + + OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); + OUT_BATCH(atom->cmd[CTX_CMD_1]); + OUT_BATCH(atom->cmd[CTX_PP_CNTL]); + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + + rrb = r100->radeon.state.color.rrb; + if (r100->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb || !rrb->bo) { + OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); + } else { + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + } + + OUT_BATCH(atom->cmd[CTX_CMD_2]); + + if (!rrb || !rrb->bo) { + OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); + } else { + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + ; + else + ; + if (r100->radeon.sarea->tiling_enabled) + cbpitch |= R200_COLOR_TILE_ENABLE; + OUT_BATCH(cbpitch); + } + + END_BATCH(); +} +static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + struct radeon_renderbuffer *rrb, *drb; + uint32_t cbpitch = 0; + uint32_t zbpitch = 0; + uint32_t dwords = atom->cmd_size; + GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate; + + rrb = r100->radeon.state.color.rrb; + if (r100->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (rrb) { + assert(rrb->bo != NULL); + cbpitch = (rrb->pitch / rrb->cpp); + if (r100->radeon.sarea->tiling_enabled) + cbpitch |= R200_COLOR_TILE_ENABLE; + } + + drb = r100->radeon.state.depth.rrb; + if (drb) + zbpitch = (drb->pitch / drb->cpp); + + /* output the first 7 bytes of context */ + BEGIN_BATCH_NO_AUTOSTATE(dwords); + + /* In the CS case we need to split this up */ + OUT_BATCH(CP_PACKET0(packet[0].start, 3)); + OUT_BATCH_TABLE((atom->cmd + 1), 4); + if (drb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); + OUT_BATCH(zbpitch); + } + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); + OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); + OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); + OUT_BATCH(atom->cmd[CTX_PP_CNTL]); + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + + + if (rrb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + } + + if (rrb) { + if (rrb->cpp == 4) + ; + else + ; + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); + OUT_BATCH(cbpitch); + } + + // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { + // OUT_BATCH_TABLE((atom->cmd + 14), 4); + // } + + END_BATCH(); +} + + + +static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r100->state.texture.unit[i].texobj; + + if (!t) + return; + + BEGIN_BATCH_NO_AUTOSTATE(dwords + 2); + OUT_BATCH_TABLE(atom->cmd, 3); + if (t && !t->image_override) { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else if (!t) { + + + OUT_BATCH(atom->cmd[10]); + } + + OUT_BATCH_TABLE((atom->cmd+4), 5); + END_BATCH(); +} /* Initialize the context's hardware state. */ @@ -221,6 +533,10 @@ void radeonInitState( r100ContextPtr rmesa ) /* Allocate state buffers: */ ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 ); + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.ctx.emit = ctx_emit_cs; + else + rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); @@ -236,6 +552,9 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 ); ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 ); + + for (i = 0; i < 3; i++) + rmesa->hw.tex[i].emit = tex_emit; if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) { ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); @@ -276,35 +595,35 @@ void radeonInitState( r100ContextPtr rmesa ) /* Fill in the packet headers: */ - rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); - rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); - rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); - rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); - rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); - rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK); - rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE); - rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL); - rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS); - rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC); - rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0); - rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0); - rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1); - rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1); - rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_2); - rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_2); - rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_0); - rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T0); - rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_1); - rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T1); - rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_2); - rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T2); - rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR); - rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); + rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); + rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); + rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); + rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); + rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); + rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); + rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); + rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); + rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS); + rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); + rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0); + rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0); + rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1); + rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1); + rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2); + rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2); + rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0); + rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0); + rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1); + rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1); + rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2); + rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2); + rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); + rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); rmesa->hw.mtl.cmd[MTL_CMD_0] = - cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); - rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0); - rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1); - rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_2); + cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); + rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); + rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); + rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); rmesa->hw.grd.cmd[GRD_CMD_0] = cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); rmesa->hw.fog.cmd[FOG_CMD_0] = diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 4b49c141a0f..615621dd987 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "radeon_context.h" +#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_swtcl.h" @@ -291,7 +292,7 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset) radeonEmitState(rmesa); radeonEmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, - // rmesa->radeon.dma.current, + rmesa->radeon.dma.current, current_offset); diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index a54e471065c..4f3acc7dafb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "radeon_context.h" +#include "common_cmdbuf.h" #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_tex.h" @@ -145,19 +146,31 @@ static GLboolean discrete_prim[0x10] = { static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) { - if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); +#if 0 + if (rmesa->radeon.dma.flush == radeonFlushElts && + rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + ELTS_BUFSZ(nr)); + GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + + rmesa->tcl.elt_used); - radeonEmitAOS( rmesa, - rmesa->tcl.aos_components, - rmesa->tcl.nr_aos_components, 0 ); + rmesa->tcl.elt_used += nr*2; + + return dest; + } + else { +#endif + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); + + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size + ELTS_BUFSZ(nr) + + AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); + + radeonEmitAOS( rmesa, + rmesa->tcl.nr_aos_components, 0 ); - return radeonAllocEltsOpenEnded( rmesa, - rmesa->tcl.vertex_format, - rmesa->tcl.hw_primitive, nr ); + return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, + rmesa->tcl.hw_primitive, nr ); + // } } #define CLOSE_ELTS() RADEON_NEWPRIM( rmesa ) @@ -179,17 +192,16 @@ static void radeonEmitPrim( GLcontext *ctx, rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); radeonEmitAOS( rmesa, - rmesa->tcl.aos_components, rmesa->tcl.nr_aos_components, start ); /* Why couldn't this packet have taken an offset param? */ radeonEmitVbufPrim( rmesa, - 0, + rmesa->tcl.vertex_format, rmesa->tcl.hw_primitive, count - start ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 9ef08fbe68a..8784dcc5edd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -315,7 +315,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, struct gl_texture_object *texObj, GLenum pname, const GLfloat *params ) { - radeonTexObjPtr t = (radeonTexObjPtr) texObj->DriverData; + radeonTexObj* t = radeon_tex_obj(texObj); if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { fprintf( stderr, "%s( %s )\n", __FUNCTION__, diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 3c28d70e376..e76b52437ff 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -903,7 +903,7 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \ RADEON_TXFORMAT_NON_POWER2) -#if 0 + static void import_tex_obj_state( r100ContextPtr rmesa, int unit, radeonTexObjPtr texobj ) @@ -921,7 +921,7 @@ static void import_tex_obj_state( r100ContextPtr rmesa, cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset; cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; - if (texobj->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) { + if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) { GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] ); txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */ txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */ @@ -931,10 +931,11 @@ static void import_tex_obj_state( r100ContextPtr rmesa, else { se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit); - if (texobj->base.tObj->Target == GL_TEXTURE_CUBE_MAP) { - int *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; - GLuint bytesPerFace = texobj->base.totalSize / 6; - ASSERT(texobj->base.totalSize % 6 == 0); + if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) { + uint32_t *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; + // GLuint bytesPerFace = texobj->base.totalSize / 6; + // ASSERT(texobj->base.totalSize % 6 == 0); + GLuint bytesPerFace = 1; // TODO RADEON_STATECHANGE( rmesa, cube[unit] ); cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; @@ -957,8 +958,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa, texobj->dirty_state &= ~(1<dirty_state & (1<validated = GL_TRUE; + return GL_TRUE; +} + static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) { + r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; + if (!ctx->Texture.Unit[unit]._ReallyEnabled) + return GL_TRUE; + + if (!radeon_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) { + _mesa_warning(ctx, + "failed to validate texture for unit %d.\n", + unit); + rmesa->state.texture.unit[unit].texobj = NULL; + return GL_FALSE; + } + rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); + return GL_TRUE; } void radeonUpdateTextureState( GLcontext *ctx ) -- cgit v1.2.3 From 9df844b109a9d2cc1d3b16315c34ef84f147c5b6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Feb 2009 23:19:42 +1000 Subject: radeon: fix alignment issues in ELT code --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 1a33595884e..0c363b39bde 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -251,7 +251,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, #if RADEON_OLD_PACKETS - BEGIN_BATCH(6); + BEGIN_BATCH(8); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_nr); @@ -363,6 +363,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint min_nr ) { GLushort *retval; + int align_min_nr; BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); @@ -373,8 +374,11 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; + /* round up min_nr to align the state */ + align_min_nr = (min_nr + 1) & ~1; + #if RADEON_OLD_PACKETS - BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(min_nr)/4); + BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0); OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(0xffff); @@ -385,7 +389,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); #else - BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(min_nr)/4); + BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); OUT_BATCH(vertex_format); OUT_BATCH(primitive | -- cgit v1.2.3 From ccf7814a315f0be05cdc36ca358e2917a3d4ac19 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Feb 2009 04:54:24 +1000 Subject: radeon: major cleanups removing old dead codepaths. This should be working gears on radeon state --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 141 +----- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 11 +- src/mesa/drivers/dri/radeon/radeon_state.c | 2 + src/mesa/drivers/dri/radeon/radeon_state_init.c | 61 +-- src/mesa/drivers/dri/radeon/radeon_tcl.c | 14 - src/mesa/drivers/dri/radeon/radeon_tex.c | 10 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 623 ++++-------------------- 7 files changed, 161 insertions(+), 701 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 0c363b39bde..78ee322b4cc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -198,9 +198,6 @@ void radeonEmitState( r100ContextPtr rmesa ) rmesa->save_on_next_emit = GL_FALSE; } - if (rmesa->radeon.cmdbuf.cs->cdw) - return; - /* this code used to return here but now it emits zbs */ /* To avoid going across the entire set of states multiple times, just check @@ -245,11 +242,6 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, radeonEmitState( rmesa ); - // if (RADEON_DEBUG & DEBUG_IOCTL) - // fprintf(stderr, "%s cmd_used/4: %d\n", __FUNCTION__, - // rmesa->store.cmd_used/4); - - #if RADEON_OLD_PACKETS BEGIN_BATCH(8); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); @@ -276,51 +268,13 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, #endif } -static void radeonFireEB(r100ContextPtr rmesa, int vertex_count, int vertex_format, int type) -{ - BATCH_LOCALS(&rmesa->radeon); - - if (vertex_count > 0) { - BEGIN_BATCH(8); - OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_DRAW_INDX, 0); - OUT_BATCH(vertex_format); - OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_IND | - ((vertex_count + 0) << 16) | - type); - - assert(0); // RADEON HAS NO INDX_BUFFERs -#if 0 - - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); - OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset, - rmesa->tcl.elt_dma_bo, - rmesa->tcl.elt_dma_offset, - RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(vertex_count/2); - } else { - OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); - OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH(rmesa->tcl.elt_dma_offset); - OUT_BATCH(vertex_count/2); - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.elt_dma_bo, - RADEON_GEM_DOMAIN_GTT, 0, 0); - } -#endif - END_BATCH(); - } -} - void radeonFlushElts( GLcontext *ctx ) { - r100ContextPtr rmesa = R100_CONTEXT(ctx); - BATCH_LOCALS(&rmesa->radeon); - int dwords; + r100ContextPtr rmesa = R100_CONTEXT(ctx); + BATCH_LOCALS(&rmesa->radeon); + int nr; uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start); - int nr = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw) * 2; + int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw); if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -328,12 +282,7 @@ void radeonFlushElts( GLcontext *ctx ) assert( rmesa->radeon.dma.flush == radeonFlushElts ); rmesa->radeon.dma.flush = NULL; - - /* Cope with odd number of elts: - */ - // rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; - // dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; - dwords = nr / 2; + nr = rmesa->tcl.elt_used; rmesa->radeon.cmdbuf.cs->cdw += dwords; @@ -341,12 +290,10 @@ void radeonFlushElts( GLcontext *ctx ) cmd[1] |= (dwords + 3) << 16; cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #else - cmd[1] |= (dwords) << 16; + cmd[1] |= (dwords + 2) << 16; cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #endif - fprintf(stderr,"nr is %d cmd1 is %08x\n", nr, cmd[1]); - rmesa->radeon.cmdbuf.cs->section_cdw += dwords; END_BATCH(); @@ -366,7 +313,6 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, int align_min_nr; BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); @@ -401,12 +347,10 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; - rmesa->tcl.elt_used = min_nr * 2; + rmesa->tcl.elt_used = min_nr; retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); - fprintf(stderr," %d elt start %d offset %d\n", min_nr, rmesa->tcl.elt_cmd_start, rmesa->tcl.elt_cmd_offset); - if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s: header prim %x \n", __FUNCTION__, primitive); @@ -450,9 +394,6 @@ void radeonEmitAOS( r100ContextPtr rmesa, { #if RADEON_OLD_PACKETS assert( nr == 1 ); - // assert( rmesa->radeon.aos[0]->aos_size == component[0]->aos_stride ); - // rmesa->ioctl.vertex_offset = - // (component[0]->aos_start + offset * component[0]->aos_stride * 4); rmesa->ioctl.bo = rmesa->tcl.aos[0].bo; rmesa->ioctl.vertex_offset = (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4); @@ -554,74 +495,6 @@ void radeonEmitAOS( r100ContextPtr rmesa, #endif } - -#if 0 -/* using already shifted color_fmt! */ -void radeonEmitBlit( r100ContextPtr rmesa, /* FIXME: which drmMinor is required? */ - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, - GLuint w, GLuint h ) -{ - drm_radeon_cmd_header_t *cmd; - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n", - __FUNCTION__, - src_pitch, src_offset, srcx, srcy, - dst_pitch, dst_offset, dstx, dsty, - w, h); - - assert( (src_pitch & 63) == 0 ); - assert( (dst_pitch & 63) == 0 ); - assert( (src_offset & 1023) == 0 ); - assert( (dst_offset & 1023) == 0 ); - assert( w < (1<<16) ); - assert( h < (1<<16) ); - - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int), - __FUNCTION__ ); - - - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = RADEON_CP_PACKET3_CNTL_BITBLT_MULTI | (5 << 16); - cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - color_fmt | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); - - cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10); - cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10); - cmd[5].i = (srcx << 16) | srcy; - cmd[6].i = (dstx << 16) | dsty; /* dst */ - cmd[7].i = (w << 16) | h; -} - - -void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ) -{ - drm_radeon_cmd_header_t *cmd; - - assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); - - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int), - __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].wait.cmd_type = RADEON_CMD_WAIT; - cmd[0].wait.flags = flags; -} -#endif - /* ================================================================ * Buffer clear */ diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index b7f07294946..ac763703bcf 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -99,6 +99,7 @@ do { \ /* Can accomodate several state changes and primitive changes without * actually firing the buffer. */ + #define RADEON_STATECHANGE( rmesa, ATOM ) \ do { \ RADEON_NEWPRIM( rmesa ); \ @@ -106,13 +107,12 @@ do { \ rmesa->hw.is_dirty = GL_TRUE; \ } while (0) -#define RADEON_DB_STATE( ATOM ) \ +#define RADEON_DB_STATE( ATOM ) \ memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \ rmesa->hw.ATOM.cmd_size * 4) -static INLINE int RADEON_DB_STATECHANGE( - r100ContextPtr rmesa, - struct radeon_state_atom *atom ) +static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, + struct radeon_state_atom *atom ) { if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { GLuint *tmp; @@ -128,12 +128,11 @@ static INLINE int RADEON_DB_STATECHANGE( return 0; } - /* Fire the buffered vertices no matter what. */ #define RADEON_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->store.cmd_used || rmesa->radeon.dma.flush ) { \ + if ( rmesa->radeon.dma.flush ) { \ radeonFlush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 1d683e5b3aa..6ffc8484809 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2060,6 +2060,8 @@ static void update_texturematrix( GLcontext *ctx ) tpc = (texMatEnabled | rmesa->TexGenEnabled); + fprintf(stderr,"setting tpc to %x %x\n", tpc, rmesa->TexGenEnabled); + /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */ vs &= ~((RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 0a9e8141911..e820bc17b99 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -432,8 +432,6 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } - - static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -442,18 +440,19 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) int i = atom->idx; radeonTexObj *t = r100->state.texture.unit[i].texobj; - if (!t) - return; + fprintf(stderr,"t is %p, i is %d\n", t, i ); - BEGIN_BATCH_NO_AUTOSTATE(dwords + 2); + if (t && !t->image_override) + dwords += 2; + BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 3); if (t && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { - - - OUT_BATCH(atom->cmd[10]); + /* workaround for old CS mechanism */ + OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); + // OUT_BATCH(r100->radeon.radeonScreen); } OUT_BATCH_TABLE((atom->cmd+4), 5); @@ -517,19 +516,25 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.max_state_size = 0; -#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ + + // rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ + + +#define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ do { \ rmesa->hw.ATOM.cmd_size = SZ; \ rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ - rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ - rmesa->hw.ATOM.name = NM; \ + rmesa->hw.ATOM.name = NM; \ rmesa->hw.ATOM.is_tcl = FLAG; \ rmesa->hw.ATOM.check = check_##CHK; \ - rmesa->hw.ATOM.dirty = GL_TRUE; \ + rmesa->hw.ATOM.dirty = GL_TRUE; \ + rmesa->hw.ATOM.idx = IDX; \ rmesa->hw.max_state_size += SZ * sizeof(int); \ } while (0) - - + +#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ + ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) + /* Allocate state buffers: */ ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 ); @@ -549,23 +554,23 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); - ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 ); - ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 ); - ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 ); + ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); + ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); + ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 ); for (i = 0; i < 3; i++) rmesa->hw.tex[i].emit = tex_emit; if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) { - ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); - ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0 ); - ALLOC_STATE( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0 ); + ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); + ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); + ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); } else { - ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); - ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0 ); - ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0 ); + ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); + ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); + ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); } ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); @@ -587,9 +592,9 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); - ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 ); - ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 ); - ALLOC_STATE( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0 ); + ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); + ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); + ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); radeonSetUpAtomList( rmesa ); @@ -810,8 +815,8 @@ void radeonInitState( r100ContextPtr rmesa ) (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); /* Initialize the texture offset to the start of the card texture heap */ - rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; + // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = + // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 4f3acc7dafb..66fb7ef164a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -146,19 +146,6 @@ static GLboolean discrete_prim[0x10] = { static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) { -#if 0 - if (rmesa->radeon.dma.flush == radeonFlushElts && - rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - - GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + - rmesa->tcl.elt_used); - - rmesa->tcl.elt_used += nr*2; - - return dest; - } - else { -#endif if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); @@ -170,7 +157,6 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, rmesa->tcl.hw_primitive, nr ); - // } } #define CLOSE_ELTS() RADEON_NEWPRIM( rmesa ) diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 8784dcc5edd..16bd87a8dc2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -171,6 +171,9 @@ static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) { GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK); + /* Force revalidation to account for switches from/to mipmapping. */ + t->validated = GL_FALSE; + t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK); /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */ @@ -343,12 +346,17 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_MAX_LEVEL: case GL_TEXTURE_MIN_LOD: case GL_TEXTURE_MAX_LOD: + /* This isn't the most efficient solution but there doesn't appear to * be a nice alternative. Since there's no LOD clamping, * we just have to rely on loading the right subset of mipmap levels * to simulate a clamped LOD. */ - driSwapOutTextureObject( (driTextureObject *) t ); + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + t->validated = GL_FALSE; + } break; default: diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index e76b52437ff..9a9af9e938a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -113,253 +113,6 @@ static const struct tx_table tx_table[] = #undef _ALPHA #undef _INVALID -/** - * This function computes the number of bytes of storage needed for - * the given texture object (all mipmap levels, all cube faces). - * The \c image[face][level].x/y/width/height parameters for upload/blitting - * are computed here. \c pp_txfilter, \c pp_txformat, etc. will be set here - * too. - * - * \param rmesa Context pointer - * \param tObj GL texture object whose images are to be posted to - * hardware state. - */ -#if 0 -static void radeonSetTexImages( r100ContextPtr rmesa, - struct gl_texture_object *tObj ) -{ - radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData; - const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; - GLint curOffset, blitWidth; - GLint i, texelBytes; - GLint numLevels; - GLint log2Width, log2Height, log2Depth; - - /* Set the hardware texture format - */ - if ( !t->image_override ) { - t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | - RADEON_TXFORMAT_ALPHA_IN_MAP); - t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - - if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) { - t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter; - } - else { - _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; - } - } - - texelBytes = baseImage->TexFormat->TexelBytes; - - /* Compute which mipmap levels we really want to send to the hardware. - */ - - if (tObj->Target != GL_TEXTURE_CUBE_MAP) - driCalculateTextureFirstLastLevel( (driTextureObject *) t ); - else { - /* r100 can't handle mipmaps for cube/3d textures, so don't waste - memory for them */ - t->base.firstLevel = t->base.lastLevel = tObj->BaseLevel; - } - log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2; - log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2; - log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2; - - numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); - - /* Calculate mipmap offsets and dimensions for blitting (uploading) - * The idea is that we lay out the mipmap levels within a block of - * memory organized as a rectangle of width BLIT_WIDTH_BYTES. - */ - curOffset = 0; - blitWidth = BLIT_WIDTH_BYTES; - t->tile_bits = 0; - - /* figure out if this texture is suitable for tiling. */ - if (texelBytes && (tObj->Target != GL_TEXTURE_RECTANGLE_NV)) { - if (rmesa->texmicrotile && (baseImage->Height > 1)) { - /* allow 32 (bytes) x 1 mip (which will use two times the space - the non-tiled version would use) max if base texture is large enough */ - if ((numLevels == 1) || - (((baseImage->Width * texelBytes / baseImage->Height) <= 32) && - (baseImage->Width * texelBytes > 64)) || - ((baseImage->Width * texelBytes / baseImage->Height) <= 16)) { - /* R100 has two microtile bits (only the txoffset reg, not the blitter) - weird: X2 + OPT: 32bit correct, 16bit completely hosed - X2: 32bit correct, 16bit correct - OPT: 32bit large mips correct, small mips hosed, 16bit completely hosed */ - t->tile_bits |= RADEON_TXO_MICRO_TILE_X2 /*| RADEON_TXO_MICRO_TILE_OPT*/; - } - } - if ((baseImage->Width * texelBytes >= 256) && (baseImage->Height >= 16)) { - /* R100 disables macro tiling only if mip width is smaller than 256 bytes, and not - in the case if height is smaller than 16 (not 100% sure), as does the r200, - so need to disable macro tiling in that case */ - if ((numLevels == 1) || ((baseImage->Width * texelBytes / baseImage->Height) <= 4)) { - t->tile_bits |= RADEON_TXO_MACRO_TILE; - } - } - } - - for (i = 0; i < numLevels; i++) { - const struct gl_texture_image *texImage; - GLuint size; - - texImage = tObj->Image[0][i + t->base.firstLevel]; - if ( !texImage ) - break; - - /* find image size in bytes */ - if (texImage->IsCompressed) { - /* need to calculate the size AFTER padding even though the texture is - submitted without padding. - Only handle pot textures currently - don't know if npot is even possible, - size calculation would certainly need (trivial) adjustments. - Align (and later pad) to 32byte, not sure what that 64byte blit width is - good for? */ - if ((t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK) == RADEON_TXFORMAT_DXT1) { - /* RGB_DXT1/RGBA_DXT1, 8 bytes per block */ - if ((texImage->Width + 3) < 8) /* width one block */ - size = texImage->CompressedSize * 4; - else if ((texImage->Width + 3) < 16) - size = texImage->CompressedSize * 2; - else size = texImage->CompressedSize; - } - else /* DXT3/5, 16 bytes per block */ - if ((texImage->Width + 3) < 8) - size = texImage->CompressedSize * 2; - else size = texImage->CompressedSize; - } - else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { - size = ((texImage->Width * texelBytes + 63) & ~63) * texImage->Height; - } - else if (t->tile_bits & RADEON_TXO_MICRO_TILE_X2) { - /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, - though the actual offset may be different (if texture is less than - 32 bytes width) to the untiled case */ - int w = (texImage->Width * texelBytes * 2 + 31) & ~31; - size = (w * ((texImage->Height + 1) / 2)) * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - } - else { - int w = (texImage->Width * texelBytes + 31) & ~31; - size = w * texImage->Height * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - } - assert(size > 0); - - /* Align to 32-byte offset. It is faster to do this unconditionally - * (no branch penalty). - */ - - curOffset = (curOffset + 0x1f) & ~0x1f; - - if (texelBytes) { - t->image[0][i].x = curOffset; /* fix x and y coords up later together with offset */ - t->image[0][i].y = 0; - t->image[0][i].width = MIN2(size / texelBytes, blitWidth); - t->image[0][i].height = (size / texelBytes) / t->image[0][i].width; - } - else { - t->image[0][i].x = curOffset % BLIT_WIDTH_BYTES; - t->image[0][i].y = curOffset / BLIT_WIDTH_BYTES; - t->image[0][i].width = MIN2(size, BLIT_WIDTH_BYTES); - t->image[0][i].height = size / t->image[0][i].width; - } - -#if 0 - /* for debugging only and only applicable to non-rectangle targets */ - assert(size % t->image[0][i].width == 0); - assert(t->image[0][i].x == 0 - || (size < BLIT_WIDTH_BYTES && t->image[0][i].height == 1)); -#endif - - if (0) - fprintf(stderr, - "level %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n", - i, texImage->Width, texImage->Height, - t->image[0][i].x, t->image[0][i].y, - t->image[0][i].width, t->image[0][i].height, size, curOffset); - - curOffset += size; - - } - - /* Align the total size of texture memory block. - */ - t->base.totalSize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; - - /* Setup remaining cube face blits, if needed */ - if (tObj->Target == GL_TEXTURE_CUBE_MAP) { - const GLuint faceSize = t->base.totalSize; - GLuint face; - /* reuse face 0 x/y/width/height - just update the offset when uploading */ - for (face = 1; face < 6; face++) { - for (i = 0; i < numLevels; i++) { - t->image[face][i].x = t->image[0][i].x; - t->image[face][i].y = t->image[0][i].y; - t->image[face][i].width = t->image[0][i].width; - t->image[face][i].height = t->image[0][i].height; - } - } - t->base.totalSize = 6 * faceSize; /* total texmem needed */ - } - - /* Hardware state: - */ - t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; - t->pp_txfilter |= (numLevels - 1) << RADEON_MAX_MIP_LEVEL_SHIFT; - - t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK | - RADEON_TXFORMAT_HEIGHT_MASK | - RADEON_TXFORMAT_CUBIC_MAP_ENABLE | - RADEON_TXFORMAT_F5_WIDTH_MASK | - RADEON_TXFORMAT_F5_HEIGHT_MASK); - t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) | - (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT)); - - if (tObj->Target == GL_TEXTURE_CUBE_MAP) { - assert(log2Width == log2Height); - t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) | - (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) | - (RADEON_TXFORMAT_CUBIC_MAP_ENABLE)); - t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) | - (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) | - (log2Width << RADEON_FACE_WIDTH_2_SHIFT) | - (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) | - (log2Width << RADEON_FACE_WIDTH_3_SHIFT) | - (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) | - (log2Width << RADEON_FACE_WIDTH_4_SHIFT) | - (log2Height << RADEON_FACE_HEIGHT_4_SHIFT)); - } - - t->pp_txsize = (((tObj->Image[0][t->base.firstLevel]->Width - 1) << 0) | - ((tObj->Image[0][t->base.firstLevel]->Height - 1) << 16)); - - /* Only need to round to nearest 32 for textures, but the blitter - * requires 64-byte aligned pitches, and we may/may not need the - * blitter. NPOT only! - */ - if ( !t->image_override ) { - if (baseImage->IsCompressed) - t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); - else - t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63); - t->pp_txpitch -= 32; - } - - t->dirty_state = R100_TEX_ALL; - - /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */ -} -#endif - - /* ================================================================ * Texture combine functions */ @@ -904,6 +657,52 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, RADEON_TXFORMAT_NON_POWER2) +static void disable_tex_obj_state( r100ContextPtr rmesa, + int unit ) +{ + /* do not use RADEON_DB_STATE to avoid stale texture caches */ + uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; + GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; + GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] ); + + RADEON_STATECHANGE( rmesa, tex[unit] ); + + RADEON_STATECHANGE( rmesa, tcl ); + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | + RADEON_Q_BIT(unit)); + + if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<radeon.glCtx, (RADEON_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = GL_TRUE; + } + + if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) { + /* this seems to be a genuine (r100 only?) hw bug. Need to remove the + cubic_map bit on unit 2 when the unit is disabled, otherwise every + 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other + units, better be safe than sorry though).*/ + RADEON_STATECHANGE( rmesa, tex[unit] ); + rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE; + } + + { + GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4; + GLuint tmp = rmesa->TexGenEnabled; + + rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<TexGenNeedNormals[unit] = 0; + rmesa->TexGenEnabled |= + (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift; + + if (tmp != rmesa->TexGenEnabled) { + rmesa->recheck_texgen[unit] = GL_TRUE; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; + } + } +} + static void import_tex_obj_state( r100ContextPtr rmesa, int unit, radeonTexObjPtr texobj ) @@ -957,6 +756,8 @@ static void import_tex_obj_state( r100ContextPtr rmesa, } texobj->dirty_state &= ~(1<radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } @@ -1102,252 +903,24 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) return GL_TRUE; } -#if 0 -static void disable_tex( GLcontext *ctx, int unit ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - - if (rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<state.texture.unit[unit].texobj != NULL ) { - /* The old texture is no longer bound to this texture unit. - * Mark it as such. - */ - - rmesa->state.texture.unit[unit].texobj->base.bound &= ~(1UL << unit); - rmesa->state.texture.unit[unit].texobj = NULL; - } - - RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= - ~((RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit); - - RADEON_STATECHANGE( rmesa, tcl ); - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | - RADEON_Q_BIT(unit)); - - if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = GL_TRUE; - } - - if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) { - /* this seems to be a genuine (r100 only?) hw bug. Need to remove the - cubic_map bit on unit 2 when the unit is disabled, otherwise every - 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other - units, better be safe than sorry though).*/ - RADEON_STATECHANGE( rmesa, tex[unit] ); - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE; - } - - { - GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4; - GLuint tmp = rmesa->TexGenEnabled; - - rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<TexGenNeedNormals[unit] = 0; - rmesa->TexGenEnabled |= - (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift; - - if (tmp != rmesa->TexGenEnabled) { - rmesa->recheck_texgen[unit] = GL_TRUE; - rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - } - } -} - -static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - - /* Need to load the 2d images associated with this unit. - */ - if (t->pp_txformat & RADEON_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~RADEON_TXFORMAT_NON_POWER2; - t->base.dirty_images[0] = ~0; - } - - ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); - - if ( t->base.dirty_images[0] ) { - RADEON_FIREVERTICES( rmesa ); - radeonSetTexImages( rmesa, tObj ); - radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock && !t->image_override ) - return GL_FALSE; - } - - return GL_TRUE; -} - -static GLboolean enable_tex_cube( GLcontext *ctx, int unit ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - GLuint face; - - /* Need to load the 2d images associated with this unit. - */ - if (t->pp_txformat & RADEON_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~RADEON_TXFORMAT_NON_POWER2; - for (face = 0; face < 6; face++) - t->base.dirty_images[face] = ~0; - } - - ASSERT(tObj->Target == GL_TEXTURE_CUBE_MAP); - - if ( t->base.dirty_images[0] || t->base.dirty_images[1] || - t->base.dirty_images[2] || t->base.dirty_images[3] || - t->base.dirty_images[4] || t->base.dirty_images[5] ) { - /* flush */ - RADEON_FIREVERTICES( rmesa ); - /* layout memory space, once for all faces */ - radeonSetTexImages( rmesa, tObj ); - } - - /* upload (per face) */ - for (face = 0; face < 6; face++) { - if (t->base.dirty_images[face]) { - radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, face ); - } - } - - if ( !t->base.memBlock ) { - /* texmem alloc failed, use s/w fallback */ - return GL_FALSE; - } - - return GL_TRUE; -} - -static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - - if (!(t->pp_txformat & RADEON_TXFORMAT_NON_POWER2)) { - t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; - t->base.dirty_images[0] = ~0; - } - - ASSERT(tObj->Target == GL_TEXTURE_RECTANGLE_NV); - - if ( t->base.dirty_images[0] ) { - RADEON_FIREVERTICES( rmesa ); - radeonSetTexImages( rmesa, tObj ); - radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock && - !t->image_override /* && !rmesa->prefer_gart_client_texturing FIXME */ ) { - fprintf(stderr, "%s: upload failed\n", __FUNCTION__); - return GL_FALSE; - } - } - - return GL_TRUE; -} - - -static GLboolean update_tex_common( GLcontext *ctx, int unit ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - GLenum format; - - /* Fallback if there's a texture border */ - if ( tObj->Image[0][tObj->BaseLevel]->Border > 0 ) { - fprintf(stderr, "%s: border\n", __FUNCTION__); - return GL_FALSE; - } - /* yuv conversion only works in first unit */ - if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) - return GL_FALSE; - - /* Update state if this is a different texture object to last - * time. - */ - if ( rmesa->state.texture.unit[unit].texobj != t ) { - if ( rmesa->state.texture.unit[unit].texobj != NULL ) { - /* The old texture is no longer bound to this texture unit. - * Mark it as such. - */ - - rmesa->state.texture.unit[unit].texobj->base.bound &= - ~(1UL << unit); - } - - rmesa->state.texture.unit[unit].texobj = t; - t->base.bound |= (1UL << unit); - t->dirty_state |= 1<hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<hw.ctx.cmd[CTX_PP_CNTL] |= - (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; - - RADEON_STATECHANGE( rmesa, tcl ); - - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); - - rmesa->recheck_texgen[unit] = GL_TRUE; - } - - if (t->dirty_state & (1<radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - - if (rmesa->recheck_texgen[unit]) { - GLboolean fallback = !radeon_validate_texgen( ctx, unit ); - TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = 0; - rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - - format = tObj->Image[0][tObj->BaseLevel]->_BaseFormat; - if ( rmesa->state.texture.unit[unit].format != format || - rmesa->state.texture.unit[unit].envMode != texUnit->EnvMode ) { - rmesa->state.texture.unit[unit].format = format; - rmesa->state.texture.unit[unit].envMode = texUnit->EnvMode; - if ( ! radeonUpdateTextureEnv( ctx, unit ) ) { - return GL_FALSE; - } - } - - FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); - return !t->border_fallback; -} -#endif - /** * Compute the cached hardware register values for the given texture object. * * \param rmesa Context pointer * \param t the r300 texture object */ -static void setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t) +static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int unit) { - const struct gl_texture_image *firstImage = - t->base.Image[0][t->mt->firstLevel]; + const struct gl_texture_image *firstImage; GLint log2Width, log2Height, log2Depth, texelBytes; - + + firstImage = t->base.Image[0][t->mt->firstLevel]; + + if (firstImage->Border > 0) { + fprintf(stderr, "%s: border\n", __FUNCTION__); + return GL_FALSE; + } + log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; @@ -1361,12 +934,12 @@ static void setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t) RADEON_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - // t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; - // t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; } else { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; + return GL_FALSE; } } @@ -1413,51 +986,57 @@ static void setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t) if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; } - -} -#if 0 -static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) -{ - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - - if ( texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT) ) { - return (enable_tex_rect( ctx, unit ) && - update_tex_common( ctx, unit )); - } - else if ( texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT) ) { - return (enable_tex_2d( ctx, unit ) && - update_tex_common( ctx, unit )); - } - else if ( texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT) ) { - return (enable_tex_cube( ctx, unit ) && - update_tex_common( ctx, unit )); - } - else if ( texUnit->_ReallyEnabled ) { - return GL_FALSE; - } - else { - disable_tex( ctx, unit ); - return GL_TRUE; - } + return GL_TRUE; } -#endif static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit) { r100ContextPtr rmesa = R100_CONTEXT(ctx); radeonTexObj *t = radeon_tex_obj(texObj); + int ret; + + fprintf(stderr,"t dirty %d %x %d\n", unit, t->dirty_state, t->validated); if (!radeon_validate_texture_miptree(ctx, texObj)) return GL_FALSE; - setup_hardware_state(rmesa, t); + /* yuv conversion only works in first unit */ + if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) + return GL_FALSE; + + + ret = setup_hardware_state(rmesa, t, unit); + if (ret == GL_FALSE) + return GL_FALSE; + + RADEON_STATECHANGE( rmesa, ctx ); + rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= + (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; + + RADEON_STATECHANGE( rmesa, tcl ); + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); + + fprintf(stderr,"setting pp cntl to %x\n", rmesa->hw.ctx.cmd[CTX_PP_CNTL]); + rmesa->recheck_texgen[unit] = GL_TRUE; if (t->dirty_state & (1<recheck_texgen[unit]) { + GLboolean fallback = !radeon_validate_texgen( ctx, unit ); + TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = 0; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; + } + + if ( ! radeonUpdateTextureEnv( ctx, unit ) ) { + return GL_FALSE; + } + FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); + t->validated = GL_TRUE; - return GL_TRUE; + return !t->border_fallback; } static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) @@ -1465,8 +1044,12 @@ static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - if (!ctx->Texture.Unit[unit]._ReallyEnabled) + fprintf(stderr,"really enabled %d\n", ctx->Texture.Unit[unit]._ReallyEnabled); + if (!ctx->Texture.Unit[unit]._ReallyEnabled) { + /* disable the unit */ + disable_tex_obj_state(rmesa, unit); return GL_TRUE; + } if (!radeon_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) { _mesa_warning(ctx, @@ -1484,6 +1067,10 @@ void radeonUpdateTextureState( GLcontext *ctx ) r100ContextPtr rmesa = R100_CONTEXT(ctx); GLboolean ok; + /* set the ctx all textures off */ + RADEON_STATECHANGE( rmesa, ctx ); + rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK)); + ok = (radeonUpdateTextureUnit( ctx, 0 ) && radeonUpdateTextureUnit( ctx, 1 ) && radeonUpdateTextureUnit( ctx, 2 )); -- cgit v1.2.3 From d2fa89140ebc5cfdd93dcb37d6106e78b01c34d8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Feb 2009 04:56:16 +1000 Subject: r200: invalidate texture paths in some more places --- src/mesa/drivers/dri/r200/r200_tex.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 52edf7ed0c1..cf0a32bf89b 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -43,8 +43,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/teximage.h" #include "main/texobj.h" -#include "texmem.h" - #include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_state.h" @@ -211,6 +209,9 @@ static void r200SetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) { GLuint anisotropy = (t->pp_txfilter & R200_MAX_ANISO_MASK); + /* Force revalidation to account for switches from/to mipmapping. */ + t->validated = GL_FALSE; + t->pp_txfilter &= ~(R200_MIN_FILTER_MASK | R200_MAG_FILTER_MASK); t->pp_txformat_x &= ~R200_VOLUME_FILTER_MASK; @@ -389,7 +390,11 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, * we just have to rely on loading the right subset of mipmap levels * to simulate a clamped LOD. */ - driSwapOutTextureObject( (driTextureObject *) t ); + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + t->validated = GL_FALSE; + } break; default: -- cgit v1.2.3 From b1df5ed6db4d79de895e37bcdd12dfbaae7bd4f6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Feb 2009 04:57:37 +1000 Subject: radeon: put back state emission lastcmd --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index e820bc17b99..c9278d85107 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -516,14 +516,11 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.max_state_size = 0; - - // rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ - - #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ do { \ rmesa->hw.ATOM.cmd_size = SZ; \ rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ + rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ rmesa->hw.ATOM.name = NM; \ rmesa->hw.ATOM.is_tcl = FLAG; \ rmesa->hw.ATOM.check = check_##CHK; \ -- cgit v1.2.3 From c3ca94bc9115f0f328327f1e96fac84b87d5efd5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Feb 2009 23:36:28 +1000 Subject: radeon: fix fallback case where t->mt is valid NULL --- src/mesa/drivers/dri/radeon/common_misc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 82cead1a25a..4770c987c87 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1469,8 +1469,9 @@ void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeonTexObj* t = radeon_tex_obj(texObj); int face, level; - // assert(texObj->_Complete); - assert(t->mt); + /* for r100 3D sw fallbacks don't have mt */ + if (!t->mt) + return; radeon_bo_map(t->mt->bo, GL_FALSE); for(face = 0; face < t->mt->faces; ++face) { @@ -1484,8 +1485,9 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeonTexObj* t = radeon_tex_obj(texObj); int face, level; - // assert(texObj->_Complete); - assert(t->mt); + /* for r100 3D sw fallbacks don't have mt */ + if (!t->mt) + return; for(face = 0; face < t->mt->faces; ++face) { for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) -- cgit v1.2.3 From 639b5fca0c5cea26a9dc393b538508aece16ce6b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Feb 2009 23:38:51 +1000 Subject: r100: fix 3D texture fallback --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 2 ++ src/mesa/drivers/dri/radeon/radeon_state_init.c | 8 +++----- src/mesa/drivers/dri/radeon/radeon_tcl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_tex.c | 10 ++++++++-- src/mesa/drivers/dri/radeon/radeon_texstate.c | 6 +++++- 5 files changed, 19 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 78ee322b4cc..45d750dbf42 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -312,7 +312,9 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLushort *retval; int align_min_nr; BATCH_LOCALS(&rmesa->radeon); + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index c9278d85107..f12d9bdb50d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -440,16 +440,14 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) int i = atom->idx; radeonTexObj *t = r100->state.texture.unit[i].texobj; - fprintf(stderr,"t is %p, i is %d\n", t, i ); - - if (t && !t->image_override) + if (t && t->mt && !t->image_override) dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 3); - if (t && !t->image_override) { + if (t && t->mt && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!t) { + } else { /* workaround for old CS mechanism */ OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); // OUT_BATCH(r100->radeon.radeonScreen); diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 66fb7ef164a..daa88f43c75 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -159,7 +159,7 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) rmesa->tcl.hw_primitive, nr ); } -#define CLOSE_ELTS() RADEON_NEWPRIM( rmesa ) +#define CLOSE_ELTS() if (0) RADEON_NEWPRIM( rmesa ) diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 16bd87a8dc2..a916b63a279 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -373,6 +373,7 @@ static void radeonDeleteTexture( GLcontext *ctx, { r100ContextPtr rmesa = R100_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); + int i; if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) { fprintf( stderr, "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj, @@ -381,7 +382,13 @@ static void radeonDeleteTexture( GLcontext *ctx, if ( rmesa ) { RADEON_FIREVERTICES( rmesa ); - + for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { + if ( t == rmesa->state.texture.unit[i].texobj ) { + rmesa->state.texture.unit[i].texobj = NULL; + rmesa->hw.tex[i].dirty = GL_FALSE; + rmesa->hw.cube[i].dirty = GL_FALSE; + } + } } if (t->mt) { @@ -453,7 +460,6 @@ void radeonInitTextureFuncs( struct dd_function_table *functions ) functions->NewTextureObject = radeonNewTextureObject; // functions->BindTexture = radeonBindTexture; functions->DeleteTexture = radeonDeleteTexture; - functions->IsTextureResident = driIsTextureResident; functions->TexEnv = radeonTexEnv; functions->TexParameter = radeonTexParameter; diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 9a9af9e938a..0c7c8555776 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -1044,7 +1044,11 @@ static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) r100ContextPtr rmesa = R100_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - fprintf(stderr,"really enabled %d\n", ctx->Texture.Unit[unit]._ReallyEnabled); + + if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) { + return GL_FALSE; + } + if (!ctx->Texture.Unit[unit]._ReallyEnabled) { /* disable the unit */ disable_tex_obj_state(rmesa, unit); -- cgit v1.2.3 From 3e4d0c2a5d709e4b87474dfe6e64d67bb217135c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Feb 2009 23:39:13 +1000 Subject: r100: remove debug code --- src/mesa/drivers/dri/radeon/radeon_state.c | 2 -- src/mesa/drivers/dri/radeon/radeon_texstate.c | 3 --- 2 files changed, 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 6ffc8484809..1d683e5b3aa 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2060,8 +2060,6 @@ static void update_texturematrix( GLcontext *ctx ) tpc = (texMatEnabled | rmesa->TexGenEnabled); - fprintf(stderr,"setting tpc to %x %x\n", tpc, rmesa->TexGenEnabled); - /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */ vs &= ~((RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 0c7c8555776..cabac6c13d5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -995,8 +995,6 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec radeonTexObj *t = radeon_tex_obj(texObj); int ret; - fprintf(stderr,"t dirty %d %x %d\n", unit, t->dirty_state, t->validated); - if (!radeon_validate_texture_miptree(ctx, texObj)) return GL_FALSE; @@ -1016,7 +1014,6 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec RADEON_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); - fprintf(stderr,"setting pp cntl to %x\n", rmesa->hw.ctx.cmd[CTX_PP_CNTL]); rmesa->recheck_texgen[unit] = GL_TRUE; if (t->dirty_state & (1< Date: Wed, 11 Feb 2009 02:41:11 +1000 Subject: radeon/r200/r300: fix span code for depth reading. makes the maskedClear test work --- src/mesa/drivers/dri/r200/r200_span.c | 16 +++++++--------- src/mesa/drivers/dri/radeon/radeon_span.c | 28 +++++++++++++--------------- 2 files changed, 20 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index 17c651395b9..384883400bd 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -61,9 +61,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define LOCAL_DEPTH_VARS \ struct radeon_renderbuffer *rrb = (void *) rb; \ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ - GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; + const GLuint bottom = dPriv->h - 1; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -118,10 +116,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d + *(GLushort *)radeon_ptr(rrb, _x, _y) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) + d = *(GLushort *)radeon_ptr(rrb, _x, _y) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -133,7 +131,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ @@ -142,7 +140,7 @@ do { \ #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0x00ffffff); \ }while(0) #define TAG(x) radeon##x##_z24_s8 @@ -157,7 +155,7 @@ do { \ */ #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ @@ -166,7 +164,7 @@ do { \ #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ d = tmp >> 24; \ diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 332a0ca69b1..43c00cb86cb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -68,9 +68,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define LOCAL_DEPTH_VARS \ struct radeon_renderbuffer *rrb = (void *) rb; \ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ - GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; + const GLuint bottom = dPriv->h - 1; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -109,10 +107,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d + *(GLushort *)radeon_ptr(rrb, _x, _y) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) + d = *(GLushort *)radeon_ptr(rrb, _x, _y) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -127,7 +125,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( drb, _x, _y ); \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ @@ -136,7 +134,7 @@ do { \ #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ @@ -147,14 +145,14 @@ do { \ #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ - _y + yo )) & 0xffffff00) >> 8; \ + d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x, \ + _y)) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \ - } while (0) + d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0x00ffffff); \ + } while (0) #endif #define TAG(x) radeon##x##_z24_s8 @@ -169,7 +167,7 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( drb, _x, _y ); \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ @@ -178,7 +176,7 @@ do { \ #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ @@ -189,14 +187,14 @@ do { \ #ifdef COMPILE_R300 #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ + GLuint offset = radeon_mba_z32( drb, _x, _y ); \ GLuint tmp = *(GLuint *)(buf + offset); \ d = tmp & 0x000000ff; \ } while (0) #else #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ GLuint tmp = *_ptr; \ d = (tmp & 0xff000000) >> 24; \ } while (0) -- cgit v1.2.3 From 18aca218a29578b5cb14a3bc492330406d3a761d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 02:41:39 +1000 Subject: radeon: r100 can't use some of the texture formats. this fixes the texrect-many test --- src/mesa/drivers/dri/radeon/common_misc.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 4770c987c87..934105a778b 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1558,12 +1558,17 @@ void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_objec /* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *radeonChoose8888TexFormat(GLenum srcFormat, - GLenum srcType) +static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, + GLenum srcFormat, + GLenum srcType) { const GLuint ui = 1; const GLubyte littleEndian = *((const GLubyte *)&ui); + /* r100 can only do this */ + if (IS_R100_CLASS(rmesa->radeonScreen)) + return _dri_texformat_argb8888; + if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || @@ -1619,7 +1624,7 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_UNSIGNED_SHORT_1_5_5_5_REV: return _dri_texformat_argb1555; default: - return do32bpt ? radeonChoose8888TexFormat(format, type) : + return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type) : _dri_texformat_argb4444; } @@ -1646,8 +1651,8 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_RGBA12: case GL_RGBA16: return !force16bpt ? - radeonChoose8888TexFormat(format, - type) : _dri_texformat_argb4444; + radeonChoose8888TexFormat(rmesa, format,type) : + _dri_texformat_argb4444; case GL_RGBA4: case GL_RGBA2: -- cgit v1.2.3 From 7394c429c065eb96801500605ab7caa0a1289193 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 05:07:31 +1000 Subject: radeon/r200: flush vertices when data in cmdbuf. This fixes a whole bunch of regressions in piglit --- src/mesa/drivers/dri/r200/r200_ioctl.h | 4 +++- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 6b9e4be30a0..316acef4593 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -39,6 +39,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_dri.h" #include "r200_lock.h" +#include "radeon_cs_legacy.h" + #include "xf86drm.h" #include "drm.h" #include "radeon_drm.h" @@ -129,7 +131,7 @@ static INLINE int R200_DB_STATECHANGE( */ #define R200_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->radeon.dma.flush ) { \ + if ( rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \ r200Flush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index ac763703bcf..4e93804646a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/simple_list.h" #include "radeon_lock.h" - +#include "radeon_cs_legacy.h" extern void radeonEmitState( r100ContextPtr rmesa ); extern void radeonEmitVertexAOS( r100ContextPtr rmesa, @@ -132,9 +132,9 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, */ #define RADEON_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->radeon.dma.flush ) { \ + if (rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \ radeonFlush( rmesa->radeon.glCtx ); \ - } \ + } \ } while (0) /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ -- cgit v1.2.3 From 45496122b7b590479a4ed60c8bbdc1725cad0211 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 05:47:55 +1000 Subject: radeon/r200/r300: merge span code into single shared file --- src/mesa/drivers/dri/r200/Makefile | 4 +- src/mesa/drivers/dri/r200/r200_context.c | 2 - src/mesa/drivers/dri/r200/r200_span.c | 202 ---------------------- src/mesa/drivers/dri/r200/r200_span.h | 44 ----- src/mesa/drivers/dri/r300/Makefile | 1 + src/mesa/drivers/dri/r300/r300_context.c | 1 - src/mesa/drivers/dri/r300/radeon_span.c | 245 --------------------------- src/mesa/drivers/dri/radeon/common_misc.c | 3 + src/mesa/drivers/dri/radeon/radeon_context.c | 1 - src/mesa/drivers/dri/radeon/radeon_span.c | 64 ++++--- src/mesa/drivers/dri/radeon/radeon_span.h | 2 - 11 files changed, 45 insertions(+), 524 deletions(-) delete mode 100644 src/mesa/drivers/dri/r200/r200_span.c delete mode 100644 src/mesa/drivers/dri/r200/r200_span.h delete mode 100644 src/mesa/drivers/dri/r300/radeon_span.c (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index d96999f7bbb..b87e9f206c7 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -21,7 +21,6 @@ DRIVER_SOURCES = r200_context.c \ r200_texstate.c \ r200_tcl.c \ r200_swtcl.c \ - r200_span.c \ r200_maos.c \ r200_sanity.c \ r200_fragshader.c \ @@ -32,6 +31,7 @@ DRIVER_SOURCES = r200_context.c \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_mipmap_tree.c \ + radeon_span.c \ $(EGL_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -56,6 +56,8 @@ COMMON_SYMLINKS = \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ radeon_cs_legacy.h \ + radeon_span.h \ + radeon_span.c \ radeon_buffer.h \ common_context.h \ common_lock.c \ diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 7a8c596ecf9..1d86a48a5d9 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -54,7 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" -#include "r200_span.h" #include "r200_pixel.h" #include "r200_tex.h" #include "r200_swtcl.h" @@ -521,7 +520,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, /* plug in a few more device driver functions */ /* XXX these should really go right after _mesa_init_driver_functions() */ r200InitPixelFuncs( ctx ); - r200InitSpanFuncs( ctx ); r200InitTnlFuncs( ctx ); r200InitState( rmesa ); r200InitSwtcl( ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c deleted file mode 100644 index 384883400bd..00000000000 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ /dev/null @@ -1,202 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/colormac.h" -#include "swrast/swrast.h" - -#include "r200_context.h" -#include "radeon_buffer.h" -#include "r200_ioctl.h" -#include "r200_state.h" -#include "r200_span.h" -#include "r200_tex.h" - -#define DBG 0 - -/* - * Note that all information needed to access pixels in a renderbuffer - * should be obtained through the gl_renderbuffer parameter, not per-context - * information. - */ -#define LOCAL_VARS \ - struct radeon_renderbuffer *rrb = (void *) rb; \ - const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ - GLuint p; \ - (void) p; - -#define LOCAL_DEPTH_VARS \ - struct radeon_renderbuffer *rrb = (void *) rb; \ - const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; - -#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS - -#define Y_FLIP(Y) (bottom - (Y)) - -#define HW_LOCK() - -#define HW_UNLOCK() - - - -/* ================================================================ - * Color buffer - */ - -/* 16 bit, RGB565 color spanline and pixel functions - */ -#define SPANTMP_PIXEL_FMT GL_RGB -#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 - -#define TAG(x) radeon##x##_RGB565 -#define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) -#include "spantmp2.h" - -/* 32 bit, ARGB8888 color spanline and pixel functions - */ -#define SPANTMP_PIXEL_FMT GL_BGRA -#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV - -#define TAG(x) radeon##x##_ARGB8888 -#define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) -#include "spantmp2.h" - - -/* ================================================================ - * Depth buffer - */ - -/* The Radeon family has depth tiling on all the time, so we have to convert - * the x,y coordinates into the memory bus address (mba) in the same - * manner as the engine. In each case, the linear block address (ba) - * is calculated, and then wired with x and y to produce the final - * memory address. - * The chip will do address translation on its own if the surface registers - * are set up correctly. It is not quite enough to get it working with hyperz too... - */ - -/* 16-bit depth buffer functions - */ -#define VALUE_TYPE GLushort - -#define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)radeon_ptr(rrb, _x, _y) = d - -#define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)radeon_ptr(rrb, _x, _y) - -#define TAG(x) radeon##x##_z16 -#include "depthtmp.h" - - -/* 24 bit depth, 8 bit stencil depthbuffer functions - */ -#define VALUE_TYPE GLuint - -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ - GLuint tmp = *_ptr; \ - tmp &= 0xff000000; \ - tmp |= ((d) & 0x00ffffff); \ - *_ptr = tmp; \ -} while (0) - -#define READ_DEPTH( d, _x, _y ) \ - do { \ - d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0x00ffffff); \ - }while(0) - -#define TAG(x) radeon##x##_z24_s8 -#include "depthtmp.h" - - -/* ================================================================ - * Stencil buffer - */ - -/* 24 bit depth, 8 bit stencil depthbuffer functions - */ -#define WRITE_STENCIL( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ - GLuint tmp = *_ptr; \ - tmp &= 0x00ffffff; \ - tmp |= (((d) & 0xff) << 24); \ - *_ptr = tmp; \ -} while (0) - -#define READ_STENCIL( d, _x, _y ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ - GLuint tmp = *_ptr; \ - tmp &= 0xff000000; \ - d = tmp >> 24; \ -} while (0) - -#define TAG(x) radeon##x##_z24_s8 -#include "stenciltmp.h" - - -void r200InitSpanFuncs( GLcontext *ctx ) -{ - struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx); - swdd->SpanRenderStart = radeonSpanRenderStart; - swdd->SpanRenderFinish = radeonSpanRenderFinish; -} - - - -/** - * Plug in the Get/Put routines for the given driRenderbuffer. - */ -void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) -{ - if (rrb->base.InternalFormat == GL_RGB5) { - radeonInitPointers_RGB565(&rrb->base); - } else if (rrb->base.InternalFormat == GL_RGBA8) { - radeonInitPointers_ARGB8888(&rrb->base); - } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { - radeonInitDepthPointers_z16(&rrb->base); - } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { - radeonInitDepthPointers_z24_s8(&rrb->base); - } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&rrb->base); - } -} diff --git a/src/mesa/drivers/dri/r200/r200_span.h b/src/mesa/drivers/dri/r200/r200_span.h deleted file mode 100644 index b2f3d5e43c8..00000000000 --- a/src/mesa/drivers/dri/r200/r200_span.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#ifndef __R200_SPAN_H__ -#define __R200_SPAN_H__ - -#include "drirenderbuffer.h" - -extern void r200InitSpanFuncs( GLcontext *ctx ); - -extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); - -#endif diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index ce425e1d61a..4042005d031 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -73,6 +73,7 @@ COMMON_SYMLINKS = \ radeon_screen.c \ radeon_screen.h \ radeon_span.h \ + radeon_span.c \ radeon_buffer.h \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index ba784e8c903..3bd54f7dff9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -429,7 +429,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); - radeonInitSpanFuncs(ctx); r300InitCmdBuf(r300); r300InitState(r300); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c deleted file mode 100644 index 5019ee44322..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ /dev/null @@ -1,245 +0,0 @@ -/************************************************************************** - -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - * - */ - -#include "main/glheader.h" -#include "swrast/swrast.h" - -#include "r300_state.h" -#include "radeon_ioctl.h" -#include "r300_ioctl.h" -#include "radeon_span.h" - -#include "radeon_buffer.h" - -#define DBG 0 - -/* - * Note that all information needed to access pixels in a renderbuffer - * should be obtained through the gl_renderbuffer parameter, not per-context - * information. - */ -#define LOCAL_VARS \ - struct radeon_renderbuffer *rrb = (void *) rb; \ - const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ - GLuint p; \ - (void)p; - -#define LOCAL_DEPTH_VARS \ - struct radeon_renderbuffer *rrb = (void *) rb; \ - const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ - GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; - -#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS - -#define Y_FLIP(Y) (bottom - (Y)) - -#define HW_LOCK() - -#define HW_UNLOCK() - -/* ================================================================ - * Color buffer - */ - -/* 16 bit, RGB565 color spanline and pixel functions - */ -#define SPANTMP_PIXEL_FMT GL_RGB -#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 - -#define TAG(x) radeon##x##_RGB565 -#define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) -#include "spantmp2.h" - -/* 32 bit, ARGB8888 color spanline and pixel functions - */ -#define SPANTMP_PIXEL_FMT GL_BGRA -#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV - -#define TAG(x) radeon##x##_ARGB8888 -#define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) -#include "spantmp2.h" - -/* ================================================================ - * Depth buffer - */ - -/* The Radeon family has depth tiling on all the time, so we have to convert - * the x,y coordinates into the memory bus address (mba) in the same - * manner as the engine. In each case, the linear block address (ba) - * is calculated, and then wired with x and y to produce the final - * memory address. - * The chip will do address translation on its own if the surface registers - * are set up correctly. It is not quite enough to get it working with hyperz - * too... - */ - -/* 16-bit depth buffer functions - */ -#define VALUE_TYPE GLushort - -#define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d - -#define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) - -#define TAG(x) radeon##x##_z16 -#include "depthtmp.h" - -/* 24 bit depth, 8 bit stencil depthbuffer functions - * - * Careful: It looks like the R300 uses ZZZS byte order while the R200 - * uses SZZZ for 24 bit depth, 8 bit stencil mode. - */ -#define VALUE_TYPE GLuint - -#ifdef COMPILE_R300 -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *_ptr; \ - tmp &= 0x000000ff; \ - tmp |= ((d << 8) & 0xffffff00); \ - *_ptr = tmp; \ -} while (0) -#else -#define WRITE_DEPTH( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *_ptr; \ - tmp &= 0xff000000; \ - tmp |= ((d) & 0x00ffffff); \ - *_ptr = tmp; \ -} while (0) -#endif - -#ifdef COMPILE_R300 -#define READ_DEPTH( d, _x, _y ) \ - do { \ - d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0xffffff00) >> 8; \ - }while(0) -#else -#define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo )) & 0x00ffffff; -#endif -/* - fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\ - d = *(GLuint*)(radeon_ptr(rrb, _x + xo, _y + yo )) & 0x00ffffff; -*/ -#define TAG(x) radeon##x##_z24_s8 -#include "depthtmp.h" - -/* ================================================================ - * Stencil buffer - */ - -/* 24 bit depth, 8 bit stencil depthbuffer functions - */ -#ifdef COMPILE_R300 -#define WRITE_STENCIL( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ - GLuint tmp = *_ptr; \ - tmp &= 0xffffff00; \ - tmp |= (d) & 0xff; \ - *_ptr = tmp; \ -} while (0) -#else -#define WRITE_STENCIL( _x, _y, d ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \ - GLuint tmp = *_ptr; \ - tmp &= 0x00ffffff; \ - tmp |= (((d) & 0xff) << 24); \ - *_ptr = tmp; \ -} while (0) -#endif - -#ifdef COMPILE_R300 -#define READ_STENCIL( d, _x, _y ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *_ptr; \ - d = tmp & 0x000000ff; \ -} while (0) -#else -#define READ_STENCIL( d, _x, _y ) \ -do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \ - GLuint tmp = *_ptr; \ - d = (tmp & 0xff000000) >> 24; \ -} while (0) -#endif - -#define TAG(x) radeon##x##_z24_s8 -#include "stenciltmp.h" - -void radeonInitSpanFuncs(GLcontext * ctx) -{ - struct swrast_device_driver *swdd = - _swrast_GetDeviceDriverReference(ctx); - swdd->SpanRenderStart = radeonSpanRenderStart; - swdd->SpanRenderFinish = radeonSpanRenderFinish; -} - -/** - * Plug in the Get/Put routines for the given driRenderbuffer. - */ -void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) -{ - if (rrb->base.InternalFormat == GL_RGB5) { - radeonInitPointers_RGB565(&rrb->base); - } else if (rrb->base.InternalFormat == GL_RGBA8) { - radeonInitPointers_ARGB8888(&rrb->base); - } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { - radeonInitDepthPointers_z16(&rrb->base); - } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { - radeonInitDepthPointers_z24_s8(&rrb->base); - } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&rrb->base); - } -} diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 934105a778b..96ed3d35768 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -73,6 +73,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_lock.h" #include "common_cmdbuf.h" #include "radeon_mipmap_tree.h" +#include "radeon_span.h" #define DRIVER_DATE "20090101" @@ -853,6 +854,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon, (*sPriv->systemTime->getUST) (&radeon->swap_ust); + radeonInitSpanFuncs( ctx ); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 1d756bd868b..3908dad3632 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -448,7 +448,6 @@ radeonCreateContext( const __GLcontextModes *glVisual, /* XXX these should really go right after _mesa_init_driver_functions() */ radeonInitIoctlFuncs( ctx ); radeonInitStateFuncs( ctx ); - radeonInitSpanFuncs( ctx ); radeonInitState( rmesa ); radeonInitSwtcl( ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 43c00cb86cb..bd613f4779c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -43,13 +43,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/glheader.h" #include "swrast/swrast.h" -#include "radeon_context.h" -#include "radeon_ioctl.h" -#include "radeon_state.h" +#include "common_context.h" +#include "common_misc.h" #include "radeon_span.h" -#include "radeon_tex.h" -#include "drirenderbuffer.h" +#include "radeon_buffer.h" #define DBG 0 @@ -62,11 +60,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct radeon_renderbuffer *rrb = (void *) rb; \ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; \ - GLuint p; \ - (void) p; + GLuint p; \ + (void)p; #define LOCAL_DEPTH_VARS \ - struct radeon_renderbuffer *rrb = (void *) rb; \ + struct radeon_renderbuffer *rrb = (void *) rb; \ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ const GLuint bottom = dPriv->h - 1; @@ -102,6 +100,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) #include "spantmp2.h" +/* ================================================================ + * Depth buffer + */ + +/* The Radeon family has depth tiling on all the time, so we have to convert + * the x,y coordinates into the memory bus address (mba) in the same + * manner as the engine. In each case, the linear block address (ba) + * is calculated, and then wired with x and y to produce the final + * memory address. + * The chip will do address translation on its own if the surface registers + * are set up correctly. It is not quite enough to get it working with hyperz + * too... + */ + /* 16-bit depth buffer functions */ #define VALUE_TYPE GLushort @@ -125,16 +137,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x, _y ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint tmp = *_ptr; \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ @@ -144,17 +156,17 @@ do { \ #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ - do { \ - d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x, \ - _y)) & 0xffffff00) >> 8; \ + do { \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - do { \ - d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0x00ffffff); \ - } while (0) + d = *(GLuint*)(radeon_ptr32(rrb, _x, _y )) & 0x00ffffff; #endif - +/* + fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\ + d = *(GLuint*)(radeon_ptr(rrb, _x, _y )) & 0x00ffffff; +*/ #define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" @@ -167,11 +179,11 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x, _y ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ + GLuint tmp = *_ptr; \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ - *(GLuint *)(buf + offset) = tmp; \ + *_ptr = tmp; \ } while (0) #else #define WRITE_STENCIL( _x, _y, d ) \ @@ -187,15 +199,15 @@ do { \ #ifdef COMPILE_R300 #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x, _y ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint tmp = *_ptr; \ d = tmp & 0x000000ff; \ } while (0) #else #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ - GLuint tmp = *_ptr; \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint tmp = *_ptr; \ d = (tmp & 0xff000000) >> 24; \ } while (0) #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h index 93d76303109..dda542c8d19 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h @@ -42,8 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_SPAN_H__ #define __RADEON_SPAN_H__ -#include "drirenderbuffer.h" - #include "radeon_buffer.h" extern void radeonInitSpanFuncs(GLcontext * ctx); -- cgit v1.2.3 From edbe1fac6a1793da7faca104691a453023d9efac Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 07:02:18 +1000 Subject: radeon: fix span init needs more work --- src/mesa/drivers/dri/r200/r200_context.c | 1 + src/mesa/drivers/dri/r300/r300_context.c | 1 + src/mesa/drivers/dri/radeon/common_misc.c | 2 -- src/mesa/drivers/dri/radeon/radeon_context.c | 1 + 4 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 1d86a48a5d9..00274fbd439 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -519,6 +519,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, #endif /* plug in a few more device driver functions */ /* XXX these should really go right after _mesa_init_driver_functions() */ + radeonInitSpanFuncs( ctx ); r200InitPixelFuncs( ctx ); r200InitTnlFuncs( ctx ); r200InitState( rmesa ); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3bd54f7dff9..9ab7e3ae881 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -429,6 +429,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); + radeonInitSpanFuncs( ctx ); r300InitCmdBuf(r300); r300InitState(r300); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 96ed3d35768..21719c69eca 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -854,8 +854,6 @@ GLboolean radeonInitContext(radeonContextPtr radeon, (*sPriv->systemTime->getUST) (&radeon->swap_ust); - radeonInitSpanFuncs( ctx ); - return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 3908dad3632..6fa01f4ded0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -446,6 +446,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); /* XXX these should really go right after _mesa_init_driver_functions() */ + radeonInitSpanFuncs( ctx ); radeonInitIoctlFuncs( ctx ); radeonInitStateFuncs( ctx ); radeonInitState( rmesa ); -- cgit v1.2.3 From c5d9a7ab3034b90614689f223b94ac81b8a84338 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 20:10:59 +1000 Subject: r200: fix build --- src/mesa/drivers/dri/radeon/radeon_screen.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 4ff4267348b..497582ee232 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -48,20 +48,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_screen.h" #include "radeon_buffer.h" #include "common_misc.h" +#include "radeon_span.h" #if !RADEON_COMMON #include "radeon_context.h" -#include "radeon_span.h" #include "radeon_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) #include "r200_context.h" #include "r200_ioctl.h" -#include "r200_span.h" #include "r200_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) #include "r300_context.h" #include "r300_fragprog.h" #include "r300_tex.h" -#include "radeon_span.h" #endif #include "utils.h" -- cgit v1.2.3 From 832446c892caa0656f9d903c42c4e05fae44ef3d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 16:50:19 +1000 Subject: r300: fix front buffer rendering properly fixes tests in glean --- src/mesa/drivers/dri/r300/r300_state.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index e5939afeeb3..bdb67a1afd3 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2740,6 +2740,27 @@ void r300UpdateClipPlanes( GLcontext *ctx ) } } +static void r300DrawBuffer( GLcontext *ctx, GLenum mode ) +{ + r300ContextPtr rmesa = R300_CONTEXT(ctx); + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s %s\n", __FUNCTION__, + _mesa_lookup_enum_by_nr( mode )); + + R300_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + + radeonSetCliprects( &rmesa->radeon ); + radeonUpdatePageFlipping(&rmesa->radeon); +} + +static void r300ReadBuffer( GLcontext *ctx, GLenum mode ) +{ + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s %s\n", __FUNCTION__, + _mesa_lookup_enum_by_nr( mode )); + +}; + /** * Initialize driver's state callback functions */ @@ -2782,4 +2803,7 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->RenderMode = r300RenderMode; functions->ClipPlane = r300ClipPlane; + + functions->DrawBuffer = r300DrawBuffer; + functions->ReadBuffer = r300ReadBuffer; } -- cgit v1.2.3 From 7e98907eb8da936d72902fa0bb456962fe6ac551 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 16:52:56 +1000 Subject: radeon: cleanup cmdbuffer --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 5 ++--- src/mesa/drivers/dri/r300/r300_context.c | 4 +++- src/mesa/drivers/dri/radeon/common_misc.c | 8 ++++++-- 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index bbc71575950..ec702f6eb3c 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -97,12 +97,12 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) struct radeon_state_atom *atom; int dwords; - cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); BEGIN_BATCH_NO_AUTOSTATE(2); OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1)); OUT_BATCH(R300_TX_FLUSH); END_BATCH(); - end_3d(r300); + end_3d(r300); /* Emit actual atoms */ foreach(atom, &r300->hw.atomlist) { @@ -724,6 +724,5 @@ void r300DestroyCmdBuf(r300ContextPtr r300) foreach(atom, &r300->hw.atomlist) { FREE(atom->cmd); } - rcommonDestroyCmdBuf(&r300->radeon); } diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 9ab7e3ae881..3e47888e458 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -487,15 +487,17 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) _swrast_DestroyContext(r300->radeon.glCtx); rcommonFlushCmdBuf(&r300->radeon, __FUNCTION__); - r300DestroyCmdBuf(r300); if (radeon->state.scissor.pClipRects) { FREE(radeon->state.scissor.pClipRects); radeon->state.scissor.pClipRects = NULL; } + r300DestroyCmdBuf(r300); + radeonCleanupContext(&r300->radeon); + /* the memory manager might be accessed when Mesa frees the shared * state, so don't destroy it earlier */ diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 21719c69eca..333db053bbb 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -866,6 +866,9 @@ void radeonCleanupContext(radeonContextPtr radeon) FILE *track; struct radeon_renderbuffer *rb; GLframebuffer *fb; + + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); fb = (void*)radeon->dri.drawable->driverPrivate; rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; @@ -906,12 +909,13 @@ void radeonCleanupContext(radeonContextPtr radeon) * radeon->glCtx->DriverCtx = NULL; */ - /* free the Mesa context */ - _mesa_destroy_context(radeon->glCtx); + /* free the option cache */ driDestroyOptionCache(&radeon->optionCache); + rcommonDestroyCmdBuf(radeon); + if (radeon->state.scissor.pClipRects) { FREE(radeon->state.scissor.pClipRects); radeon->state.scissor.pClipRects = 0; -- cgit v1.2.3 From 3713a7accf8e10049c878ae62f6bc199ef1566eb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 19:03:56 +1000 Subject: radeon: unmap in case of two dma regions being used for one cmdbuf --- src/mesa/drivers/dri/radeon/common_misc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 333db053bbb..9456f2a4389 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2446,6 +2446,7 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) } if (rmesa->dma.current) { + radeon_bo_unmap(rmesa->dma.current); radeon_bo_unref(rmesa->dma.current); rmesa->dma.current = 0; } -- cgit v1.2.3 From f3f1f7dc20484a60b1325e60e0c9bb994ab591f1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Feb 2009 19:04:39 +1000 Subject: r300: disable assert that fires --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index ec702f6eb3c..303efe3ada1 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -282,7 +282,7 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); } else if (!t) { - assert(0); + //assert(0); } else { if (t->bo) { BEGIN_BATCH_NO_AUTOSTATE(4); -- cgit v1.2.3 From 1090d206de011a67d236d8c4ae32d2d42b2f6337 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 21:16:39 +1000 Subject: radeon/r200/r300: another big merge upheavel. This merges lots of the hw state atom emission and firevertices code. it also removes a lot of the extra radeon crap from r300 and merge scissor --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 195 +++++------------------ src/mesa/drivers/dri/r200/r200_context.c | 32 +--- src/mesa/drivers/dri/r200/r200_context.h | 14 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 61 +------ src/mesa/drivers/dri/r200/r200_ioctl.h | 14 +- src/mesa/drivers/dri/r200/r200_state.c | 29 +--- src/mesa/drivers/dri/r200/r200_state_init.c | 15 +- src/mesa/drivers/dri/r200/r200_swtcl.c | 10 +- src/mesa/drivers/dri/r200/r200_tcl.c | 6 +- src/mesa/drivers/dri/r200/r200_tex.c | 2 +- src/mesa/drivers/dri/r300/Makefile | 4 - src/mesa/drivers/dri/r300/r300_cmdbuf.c | 119 ++------------ src/mesa/drivers/dri/r300/r300_context.c | 32 ++-- src/mesa/drivers/dri/r300/r300_context.h | 9 +- src/mesa/drivers/dri/r300/r300_emit.c | 1 - src/mesa/drivers/dri/r300/r300_emit.h | 32 ++-- src/mesa/drivers/dri/r300/r300_ioctl.c | 7 +- src/mesa/drivers/dri/r300/r300_render.c | 2 - src/mesa/drivers/dri/r300/r300_state.c | 16 +- src/mesa/drivers/dri/r300/r300_state.h | 15 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/r300/r300_tex.c | 2 +- src/mesa/drivers/dri/r300/r300_texmem.c | 58 ------- src/mesa/drivers/dri/r300/r300_texstate.c | 1 - src/mesa/drivers/dri/r300/radeon_context.c | 75 --------- src/mesa/drivers/dri/r300/radeon_context.h | 43 ----- src/mesa/drivers/dri/r300/radeon_ioctl.c | 69 -------- src/mesa/drivers/dri/r300/radeon_ioctl.h | 57 ------- src/mesa/drivers/dri/r300/radeon_state.c | 109 ------------- src/mesa/drivers/dri/r300/radeon_state.h | 39 ----- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 14 +- src/mesa/drivers/dri/radeon/common_context.h | 27 ++-- src/mesa/drivers/dri/radeon/common_misc.c | 155 ++++++++++++++++-- src/mesa/drivers/dri/radeon/common_misc.h | 5 + src/mesa/drivers/dri/radeon/radeon_context.c | 46 ++---- src/mesa/drivers/dri/radeon/radeon_context.h | 24 +-- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 202 +++--------------------- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 14 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 2 +- src/mesa/drivers/dri/radeon/radeon_state.c | 26 +-- src/mesa/drivers/dri/radeon/radeon_state_init.c | 12 +- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 12 +- src/mesa/drivers/dri/radeon/radeon_tcl.c | 8 +- src/mesa/drivers/dri/radeon/radeon_tex.c | 2 +- 44 files changed, 353 insertions(+), 1266 deletions(-) delete mode 100644 src/mesa/drivers/dri/r300/r300_texmem.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_context.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_ioctl.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_ioctl.h delete mode 100644 src/mesa/drivers/dri/r300/radeon_state.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_state.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index eba5d6e0198..aa64232a93b 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_sanity.h" #include "radeon_reg.h" -#define DEBUG_CMDBUF 0 - /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. */ @@ -58,161 +56,54 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; - make_empty_list(&rmesa->hw.atomlist); - rmesa->hw.atomlist.name = "atom-list"; - - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ctx ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.set ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lin ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msk ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpt ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vtx ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vap ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vte ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msc ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cst ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.zbs ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcl ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msl ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcg ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.grd ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.fog ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tam ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tf ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.atf ); + make_empty_list(&rmesa->radeon.hw.atomlist); + rmesa->radeon.hw.atomlist.name = "atom-list"; + + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf ); for (i = 0; i < mtu; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tex[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] ); for (i = 0; i < mtu; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cube[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] ); for (i = 0; i < 6; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pix[i] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[0] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[1] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] ); for (i = 0; i < 8; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lit[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] ); for (i = 0; i < 3 + mtu; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mat[i] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.eye ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.glt ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt ); for (i = 0; i < 2; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mtl[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] ); for (i = 0; i < 6; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ucp[i] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.spr ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ptp ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.prf ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pvs ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[0] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[1] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[0] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[1] ); -} - -static void r200SaveHwState( r200ContextPtr rmesa ) -{ - struct radeon_state_atom *atom; - char * dest = rmesa->backup_store.cmd_buf; - uint32_t dwords; - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->backup_store.cmd_used = 0; - - foreach( atom, &rmesa->hw.atomlist ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) { - int size = atom->cmd_size * 4; - - if (atom->emit) { - (*atom->emit)(rmesa->radeon.glCtx, atom); - } else { - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->backup_store.cmd_used += size; - } - if (R200_DEBUG & DEBUG_STATE) - radeon_print_state_atom( atom ); - } - } - - assert( rmesa->backup_store.cmd_used <= R200_CMD_BUF_SZ ); - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "Returning to r200EmitState\n"); -} - -static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) -{ - BATCH_LOCALS(&r200->radeon); - struct radeon_state_atom *atom; - int dwords; - - /* Emit actual atoms */ - foreach(atom, &r200->hw.atomlist) { - if ((atom->dirty || r200->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r200->radeon.glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(atom); - } - if (atom->emit) { - (*atom->emit)(r200->radeon.glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -void r200EmitState( r200ContextPtr rmesa ) -{ - char *dest; - int mtu; - struct radeon_state_atom *atom; - uint32_t dwords; - - if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->save_on_next_emit) { - r200SaveHwState(rmesa); - rmesa->save_on_next_emit = GL_FALSE; - } - - if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty) - return; - - mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state, and inline the - * r200AllocCmdBuf code here without all the checks. - */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - - if (!rmesa->radeon.cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - r200EmitAtoms(rmesa, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - r200EmitAtoms(rmesa, GL_TRUE); - rmesa->hw.is_dirty = GL_FALSE; - rmesa->hw.all_dirty = GL_FALSE; + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] ); } /* Fire a section of the retained (indexed_verts) buffer as a regular @@ -227,7 +118,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, assert(!(primitive & R200_VF_PRIM_WALK_IND)); - r200EmitState( rmesa ); + radeonEmitState(&rmesa->radeon); if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, @@ -313,7 +204,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, assert((primitive & R200_VF_PRIM_WALK_IND)); - r200EmitState( rmesa ); + radeonEmitState(&rmesa->radeon); rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, R200_ELT_BUF_SZ, 4, diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 00274fbd439..1f5a9f2427b 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -61,6 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_maos.h" #include "r200_vertprog.h" +#include "radeon_span.h" + #define need_GL_ARB_multisample #define need_GL_ARB_texture_compression #define need_GL_ARB_vertex_buffer_object @@ -259,43 +261,17 @@ static void r200_get_lock(radeonContextPtr radeon) } } - -static void r200_vtbl_flush(GLcontext *ctx) -{ - R200_FIREVERTICES(R200_CONTEXT(ctx)); -} - -static void r200_vtbl_flush_vertices(radeonContextPtr rmesa) -{ - R200_FIREVERTICES(((r200ContextPtr)rmesa)); -} - -static void r200_vtbl_set_all_dirty(GLcontext *ctx) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - rmesa->hw.all_dirty = GL_TRUE; -} - static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { } -static void r200_vtbl_emit_state(radeonContextPtr rmesa) -{ - r200EmitState((r200ContextPtr)rmesa); -} - static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; - radeon->vtbl.flush = r200_vtbl_flush; - radeon->vtbl.flush_vertices = r200_vtbl_flush_vertices; - radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; - radeon->vtbl.emit_state = r200_vtbl_emit_state; radeon->vtbl.swtcl_flush = r200_swtcl_flush; } @@ -390,7 +366,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->hw.all_dirty = 1; + rmesa->radeon.hw.all_dirty = 1; /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have all of them in @@ -565,7 +541,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) /* check if we're deleting the currently bound context */ if (rmesa == current) { - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); _mesa_make_current(NULL, NULL, NULL); } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 862751bd404..96f47ea92bb 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -469,9 +469,6 @@ struct r200_texture_state { struct r200_hw_state { - /* Head of the linked list of state atoms. */ - struct radeon_state_atom atomlist; - /* Hardware state, stored as cmdbuf commands: * -- Need to doublebuffer for * - reviving state after loss of context @@ -512,9 +509,6 @@ struct r200_hw_state { struct radeon_state_atom atf; struct radeon_state_atom spr; struct radeon_state_atom ptp; - - int max_state_size; /* Number of bytes necessary for a full state emit. */ - GLboolean is_dirty, all_dirty; }; struct r200_state { @@ -600,16 +594,10 @@ struct r200_context { */ struct radeon_ioctl ioctl; struct radeon_store store; - /* A full state emit as of the first state emit in the main store, in case - * the context is lost. - */ - struct radeon_store backup_store; /* Clientdata textures; */ - GLuint prefer_gart_client_texturing; - - GLboolean save_on_next_emit; + GLuint prefer_gart_client_texturing; /* TCL stuff */ diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 0b7f6644573..8f64c8c6d90 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -57,34 +57,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 - -/* At this point we were in FlushCmdBufLocked but we had lost our context, so - * we need to unwire our current cmdbuf, hook the one with the saved state in - * it, flush it, and then put the current one back. This is so commands at the - * start of a cmdbuf can rely on the state being kept from the previous one. - */ -static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) -{ - GLuint nr_released_bufs; - struct radeon_store saved_store; - - if (rmesa->backup_store.cmd_used == 0) - return; - - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "Emitting backup state on lost context\n"); - - rmesa->radeon.lost_context = GL_FALSE; - - nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; - saved_store = rmesa->store; - rmesa->radeon.dma.nr_released_bufs = 0; - rmesa->store = rmesa->backup_store; - rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); - rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; - rmesa->store = saved_store; -} - static void r200UserClear(GLcontext *ctx, GLuint flags) { if (flags & (RADEON_FRONT | RADEON_BACK)) { @@ -291,36 +263,9 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) else r200KernelClear(ctx, flags); - rmesa->hw.all_dirty = GL_TRUE; -} - - -void r200Flush( GLcontext *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( ctx ); - - r200EmitState( rmesa ); - - if (rmesa->radeon.cmdbuf.cs->cdw) - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); + rmesa->radeon.hw.all_dirty = GL_TRUE; } -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void r200Finish( GLcontext *ctx ) -{ - r200Flush( ctx ); - radeon_common_finish(ctx); -} - - /* This version of AllocateMemoryMESA allocates only GART memory, and * only does so after the point at which the driver has been * initialized. @@ -458,7 +403,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) void r200InitIoctlFuncs( struct dd_function_table *functions ) { functions->Clear = r200Clear; - functions->Finish = r200Finish; - functions->Flush = r200Flush; + functions->Finish = radeonFinish; + functions->Flush = radeonFlush; } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 316acef4593..6b114971c3d 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_cmdbuf.h" -extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, @@ -101,7 +100,7 @@ do { \ do { \ R200_NEWPRIM( rmesa ); \ rmesa->hw.ATOM.dirty = GL_TRUE; \ - rmesa->hw.is_dirty = GL_TRUE; \ + rmesa->radeon.hw.is_dirty = GL_TRUE; \ } while (0) #define R200_DB_STATE( ATOM ) \ @@ -116,7 +115,7 @@ static INLINE int R200_DB_STATECHANGE( GLuint *tmp; R200_NEWPRIM( rmesa ); atom->dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; + rmesa->radeon.hw.is_dirty = GL_TRUE; tmp = atom->cmd; atom->cmd = atom->lastcmd; atom->lastcmd = tmp; @@ -127,15 +126,6 @@ static INLINE int R200_DB_STATECHANGE( } -/* Fire the buffered vertices no matter what. - */ -#define R200_FIREVERTICES( rmesa ) \ -do { \ - if ( rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \ - r200Flush( rmesa->radeon.glCtx ); \ - } \ -} while (0) - /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ * are available, you will also be adding an rmesa->state.max_state_size because * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index f3d809d62cb..5c41018cdbd 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -524,25 +524,6 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) } } - -/* ============================================================= - * Scissoring - */ - - -static void r200Scissor( GLcontext *ctx, - GLint x, GLint y, GLsizei w, GLsizei h ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if ( ctx->Scissor.Enabled ) { - R200_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */ - radeonUpdateScissor( ctx ); - } - -} - - /* ============================================================= * Culling */ @@ -787,7 +768,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); LOCK_HARDWARE( &rmesa->radeon ); /* FIXME: Use window x,y offsets into stipple RAM. @@ -1638,7 +1619,7 @@ void r200UpdateWindow( GLcontext *ctx ) float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); R200_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; @@ -1783,7 +1764,7 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - R200_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { /* 0 (GL_NONE) buffers or multiple color drawing buffers */ @@ -2057,7 +2038,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); rmesa->radeon.state.scissor.enabled = state; radeonUpdateScissor( ctx ); break; @@ -2575,7 +2556,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->PointParameterfv = r200PointParameter; functions->PointSize = r200PointSize; functions->RenderMode = r200RenderMode; - functions->Scissor = r200Scissor; + functions->Scissor = radeonScissor; functions->ShadeModel = r200ShadeModel; functions->StencilFuncSeparate = r200StencilFuncSeparate; functions->StencilMaskSeparate = r200StencilMaskSeparate; diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 1e904ea4321..d11baacae95 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -46,8 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_buffer.h" #include "radeon_mipmap_tree.h" #include "radeon_cs.h" -#include "common_context.h" -#include "common_cmdbuf.h" +#include "common_misc.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -177,8 +176,8 @@ void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) fprintf(stderr, msg); fprintf(stderr, ": "); - foreach(l, &rmesa->hw.atomlist) { - if (l->dirty || rmesa->hw.all_dirty) + foreach(l, &rmesa->radeon.hw.atomlist) { + if (l->dirty || rmesa->radeon.hw.all_dirty) fprintf(stderr, "%s, ", l->name); } @@ -649,7 +648,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch; #endif - rmesa->hw.max_state_size = 0; + rmesa->radeon.hw.max_state_size = 0; #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ do { \ @@ -660,7 +659,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ATOM.idx = IDX; \ rmesa->hw.ATOM.check = check_##CHK; \ rmesa->hw.ATOM.dirty = GL_FALSE; \ - rmesa->hw.max_state_size += SZ * sizeof(int); \ + rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ } while (0) @@ -1405,7 +1404,7 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); - rmesa->hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); + rcommonInitCmdBuf(&rmesa->radeon); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index a39072d1d2b..df786561e17 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -204,8 +204,6 @@ static void r200SetVertexFormat( GLcontext *ctx ) static void r200RenderStart( GLcontext *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - r200SetVertexFormat( ctx ); } @@ -271,11 +269,11 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { r200ContextPtr rmesa = R200_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->hw.max_state_size + (12*sizeof(int)), + rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - r200EmitState(rmesa); + radeonEmitState(&rmesa->radeon); r200EmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, @@ -649,7 +647,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) if (mode) { rmesa->radeon.Fallback |= bit; if (oldfallback == 0) { - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); rmesa->radeon.swtcl.RenderIndex = ~0; @@ -914,6 +912,4 @@ void r200InitSwtcl( GLcontext *ctx ) void r200DestroySwtcl( GLcontext *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 4c4df14ef82..8e0fb14e70e 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -123,7 +123,7 @@ static GLboolean discrete_prim[0x10] = { #define RESET_STIPPLE() do { \ R200_STATECHANGE( rmesa, lin ); \ - r200EmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) #define AUTO_STIPPLE( mode ) do { \ @@ -134,7 +134,7 @@ static GLboolean discrete_prim[0x10] = { else \ rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \ ~R200_LINE_PATTERN_AUTO_RESET; \ - r200EmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) @@ -189,7 +189,7 @@ static void r200EmitPrim( GLcontext *ctx, // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index cf0a32bf89b..c0d1723c77c 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -420,7 +420,7 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) if (rmesa) { int i; - R200_FIREVERTICES(rmesa); + radeon_firevertices(&rmesa->radeon); for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { if ( t == rmesa->state.texture.unit[i].texobj ) { rmesa->state.texture.unit[i].texobj = NULL; diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 4042005d031..abdd1da490e 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -26,11 +26,7 @@ DRIVER_SOURCES = \ radeon_screen.c \ common_lock.c \ common_misc.c \ - radeon_context.c \ - radeon_ioctl.c \ radeon_span.c \ - radeon_state.c \ - r300_context.c \ r300_ioctl.c \ r300_cmdbuf.c \ r300_state.c \ diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 303efe3ada1..d6acb39d9f9 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -45,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "radeon_buffer.h" -#include "radeon_ioctl.h" #include "r300_context.h" #include "r300_ioctl.h" #include "radeon_reg.h" @@ -61,111 +60,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 # define RADEON_ONE_REG_WR (1 << 15) -// Set this to 1 for extremely verbose debugging of command buffers -#define DEBUG_CMDBUF 0 - /** # of dwords reserved for additional instructions that may need to be written * during flushing. */ #define SPACE_FOR_FLUSHING 4 -static void r300PrintStateAtom(r300ContextPtr r300, - struct radeon_state_atom *state) -{ - int i; - int dwords = (*state->check) (r300->radeon.glCtx, state); - - fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); - - if (RADEON_DEBUG & DEBUG_VERBOSE) { - for (i = 0; i < dwords; i++) { - fprintf(stderr, " %s[%d]: %08x\n", - state->name, i, state->cmd[i]); - } - } -} - -/** - * Emit all atoms with a dirty field equal to dirty. - * - * The caller must have ensured that there is enough space in the command - * buffer. - */ -static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) -{ - BATCH_LOCALS(&r300->radeon); - struct radeon_state_atom *atom; - int dwords; - - cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1)); - OUT_BATCH(R300_TX_FLUSH); - END_BATCH(); - end_3d(r300); - - /* Emit actual atoms */ - foreach(atom, &r300->hw.atomlist) { - if ((atom->dirty || r300->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r300->radeon.glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - r300PrintStateAtom(r300, atom); - } - if (atom->emit) { - (*atom->emit)(r300->radeon.glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -/** - * Copy dirty hardware state atoms into the command buffer. - * - * We also copy out clean state if we're at the start of a buffer. That makes - * it easy to recover from lost contexts. - */ -void r300EmitState(r300ContextPtr r300) -{ - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (r300->radeon.cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty) - return; - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state. - */ - rcommonEnsureCmdBufSpace(&r300->radeon, r300->hw.max_state_size, __FUNCTION__); - - if (!r300->radeon.cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - r300EmitAtoms(r300, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - r300EmitAtoms(r300, GL_TRUE); - r300->hw.is_dirty = GL_FALSE; - r300->hw.all_dirty = GL_FALSE; -} - static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) { if (r300->radeon.radeonScreen->kernel_mm) { @@ -405,8 +304,8 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) r300->hw.ATOM.idx = (IDX); \ r300->hw.ATOM.check = check_##CHK; \ r300->hw.ATOM.dirty = GL_FALSE; \ - r300->hw.max_state_size += (SZ); \ - insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM); \ + r300->radeon.hw.max_state_size += (SZ); \ + insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \ } while (0) /** * Allocate memory for the command buffer and initialize the state atom @@ -425,7 +324,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; - r300->hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ + r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ mtu = r300->radeon.glCtx->Const.MaxTextureUnits; if (RADEON_DEBUG & DEBUG_TEXTURE) { @@ -433,8 +332,8 @@ void r300InitCmdBuf(r300ContextPtr r300) } /* Setup the atom linked list */ - make_empty_list(&r300->hw.atomlist); - r300->hw.atomlist.name = "atom-list"; + make_empty_list(&r300->radeon.hw.atomlist); + r300->radeon.hw.atomlist.name = "atom-list"; /* Initialize state atoms */ ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0); @@ -708,10 +607,10 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0); - r300->hw.is_dirty = GL_TRUE; - r300->hw.all_dirty = GL_TRUE; + r300->radeon.hw.is_dirty = GL_TRUE; + r300->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&r300->radeon, r300->hw.max_state_size); + rcommonInitCmdBuf(&r300->radeon); } /** @@ -721,7 +620,7 @@ void r300DestroyCmdBuf(r300ContextPtr r300) { struct radeon_state_atom *atom; - foreach(atom, &r300->hw.atomlist) { + foreach(atom, &r300->radeon.hw.atomlist) { FREE(atom->cmd); } diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3e47888e458..e4dc37debc2 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -55,7 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" -#include "radeon_ioctl.h" #include "radeon_span.h" #include "r300_context.h" #include "r300_cmdbuf.h" @@ -198,22 +197,6 @@ static void r300_get_lock(radeonContextPtr rmesa) } } -static void r300_vtbl_flush(GLcontext *ctx) -{ - r300Flush(ctx); -} - -static void r300_vtbl_set_all_dirty(GLcontext *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - rmesa->hw.all_dirty = GL_TRUE; -} - -static void r300_vtbl_emit_state(radeonContextPtr rmesa) -{ - r300EmitState((r300ContextPtr)rmesa); -} - static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { /* please flush pipe do all pending work */ @@ -243,22 +226,25 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes R300_WAIT_3D | R300_WAIT_3D_CLEAN)); } -static void r300_vtbl_flush_vertices(radeonContextPtr rmesa) +static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - R300_FIREVERTICES(((r300ContextPtr)rmesa)); + BATCH_LOCALS(radeon); + cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(cmdpacket0(radeon->radeonScreen, R300_TX_INVALTAGS, 1)); + OUT_BATCH(R300_TX_FLUSH); + END_BATCH(); + end_3d(radeon); } static void r300_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r300_get_lock; radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; - radeon->vtbl.flush = r300_vtbl_flush; - radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; - radeon->vtbl.emit_state = r300_vtbl_emit_state; - radeon->vtbl.flush_vertices = r300_vtbl_flush_vertices; radeon->vtbl.swtcl_flush = r300_swtcl_flush; + radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 9e97a136e39..75393bcd14c 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "dri_util.h" #include "texmem.h" +#include "common_context.h" #include "radeon_context.h" #include "radeon_bo.h" @@ -53,7 +54,7 @@ struct r300_context; typedef struct r300_context r300ContextRec; typedef struct r300_context *r300ContextPtr; -#include "radeon_lock.h" + #include "main/mm.h" /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . @@ -304,12 +305,6 @@ struct r300_texture_state { * Cache for hardware register state. */ struct r300_hw_state { - struct radeon_state_atom atomlist; - - GLboolean is_dirty; - GLboolean all_dirty; - int max_state_size; /* in dwords */ - struct radeon_state_atom vpt; /* viewport (1D98) */ struct radeon_state_atom vap_cntl; struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4a18397aa8f..20afae6a097 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "r300_context.h" -#include "radeon_ioctl.h" #include "r300_state.h" #include "r300_emit.h" #include "r300_ioctl.h" diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 290bd614c52..6c026466058 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -146,36 +146,36 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) /** * Must be sent to switch to 2d commands */ -void static INLINE end_3d(r300ContextPtr rmesa) +void static INLINE end_3d(radeonContextPtr radeon) { - BATCH_LOCALS(&rmesa->radeon); + BATCH_LOCALS(radeon); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); - END_BATCH(); - } + if (!radeon->radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdpacify(radeon->radeonScreen)); + END_BATCH(); + } } void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { BATCH_LOCALS(&rmesa->radeon); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); - END_BATCH(); - } + if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); + END_BATCH(); + } } -void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) +void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) { - BATCH_LOCALS(&rmesa->radeon); + BATCH_LOCALS(radeon); uint32_t wait_until; - if (!rmesa->radeon.radeonScreen->kernel_mm) { + if (!radeon->radeonScreen->kernel_mm) { BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); + OUT_BATCH(cmdwait(radeon->radeonScreen, flags)); END_BATCH(); } else { switch(flags) { diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index f07252fbe24..ee334150951 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -48,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_buffer.h" #include "r300_context.h" -#include "radeon_ioctl.h" #include "r300_ioctl.h" #include "r300_cmdbuf.h" #include "r300_state.h" @@ -94,8 +93,8 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, } /* TODO in bufmgr */ - cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - end_3d(rmesa); + cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + end_3d(&rmesa->radeon); if (flags & CLEARBUFFER_COLOR) { assert(rrb != 0); @@ -195,7 +194,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, } r300EmitCacheFlush(rmesa); - cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); R300_STATECHANGE(r300, cb); R300_STATECHANGE(r300, cmk); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 23d068c3399..393bf754ff2 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -66,8 +66,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_vp_build.h" #include "radeon_reg.h" #include "radeon_macros.h" -#include "radeon_ioctl.h" -#include "radeon_state.h" #include "r300_context.h" #include "r300_ioctl.h" #include "r300_state.h" diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index bdb67a1afd3..1e7d9af11dc 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -53,8 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vbo/vbo.h" #include "tnl/tnl.h" -#include "radeon_ioctl.h" -#include "radeon_state.h" #include "radeon_buffer.h" #include "r300_context.h" #include "r300_ioctl.h" @@ -1087,7 +1085,7 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; - R300_FIREVERTICES(rmesa); + radeon_firevertices(&rmesa->radeon); R300_STATECHANGE(rmesa, vpt); rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); @@ -2112,6 +2110,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) */ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(cap), @@ -2157,8 +2156,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_POLYGON_OFFSET_FILL: r300SetPolygonOffsetState(ctx, state); break; + case GL_SCISSOR_TEST: + radeon_firevertices(&rmesa->radeon); + rmesa->radeon.state.scissor.enabled = state; + radeonUpdateScissor( ctx ); + break; default: - radeonEnable(ctx, cap, state); break; } } @@ -2405,7 +2408,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; } - r300->hw.all_dirty = GL_TRUE; + r300->radeon.hw.all_dirty = GL_TRUE; } void r300UpdateShaders(r300ContextPtr rmesa) @@ -2747,7 +2750,7 @@ static void r300DrawBuffer( GLcontext *ctx, GLenum mode ) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - R300_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ radeonSetCliprects( &rmesa->radeon ); radeonUpdatePageFlipping(&rmesa->radeon); @@ -2803,6 +2806,7 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->RenderMode = r300RenderMode; functions->ClipPlane = r300ClipPlane; + functions->Scissor = radeonScissor; functions->DrawBuffer = r300DrawBuffer; functions->ReadBuffer = r300ReadBuffer; diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index 4d0a25fb0e1..247a20ee516 100644 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ b/src/mesa/drivers/dri/r300/r300_state.h @@ -39,26 +39,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_NEWPRIM( rmesa ) \ do { \ + if ( rmesa->radeon.dma.flush ) \ + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) #define R300_STATECHANGE(r300, atom) \ do { \ R300_NEWPRIM(r300); \ r300->hw.atom.dirty = GL_TRUE; \ - r300->hw.is_dirty = GL_TRUE; \ + r300->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -#define R300_PRINT_STATE(r300, atom) \ - r300PrintStateAtom(r300, &r300->hw.atom) - -/* Fire the buffered vertices no matter what. - TODO: This has not been implemented yet - */ -#define R300_FIREVERTICES( r300 ) \ - do { \ - r300Flush( (r300)->radeon.glCtx ); \ - } while (0) - // r300_state.c extern int future_hw_tcl_on; void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 98208cd77e6..34e752178af 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -626,7 +626,7 @@ void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) r300ContextPtr rmesa = R300_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->hw.max_state_size + (12*sizeof(int)), + rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); r300EmitState(rmesa); r300EmitVertexAOS(rmesa, diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 989aa462aea..e316e2d822b 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -263,7 +263,7 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) if (rmesa) { int i; - R300_FIREVERTICES(rmesa); + radeon_firevertices(&rmesa->radeon); for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i) if (rmesa->hw.textures[i] == t) diff --git a/src/mesa/drivers/dri/r300/r300_texmem.c b/src/mesa/drivers/dri/r300/r300_texmem.c deleted file mode 100644 index 53eeca13866..00000000000 --- a/src/mesa/drivers/dri/r300/r300_texmem.c +++ /dev/null @@ -1,58 +0,0 @@ -/************************************************************************** - -Copyright (C) Tungsten Graphics 2002. All Rights Reserved. -The Weather Channel, Inc. funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 -license. This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation on the rights to use, copy, modify, merge, publish, -distribute, sub license, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR -SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR -IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Gareth Hughes - * - * \author Kevin E. Martin - */ - -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/colormac.h" -#include "main/macros.h" -#include "main/simple_list.h" -#include "radeon_reg.h" /* gets definition for usleep */ -#include "r300_context.h" -#include "r300_state.h" -#include "r300_cmdbuf.h" -#include "r300_emit.h" -#include "r300_mipmap_tree.h" -#include "radeon_ioctl.h" -#include "r300_tex.h" -#include "r300_ioctl.h" -#include /* for usleep() */ - - diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 6e2b1309c5d..50ecc570bd1 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "r300_state.h" #include "r300_ioctl.h" -#include "radeon_ioctl.h" #include "radeon_mipmap_tree.h" #include "radeon_cs.h" #include "r300_tex.h" diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c deleted file mode 100644 index 13a76824165..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ /dev/null @@ -1,75 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file radeon_context.c - * Common context initialization. - * - * \author Keith Whitwell - */ - -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/state.h" -#include "main/matrix.h" -#include "main/framebuffer.h" - -#include "drivers/common/driverfuncs.h" -#include "swrast/swrast.h" - -#include "radeon_buffer.h" -#include "radeon_screen.h" -#include "radeon_ioctl.h" -#include "radeon_macros.h" -#include "radeon_reg.h" - -#include "radeon_state.h" -#include "r300_state.h" - -#include "utils.h" -#include "vblank.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ -#include "drirenderbuffer.h" - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) -{ - radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, - radeon->glCtx); - - return GL_TRUE; -} - diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index 736bf7c6493..005edf8448a 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -67,20 +67,6 @@ extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode); /* TCL fallbacks */ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); -#define RADEON_TCL_FALLBACK_RASTER 0x0001 /* rasterization */ -#define RADEON_TCL_FALLBACK_UNFILLED 0x0002 /* unfilled tris */ -#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x0004 /* twoside tris */ -#define RADEON_TCL_FALLBACK_MATERIAL 0x0008 /* material in vb */ -#define RADEON_TCL_FALLBACK_TEXGEN_0 0x0010 /* texgen, unit 0 */ -#define RADEON_TCL_FALLBACK_TEXGEN_1 0x0020 /* texgen, unit 1 */ -#define RADEON_TCL_FALLBACK_TEXGEN_2 0x0040 /* texgen, unit 2 */ -#define RADEON_TCL_FALLBACK_TEXGEN_3 0x0080 /* texgen, unit 3 */ -#define RADEON_TCL_FALLBACK_TEXGEN_4 0x0100 /* texgen, unit 4 */ -#define RADEON_TCL_FALLBACK_TEXGEN_5 0x0200 /* texgen, unit 5 */ -#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x0400 /* user disable */ -#define RADEON_TCL_FALLBACK_BITMAP 0x0800 /* draw bitmap with points */ -#define RADEON_TCL_FALLBACK_VERTEX_PROGRAM 0x1000 /* vertex program active */ - #if R200_MERGED #define TCL_FALLBACK( ctx, bit, mode ) radeonTclFallback( ctx, bit, mode ) #else @@ -88,33 +74,4 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); #endif -extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h); -extern GLboolean radeonInitContext(radeonContextPtr radeon, - struct dd_function_table *functions, - const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate); -extern void radeonCleanupContext(radeonContextPtr radeon); -extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); -extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); -void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); - -/* ================================================================ - * Debugging: - */ -#define DO_DEBUG 1 - -#if DO_DEBUG -extern int RADEON_DEBUG; -#else -#define RADEON_DEBUG 0 -#endif - -#define DEBUG_SYNC 0x1000 -#define DEBUG_PIXEL 0x2000 -#define DEBUG_MEMORY 0x4000 - #endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.c b/src/mesa/drivers/dri/r300/radeon_ioctl.c deleted file mode 100644 index 120d6c03ab8..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.c +++ /dev/null @@ -1,69 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/macros.h" -#include "main/context.h" -#include "swrast/swrast.h" -#include "r300_context.h" -#include "radeon_ioctl.h" -#include "radeon_buffer.h" -#include "r300_ioctl.h" -#include "r300_state.h" -#include "radeon_reg.h" - -#include "drirenderbuffer.h" -#include "vblank.h" - -void radeonFlush(GLcontext * ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - if (IS_R300_CLASS(radeon->radeonScreen)) - r300Flush(ctx); -} - - -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void radeonFinish(GLcontext * ctx) -{ - radeonFlush(ctx); - radeon_common_finish(ctx); -} diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.h b/src/mesa/drivers/dri/r300/radeon_ioctl.h deleted file mode 100644 index 3add775b822..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.h +++ /dev/null @@ -1,57 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#ifndef __RADEON_IOCTL_H__ -#define __RADEON_IOCTL_H__ - -#include "main/simple_list.h" -#include "radeon_dri.h" -#include "radeon_lock.h" - -#include "xf86drm.h" -#include "drm.h" -#if 0 -#include "r200context.h" -#endif -#include "radeon_drm.h" - -extern void radeonCopyBuffer(__DRIdrawablePrivate * drawable, - const drm_clip_rect_t * rect); -extern void radeonPageFlip(__DRIdrawablePrivate * drawable); -extern void radeonFlush(GLcontext * ctx); -extern void radeonFinish(GLcontext * ctx); -extern void radeonWaitForIdleLocked(radeonContextPtr radeon); -extern uint32_t radeonGetAge(radeonContextPtr radeon); - -#endif /* __RADEON_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c deleted file mode 100644 index 0ee5313043e..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ /dev/null @@ -1,109 +0,0 @@ -/************************************************************************** - -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/api_arrayelt.h" -#include "main/enums.h" -#include "main/framebuffer.h" -#include "main/colormac.h" -#include "main/light.h" - -#include "swrast/swrast.h" -#include "vbo/vbo.h" -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" -#include "swrast_setup/swrast_setup.h" - -#include "radeon_ioctl.h" -#include "radeon_state.h" -#include "r300_ioctl.h" - - -/* ============================================================= - * Scissoring - */ - -static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - if (ctx->Scissor.Enabled) { - /* We don't pipeline cliprect changes */ - r300Flush(ctx); - radeonUpdateScissor(ctx); - } -} - -/** - * Handle common enable bits. - * Called as a fallback by r200Enable/r300Enable. - */ -void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - switch(cap) { - case GL_SCISSOR_TEST: - /* We don't pipeline cliprect & scissor changes */ - r300Flush(ctx); - - radeon->state.scissor.enabled = state; - radeonUpdateScissor(ctx); - break; - - default: - return; - } -} - - -/** - * Initialize default state. - * This function is called once at context init time from - * r200InitState/r300InitState - */ -void radeonInitState(radeonContextPtr radeon) -{ - radeon->Fallback = 0; -} - - -/** - * Initialize common state functions. - * Called by r200InitStateFuncs/r300InitStateFuncs - */ -void radeonInitStateFuncs(struct dd_function_table *functions) -{ - functions->Scissor = radeonScissor; -} diff --git a/src/mesa/drivers/dri/r300/radeon_state.h b/src/mesa/drivers/dri/r300/radeon_state.h deleted file mode 100644 index 279b1084122..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_state.h +++ /dev/null @@ -1,39 +0,0 @@ -/* -Copyright (C) 2004 Nicolai Haehnle. All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Nicolai Haehnle - */ - -#ifndef __RADEON_STATE_H__ -#define __RADEON_STATE_H__ - -extern void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state); - -extern void radeonInitState(radeonContextPtr radeon); -extern void radeonInitStateFuncs(struct dd_function_table* functions); - -#endif diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index 071e29ee023..5526934209e 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -1,10 +1,12 @@ #ifndef COMMON_CMDBUF_H #define COMMON_CMDBUF_H +#include "radeon_cs.h" + void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); -void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size); +void rcommonInitCmdBuf(radeonContextPtr rmesa); void rcommonDestroyCmdBuf(radeonContextPtr rmesa); void rcommonBeginBatch(radeonContextPtr rmesa, @@ -128,4 +130,14 @@ void rcommonBeginBatch(radeonContextPtr rmesa, /** Write a 32 bit float to the ring; requires 1 dword. */ #define OUT_BATCH_FLOAT32(f) \ OUT_BATCH(radeonPackFloat32((f))); + + +/* Fire the buffered vertices no matter what. + */ +static INLINE void radeon_firevertices(radeonContextPtr radeon) +{ + if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) + radeonFlush(radeon->glCtx); +} + #endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 618e74d4583..c3a445e0d24 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -111,6 +111,13 @@ struct radeon_state_atom { void (*emit) (GLcontext *, struct radeon_state_atom *atom); }; +struct radeon_hw_state { + /* Head of the linked list of state atoms. */ + struct radeon_state_atom atomlist; + int max_state_size; /* Number of bytes necessary for a full state emit. */ + GLboolean is_dirty, all_dirty; +}; + /* Texture related */ typedef struct _radeon_texture_image radeon_texture_image; @@ -206,17 +213,6 @@ struct radeon_dma_buffer { drmBufPtr buf; }; -/* A retained region, eg vertices for indexed vertices. - */ -struct radeon_dma_region { - struct radeon_dma_buffer *buf; - char *address; /* == buf->address */ - int start, end, ptr; /* offsets from start of buf */ - int aos_start; - int aos_stride; - int aos_size; -}; - struct radeon_aos { struct radeon_bo *bo; /** Buffer object where vertex data is stored */ int offset; /** Offset into buffer object, in bytes */ @@ -388,6 +384,7 @@ struct radeon_context { float initialMaxAnisotropy; struct radeon_dma dma; + struct radeon_hw_state hw; /* Rasterization and vertex state: */ GLuint TclFallback; @@ -434,13 +431,11 @@ struct radeon_context { struct { void (*get_lock)(radeonContextPtr radeon); void (*update_viewport_offset)(GLcontext *ctx); - void (*flush)(GLcontext *ctx); - void (*set_all_dirty)(GLcontext *ctx); void (*update_draw_buffer)(GLcontext *ctx); void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); - void (*emit_state)(radeonContextPtr rmesa); - void (*flush_vertices)(radeonContextPtr rmesa); void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); + void (*pre_emit_atoms)(radeonContextPtr rmesa); + void (*pre_emit_state)(radeonContextPtr rmesa); } vtbl; }; @@ -502,4 +497,6 @@ extern int RADEON_DEBUG; #define RADEON_DEBUG 0 #endif +#include "common_misc.h" +#include "common_cmdbuf.h" #endif diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 9456f2a4389..12536b16723 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/light.h" #include "main/framebuffer.h" +#include "main/simple_list.h" #include "swrast/swrast.h" #include "vbo/vbo.h" @@ -81,6 +82,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. int RADEON_DEBUG = (0); #endif +#define DEBUG_CMDBUF 0 + /* ============================================================= * Scissoring */ @@ -215,6 +218,21 @@ void radeonUpdateScissor( GLcontext *ctx ) } } +/* ============================================================= + * Scissoring + */ + +void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + if (ctx->Scissor.Enabled) { + /* We don't pipeline cliprect changes */ + radeon_firevertices(radeon); + radeonUpdateScissor(ctx); + } +} + + /* ================================================================ * SwapBuffers with client-side throttling */ @@ -367,7 +385,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); } - rmesa->vtbl.flush(rmesa->glCtx); + radeon_firevertices(rmesa); LOCK_HARDWARE( rmesa ); /* Throttle the frame rate -- only allow one pending swap buffers @@ -437,7 +455,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, } rmesa->swap_ust = ust; - rmesa->vtbl.set_all_dirty(rmesa->glCtx); + rmesa->hw.all_dirty = GL_TRUE; } } @@ -465,7 +483,7 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) rmesa->sarea->pfCurrentPage); } - rmesa->vtbl.flush(rmesa->glCtx); + radeon_firevertices(rmesa); LOCK_HARDWARE( rmesa ); @@ -516,16 +534,111 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) rmesa->vtbl.update_draw_buffer(rmesa->glCtx); } +void radeonFlush(GLcontext *ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->dma.flush) + radeon->dma.flush( ctx ); + + radeonEmitState(radeon); + + if (radeon->cmdbuf.cs->cdw) + rcommonFlushCmdBuf(radeon, __FUNCTION__); +} + +static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) +{ + BATCH_LOCALS(radeon); + struct radeon_state_atom *atom; + int dwords; + + if (radeon->vtbl.pre_emit_atoms) + radeon->vtbl.pre_emit_atoms(radeon); + + /* Emit actual atoms */ + foreach(atom, &radeon->hw.atomlist) { + if ((atom->dirty || radeon->hw.all_dirty) == dirty) { + dwords = (*atom->check) (radeon->glCtx, atom); + if (dwords) { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + radeon_print_state_atom(atom); + } + if (atom->emit) { + (*atom->emit)(radeon->glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } + } + } + } + + COMMIT_BATCH(); +} + +void radeonEmitState(radeonContextPtr radeon) +{ + if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->vtbl.pre_emit_state) + radeon->vtbl.pre_emit_state(radeon); + + /* this code used to return here but now it emits zbs */ + if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) + return; + + /* To avoid going across the entire set of states multiple times, just check + * for enough space for the case of emitting all state, and inline the + * radeonAllocCmdBuf code here without all the checks. + */ + rcommonEnsureCmdBufSpace(radeon, radeon->hw.max_state_size, __FUNCTION__); + + /* We always always emit zbs, this is due to a bug found by keithw in + the hardware and rediscovered after Erics changes by me. + if you ever touch this code make sure you emit zbs otherwise + you get tcl lockups on at least M7/7500 class of chips - airlied */ + /* special r100 case */ + // rmesa->hw.zbs.dirty=1; + + if (!radeon->cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + radeonEmitAtoms(radeon, GL_FALSE); + } + + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + + radeonEmitAtoms(radeon, GL_TRUE); + radeon->hw.is_dirty = GL_FALSE; + radeon->hw.all_dirty = GL_FALSE; + +} + /* Make sure all commands have been sent to the hardware and have * completed processing. */ -void radeon_common_finish(GLcontext * ctx) +void radeonFinish(GLcontext * ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; int i; + radeonFlush(ctx); + if (radeon->radeonScreen->kernel_mm) { for (i = 0; i < fb->_NumColorDrawBuffers; i++) { struct radeon_renderbuffer *rrb; @@ -611,7 +724,7 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) rmesa->cmdbuf.flushing = 1; if (rmesa->cmdbuf.cs->cdw) { ret = radeon_cs_emit(rmesa->cmdbuf.cs); - rmesa->vtbl.set_all_dirty(rmesa->glCtx); + rmesa->hw.all_dirty = GL_TRUE; } radeon_cs_erase(rmesa->cmdbuf.cs); rmesa->cmdbuf.flushing = 0; @@ -650,20 +763,18 @@ void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *ca } } -void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) +void rcommonInitCmdBuf(radeonContextPtr rmesa) { GLuint size; /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, "command_buffer_size"); - if (size < 2 * max_state_size) { - size = 2 * max_state_size + 65535; + if (size < 2 * rmesa->hw.max_state_size) { + size = 2 * rmesa->hw.max_state_size + 65535; } if (size > 64 * 256) size = 64 * 256; - size = 64 * 1024 / 4; - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", sizeof(drm_r300_cmd_header_t)); @@ -671,7 +782,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) sizeof(drm_radeon_cmd_buffer_t)); fprintf(stderr, "Allocating %d bytes command buffer (max state is %d bytes)\n", - size * 4, max_state_size * 4); + size * 4, rmesa->hw.max_state_size * 4); } if (rmesa->radeonScreen->kernel_mm) { @@ -725,7 +836,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n, if (!rmesa->cmdbuf.cs->cdw && dostate) { if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "Reemit state after flush (from %s)\n", function); - rmesa->vtbl.emit_state(rmesa); + radeonEmitState(rmesa); } radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); } @@ -927,6 +1038,20 @@ void radeonCleanupContext(radeonContextPtr radeon) } } +/* Force the context `c' to be unbound from its buffer. + */ +GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) +{ + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, + radeon->glCtx); + + return GL_TRUE; +} + + static void radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, GLframebuffer *draw) @@ -1810,7 +1935,7 @@ static void radeon_teximage( radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); - rmesa->vtbl.flush_vertices(rmesa); + radeon_firevertices(rmesa); t->validated = GL_FALSE; @@ -1968,7 +2093,7 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); - rmesa->vtbl.flush_vertices(rmesa); + radeon_firevertices(rmesa); t->validated = GL_FALSE; pixels = _mesa_validate_pbo_teximage(ctx, dims, @@ -2373,7 +2498,7 @@ void radeonSpanRenderStart(GLcontext * ctx) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); int i; - rmesa->vtbl.flush_vertices(rmesa); + radeon_firevertices(rmesa); for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 80b34aa6bd3..ebf287a0316 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -6,6 +6,7 @@ void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); +void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h); void radeonWaitForIdleLocked(radeonContextPtr radeon); extern uint32_t radeonGetAge(radeonContextPtr radeon); @@ -26,6 +27,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon, void *sharedContextPrivate); void radeonCleanupContext(radeonContextPtr radeon); +GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, @@ -132,6 +134,9 @@ void rcommon_flush_last_swtcl_prim(GLcontext *ctx); void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +void radeonFlush(GLcontext *ctx); +void radeonFinish(GLcontext * ctx); +void radeonEmitState(radeonContextPtr radeon); static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) { diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 6fa01f4ded0..b25f036c442 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -215,29 +215,17 @@ static void r100_get_lock(radeonContextPtr radeon) } } -static void r100_vtbl_flush(GLcontext *ctx) -{ - RADEON_FIREVERTICES(R100_CONTEXT(ctx)); -} - -static void r100_vtbl_set_all_dirty(GLcontext *ctx) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - rmesa->hw.all_dirty = GL_TRUE; -} - static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { } -static void r100_vtbl_emit_state(radeonContextPtr rmesa) +static void r100_vtbl_pre_emit_state(radeonContextPtr radeon) { - radeonEmitState((r100ContextPtr)rmesa); -} - -static void r100_vtbl_flush_vertices(radeonContextPtr rmesa) -{ - RADEON_FIREVERTICES(((r100ContextPtr)rmesa)); + r100ContextPtr rmesa = (r100ContextPtr)radeon; + + /* r100 always needs to emit ZBS to avoid TCL lockups */ + rmesa->hw.zbs.dirty = 1; + radeon->hw.is_dirty = 1; } @@ -245,13 +233,10 @@ static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; - radeon->vtbl.flush = r100_vtbl_flush; - radeon->vtbl.set_all_dirty = r100_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; - radeon->vtbl.emit_state = r100_vtbl_emit_state; radeon->vtbl.swtcl_flush = r100_swtcl_flush; - radeon->vtbl.flush_vertices = r100_vtbl_flush_vertices; + radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; } /* Create the device specific context. @@ -344,7 +329,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have all of them in @@ -503,7 +488,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) /* check if we're deleting the currently bound context */ if (rmesa == current) { - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); _mesa_make_current(NULL, NULL, NULL); } @@ -553,16 +538,3 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) } } - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean -radeonUnbindContext( __DRIcontextPrivate *driContextPriv ) -{ - r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx); - - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 358095a2b9d..d05e47f16e7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -296,10 +296,7 @@ struct radeon_texture_state { #define SHN_SHININESS 1 #define SHN_STATE_SIZE 2 -struct radeon_hw_state { - /* Head of the linked list of state atoms. */ - struct radeon_state_atom atomlist; - +struct r100_hw_state { /* Hardware state, stored as cmdbuf commands: * -- Need to doublebuffer for * - eliding noop statechange loops? (except line stipple count) @@ -324,8 +321,6 @@ struct radeon_hw_state { struct radeon_state_atom glt; struct radeon_state_atom txr[3]; /* for NPOT */ - int max_state_size; /* Number of bytes necessary for a full state emit. */ - GLboolean is_dirty, all_dirty; }; @@ -354,14 +349,6 @@ struct radeon_tcl_info { struct radeon_bo *indexed_bo; -// struct radeon_dma_region indexed_verts; - struct radeon_dma_region obj; - struct radeon_dma_region rgba; - struct radeon_dma_region spec; - struct radeon_dma_region fog; - struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; - struct radeon_dma_region norm; - int elt_cmd_offset; /** Offset into the cmdbuf */ int elt_cmd_start; int elt_used; @@ -391,8 +378,6 @@ struct r100_swtcl_info { GLuint specoffset; GLboolean needproj; - - struct radeon_dma_region indexed_verts; }; @@ -411,17 +396,13 @@ struct r100_context { /* Driver and hardware state management */ - struct radeon_hw_state hw; + struct r100_hw_state hw; struct r100_state state; /* Vertex buffers */ struct radeon_ioctl ioctl; struct radeon_store store; - /* A full state emit as of the first state emit in the main store, in case - * the context is lost. - */ - struct radeon_store backup_store; /* TCL stuff */ @@ -455,7 +436,6 @@ struct r100_context { GLuint c_textureBytes; GLuint c_vertexBuffers; - GLboolean save_on_next_emit; }; #define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 45d750dbf42..d0cd9ce7a60 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -59,60 +59,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_TIMEOUT 512 #define RADEON_IDLE_RETRY 16 -#define DEBUG_CMDBUF 1 - -static void radeonSaveHwState( r100ContextPtr rmesa ) -{ - struct radeon_state_atom *atom; - char * dest = rmesa->backup_store.cmd_buf; - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->backup_store.cmd_used = 0; - - foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->check( rmesa->radeon.glCtx, 0 ) ) { - int size = atom->cmd_size * 4; - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->backup_store.cmd_used += size; - if (RADEON_DEBUG & DEBUG_STATE) - radeon_print_state_atom( atom ); - } - } - - assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ ); - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Returning to radeonEmitState\n"); -} - -/* At this point we were in FlushCmdBufLocked but we had lost our context, so - * we need to unwire our current cmdbuf, hook the one with the saved state in - * it, flush it, and then put the current one back. This is so commands at the - * start of a cmdbuf can rely on the state being kept from the previous one. - */ -static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa ) -{ - GLuint nr_released_bufs; - struct radeon_store saved_store; - - if (rmesa->backup_store.cmd_used == 0) - return; - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Emitting backup state on lost context\n"); - - rmesa->radeon.lost_context = GL_FALSE; - - nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; - saved_store = rmesa->store; - rmesa->radeon.dma.nr_released_bufs = 0; - rmesa->store = rmesa->backup_store; - rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); - rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; - rmesa->store = saved_store; -} /* ============================================================= * Kernel command buffer handling @@ -125,107 +71,33 @@ void radeonSetUpAtomList( r100ContextPtr rmesa ) { int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; - make_empty_list(&rmesa->hw.atomlist); - rmesa->hw.atomlist.name = "atom-list"; + make_empty_list(&rmesa->radeon.hw.atomlist); + rmesa->radeon.hw.atomlist.name = "atom-list"; - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ctx); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.set); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lin); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msk); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.vpt); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tcl); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msc); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc); for (i = 0; i < mtu; ++i) { - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tex[i]); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.txr[i]); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.cube[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i]); } - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.zbs); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mtl); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mtl); for (i = 0; i < 3 + mtu; ++i) - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mat[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i]); for (i = 0; i < 8; ++i) - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lit[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]); for (i = 0; i < 6; ++i) - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ucp[i]); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.eye); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.grd); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.fog); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt); -} - -static INLINE void radeonEmitAtoms(r100ContextPtr r100, GLboolean dirty) -{ - BATCH_LOCALS(&r100->radeon); - struct radeon_state_atom *atom; - int dwords; - - /* Emit actual atoms */ - foreach(atom, &r100->hw.atomlist) { - if ((atom->dirty || r100->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r100->radeon.glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(atom); - } - if (atom->emit) { - (*atom->emit)(r100->radeon.glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -void radeonEmitState( r100ContextPtr rmesa ) -{ - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->save_on_next_emit) { - radeonSaveHwState(rmesa); - rmesa->save_on_next_emit = GL_FALSE; - } - - /* this code used to return here but now it emits zbs */ - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state, and inline the - * radeonAllocCmdBuf code here without all the checks. - */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - - /* We always always emit zbs, this is due to a bug found by keithw in - the hardware and rediscovered after Erics changes by me. - if you ever touch this code make sure you emit zbs otherwise - you get tcl lockups on at least M7/7500 class of chips - airlied */ - rmesa->hw.zbs.dirty=1; - - if (!rmesa->radeon.cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - radeonEmitAtoms(rmesa, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - radeonEmitAtoms(rmesa, GL_TRUE); - rmesa->hw.is_dirty = GL_FALSE; - rmesa->hw.all_dirty = GL_FALSE; - + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt); } /* Fire a section of the retained (indexed_verts) buffer as a regular @@ -240,7 +112,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - radeonEmitState( rmesa ); + radeonEmitState(&rmesa->radeon); #if RADEON_OLD_PACKETS BEGIN_BATCH(8); @@ -318,7 +190,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - radeonEmitState( rmesa ); + radeonEmitState(&rmesa->radeon); rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; @@ -679,35 +551,9 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } UNLOCK_HARDWARE( &rmesa->radeon ); - rmesa->hw.all_dirty = GL_TRUE; -} - -void radeonFlush( GLcontext *ctx ) -{ - r100ContextPtr rmesa = R100_CONTEXT( ctx ); - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( ctx ); - - radeonEmitState( rmesa ); - - if (rmesa->radeon.cmdbuf.cs->cdw) - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); -} - -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void radeonFinish( GLcontext *ctx ) -{ - radeonFlush( ctx ); - radeon_common_finish(ctx); + rmesa->radeon.hw.all_dirty = GL_TRUE; } - void radeonInitIoctlFuncs( GLcontext *ctx ) { ctx->Driver.Clear = radeonClear; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index 4e93804646a..6d616bf8045 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_lock.h" #include "radeon_cs_legacy.h" -extern void radeonEmitState( r100ContextPtr rmesa ); extern void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, @@ -104,7 +103,7 @@ do { \ do { \ RADEON_NEWPRIM( rmesa ); \ rmesa->hw.ATOM.dirty = GL_TRUE; \ - rmesa->hw.is_dirty = GL_TRUE; \ + rmesa->radeon.hw.is_dirty = GL_TRUE; \ } while (0) #define RADEON_DB_STATE( ATOM ) \ @@ -118,7 +117,7 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, GLuint *tmp; RADEON_NEWPRIM( rmesa ); atom->dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; + rmesa->radeon.hw.is_dirty = GL_TRUE; tmp = atom->cmd; atom->cmd = atom->lastcmd; atom->lastcmd = tmp; @@ -128,15 +127,6 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, return 0; } -/* Fire the buffered vertices no matter what. - */ -#define RADEON_FIREVERTICES( rmesa ) \ -do { \ - if (rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \ - radeonFlush( rmesa->radeon.glCtx ); \ - } \ -} while (0) - /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ * are available, you will also be adding an rmesa->state.max_state_size because * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 497582ee232..7397218fb6c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1523,7 +1523,7 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyBuffer = radeonDestroyBuffer, .SwapBuffers = radeonSwapBuffers, .MakeCurrent = radeonMakeCurrent, - .UnbindContext = r200UnbindContext, + .UnbindContext = radeonUnbindContext, .GetSwapInfo = getSwapInfo, .GetDrawableMSC = driDrawableGetMSC32, .WaitForMSC = driWaitForMSC32, diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 1d683e5b3aa..a9ec1d51c7e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" +#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_tcl.h" @@ -406,23 +407,6 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) } } - -/* ============================================================= - * Scissoring - */ -static void radeonScissor( GLcontext *ctx, - GLint x, GLint y, GLsizei w, GLsizei h ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - - if ( ctx->Scissor.Enabled ) { - RADEON_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */ - radeonUpdateScissor( ctx ); - } - -} - - /* ============================================================= * Culling */ @@ -567,7 +551,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); LOCK_HARDWARE( &rmesa->radeon ); /* FIXME: Use window x,y offsets into stipple RAM. @@ -1415,7 +1399,7 @@ void radeonUpdateWindow( GLcontext *ctx ) float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); RADEON_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; @@ -1561,7 +1545,7 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { /* 0 (GL_NONE) buffers or multiple color drawing buffers */ @@ -1843,7 +1827,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); rmesa->radeon.state.scissor.enabled = state; radeonUpdateScissor( ctx ); break; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index f12d9bdb50d..1cfb539e713 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -171,8 +171,8 @@ void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) fprintf(stderr, msg); fprintf(stderr, ": "); - foreach(l, &rmesa->hw.atomlist) { - if (l->dirty || rmesa->hw.all_dirty) + foreach(l, &rmesa->radeon.hw.atomlist) { + if (l->dirty || rmesa->radeon.hw.all_dirty) fprintf(stderr, "%s, ", l->name); } @@ -512,7 +512,7 @@ void radeonInitState( r100ContextPtr rmesa ) drawPitch = rmesa->radeon.radeonScreen->frontPitch; } - rmesa->hw.max_state_size = 0; + rmesa->radeon.hw.max_state_size = 0; #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ do { \ @@ -524,7 +524,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.ATOM.check = check_##CHK; \ rmesa->hw.ATOM.dirty = GL_TRUE; \ rmesa->hw.ATOM.idx = IDX; \ - rmesa->hw.max_state_size += SZ * sizeof(int); \ + rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ } while (0) #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ @@ -932,7 +932,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; - rmesa->hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); + rcommonInitCmdBuf(&rmesa->radeon); } diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 615621dd987..995ab2099e4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -285,11 +285,11 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset) r100ContextPtr rmesa = R100_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->hw.max_state_size + (12*sizeof(int)), + rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - radeonEmitState(rmesa); + radeonEmitState(&rmesa->radeon); radeonEmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, @@ -372,9 +372,6 @@ static GLboolean radeon_run_render( GLcontext *ctx, tnl_render_func *tab = TAG(render_tab_verts); GLuint i; - if (rmesa->swtcl.indexed_verts.buf) - RELEASE_ELT_VERTS(); - if (rmesa->radeon.swtcl.RenderIndex != 0 || !radeon_dma_validate_render( ctx, VB )) return GL_TRUE; @@ -750,7 +747,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) if (mode) { rmesa->radeon.Fallback |= bit; if (oldfallback == 0) { - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); rmesa->radeon.swtcl.RenderIndex = ~0; @@ -831,7 +828,4 @@ void radeonDestroySwtcl( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - // if (rmesa->swtcl.indexed_verts.buf) - // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - // __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index daa88f43c75..7281800ce2f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -126,7 +126,7 @@ static GLboolean discrete_prim[0x10] = { #define RESET_STIPPLE() do { \ RADEON_STATECHANGE( rmesa, lin ); \ - radeonEmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) #define AUTO_STIPPLE( mode ) do { \ @@ -137,7 +137,7 @@ static GLboolean discrete_prim[0x10] = { else \ rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \ ~RADEON_LINE_PATTERN_AUTO_RESET; \ - radeonEmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) @@ -149,7 +149,7 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size + ELTS_BUFSZ(nr) + + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) + AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); radeonEmitAOS( rmesa, @@ -178,7 +178,7 @@ static void radeonEmitPrim( GLcontext *ctx, rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); radeonEmitAOS( rmesa, rmesa->tcl.nr_aos_components, diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index a916b63a279..e1b988bf4dc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -381,7 +381,7 @@ static void radeonDeleteTexture( GLcontext *ctx, } if ( rmesa ) { - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { if ( t == rmesa->state.texture.unit[i].texobj ) { rmesa->state.texture.unit[i].texobj = NULL; -- cgit v1.2.3 From df4a1348b1f869338d4742b213dbde9d64de4c7a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 21:44:34 +1000 Subject: r100/r200: fix front rendering issue. --- src/mesa/drivers/dri/r200/r200_state.c | 1 + src/mesa/drivers/dri/r300/r300_state.c | 3 --- src/mesa/drivers/dri/radeon/common_misc.c | 1 - src/mesa/drivers/dri/radeon/radeon_state.c | 2 +- 4 files changed, 2 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 5c41018cdbd..84b0d90c69f 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1783,6 +1783,7 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) } radeonSetCliprects( &rmesa->radeon ); + radeonUpdatePageFlipping(&rmesa->radeon); /* We'll set the drawing engine's offset/pitch parameters later * when we update other state. diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 1e7d9af11dc..4258a610000 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2692,8 +2692,6 @@ void r300InitState(r300ContextPtr r300) GLcontext *ctx = r300->radeon.glCtx; GLuint depth_fmt; - radeonInitState(&r300->radeon); - switch (ctx->Visual.depthBits) { case 16: r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffff; @@ -2769,7 +2767,6 @@ static void r300ReadBuffer( GLcontext *ctx, GLenum mode ) */ void r300InitStateFuncs(struct dd_function_table *functions) { - radeonInitStateFuncs(functions); functions->UpdateState = r300InvalidateState; functions->AlphaFunc = r300AlphaFunc; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 12536b16723..f0035e54cfd 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2595,7 +2595,6 @@ again_alloc: bos[0].write_domain =0 ; bos[0].new_accounted = 0; -again: ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1); if (ret == RADEON_CS_SPACE_OP_TO_BIG) { fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen"); diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index a9ec1d51c7e..7f90bc8090b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1564,7 +1564,7 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) } radeonSetCliprects( &rmesa->radeon ); - + radeonUpdatePageFlipping(&rmesa->radeon); /* We'll set the drawing engine's offset/pitch parameters later * when we update other state. */ -- cgit v1.2.3 From 23d3559bd4ece1fcab5513ebdaa38600d6654374 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 22:38:10 +1000 Subject: radeon: renaming and headers cleanup --- src/mesa/drivers/dri/radeon/Makefile | 17 +- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 143 -- src/mesa/drivers/dri/radeon/common_context.h | 502 ---- src/mesa/drivers/dri/radeon/common_lock.c | 126 - src/mesa/drivers/dri/radeon/common_lock.h | 120 - src/mesa/drivers/dri/radeon/common_misc.c | 2715 -------------------- src/mesa/drivers/dri/radeon/common_misc.h | 166 -- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 2 +- src/mesa/drivers/dri/radeon/radeon_cmdbuf.h | 143 ++ src/mesa/drivers/dri/radeon/radeon_common.c | 843 ++++++ src/mesa/drivers/dri/radeon/radeon_common.h | 56 + .../drivers/dri/radeon/radeon_common_context.c | 584 +++++ .../drivers/dri/radeon/radeon_common_context.h | 513 ++++ src/mesa/drivers/dri/radeon/radeon_context.c | 42 +- src/mesa/drivers/dri/radeon/radeon_context.h | 3 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 4 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.h | 2 +- src/mesa/drivers/dri/radeon/radeon_dma.c | 323 +++ src/mesa/drivers/dri/radeon/radeon_dma.h | 51 + src/mesa/drivers/dri/radeon/radeon_ioctl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_lock.c | 124 + src/mesa/drivers/dri/radeon/radeon_lock.h | 81 +- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 4 +- src/mesa/drivers/dri/radeon/radeon_span.c | 226 +- src/mesa/drivers/dri/radeon/radeon_state.c | 1 - src/mesa/drivers/dri/radeon/radeon_state_init.c | 1 - src/mesa/drivers/dri/radeon/radeon_swtcl.c | 1 - src/mesa/drivers/dri/radeon/radeon_tcl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texture.c | 849 ++++++ src/mesa/drivers/dri/radeon/radeon_texture.h | 108 + 31 files changed, 3916 insertions(+), 3840 deletions(-) delete mode 100644 src/mesa/drivers/dri/radeon/common_cmdbuf.h delete mode 100644 src/mesa/drivers/dri/radeon/common_context.h delete mode 100644 src/mesa/drivers/dri/radeon/common_lock.c delete mode 100644 src/mesa/drivers/dri/radeon/common_lock.h delete mode 100644 src/mesa/drivers/dri/radeon/common_misc.c delete mode 100644 src/mesa/drivers/dri/radeon/common_misc.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_cmdbuf.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_common.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_common.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_common_context.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_common_context.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_dma.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_dma.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_lock.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_texture.c create mode 100644 src/mesa/drivers/dri/radeon/radeon_texture.h (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 2d00f521a60..16bc063bafd 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -8,6 +8,16 @@ LIBNAME = radeon_dri.so MINIGLX_SOURCES = server/radeon_dri.c +RADEON_COMMON_SOURCES = \ + radeon_texture.c \ + radeon_common_context.c \ + radeon_dma.c \ + radeon_lock.c \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ + radeon_mipmap_tree.c \ + radeon_span.c + DRIVER_SOURCES = \ radeon_context.c \ radeon_ioctl.c \ @@ -18,14 +28,9 @@ DRIVER_SOURCES = \ radeon_texstate.c \ radeon_tcl.c \ radeon_swtcl.c \ - radeon_span.c \ radeon_maos.c \ radeon_sanity.c \ - common_lock.c \ - common_misc.c \ - radeon_bo_legacy.c \ - radeon_cs_legacy.c \ - radeon_mipmap_tree.c + $(RADEON_COMMON_SOURCES) C_SOURCES = \ $(COMMON_SOURCES) \ diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h deleted file mode 100644 index 5526934209e..00000000000 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ /dev/null @@ -1,143 +0,0 @@ -#ifndef COMMON_CMDBUF_H -#define COMMON_CMDBUF_H - -#include "radeon_cs.h" - -void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); -int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); -int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); -void rcommonInitCmdBuf(radeonContextPtr rmesa); -void rcommonDestroyCmdBuf(radeonContextPtr rmesa); - -void rcommonBeginBatch(radeonContextPtr rmesa, - int n, - int dostate, - const char *file, - const char *function, - int line); - -#define RADEON_CP_PACKET3_NOP 0xC0001000 -#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 -#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 -#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 -#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 -#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 -#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 -#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 -#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 -#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 -#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 -#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 -#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 -#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 -#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 -#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 -#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 -#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 -#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 -#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 -#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 - -#define CP_PACKET2 (2 << 30) -#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) -#define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - -/** - * Every function writing to the command buffer needs to declare this - * to get the necessary local variables. - */ -#define BATCH_LOCALS(rmesa) \ - const radeonContextPtr b_l_rmesa = rmesa - -/** - * Prepare writing n dwords to the command buffer, - * including producing any necessary state emits on buffer wraparound. - */ -#define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__) - -/** - * Same as BEGIN_BATCH, but do not cause automatic state emits. - */ -#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__) - -/** - * Write one dword to the command buffer. - */ -#define OUT_BATCH(data) \ - do { \ - radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ - } while(0) - -/** - * Write a relocated dword to the command buffer. - */ -#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ - do { \ - if (0 && offset) { \ - fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ - __FILE__, __FUNCTION__, __LINE__, offset); \ - } \ - radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ - radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ - bo, rd, wd, flags); \ - if (!b_l_rmesa->radeonScreen->kernel_mm) \ - b_l_rmesa->cmdbuf.cs->section_cdw += 2; \ - } while(0) - - -/** - * Write n dwords from ptr to the command buffer. - */ -#define OUT_BATCH_TABLE(ptr,n) \ - do { \ - int _i; \ - for (_i=0; _i < n; _i++) {\ - radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\ - }\ - } while(0) - -/** - * Finish writing dwords to the command buffer. - * The number of (direct or indirect) OUT_BATCH calls between the previous - * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. - */ -#define END_BATCH() \ - do { \ - radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ - } while(0) - -/** - * After the last END_BATCH() of rendering, this indicates that flushing - * the command buffer now is okay. - */ -#define COMMIT_BATCH() \ - do { \ - } while(0) - - -/** Single register write to command buffer; requires 2 dwords. */ -#define OUT_BATCH_REGVAL(reg, val) \ - OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ - OUT_BATCH((val)) - -/** Continuous register range write to command buffer; requires 1 dword, - * expects count dwords afterwards for register contents. */ -#define OUT_BATCH_REGSEQ(reg, count) \ - OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))); - -/** Write a 32 bit float to the ring; requires 1 dword. */ -#define OUT_BATCH_FLOAT32(f) \ - OUT_BATCH(radeonPackFloat32((f))); - - -/* Fire the buffered vertices no matter what. - */ -static INLINE void radeon_firevertices(radeonContextPtr radeon) -{ - if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) - radeonFlush(radeon->glCtx); -} - -#endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h deleted file mode 100644 index c3a445e0d24..00000000000 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ /dev/null @@ -1,502 +0,0 @@ - -#ifndef COMMON_CONTEXT_H -#define COMMON_CONTEXT_H - -#include "main/mm.h" -#include "math/m_vector.h" -#include "texmem.h" -#include "tnl/t_context.h" -#include "main/colormac.h" - -#include "radeon_screen.h" -#include "radeon_drm.h" -#include "dri_util.h" -#include "tnl/t_vertex.h" - -/* This union is used to avoid warnings/miscompilation - with float to uint32_t casts due to strict-aliasing */ -typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; - -struct radeon_context; -typedef struct radeon_context radeonContextRec; -typedef struct radeon_context *radeonContextPtr; - - -#define TEX_0 0x1 -#define TEX_1 0x2 -#define TEX_2 0x4 -#define TEX_3 0x8 -#define TEX_4 0x10 -#define TEX_5 0x20 - -/* Rasterizing fallbacks */ -/* See correponding strings in r200_swtcl.c */ -#define RADEON_FALLBACK_TEXTURE 0x0001 -#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 -#define RADEON_FALLBACK_STENCIL 0x0004 -#define RADEON_FALLBACK_RENDER_MODE 0x0008 -#define RADEON_FALLBACK_BLEND_EQ 0x0010 -#define RADEON_FALLBACK_BLEND_FUNC 0x0020 -#define RADEON_FALLBACK_DISABLE 0x0040 -#define RADEON_FALLBACK_BORDER_MODE 0x0080 - -#define R200_FALLBACK_TEXTURE 0x01 -#define R200_FALLBACK_DRAW_BUFFER 0x02 -#define R200_FALLBACK_STENCIL 0x04 -#define R200_FALLBACK_RENDER_MODE 0x08 -#define R200_FALLBACK_DISABLE 0x10 -#define R200_FALLBACK_BORDER_MODE 0x20 - -#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ -#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ -#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ -#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ -#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ -#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ -#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ -#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ -#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ - -/* The blit width for texture uploads - */ -#define BLIT_WIDTH_BYTES 1024 - -/* Use the templated vertex format: - */ -#define COLOR_IS_RGBA -#define TAG(x) radeon##x -#include "tnl_dd/t_dd_vertex.h" -#undef TAG - -struct radeon_colorbuffer_state { - GLuint clear; - int roundEnable; - struct radeon_renderbuffer *rrb; -}; - -struct radeon_depthbuffer_state { - GLuint clear; - GLfloat scale; - struct radeon_renderbuffer *rrb; -}; - -struct radeon_scissor_state { - drm_clip_rect_t rect; - GLboolean enabled; - - GLuint numClipRects; /* Cliprects active */ - GLuint numAllocedClipRects; /* Cliprects available */ - drm_clip_rect_t *pClipRects; -}; - -struct radeon_stencilbuffer_state { - GLboolean hwBuffer; - GLuint clear; /* rb3d_stencilrefmask value */ -}; - -struct radeon_stipple_state { - GLuint mask[32]; -}; - -struct radeon_state_atom { - struct radeon_state_atom *next, *prev; - const char *name; /* for debug */ - int cmd_size; /* size in bytes */ - GLuint idx; - GLuint is_tcl; - GLuint *cmd; /* one or more cmd's */ - GLuint *lastcmd; /* one or more cmd's */ - GLboolean dirty; /* dirty-mark in emit_state_list */ - int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */ - void (*emit) (GLcontext *, struct radeon_state_atom *atom); -}; - -struct radeon_hw_state { - /* Head of the linked list of state atoms. */ - struct radeon_state_atom atomlist; - int max_state_size; /* Number of bytes necessary for a full state emit. */ - GLboolean is_dirty, all_dirty; -}; - - -/* Texture related */ -typedef struct _radeon_texture_image radeon_texture_image; - -struct _radeon_texture_image { - struct gl_texture_image base; - - /** - * If mt != 0, the image is stored in hardware format in the - * given mipmap tree. In this case, base.Data may point into the - * mapping of the buffer object that contains the mipmap tree. - * - * If mt == 0, the image is stored in normal memory pointed to - * by base.Data. - */ - struct _radeon_mipmap_tree *mt; - struct radeon_bo *bo; - - int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ - int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ -}; - - -static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image) -{ - return (radeon_texture_image*)image; -} - - -typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; - -#define RADEON_TXO_MICRO_TILE (1 << 3) - -/* Texture object in locally shared texture space. - */ -struct radeon_tex_obj { - // driTextureObject base; - struct gl_texture_object base; - struct _radeon_mipmap_tree *mt; - - /** - * This is true if we've verified that the mipmap tree above is complete - * and so on. - */ - GLboolean validated; - - GLuint override_offset; - GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ - GLuint tile_bits; /* hw texture tile bits used on this texture */ - struct radeon_bo *bo; - - GLuint bufAddr; /* Offset to start of locally - shared texture block */ - - GLuint dirty_state; /* Flags (1 per texunit) for - whether or not this texobj - has dirty hardware state - (pp_*) that needs to be - brought into the - texunit. */ - - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; - /* Six, for the cube faces */ - - - - GLuint pp_txfilter; /* hardware register values */ - GLuint pp_txformat; - GLuint pp_txformat_x; - GLuint pp_txoffset; /* Image location in texmem. - All cube faces follow. */ - GLuint pp_txsize; /* npot only */ - GLuint pp_txpitch; /* npot only */ - GLuint pp_border_color; - GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ - - GLuint pp_txfilter_1; /* r300 */ - - GLboolean border_fallback; - - -}; - -static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj) -{ - return (radeonTexObj*)texObj; -} - -/* Need refcounting on dma buffers: - */ -struct radeon_dma_buffer { - int refcount; /* the number of retained regions in buf */ - drmBufPtr buf; -}; - -struct radeon_aos { - struct radeon_bo *bo; /** Buffer object where vertex data is stored */ - int offset; /** Offset into buffer object, in bytes */ - int components; /** Number of components per vertex */ - int stride; /** Stride in dwords (may be 0 for repeating) */ - int count; /** Number of vertices */ -}; - -struct radeon_dma { - /* Active dma region. Allocations for vertices and retained - * regions come from here. Also used for emitting random vertices, - * these may be flushed by calling flush_current(); - */ - struct radeon_bo *current; /** Buffer that DMA memory is allocated from */ - int current_used; /** Number of bytes allocated and forgotten about */ - int current_vertexptr; /** End of active vertex region */ - - /** - * If current_vertexptr != current_used then flush must be non-zero. - * flush must be called before non-active vertex allocations can be - * performed. - */ - void (*flush) (GLcontext *); - - /* Number of "in-flight" DMA buffers, i.e. the number of buffers - * for which a DISCARD command is currently queued in the command buffer -. - */ - GLuint nr_released_bufs; -}; - -/* radeon_swtcl.c - */ -struct radeon_swtcl_info { - - GLuint RenderIndex; - GLuint vertex_size; - GLubyte *verts; - - /* Fallback rasterization functions - */ - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - GLuint vertex_attr_count; - -}; - -struct radeon_ioctl { - GLuint vertex_offset; - struct radeon_bo *bo; - GLuint vertex_size; -}; - -#define RADEON_MAX_PRIMS 64 - -struct radeon_prim { - GLuint start; - GLuint end; - GLuint prim; -}; - -static INLINE GLuint radeonPackColor(GLuint cpp, - GLubyte r, GLubyte g, - GLubyte b, GLubyte a) -{ - switch (cpp) { - case 2: - return PACK_COLOR_565(r, g, b); - case 4: - return PACK_COLOR_8888(a, r, g, b); - default: - return 0; - } -} - -#define MAX_CMD_BUF_SZ (16*1024) - -#define MAX_DMA_BUF_SZ (64*1024) - -struct radeon_store { - GLuint statenr; - GLuint primnr; - char cmd_buf[MAX_CMD_BUF_SZ]; - int cmd_used; - int elts_start; -}; - -struct radeon_dri_mirror { - __DRIcontextPrivate *context; /* DRI context */ - __DRIscreenPrivate *screen; /* DRI screen */ - - /** - * DRI drawable bound to this context for drawing. - */ - __DRIdrawablePrivate *drawable; - - /** - * DRI drawable bound to this context for reading. - */ - __DRIdrawablePrivate *readable; - - drm_context_t hwContext; - drm_hw_lock_t *hwLock; - int fd; - int drmMinor; -}; - -#define DEBUG_TEXTURE 0x001 -#define DEBUG_STATE 0x002 -#define DEBUG_IOCTL 0x004 -#define DEBUG_PRIMS 0x008 -#define DEBUG_VERTS 0x010 -#define DEBUG_FALLBACKS 0x020 -#define DEBUG_VFMT 0x040 -#define DEBUG_CODEGEN 0x080 -#define DEBUG_VERBOSE 0x100 -#define DEBUG_DRI 0x200 -#define DEBUG_DMA 0x400 -#define DEBUG_SANITY 0x800 -#define DEBUG_SYNC 0x1000 -#define DEBUG_PIXEL 0x2000 -#define DEBUG_MEMORY 0x4000 - - - -typedef void (*radeon_tri_func) (radeonContextPtr, - radeonVertex *, - radeonVertex *, radeonVertex *); - -typedef void (*radeon_line_func) (radeonContextPtr, - radeonVertex *, radeonVertex *); - -typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); - -struct radeon_state { - struct radeon_colorbuffer_state color; - struct radeon_depthbuffer_state depth; - struct radeon_scissor_state scissor; - struct radeon_stencilbuffer_state stencil; -}; - -/** - * This structure holds the command buffer while it is being constructed. - * - * The first batch of commands in the buffer is always the state that needs - * to be re-emitted when the context is lost. This batch can be skipped - * otherwise. - */ -struct radeon_cmdbuf { - struct radeon_cs_manager *csm; - struct radeon_cs *cs; - int size; /** # of dwords total */ - unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ -}; - -struct radeon_context { - GLcontext *glCtx; - radeonScreenPtr radeonScreen; /* Screen private DRI data */ - - /* Texture object bookkeeping - */ - unsigned nr_heaps; - driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; - driTextureObject swapped; - int texture_depth; - float initialMaxAnisotropy; - - struct radeon_dma dma; - struct radeon_hw_state hw; - /* Rasterization and vertex state: - */ - GLuint TclFallback; - GLuint Fallback; - GLuint NewGLState; - DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ - - /* Page flipping */ - GLuint doPageFlip; - - /* Drawable, cliprect and scissor information */ - GLuint numClipRects; /* Cliprects for the draw buffer */ - drm_clip_rect_t *pClipRects; - unsigned int lastStamp; - GLboolean lost_context; - drm_radeon_sarea_t *sarea; /* Private SAREA data */ - - /* Mirrors of some DRI state */ - struct radeon_dri_mirror dri; - - /* Busy waiting */ - GLuint do_usleeps; - GLuint do_irqs; - GLuint irqsEmitted; - drm_radeon_irq_wait_t iw; - - /* buffer swap */ - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; - - /* Derived state - for r300 only */ - struct radeon_state state; - - struct radeon_swtcl_info swtcl; - /* Configuration cache - */ - driOptionCache optionCache; - - struct radeon_cmdbuf cmdbuf; - - struct { - void (*get_lock)(radeonContextPtr radeon); - void (*update_viewport_offset)(GLcontext *ctx); - void (*update_draw_buffer)(GLcontext *ctx); - void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); - void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); - void (*pre_emit_atoms)(radeonContextPtr rmesa); - void (*pre_emit_state)(radeonContextPtr rmesa); - } vtbl; -}; - -#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) - -/** - * This function takes a float and packs it into a uint32_t - */ -static INLINE uint32_t radeonPackFloat32(float fl) -{ - union { - float fl; - uint32_t u; - } u; - - u.fl = fl; - return u.u; -} - -/* This is probably wrong for some values, I need to test this - * some more. Range checking would be a good idea also.. - * - * But it works for most things. I'll fix it later if someone - * else with a better clue doesn't - */ -static INLINE uint32_t radeonPackFloat24(float f) -{ - float mantissa; - int exponent; - uint32_t float24 = 0; - - if (f == 0.0) - return 0; - - mantissa = frexpf(f, &exponent); - - /* Handle -ve */ - if (mantissa < 0) { - float24 |= (1 << 23); - mantissa = mantissa * -1.0; - } - /* Handle exponent, bias of 63 */ - exponent += 62; - float24 |= (exponent << 16); - /* Kill 7 LSB of mantissa */ - float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7; - - return float24; -} - -/* ================================================================ - * Debugging: - */ -#define DO_DEBUG 1 - -#if DO_DEBUG -extern int RADEON_DEBUG; -#else -#define RADEON_DEBUG 0 -#endif - -#include "common_misc.h" -#include "common_cmdbuf.h" -#endif diff --git a/src/mesa/drivers/dri/radeon/common_lock.c b/src/mesa/drivers/dri/radeon/common_lock.c deleted file mode 100644 index 91600ac4cda..00000000000 --- a/src/mesa/drivers/dri/radeon/common_lock.c +++ /dev/null @@ -1,126 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Gareth Hughes - * Keith Whitwell - * Kevin E. Martin - */ - -#include "main/glheader.h" -#include "main/mtypes.h" -#include "main/colormac.h" -#include "dri_util.h" -#include "radeon_screen.h" -#include "common_context.h" -#include "common_lock.h" -#include "common_misc.h" - -#include "drirenderbuffer.h" - -#if DEBUG_LOCKING -char *prevLockFile = NULL; -int prevLockLine = 0; -#endif - -/* Turn on/off page flipping according to the flags in the sarea: - */ -void radeonUpdatePageFlipping(radeonContextPtr rmesa) -{ - int use_back; - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - GLframebuffer *fb = drawable->driverPrivate; - - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - rmesa->vtbl.update_draw_buffer(rmesa->glCtx); - } - - use_back = rmesa->glCtx->DrawBuffer ? - (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == - BUFFER_BACK_LEFT) : 1; - use_back ^= (rmesa->sarea->pfCurrentPage == 1); - - if (use_back) - rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - else - rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - - rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; -} - -/* Update the hardware state. This is called if another context has - * grabbed the hardware lock, which includes the X server. This - * function also updates the driver's window state after the X server - * moves, resizes or restacks a window -- the change will be reflected - * in the drawable position and clip rects. Since the X server grabs - * the hardware lock when it changes the window state, this routine will - * automatically be called after such a change. - */ -void radeonGetLock(radeonContextPtr rmesa, GLuint flags) -{ - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->dri.readable; - __DRIscreenPrivate *sPriv = rmesa->dri.screen; - drm_radeon_sarea_t *sarea = rmesa->sarea; - - assert(drawable != NULL); - - drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); - - /* The window might have moved, so we might need to get new clip - * rects. - * - * NOTE: This releases and regrabs the hw lock to allow the X server - * to respond to the DRI protocol request for new drawable info. - * Since the hardware state depends on having the latest drawable - * clip rects, all state checking must be done _after_ this call. - */ - DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); - if (drawable != readable) { - DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); - } - - if (rmesa->lastStamp != drawable->lastStamp) { - radeonUpdatePageFlipping(rmesa); - radeonSetCliprects(rmesa); - rmesa->vtbl.update_viewport_offset(rmesa->glCtx); - driUpdateFramebufferSize(rmesa->glCtx, drawable); - } - - rmesa->vtbl.get_lock(rmesa); - - rmesa->lost_context = GL_TRUE; -} diff --git a/src/mesa/drivers/dri/radeon/common_lock.h b/src/mesa/drivers/dri/radeon/common_lock.h deleted file mode 100644 index 431b076f025..00000000000 --- a/src/mesa/drivers/dri/radeon/common_lock.h +++ /dev/null @@ -1,120 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Gareth Hughes - * Keith Whitwell - * Kevin E. Martin - */ - -#ifndef COMMON_LOCK_H -#define COMMON_LOCK_H - -#include "main/colormac.h" -#include "radeon_screen.h" -#include "common_context.h" - -extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); - -/* Turn DEBUG_LOCKING on to find locking conflicts. - */ -#define DEBUG_LOCKING 0 - -#if DEBUG_LOCKING -extern char *prevLockFile; -extern int prevLockLine; - -#define DEBUG_LOCK() \ - do { \ - prevLockFile = (__FILE__); \ - prevLockLine = (__LINE__); \ - } while (0) - -#define DEBUG_RESET() \ - do { \ - prevLockFile = 0; \ - prevLockLine = 0; \ - } while (0) - -#define DEBUG_CHECK_LOCK() \ - do { \ - if ( prevLockFile ) { \ - fprintf( stderr, \ - "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ - prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ - exit( 1 ); \ - } \ - } while (0) - -#else - -#define DEBUG_LOCK() -#define DEBUG_RESET() -#define DEBUG_CHECK_LOCK() - -#endif - -/* - * !!! We may want to separate locks from locks with validation. This - * could be used to improve performance for those things commands that - * do not do any drawing !!! - */ - -/* Lock the hardware and validate our state. - */ -#define LOCK_HARDWARE( rmesa ) \ - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ - if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ - DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ - if ( __ret ) \ - radeonGetLock( (rmesa), 0 ); \ - } \ - DEBUG_LOCK(); \ - } while (0) - -#define UNLOCK_HARDWARE( rmesa ) \ - do { \ - if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ - DRM_UNLOCK( (rmesa)->dri.fd, \ - (rmesa)->dri.hwLock, \ - (rmesa)->dri.hwContext ); \ - DEBUG_RESET(); \ - } \ - } while (0) - -#endif diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c deleted file mode 100644 index f0035e54cfd..00000000000 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ /dev/null @@ -1,2715 +0,0 @@ -/************************************************************************** - -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/api_arrayelt.h" -#include "main/enums.h" -#include "main/colormac.h" -#include "main/light.h" -#include "main/framebuffer.h" -#include "main/simple_list.h" - -#include "swrast/swrast.h" -#include "vbo/vbo.h" -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" -#include "swrast_setup/swrast_setup.h" -#include "main/mipmap.h" -#include "main/texformat.h" -#include "main/texstore.h" -#include "main/teximage.h" -#include "main/texobj.h" - -#include "drirenderbuffer.h" -#include "vblank.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ - -#include "radeon_bo.h" -#include "radeon_cs.h" -#include "radeon_bo_legacy.h" -#include "radeon_cs_legacy.h" -#include "radeon_bo_gem.h" -#include "radeon_cs_gem.h" -#include "dri_util.h" -#include "radeon_drm.h" -#include "radeon_buffer.h" -#include "radeon_screen.h" -#include "common_context.h" -#include "common_misc.h" -#include "common_lock.h" -#include "common_cmdbuf.h" -#include "radeon_mipmap_tree.h" -#include "radeon_span.h" - -#define DRIVER_DATE "20090101" - -#ifndef RADEON_DEBUG -int RADEON_DEBUG = (0); -#endif - -#define DEBUG_CMDBUF 0 - -/* ============================================================= - * Scissoring - */ - -static GLboolean intersect_rect(drm_clip_rect_t * out, - drm_clip_rect_t * a, drm_clip_rect_t * b) -{ - *out = *a; - if (b->x1 > out->x1) - out->x1 = b->x1; - if (b->y1 > out->y1) - out->y1 = b->y1; - if (b->x2 < out->x2) - out->x2 = b->x2; - if (b->y2 < out->y2) - out->y2 = b->y2; - if (out->x1 >= out->x2) - return GL_FALSE; - if (out->y1 >= out->y2) - return GL_FALSE; - return GL_TRUE; -} - -void radeonRecalcScissorRects(radeonContextPtr radeon) -{ - drm_clip_rect_t *out; - int i; - - /* Grow cliprect store? - */ - if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) { - while (radeon->state.scissor.numAllocedClipRects < - radeon->numClipRects) { - radeon->state.scissor.numAllocedClipRects += 1; /* zero case */ - radeon->state.scissor.numAllocedClipRects *= 2; - } - - if (radeon->state.scissor.pClipRects) - FREE(radeon->state.scissor.pClipRects); - - radeon->state.scissor.pClipRects = - MALLOC(radeon->state.scissor.numAllocedClipRects * - sizeof(drm_clip_rect_t)); - - if (radeon->state.scissor.pClipRects == NULL) { - radeon->state.scissor.numAllocedClipRects = 0; - return; - } - } - - out = radeon->state.scissor.pClipRects; - radeon->state.scissor.numClipRects = 0; - - for (i = 0; i < radeon->numClipRects; i++) { - if (intersect_rect(out, - &radeon->pClipRects[i], - &radeon->state.scissor.rect)) { - radeon->state.scissor.numClipRects++; - out++; - } - } -} - -/** - * Update cliprects and scissors. - */ -void radeonSetCliprects(radeonContextPtr radeon) -{ - __DRIdrawablePrivate *const drawable = radeon->dri.drawable; - __DRIdrawablePrivate *const readable = radeon->dri.readable; - GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; - GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; - - if (!radeon->radeonScreen->driScreen->dri2.enabled) { - if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* Can't ignore 2d windows if we are page flipping. */ - if (drawable->numBackClipRects == 0 || radeon->doPageFlip || - radeon->sarea->pfCurrentPage == 1) { - radeon->numClipRects = drawable->numClipRects; - radeon->pClipRects = drawable->pClipRects; - } else { - radeon->numClipRects = drawable->numBackClipRects; - radeon->pClipRects = drawable->pBackClipRects; - } - } else { - /* front buffer (or none, or multiple buffers */ - radeon->numClipRects = drawable->numClipRects; - radeon->pClipRects = drawable->pClipRects; - } - } - - if ((draw_fb->Width != drawable->w) || - (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(radeon->glCtx, draw_fb, - drawable->w, drawable->h); - draw_fb->Initialized = GL_TRUE; - } - - if (drawable != readable) { - if ((read_fb->Width != readable->w) || - (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(radeon->glCtx, read_fb, - readable->w, readable->h); - read_fb->Initialized = GL_TRUE; - } - } - - if (radeon->state.scissor.enabled) - radeonRecalcScissorRects(radeon); - - radeon->lastStamp = drawable->lastStamp; -} - -void radeonUpdateScissor( GLcontext *ctx ) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - - if ( rmesa->dri.drawable ) { - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; - - int x = ctx->Scissor.X; - int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; - int w = ctx->Scissor.X + ctx->Scissor.Width - 1; - int h = dPriv->h - ctx->Scissor.Y - 1; - - rmesa->state.scissor.rect.x1 = x + dPriv->x; - rmesa->state.scissor.rect.y1 = y + dPriv->y; - rmesa->state.scissor.rect.x2 = w + dPriv->x + 1; - rmesa->state.scissor.rect.y2 = h + dPriv->y + 1; - - radeonRecalcScissorRects( rmesa ); - } -} - -/* ============================================================= - * Scissoring - */ - -void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - if (ctx->Scissor.Enabled) { - /* We don't pipeline cliprect changes */ - radeon_firevertices(radeon); - radeonUpdateScissor(ctx); - } -} - - -/* ================================================================ - * SwapBuffers with client-side throttling - */ - -static uint32_t radeonGetLastFrame(radeonContextPtr radeon) -{ - drm_radeon_getparam_t gp; - int ret; - uint32_t frame; - - gp.param = RADEON_PARAM_LAST_FRAME; - gp.value = (int *)&frame; - ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp)); - if (ret) { - fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, - ret); - exit(1); - } - - return frame; -} - -uint32_t radeonGetAge(radeonContextPtr radeon) -{ - drm_radeon_getparam_t gp; - int ret; - uint32_t age; - - gp.param = RADEON_PARAM_LAST_CLEAR; - gp.value = (int *)&age; - ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, - &gp, sizeof(gp)); - if (ret) { - fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, - ret); - exit(1); - } - - return age; -} - -static void radeonEmitIrqLocked(radeonContextPtr radeon) -{ - drm_radeon_irq_emit_t ie; - int ret; - - ie.irq_seq = &radeon->iw.irq_seq; - ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_IRQ_EMIT, - &ie, sizeof(ie)); - if (ret) { - fprintf(stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, - ret); - exit(1); - } -} - -static void radeonWaitIrq(radeonContextPtr radeon) -{ - int ret; - - do { - ret = drmCommandWrite(radeon->dri.fd, DRM_RADEON_IRQ_WAIT, - &radeon->iw, sizeof(radeon->iw)); - } while (ret && (errno == EINTR || errno == EBUSY)); - - if (ret) { - fprintf(stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, - ret); - exit(1); - } -} - -static void radeonWaitForFrameCompletion(radeonContextPtr radeon) -{ - drm_radeon_sarea_t *sarea = radeon->sarea; - - if (radeon->do_irqs) { - if (radeonGetLastFrame(radeon) < sarea->last_frame) { - if (!radeon->irqsEmitted) { - while (radeonGetLastFrame(radeon) < - sarea->last_frame) ; - } else { - UNLOCK_HARDWARE(radeon); - radeonWaitIrq(radeon); - LOCK_HARDWARE(radeon); - } - radeon->irqsEmitted = 10; - } - - if (radeon->irqsEmitted) { - radeonEmitIrqLocked(radeon); - radeon->irqsEmitted--; - } - } else { - while (radeonGetLastFrame(radeon) < sarea->last_frame) { - UNLOCK_HARDWARE(radeon); - if (radeon->do_usleeps) - DO_USLEEP(1); - LOCK_HARDWARE(radeon); - } - } -} - -/* wait for idle */ -void radeonWaitForIdleLocked(radeonContextPtr radeon) -{ - int ret; - int i = 0; - - do { - ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_CP_IDLE); - if (ret) - DO_USLEEP(1); - } while (ret && ++i < 100); - - if (ret < 0) { - UNLOCK_HARDWARE(radeon); - fprintf(stderr, "Error: R300 timed out... exiting\n"); - exit(-1); - } -} - -static void radeonWaitForIdle(radeonContextPtr radeon) -{ - LOCK_HARDWARE(radeon); - radeonWaitForIdleLocked(radeon); - UNLOCK_HARDWARE(radeon); -} - - -/* Copy the back color buffer to the front color buffer. - */ -void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, - const drm_clip_rect_t *rect) -{ - radeonContextPtr rmesa; - GLint nbox, i, ret; - GLboolean missed_target; - int64_t ust; - __DRIscreenPrivate *psp; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); - } - - radeon_firevertices(rmesa); - LOCK_HARDWARE( rmesa ); - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion( rmesa ); - if (!rect) - { - UNLOCK_HARDWARE( rmesa ); - driWaitForVBlank( dPriv, & missed_target ); - LOCK_HARDWARE( rmesa ); - } - - nbox = dPriv->numClipRects; /* must be in locked region */ - - for ( i = 0 ; i < nbox ; ) { - GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; - GLint n = 0; - - for ( ; i < nr ; i++ ) { - - *b = box[i]; - - if (rect) - { - if (rect->x1 > b->x1) - b->x1 = rect->x1; - if (rect->y1 > b->y1) - b->y1 = rect->y1; - if (rect->x2 < b->x2) - b->x2 = rect->x2; - if (rect->y2 < b->y2) - b->y2 = rect->y2; - - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } - - b++; - n++; - } - rmesa->sarea->nbox = n; - - if (!n) - continue; - - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( rmesa ); - exit( 1 ); - } - } - - UNLOCK_HARDWARE( rmesa ); - if (!rect) - { - psp = dPriv->driScreenPriv; - rmesa->swap_count++; - (*psp->systemTime->getUST)( & ust ); - if ( missed_target ) { - rmesa->swap_missed_count++; - rmesa->swap_missed_ust = ust - rmesa->swap_ust; - } - - rmesa->swap_ust = ust; - rmesa->hw.all_dirty = GL_TRUE; - - } -} - -void radeonPageFlip( __DRIdrawablePrivate *dPriv ) -{ - radeonContextPtr rmesa; - GLint ret; - GLboolean missed_target; - __DRIscreenPrivate *psp; - struct radeon_renderbuffer *rrb; - GLframebuffer *fb = dPriv->driverPrivate; - - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); - - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - - psp = dPriv->driScreenPriv; - - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); - } - - radeon_firevertices(rmesa); - - LOCK_HARDWARE( rmesa ); - - if (!dPriv->numClipRects) { - UNLOCK_HARDWARE(rmesa); - usleep(10000); /* throttle invisible client 10ms */ - return; - } - - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; - b[0] = box[0]; - rmesa->sarea->nbox = 1; - - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion( rmesa ); - UNLOCK_HARDWARE( rmesa ); - driWaitForVBlank( dPriv, & missed_target ); - if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); - } - LOCK_HARDWARE( rmesa ); - - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); - - UNLOCK_HARDWARE( rmesa ); - - if ( ret ) { - fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); - } - - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); - - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. - */ - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); - - rmesa->state.color.rrb = rrb; - - if (rmesa->vtbl.update_draw_buffer) - rmesa->vtbl.update_draw_buffer(rmesa->glCtx); -} - -void radeonFlush(GLcontext *ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (radeon->dma.flush) - radeon->dma.flush( ctx ); - - radeonEmitState(radeon); - - if (radeon->cmdbuf.cs->cdw) - rcommonFlushCmdBuf(radeon, __FUNCTION__); -} - -static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) -{ - BATCH_LOCALS(radeon); - struct radeon_state_atom *atom; - int dwords; - - if (radeon->vtbl.pre_emit_atoms) - radeon->vtbl.pre_emit_atoms(radeon); - - /* Emit actual atoms */ - foreach(atom, &radeon->hw.atomlist) { - if ((atom->dirty || radeon->hw.all_dirty) == dirty) { - dwords = (*atom->check) (radeon->glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(atom); - } - if (atom->emit) { - (*atom->emit)(radeon->glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -void radeonEmitState(radeonContextPtr radeon) -{ - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (radeon->vtbl.pre_emit_state) - radeon->vtbl.pre_emit_state(radeon); - - /* this code used to return here but now it emits zbs */ - if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) - return; - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state, and inline the - * radeonAllocCmdBuf code here without all the checks. - */ - rcommonEnsureCmdBufSpace(radeon, radeon->hw.max_state_size, __FUNCTION__); - - /* We always always emit zbs, this is due to a bug found by keithw in - the hardware and rediscovered after Erics changes by me. - if you ever touch this code make sure you emit zbs otherwise - you get tcl lockups on at least M7/7500 class of chips - airlied */ - /* special r100 case */ - // rmesa->hw.zbs.dirty=1; - - if (!radeon->cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - radeonEmitAtoms(radeon, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - radeonEmitAtoms(radeon, GL_TRUE); - radeon->hw.is_dirty = GL_FALSE; - radeon->hw.all_dirty = GL_FALSE; - -} - - -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void radeonFinish(GLcontext * ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; - int i; - - radeonFlush(ctx); - - if (radeon->radeonScreen->kernel_mm) { - for (i = 0; i < fb->_NumColorDrawBuffers; i++) { - struct radeon_renderbuffer *rrb; - rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; - if (rrb->bo) - radeon_bo_wait(rrb->bo); - } - } else if (radeon->do_irqs) { - LOCK_HARDWARE(radeon); - radeonEmitIrqLocked(radeon); - UNLOCK_HARDWARE(radeon); - radeonWaitIrq(radeon); - } else { - radeonWaitForIdle(radeon); - } -} - -/** - * Swap front and back buffer. - */ -void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - radeonContextPtr radeon; - GLcontext *ctx; - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = radeon->glCtx; - - if (ctx->Visual.doubleBufferMode) { - _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ - if (radeon->doPageFlip) { - radeonPageFlip(dPriv); - } else { - radeonCopyBuffer(dPriv, NULL); - } - } - } else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", - __FUNCTION__); - } -} - -void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h ) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - radeonContextPtr radeon; - GLcontext *ctx; - - radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - ctx = radeon->glCtx; - - if (ctx->Visual.doubleBufferMode) { - drm_clip_rect_t rect; - rect.x1 = x + dPriv->x; - rect.y1 = (dPriv->h - y - h) + dPriv->y; - rect.x2 = rect.x1 + w; - rect.y2 = rect.y1 + h; - _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ - radeonCopyBuffer(dPriv, &rect); - } - } else { - /* XXX this shouldn't be an error but we can't handle it for now */ - _mesa_problem(NULL, "%s: drawable has no context!", - __FUNCTION__); - } -} - -/* cmdbuffer */ -/** - * Send the current command buffer via ioctl to the hardware. - */ -int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) -{ - int ret = 0; - - if (rmesa->cmdbuf.flushing) { - fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n"); - exit(-1); - } - rmesa->cmdbuf.flushing = 1; - if (rmesa->cmdbuf.cs->cdw) { - ret = radeon_cs_emit(rmesa->cmdbuf.cs); - rmesa->hw.all_dirty = GL_TRUE; - } - radeon_cs_erase(rmesa->cmdbuf.cs); - rmesa->cmdbuf.flushing = 0; - return ret; -} - -int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller) -{ - int ret; - - radeonReleaseDmaRegion(rmesa); - - LOCK_HARDWARE(rmesa); - ret = rcommonFlushCmdBufLocked(rmesa, caller); - UNLOCK_HARDWARE(rmesa); - - if (ret) { - fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret); - _mesa_exit(ret); - } - - return ret; -} - -/** - * Make sure that enough space is available in the command buffer - * by flushing if necessary. - * - * \param dwords The number of dwords we need to be free on the command buffer - */ -void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller) -{ - if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size || - radeon_cs_need_flush(rmesa->cmdbuf.cs)) { - rcommonFlushCmdBuf(rmesa, caller); - } -} - -void rcommonInitCmdBuf(radeonContextPtr rmesa) -{ - GLuint size; - /* Initialize command buffer */ - size = 256 * driQueryOptioni(&rmesa->optionCache, - "command_buffer_size"); - if (size < 2 * rmesa->hw.max_state_size) { - size = 2 * rmesa->hw.max_state_size + 65535; - } - if (size > 64 * 256) - size = 64 * 256; - - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { - fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", - sizeof(drm_r300_cmd_header_t)); - fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%zd\n", - sizeof(drm_radeon_cmd_buffer_t)); - fprintf(stderr, - "Allocating %d bytes command buffer (max state is %d bytes)\n", - size * 4, rmesa->hw.max_state_size * 4); - } - - if (rmesa->radeonScreen->kernel_mm) { - int fd = rmesa->radeonScreen->driScreen->fd; - rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); - } else { - rmesa->cmdbuf.csm = radeon_cs_manager_legacy_ctor(rmesa); - } - if (rmesa->cmdbuf.csm == NULL) { - /* FIXME: fatal error */ - return; - } - rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); - assert(rmesa->cmdbuf.cs != NULL); - rmesa->cmdbuf.size = size; - - if (!rmesa->radeonScreen->kernel_mm) { - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); - } else { - struct drm_radeon_gem_info mminfo; - - if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) - { - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_size); - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size); - } - } - -} -/** - * Destroy the command buffer - */ -void rcommonDestroyCmdBuf(radeonContextPtr rmesa) -{ - radeon_cs_destroy(rmesa->cmdbuf.cs); - if (rmesa->radeonScreen->driScreen->dri2.enabled || rmesa->radeonScreen->kernel_mm) { - radeon_cs_manager_gem_dtor(rmesa->cmdbuf.csm); - } else { - radeon_cs_manager_legacy_dtor(rmesa->cmdbuf.csm); - } -} - -void rcommonBeginBatch(radeonContextPtr rmesa, int n, - int dostate, - const char *file, - const char *function, - int line) -{ - rcommonEnsureCmdBufSpace(rmesa, n, function); - if (!rmesa->cmdbuf.cs->cdw && dostate) { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "Reemit state after flush (from %s)\n", function); - radeonEmitState(rmesa); - } - radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); -} - - - -/* Return various strings for glGetString(). - */ -static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - static char buffer[128]; - - switch (name) { - case GL_VENDOR: - if (IS_R300_CLASS(radeon->radeonScreen)) - return (GLubyte *) "DRI R300 Project"; - else - return (GLubyte *) "Tungsten Graphics, Inc."; - - case GL_RENDERER: - { - unsigned offset; - GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : - radeon->radeonScreen->AGPMode; - const char* chipname; - - if (IS_R300_CLASS(radeon->radeonScreen)) - chipname = "R300"; - else if (IS_R200_CLASS(radeon->radeonScreen)) - chipname = "R200"; - else - chipname = "R100"; - - offset = driGetRendererString(buffer, chipname, DRIVER_DATE, - agp_mode); - - if (IS_R300_CLASS(radeon->radeonScreen)) { - sprintf(&buffer[offset], " %sTCL", - (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) - ? "" : "NO-"); - } else { - sprintf(&buffer[offset], " %sTCL", - !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) - ? "" : "NO-"); - } - - if (radeon->radeonScreen->driScreen->dri2.enabled) - strcat(buffer, " DRI2"); - - return (GLubyte *) buffer; - } - - default: - return NULL; - } -} - -/* Initialize the driver's misc functions. - */ -static void radeonInitDriverFuncs(struct dd_function_table *functions) -{ - functions->GetString = radeonGetString; -} - -/** - * Create and initialize all common fields of the context, - * including the Mesa context itself. - */ -GLboolean radeonInitContext(radeonContextPtr radeon, - struct dd_function_table* functions, - const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate) -{ - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); - GLcontext* ctx; - GLcontext* shareCtx; - int fthrottle_mode; - - /* Fill in additional standard functions. */ - radeonInitDriverFuncs(functions); - - radeon->radeonScreen = screen; - /* Allocate and initialize the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx; - else - shareCtx = NULL; - radeon->glCtx = _mesa_create_context(glVisual, shareCtx, - functions, (void *)radeon); - if (!radeon->glCtx) - return GL_FALSE; - - ctx = radeon->glCtx; - driContextPriv->driverPrivate = radeon; - - /* DRI fields */ - radeon->dri.context = driContextPriv; - radeon->dri.screen = sPriv; - radeon->dri.drawable = NULL; - radeon->dri.readable = NULL; - radeon->dri.hwContext = driContextPriv->hHWContext; - radeon->dri.hwLock = &sPriv->pSAREA->lock; - radeon->dri.fd = sPriv->fd; - radeon->dri.drmMinor = sPriv->drm_version.minor; - - radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + - screen->sarea_priv_offset); - - /* Setup IRQs */ - fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); - radeon->iw.irq_seq = -1; - radeon->irqsEmitted = 0; - radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - radeon->radeonScreen->irq); - - radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - - if (!radeon->do_irqs) - fprintf(stderr, - "IRQ's not enabled, falling back to %s: %d %d\n", - radeon->do_usleeps ? "usleeps" : "busy waits", - fthrottle_mode, radeon->radeonScreen->irq); - - (*sPriv->systemTime->getUST) (&radeon->swap_ust); - - return GL_TRUE; -} - -/** - * Cleanup common context fields. - * Called by r200DestroyContext/r300DestroyContext - */ -void radeonCleanupContext(radeonContextPtr radeon) -{ - FILE *track; - struct radeon_renderbuffer *rb; - GLframebuffer *fb; - - /* free the Mesa context */ - _mesa_destroy_context(radeon->glCtx); - - fb = (void*)radeon->dri.drawable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - fb = (void*)radeon->dri.readable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - - /* _mesa_destroy_context() might result in calls to functions that - * depend on the DriverCtx, so don't set it to NULL before. - * - * radeon->glCtx->DriverCtx = NULL; - */ - - - - /* free the option cache */ - driDestroyOptionCache(&radeon->optionCache); - - rcommonDestroyCmdBuf(radeon); - - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = 0; - } - track = fopen("/tmp/tracklog", "w"); - if (track) { - radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); - fclose(track); - } -} - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) -{ - radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, - radeon->glCtx); - - return GL_TRUE; -} - - -static void -radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) -{ - /* if radeon->fake */ - struct radeon_renderbuffer *rb; - - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } -} - -static void -radeon_make_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) -{ - int size = 4096*4096*4; - /* if radeon->fake */ - struct radeon_renderbuffer *rb; - - if (radeon->radeonScreen->kernel_mm) { - radeon_make_kernel_renderbuffer_current(radeon, draw); - return; - } - - - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } -} - - -void -radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) -{ - unsigned int attachments[10]; - __DRIbuffer *buffers; - __DRIscreen *screen; - struct radeon_renderbuffer *rb; - int i, count; - GLframebuffer *draw; - radeonContextPtr radeon; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); - - draw = drawable->driverPrivate; - screen = context->driScreenPriv; - radeon = (radeonContextPtr) context->driverPrivate; - i = 0; - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_FRONT_LEFT; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_BACK_LEFT; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_DEPTH; - } - - buffers = (*screen->dri2.loader->getBuffers)(drawable, - &drawable->w, - &drawable->h, - attachments, i, - &count, - drawable->loaderPrivate); - if (buffers == NULL) - return; - - /* set one cliprect to cover the whole drawable */ - drawable->x = 0; - drawable->y = 0; - drawable->backX = 0; - drawable->backY = 0; - drawable->numClipRects = 1; - drawable->pClipRects[0].x1 = 0; - drawable->pClipRects[0].y1 = 0; - drawable->pClipRects[0].x2 = drawable->w; - drawable->pClipRects[0].y2 = drawable->h; - drawable->numBackClipRects = 1; - drawable->pBackClipRects[0].x1 = 0; - drawable->pBackClipRects[0].y1 = 0; - drawable->pBackClipRects[0].x2 = drawable->w; - drawable->pBackClipRects[0].y2 = drawable->h; - for (i = 0; i < count; i++) { - switch (buffers[i].attachment) { - case __DRI_BUFFER_FRONT_LEFT: - rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - if (rb->bo == NULL) { - fprintf(stderr, "failled to attach front %d\n", - buffers[i].name); - } - break; - case __DRI_BUFFER_BACK_LEFT: - rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - break; - case __DRI_BUFFER_DEPTH: - rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - break; - case __DRI_BUFFER_STENCIL: - break; - case __DRI_BUFFER_ACCUM: - default: - fprintf(stderr, - "unhandled buffer attach event, attacment type %d\n", - buffers[i].attachment); - return; - } - } - radeon = (radeonContextPtr) context->driverPrivate; - driUpdateFramebufferSize(radeon->glCtx, drawable); -} - -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) -{ - radeonContextPtr radeon; - GLframebuffer *dfb, *rfb; - - if (!driContextPriv) { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current(NULL, NULL, NULL); - return GL_TRUE; - } - radeon = (radeonContextPtr) driContextPriv->driverPrivate; - dfb = driDrawPriv->driverPrivate; - rfb = driReadPriv->driverPrivate; - - if (driContextPriv->driScreenPriv->dri2.enabled) { - radeon_update_renderbuffers(driContextPriv, driDrawPriv); - if (driDrawPriv != driReadPriv) - radeon_update_renderbuffers(driContextPriv, driReadPriv); - radeon->state.color.rrb = - (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - radeon->state.depth.rrb = - (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; - } else { - radeon_make_renderbuffer_current(radeon, dfb); - } - - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, dfb, rfb); - - driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); - if (driReadPriv != driDrawPriv) - driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - - - - _mesa_make_current(radeon->glCtx, dfb, rfb); - - if (radeon->dri.drawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = - (radeon->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&radeon-> - optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank(driDrawPriv); - } - } - - radeon->dri.readable = driReadPriv; - - if (radeon->dri.drawable != driDrawPriv || - radeon->lastStamp != driDrawPriv->lastStamp) { - radeon->dri.drawable = driDrawPriv; - - radeonSetCliprects(radeon); - radeon->vtbl.update_viewport_offset(radeon->glCtx); - } - - _mesa_update_state(radeon->glCtx); - - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeonUpdatePageFlipping(radeon); - } - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} - - -#if defined(USE_X86_ASM) -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int __tmp; \ - __asm__ __volatile__( "rep ; movsl" \ - : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ - : "0" (nr), \ - "D" ((long)dst), \ - "S" ((long)src) ); \ -} while (0) -#else -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int j; \ - for ( j = 0 ; j < nr ; j++ ) \ - dst[j] = ((int *)src)[j]; \ - dst += nr; \ -} while (0) -#endif - -static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 4) - COPY_DWORDS(out, data, count); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out++; - data += stride; - } -} - -void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 8) - COPY_DWORDS(out, data, count * 2); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out += 2; - data += stride; - } -} - -void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 12) { - COPY_DWORDS(out, data, count * 3); - } - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out += 3; - data += stride; - } -} - -static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 16) - COPY_DWORDS(out, data, count * 4); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out[3] = *(int *)(data + 12); - out += 4; - data += stride; - } -} - -void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, - GLvoid * data, int size, int stride, int count) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - uint32_t *out; - - if (stride == 0) { - radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); - count = 1; - aos->stride = 0; - } else { - radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); - aos->stride = size; - } - - aos->components = size; - aos->count = count; - - out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); - switch (size) { - case 1: radeonEmitVec4(out, data, stride, count); break; - case 2: radeonEmitVec8(out, data, stride, count); break; - case 3: radeonEmitVec12(out, data, stride, count); break; - case 4: radeonEmitVec16(out, data, stride, count); break; - default: - assert(0); - break; - } -} - - -void radeon_print_state_atom( struct radeon_state_atom *state ) -{ - int i; - - fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); - - if (RADEON_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < state->cmd_size ; i++) - fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); - -} - -/* textures */ -/** - * Allocate an empty texture image object. - */ -struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx) -{ - return CALLOC(sizeof(radeon_texture_image)); -} - -/** - * Free memory associated with this texture image. - */ -void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) -{ - radeon_texture_image* image = get_radeon_texture_image(timage); - - if (image->mt) { - radeon_miptree_unreference(image->mt); - image->mt = 0; - assert(!image->base.Data); - } else { - _mesa_free_texture_image_data(ctx, timage); - } - if (image->bo) { - radeon_bo_unref(image->bo); - image->bo = NULL; - } - if (timage->Data) { - _mesa_free_texmemory(timage->Data); - timage->Data = NULL; - } -} - -/* Set Data pointer and additional data for mapped texture image */ -static void teximage_set_map_data(radeon_texture_image *image) -{ - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - - image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; - image->base.RowStride = lvl->rowstride / image->mt->bpp; -} - - -/** - * Map a single texture image for glTexImage and friends. - */ -void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable) -{ - if (image->mt) { - assert(!image->base.Data); - - radeon_bo_map(image->mt->bo, write_enable); - teximage_set_map_data(image); - } -} - - -void radeon_teximage_unmap(radeon_texture_image *image) -{ - if (image->mt) { - assert(image->base.Data); - - image->base.Data = 0; - radeon_bo_unmap(image->mt->bo); - } -} - -/** - * Map a validated texture for reading during software rendering. - */ -void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - int face, level; - - /* for r100 3D sw fallbacks don't have mt */ - if (!t->mt) - return; - - radeon_bo_map(t->mt->bo, GL_FALSE); - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) - teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level])); - } -} - -void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - int face, level; - - /* for r100 3D sw fallbacks don't have mt */ - if (!t->mt) - return; - - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) - texObj->Image[face][level]->Data = 0; - } - radeon_bo_unmap(t->mt->bo); -} - -GLuint radeon_face_for_target(GLenum target) -{ - switch (target) { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - default: - return 0; - } -} - -/** - * Wraps Mesa's implementation to ensure that the base level image is mapped. - * - * This relies on internal details of _mesa_generate_mipmap, in particular - * the fact that the memory for recreated texture images is always freed. - */ -static void radeon_generate_mipmap(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; - int i, face; - - - _mesa_generate_mipmap(ctx, target, texObj); - - for (face = 0; face < nr_faces; face++) { - for (i = texObj->BaseLevel + 1; i < texObj->MaxLevel; i++) { - radeon_texture_image *image; - - image = get_radeon_texture_image(texObj->Image[face][i]); - - if (image == NULL) - break; - - image->mtlevel = i; - image->mtface = face; - - radeon_miptree_unreference(image->mt); - image->mt = NULL; - } - } - -} - -void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) -{ - GLuint face = radeon_face_for_target(target); - radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); - - radeon_teximage_map(baseimage, GL_FALSE); - radeon_generate_mipmap(ctx, target, texObj); - radeon_teximage_unmap(baseimage); -} - - -/* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, - GLenum srcFormat, - GLenum srcType) -{ - const GLuint ui = 1; - const GLubyte littleEndian = *((const GLubyte *)&ui); - - /* r100 can only do this */ - if (IS_R100_CLASS(rmesa->radeonScreen)) - return _dri_texformat_argb8888; - - if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { - return &_mesa_texformat_rgba8888; - } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { - return &_mesa_texformat_rgba8888_rev; - } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8)) { - return &_mesa_texformat_argb8888_rev; - } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { - return &_mesa_texformat_argb8888; - } else - return _dri_texformat_argb8888; -} - -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - const GLboolean do32bpt = - (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32); - const GLboolean force16bpt = - (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16); - (void)format; - -#if 0 - fprintf(stderr, "InternalFormat=%s(%d) type=%s format=%s\n", - _mesa_lookup_enum_by_nr(internalFormat), internalFormat, - _mesa_lookup_enum_by_nr(type), _mesa_lookup_enum_by_nr(format)); - fprintf(stderr, "do32bpt=%d force16bpt=%d\n", do32bpt, force16bpt); -#endif - - switch (internalFormat) { - case 4: - case GL_RGBA: - case GL_COMPRESSED_RGBA: - switch (type) { - case GL_UNSIGNED_INT_10_10_10_2: - case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? _dri_texformat_argb8888 : - _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - default: - return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type) : - _dri_texformat_argb4444; - } - - case 3: - case GL_RGB: - case GL_COMPRESSED_RGB: - switch (type) { - case GL_UNSIGNED_SHORT_4_4_4_4: - case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return _dri_texformat_argb4444; - case GL_UNSIGNED_SHORT_5_5_5_1: - case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return _dri_texformat_argb1555; - case GL_UNSIGNED_SHORT_5_6_5: - case GL_UNSIGNED_SHORT_5_6_5_REV: - return _dri_texformat_rgb565; - default: - return do32bpt ? _dri_texformat_argb8888 : - _dri_texformat_rgb565; - } - - case GL_RGBA8: - case GL_RGB10_A2: - case GL_RGBA12: - case GL_RGBA16: - return !force16bpt ? - radeonChoose8888TexFormat(rmesa, format,type) : - _dri_texformat_argb4444; - - case GL_RGBA4: - case GL_RGBA2: - return _dri_texformat_argb4444; - - case GL_RGB5_A1: - return _dri_texformat_argb1555; - - case GL_RGB8: - case GL_RGB10: - case GL_RGB12: - case GL_RGB16: - return !force16bpt ? _dri_texformat_argb8888 : - _dri_texformat_rgb565; - - case GL_RGB5: - case GL_RGB4: - case GL_R3_G3_B2: - return _dri_texformat_rgb565; - - case GL_ALPHA: - case GL_ALPHA4: - case GL_ALPHA8: - case GL_ALPHA12: - case GL_ALPHA16: - case GL_COMPRESSED_ALPHA: - return _dri_texformat_a8; - - case 1: - case GL_LUMINANCE: - case GL_LUMINANCE4: - case GL_LUMINANCE8: - case GL_LUMINANCE12: - case GL_LUMINANCE16: - case GL_COMPRESSED_LUMINANCE: - return _dri_texformat_l8; - - case 2: - case GL_LUMINANCE_ALPHA: - case GL_LUMINANCE4_ALPHA4: - case GL_LUMINANCE6_ALPHA2: - case GL_LUMINANCE8_ALPHA8: - case GL_LUMINANCE12_ALPHA4: - case GL_LUMINANCE12_ALPHA12: - case GL_LUMINANCE16_ALPHA16: - case GL_COMPRESSED_LUMINANCE_ALPHA: - return _dri_texformat_al88; - - case GL_INTENSITY: - case GL_INTENSITY4: - case GL_INTENSITY8: - case GL_INTENSITY12: - case GL_INTENSITY16: - case GL_COMPRESSED_INTENSITY: - return _dri_texformat_i8; - - case GL_YCBCR_MESA: - if (type == GL_UNSIGNED_SHORT_8_8_APPLE || - type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; - else - return &_mesa_texformat_ycbcr_rev; - - case GL_RGB_S3TC: - case GL_RGB4_S3TC: - case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; - - case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; - - case GL_RGBA_S3TC: - case GL_RGBA4_S3TC: - case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; - - case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; - - case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; - case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; - case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; - case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; - case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; - case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; - case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; - case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; - case GL_RGB16F_ARB: - return &_mesa_texformat_rgba_float16; - case GL_RGB32F_ARB: - return &_mesa_texformat_rgba_float32; - case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; - case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; - - case GL_DEPTH_COMPONENT: - case GL_DEPTH_COMPONENT16: - case GL_DEPTH_COMPONENT24: - case GL_DEPTH_COMPONENT32: -#if 0 - switch (type) { - case GL_UNSIGNED_BYTE: - case GL_UNSIGNED_SHORT: - return &_mesa_texformat_z16; - case GL_UNSIGNED_INT: - return &_mesa_texformat_z32; - case GL_UNSIGNED_INT_24_8_EXT: - default: - return &_mesa_texformat_z24_s8; - } -#else - return &_mesa_texformat_z16; -#endif - - default: - _mesa_problem(ctx, - "unexpected internalFormat 0x%x in r300ChooseTextureFormat", - (int)internalFormat); - return NULL; - } - - return NULL; /* never get here */ -} - -/** - * All glTexImage calls go through this function. - */ -static void radeon_teximage( - GLcontext *ctx, int dims, - GLint face, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLsizei imageSize, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage, - int compressed) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - radeonTexObj* t = radeon_tex_obj(texObj); - radeon_texture_image* image = get_radeon_texture_image(texImage); - - radeon_firevertices(rmesa); - - t->validated = GL_FALSE; - - /* Choose and fill in the texture format for this image */ - texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type); - _mesa_set_fetch_functions(texImage, dims); - - if (texImage->TexFormat->TexelBytes == 0) { - texImage->IsCompressed = GL_TRUE; - texImage->CompressedSize = - ctx->Driver.CompressedTextureSize(ctx, texImage->Width, - texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); - } else { - texImage->IsCompressed = GL_FALSE; - texImage->CompressedSize = 0; - } - - /* Allocate memory for image */ - radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ - - if (!t->mt) - radeon_try_alloc_miptree(rmesa, t, texImage, face, level); - if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { - image->mt = t->mt; - image->mtlevel = level - t->mt->firstLevel; - image->mtface = face; - radeon_miptree_reference(t->mt); - } else { - int size; - if (texImage->IsCompressed) { - size = texImage->CompressedSize; - } else { - size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; - } - texImage->Data = _mesa_alloc_texmemory(size); - } - - /* Upload texture image; note that the spec allows pixels to be NULL */ - if (compressed) { - pixels = _mesa_validate_pbo_compressed_teximage( - ctx, imageSize, pixels, packing, "glCompressedTexImage"); - } else { - pixels = _mesa_validate_pbo_teximage( - ctx, dims, width, height, depth, - format, type, pixels, packing, "glTexImage"); - } - - if (pixels) { - radeon_teximage_map(image, GL_TRUE); - - if (compressed) { - memcpy(texImage->Data, pixels, imageSize); - } else { - GLuint dstRowStride; - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; - } - if (!texImage->TexFormat->StoreImage(ctx, dims, - texImage->_BaseFormat, - texImage->TexFormat, - texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */ - dstRowStride, - texImage->ImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); - } - - } - - /* SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - radeon_generate_mipmap(ctx, texObj->Target, texObj); - } - - if (pixels) - radeon_teximage_unmap(image); - - _mesa_unmap_teximage_pbo(ctx, packing); - - -} - -void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - radeon_teximage(ctx, 1, 0, level, internalFormat, width, 1, 1, - 0, format, type, pixels, packing, texObj, texImage, 0); -} - -void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) - -{ - GLuint face = radeon_face_for_target(target); - - radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, - 0, format, type, pixels, packing, texObj, texImage, 0); -} - -void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - GLuint face = radeon_face_for_target(target); - - radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, - imageSize, 0, 0, data, 0, texObj, texImage, 1); -} - -void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - radeon_teximage(ctx, 3, 0, level, internalFormat, width, height, depth, - 0, format, type, pixels, packing, texObj, texImage, 0); -} - -/** - * Update a subregion of the given texture image. - */ -static void radeon_texsubimage(GLcontext* ctx, int dims, int level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage, - int compressed) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - radeonTexObj* t = radeon_tex_obj(texObj); - radeon_texture_image* image = get_radeon_texture_image(texImage); - - radeon_firevertices(rmesa); - - t->validated = GL_FALSE; - pixels = _mesa_validate_pbo_teximage(ctx, dims, - width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); - - if (pixels) { - GLint dstRowStride; - radeon_teximage_map(image, GL_TRUE); - - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes; - } - - if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, - texImage->TexFormat, texImage->Data, - xoffset, yoffset, zoffset, - dstRowStride, - texImage->ImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); - - - } - - /* GL_SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - radeon_generate_mipmap(ctx, texObj->Target, texObj); - } - radeon_teximage_unmap(image); - - _mesa_unmap_teximage_pbo(ctx, packing); - - -} - -void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - radeon_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, - format, type, pixels, packing, texObj, texImage, 0); -} - -void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, - 1, format, type, pixels, packing, texObj, texImage, - 0); -} - -void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint xoffset, - GLint yoffset, GLsizei width, - GLsizei height, GLenum format, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, - format, 0, data, 0, texObj, texImage, 1); -} - - -void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - radeon_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, - format, type, pixels, packing, texObj, texImage, 0); -} - -static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, - GLuint numrows, GLuint rowsize) -{ - assert(rowsize <= dststride); - assert(rowsize <= srcstride); - - if (rowsize == srcstride && rowsize == dststride) { - memcpy(dst, src, numrows*rowsize); - } else { - GLuint i; - for(i = 0; i < numrows; ++i) { - memcpy(dst, src, rowsize); - dst += dststride; - src += srcstride; - } - } -} - - -/** - * Ensure that the given image is stored in the given miptree from now on. - */ -static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level) -{ - radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; - unsigned char *dest; - - assert(image->mt != mt); - assert(dstlvl->width == image->base.Width); - assert(dstlvl->height == image->base.Height); - assert(dstlvl->depth == image->base.Depth); - - - radeon_bo_map(mt->bo, GL_TRUE); - dest = mt->bo->ptr + dstlvl->faces[face].offset; - - if (image->mt) { - /* Format etc. should match, so we really just need a memcpy(). - * In fact, that memcpy() could be done by the hardware in many - * cases, provided that we have a proper memory manager. - */ - radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; - - assert(srclvl->size == dstlvl->size); - assert(srclvl->rowstride == dstlvl->rowstride); - - radeon_bo_map(image->mt->bo, GL_FALSE); - - memcpy(dest, - image->mt->bo->ptr + srclvl->faces[face].offset, - dstlvl->size); - radeon_bo_unmap(image->mt->bo); - - radeon_miptree_unreference(image->mt); - } else { - uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; - -// if (mt->tilebits) -// WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); - - copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, - image->base.Height * image->base.Depth, srcrowstride); - - _mesa_free_texmemory(image->base.Data); - image->base.Data = 0; - } - - radeon_bo_unmap(mt->bo); - - image->mt = mt; - image->mtface = face; - image->mtlevel = level; - radeon_miptree_reference(image->mt); -} - -int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - radeonTexObj *t = radeon_tex_obj(texObj); - radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]); - int face, level; - - if (t->validated || t->image_override) - return GL_TRUE; - - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj); - - if (baseimage->base.Border > 0) - return GL_FALSE; - - /* Ensure a matching miptree exists. - * - * Differing mipmap trees can result when the app uses TexImage to - * change texture dimensions. - * - * Prefer to use base image's miptree if it - * exists, since that most likely contains more valid data (remember - * that the base level is usually significantly larger than the rest - * of the miptree, so cubemaps are the only possible exception). - */ - if (baseimage->mt && - baseimage->mt != t->mt && - radeon_miptree_matches_texture(baseimage->mt, &t->base)) { - radeon_miptree_unreference(t->mt); - t->mt = baseimage->mt; - radeon_miptree_reference(t->mt); - } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - } - - if (!t->mt) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, " Allocate new miptree\n"); - radeon_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel); - if (!t->mt) { - _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree"); - return GL_FALSE; - } - } - - /* Ensure all images are stored in the single main miptree */ - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { - radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, " face %i, level %i... %p vs %p ", face, level, t->mt, image->mt); - if (t->mt == image->mt) { - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "OK\n"); - continue; - } - - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "migrating\n"); - migrate_image_to_miptree(t->mt, image, face, level); - } - } - - return GL_TRUE; -} - - -GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr; - const __DRIdrawablePrivate *dPriv = rrb->dPriv; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - GLint nmacroblkpl; - GLint nmicroblkpl; - - x += dPriv->x; - y += dPriv->y; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - nmacroblkpl = rrb->pitch >> 5; - offset += ((y >> 4) * nmacroblkpl) << 11; - offset += ((y & 15) >> 1) << 8; - offset += (y & 1) << 4; - offset += (x >> 5) << 11; - offset += ((x & 31) >> 2) << 5; - offset += (x & 3) << 2; - } else { - nmacroblkpl = rrb->pitch >> 6; - offset += ((y >> 3) * nmacroblkpl) << 11; - offset += (y & 7) << 8; - offset += (x >> 6) << 11; - offset += ((x & 63) >> 3) << 5; - offset += (x & 7) << 2; - } - } else { - nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; - offset += (y * nmicroblkpl) << 5; - offset += (x >> 3) << 5; - offset += (x & 7) << 2; - } - } - return &ptr[offset]; -} - -GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr; - const __DRIdrawablePrivate *dPriv = rrb->dPriv; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - GLint nmacroblkpl; - GLint nmicroblkpl; - - x += dPriv->x; - y += dPriv->y; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - nmacroblkpl = rrb->pitch >> 6; - offset += ((y >> 4) * nmacroblkpl) << 11; - offset += ((y & 15) >> 1) << 8; - offset += (y & 1) << 4; - offset += (x >> 6) << 11; - offset += ((x & 63) >> 3) << 5; - offset += (x & 7) << 1; - } else { - nmacroblkpl = rrb->pitch >> 7; - offset += ((y >> 3) * nmacroblkpl) << 11; - offset += (y & 7) << 8; - offset += (x >> 7) << 11; - offset += ((x & 127) >> 4) << 5; - offset += (x & 15) << 2; - } - } else { - nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; - offset += (y * nmicroblkpl) << 5; - offset += (x >> 4) << 5; - offset += (x & 15) << 2; - } - } - return &ptr[offset]; -} - -GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, - GLint x, GLint y) -{ - GLubyte *ptr = rrb->bo->ptr; - const __DRIdrawablePrivate *dPriv = rrb->dPriv; - uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; - GLint offset; - GLint microblkxs; - GLint macroblkxs; - GLint nmacroblkpl; - GLint nmicroblkpl; - - x += dPriv->x; - y += dPriv->y; - - if (rrb->has_surface || !(rrb->bo->flags & mask)) { - offset = x * rrb->cpp + y * rrb->pitch; - } else { - offset = 0; - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { - microblkxs = 16 / rrb->cpp; - macroblkxs = 128 / rrb->cpp; - nmacroblkpl = rrb->pitch / macroblkxs; - offset += ((y >> 4) * nmacroblkpl) << 11; - offset += ((y & 15) >> 1) << 8; - offset += (y & 1) << 4; - offset += (x / macroblkxs) << 11; - offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; - offset += (x & (microblkxs - 1)) * rrb->cpp; - } else { - microblkxs = 32 / rrb->cpp; - macroblkxs = 256 / rrb->cpp; - nmacroblkpl = rrb->pitch / macroblkxs; - offset += ((y >> 3) * nmacroblkpl) << 11; - offset += (y & 7) << 8; - offset += (x / macroblkxs) << 11; - offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; - offset += (x & (microblkxs - 1)) * rrb->cpp; - } - } else { - microblkxs = 32 / rrb->cpp; - nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; - offset += (y * nmicroblkpl) << 5; - offset += (x / microblkxs) << 5; - offset += (x & (microblkxs - 1)) * rrb->cpp; - } - } - return &ptr[offset]; -} - - -static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) -{ - struct radeon_renderbuffer *rrb = (void*)rb; - int r; - - if (rrb->bo) { - r = radeon_bo_map(rrb->bo, write); - if (r) { - fprintf(stderr, "(%s) error(%d) mapping buffer.\n", - __FUNCTION__, r); - } - } -} - -static void unmap_buffer(struct gl_renderbuffer *rb) -{ - struct radeon_renderbuffer *rrb = (void*)rb; - - if (rrb->bo) { - radeon_bo_unmap(rrb->bo); - } -} - -void radeonSpanRenderStart(GLcontext * ctx) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - int i; - - radeon_firevertices(rmesa); - - for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) - ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); - } - - /* color draw buffers */ - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { - map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); - } - - map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); - - if (ctx->DrawBuffer->_DepthBuffer) { - map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); - } - if (ctx->DrawBuffer->_StencilBuffer) - map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); - - /* The locking and wait for idle should really only be needed in classic mode. - * In a future memory manager based implementation, this should become - * unnecessary due to the fact that mapping our buffers, textures, etc. - * should implicitly wait for any previous rendering commands that must - * be waited on. */ - LOCK_HARDWARE(rmesa); - radeonWaitForIdleLocked(rmesa); -} - -void radeonSpanRenderFinish(GLcontext * ctx) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - int i; - _swrast_flush(ctx); - UNLOCK_HARDWARE(rmesa); - - for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) - ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); - } - - /* color draw buffers */ - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) - unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); - - unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); - - if (ctx->DrawBuffer->_DepthBuffer) - unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); - if (ctx->DrawBuffer->_StencilBuffer) - unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); -} - -void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) -{ - struct radeon_cs_space_check bos[1]; - int flushed = 0, ret; - - size = MAX2(size, MAX_DMA_BUF_SZ * 16); - - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) { - rmesa->dma.flush(rmesa->glCtx); - } - - if (rmesa->dma.nr_released_bufs > 4) { - rcommonFlushCmdBuf(rmesa, __FUNCTION__); - rmesa->dma.nr_released_bufs = 0; - } - - if (rmesa->dma.current) { - radeon_bo_unmap(rmesa->dma.current); - radeon_bo_unref(rmesa->dma.current); - rmesa->dma.current = 0; - } - -again_alloc: - rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom, - 0, size, 4, RADEON_GEM_DOMAIN_GTT, - 0); - - if (!rmesa->dma.current) { - rcommonFlushCmdBuf(rmesa, __FUNCTION__); - rmesa->dma.nr_released_bufs = 0; - goto again_alloc; - } - - rmesa->dma.current_used = 0; - rmesa->dma.current_vertexptr = 0; - - bos[0].bo = rmesa->dma.current; - bos[0].read_domains = RADEON_GEM_DOMAIN_GTT; - bos[0].write_domain =0 ; - bos[0].new_accounted = 0; - - ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1); - if (ret == RADEON_CS_SPACE_OP_TO_BIG) { - fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen"); - assert(0); - } else if (ret == RADEON_CS_SPACE_FLUSH) { - rcommonFlushCmdBuf(rmesa, __FUNCTION__); - if (flushed) { - fprintf(stderr,"flushed but still no space\n"); - assert(0); - } - flushed = 1; - goto again_alloc; - } - radeon_bo_map(rmesa->dma.current, 1); -} - -/* Allocates a region from rmesa->dma.current. If there isn't enough - * space in current, grab a new buffer (and discard what was left of current) - */ -void radeonAllocDmaRegion(radeonContextPtr rmesa, - struct radeon_bo **pbo, int *poffset, - int bytes, int alignment) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush(rmesa->glCtx); - - assert(rmesa->dma.current_used == rmesa->dma.current_vertexptr); - - alignment--; - rmesa->dma.current_used = (rmesa->dma.current_used + alignment) & ~alignment; - - if (!rmesa->dma.current || rmesa->dma.current_used + bytes > rmesa->dma.current->size) - radeonRefillCurrentDmaRegion(rmesa, (bytes + 15) & ~15); - - *poffset = rmesa->dma.current_used; - *pbo = rmesa->dma.current; - radeon_bo_ref(*pbo); - - /* Always align to at least 16 bytes */ - rmesa->dma.current_used = (rmesa->dma.current_used + bytes + 15) & ~15; - rmesa->dma.current_vertexptr = rmesa->dma.current_used; - - assert(rmesa->dma.current_used <= rmesa->dma.current->size); -} - -void radeonReleaseDmaRegion(radeonContextPtr rmesa) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %p\n", __FUNCTION__, rmesa->dma.current); - if (rmesa->dma.current) { - rmesa->dma.nr_released_bufs++; - radeon_bo_unmap(rmesa->dma.current); - radeon_bo_unref(rmesa->dma.current); - } - rmesa->dma.current = NULL; -} - - -/* Flush vertices in the current dma region. - */ -void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - struct radeon_dma *dma = &rmesa->dma; - - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - dma->flush = NULL; - - if (dma->current) { - GLuint current_offset = dma->current_used; - - assert (dma->current_used + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - dma->current_vertexptr); - - if (dma->current_used != dma->current_vertexptr) { - dma->current_used = dma->current_vertexptr; - - rmesa->vtbl.swtcl_flush(ctx, current_offset); - } - rmesa->swtcl.numverts = 0; - } -} -/* Alloc space in the current dma region. - */ -void * -rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) -{ - GLuint bytes = vsize * nverts; - void *head; - - if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) { - radeonRefillCurrentDmaRegion(rmesa, bytes); - } - - if (!rmesa->dma.flush) { - rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = rcommon_flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->dma.flush == rcommon_flush_last_swtcl_prim ); - ASSERT( rmesa->dma.current_used + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current_vertexptr ); - -// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, -// rmesa->radeon.dma.current_vertexptr); - head = (rmesa->dma.current->ptr + rmesa->dma.current_vertexptr); - rmesa->dma.current_vertexptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; -} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h deleted file mode 100644 index ebf287a0316..00000000000 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ /dev/null @@ -1,166 +0,0 @@ -#ifndef COMMON_MISC_H -#define COMMON_MISC_H - -#include "common_context.h" -#include "radeon_buffer.h" -void radeonRecalcScissorRects(radeonContextPtr radeon); -void radeonSetCliprects(radeonContextPtr radeon); -void radeonUpdateScissor( GLcontext *ctx ); -void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h); - -void radeonWaitForIdleLocked(radeonContextPtr radeon); -extern uint32_t radeonGetAge(radeonContextPtr radeon); -void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, - const drm_clip_rect_t *rect); -void radeonPageFlip( __DRIdrawablePrivate *dPriv ); -void radeon_common_finish(GLcontext * ctx); -void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); -void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h ); - -void radeonUpdatePageFlipping(radeonContextPtr rmesa); - -GLboolean radeonInitContext(radeonContextPtr radeon, - struct dd_function_table* functions, - const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate); - -void radeonCleanupContext(radeonContextPtr radeon); -GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); -void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); -GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); - -void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count); -void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count); - -void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, - GLvoid * data, int size, int stride, int count); -void radeon_print_state_atom( struct radeon_state_atom *state ); - -struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx); -void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage); - -void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable); -void radeon_teximage_unmap(radeon_texture_image *image); -void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj); -void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); -void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); -int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); -GLuint radeon_face_for_target(GLenum target); -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type); - -void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); -void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); -void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); -void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); -void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); -void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); -void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint xoffset, - GLint yoffset, GLsizei width, - GLsizei height, GLenum format, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); - -void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage); - -void radeonSpanRenderStart(GLcontext * ctx); -void radeonSpanRenderFinish(GLcontext * ctx); -GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, - GLint x, GLint y); -GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, - GLint x, GLint y); -GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, - GLint x, GLint y); -void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size); -void radeonAllocDmaRegion(radeonContextPtr rmesa, - struct radeon_bo **pbo, int *poffset, - int bytes, int alignment); -void radeonReleaseDmaRegion(radeonContextPtr rmesa); - -void rcommon_flush_last_swtcl_prim(GLcontext *ctx); - -void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); - -void radeonFlush(GLcontext *ctx); -void radeonFinish(GLcontext * ctx); -void radeonEmitState(radeonContextPtr radeon); - -static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) -{ - struct radeon_renderbuffer *rrb; - rrb = rmesa->state.depth.rrb; - if (!rrb) - return NULL; - - return rrb; -} - -static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) -{ - struct radeon_renderbuffer *rrb; - GLframebuffer *fb = rmesa->dri.drawable->driverPrivate; - - rrb = rmesa->state.color.rrb; - if (rmesa->radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } - if (!rrb) - return NULL; - return rrb; -} - - -#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index a716f1059b9..b7658353af0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -47,7 +47,7 @@ #include "radeon_drm.h" #include "radeon_bo.h" #include "radeon_bo_legacy.h" -#include "common_context.h" +#include "radeon_common.h" struct bo_legacy { struct radeon_bo base; diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h new file mode 100644 index 00000000000..5526934209e --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -0,0 +1,143 @@ +#ifndef COMMON_CMDBUF_H +#define COMMON_CMDBUF_H + +#include "radeon_cs.h" + +void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); +int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); +int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); +void rcommonInitCmdBuf(radeonContextPtr rmesa); +void rcommonDestroyCmdBuf(radeonContextPtr rmesa); + +void rcommonBeginBatch(radeonContextPtr rmesa, + int n, + int dostate, + const char *file, + const char *function, + int line); + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + +#define CP_PACKET2 (2 << 30) +#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) +#define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) + +/** + * Every function writing to the command buffer needs to declare this + * to get the necessary local variables. + */ +#define BATCH_LOCALS(rmesa) \ + const radeonContextPtr b_l_rmesa = rmesa + +/** + * Prepare writing n dwords to the command buffer, + * including producing any necessary state emits on buffer wraparound. + */ +#define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__) + +/** + * Same as BEGIN_BATCH, but do not cause automatic state emits. + */ +#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__) + +/** + * Write one dword to the command buffer. + */ +#define OUT_BATCH(data) \ + do { \ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ + } while(0) + +/** + * Write a relocated dword to the command buffer. + */ +#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ + do { \ + if (0 && offset) { \ + fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ + __FILE__, __FUNCTION__, __LINE__, offset); \ + } \ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ + radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ + bo, rd, wd, flags); \ + if (!b_l_rmesa->radeonScreen->kernel_mm) \ + b_l_rmesa->cmdbuf.cs->section_cdw += 2; \ + } while(0) + + +/** + * Write n dwords from ptr to the command buffer. + */ +#define OUT_BATCH_TABLE(ptr,n) \ + do { \ + int _i; \ + for (_i=0; _i < n; _i++) {\ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\ + }\ + } while(0) + +/** + * Finish writing dwords to the command buffer. + * The number of (direct or indirect) OUT_BATCH calls between the previous + * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. + */ +#define END_BATCH() \ + do { \ + radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\ + } while(0) + +/** + * After the last END_BATCH() of rendering, this indicates that flushing + * the command buffer now is okay. + */ +#define COMMIT_BATCH() \ + do { \ + } while(0) + + +/** Single register write to command buffer; requires 2 dwords. */ +#define OUT_BATCH_REGVAL(reg, val) \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ + OUT_BATCH((val)) + +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define OUT_BATCH_REGSEQ(reg, count) \ + OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))); + +/** Write a 32 bit float to the ring; requires 1 dword. */ +#define OUT_BATCH_FLOAT32(f) \ + OUT_BATCH(radeonPackFloat32((f))); + + +/* Fire the buffered vertices no matter what. + */ +static INLINE void radeon_firevertices(radeonContextPtr radeon) +{ + if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) + radeonFlush(radeon->glCtx); +} + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c new file mode 100644 index 00000000000..87b6dac40bc --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -0,0 +1,843 @@ +/************************************************************************** + +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Keith Whitwell + */ + +/* + - Scissor implementation + - buffer swap/copy ioctls + - finish/flush + - state emission + - cmdbuffer management +*/ + +#include +#include "main/glheader.h" +#include "main/imports.h" +#include "main/context.h" +#include "main/api_arrayelt.h" +#include "main/enums.h" +#include "main/colormac.h" +#include "main/light.h" +#include "main/framebuffer.h" +#include "main/simple_list.h" + +#include "swrast/swrast.h" +#include "vbo/vbo.h" +#include "tnl/tnl.h" +#include "tnl/t_pipeline.h" +#include "swrast_setup/swrast_setup.h" + +#include "dri_util.h" +#include "drirenderbuffer.h" +#include "vblank.h" + +#include "radeon_common.h" +#include "radeon_common.h" +#include "radeon_bo.h" +#include "radeon_cs.h" +#include "radeon_bo_legacy.h" +#include "radeon_cs_legacy.h" +#include "radeon_bo_gem.h" +#include "radeon_cs_gem.h" +#include "radeon_drm.h" +#include "radeon_mipmap_tree.h" + +#define DEBUG_CMDBUF 0 + +/* ============================================================= + * Scissoring + */ + +static GLboolean intersect_rect(drm_clip_rect_t * out, + drm_clip_rect_t * a, drm_clip_rect_t * b) +{ + *out = *a; + if (b->x1 > out->x1) + out->x1 = b->x1; + if (b->y1 > out->y1) + out->y1 = b->y1; + if (b->x2 < out->x2) + out->x2 = b->x2; + if (b->y2 < out->y2) + out->y2 = b->y2; + if (out->x1 >= out->x2) + return GL_FALSE; + if (out->y1 >= out->y2) + return GL_FALSE; + return GL_TRUE; +} + +void radeonRecalcScissorRects(radeonContextPtr radeon) +{ + drm_clip_rect_t *out; + int i; + + /* Grow cliprect store? + */ + if (radeon->state.scissor.numAllocedClipRects < radeon->numClipRects) { + while (radeon->state.scissor.numAllocedClipRects < + radeon->numClipRects) { + radeon->state.scissor.numAllocedClipRects += 1; /* zero case */ + radeon->state.scissor.numAllocedClipRects *= 2; + } + + if (radeon->state.scissor.pClipRects) + FREE(radeon->state.scissor.pClipRects); + + radeon->state.scissor.pClipRects = + MALLOC(radeon->state.scissor.numAllocedClipRects * + sizeof(drm_clip_rect_t)); + + if (radeon->state.scissor.pClipRects == NULL) { + radeon->state.scissor.numAllocedClipRects = 0; + return; + } + } + + out = radeon->state.scissor.pClipRects; + radeon->state.scissor.numClipRects = 0; + + for (i = 0; i < radeon->numClipRects; i++) { + if (intersect_rect(out, + &radeon->pClipRects[i], + &radeon->state.scissor.rect)) { + radeon->state.scissor.numClipRects++; + out++; + } + } +} + +/** + * Update cliprects and scissors. + */ +void radeonSetCliprects(radeonContextPtr radeon) +{ + __DRIdrawablePrivate *const drawable = radeon->dri.drawable; + __DRIdrawablePrivate *const readable = radeon->dri.readable; + GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; + GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; + + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { + /* Can't ignore 2d windows if we are page flipping. */ + if (drawable->numBackClipRects == 0 || radeon->doPageFlip || + radeon->sarea->pfCurrentPage == 1) { + radeon->numClipRects = drawable->numClipRects; + radeon->pClipRects = drawable->pClipRects; + } else { + radeon->numClipRects = drawable->numBackClipRects; + radeon->pClipRects = drawable->pBackClipRects; + } + } else { + /* front buffer (or none, or multiple buffers */ + radeon->numClipRects = drawable->numClipRects; + radeon->pClipRects = drawable->pClipRects; + } + } + + if ((draw_fb->Width != drawable->w) || + (draw_fb->Height != drawable->h)) { + _mesa_resize_framebuffer(radeon->glCtx, draw_fb, + drawable->w, drawable->h); + draw_fb->Initialized = GL_TRUE; + } + + if (drawable != readable) { + if ((read_fb->Width != readable->w) || + (read_fb->Height != readable->h)) { + _mesa_resize_framebuffer(radeon->glCtx, read_fb, + readable->w, readable->h); + read_fb->Initialized = GL_TRUE; + } + } + + if (radeon->state.scissor.enabled) + radeonRecalcScissorRects(radeon); + + radeon->lastStamp = drawable->lastStamp; +} + +void radeonUpdateScissor( GLcontext *ctx ) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + + if ( rmesa->dri.drawable ) { + __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; + + int x = ctx->Scissor.X; + int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; + int w = ctx->Scissor.X + ctx->Scissor.Width - 1; + int h = dPriv->h - ctx->Scissor.Y - 1; + + rmesa->state.scissor.rect.x1 = x + dPriv->x; + rmesa->state.scissor.rect.y1 = y + dPriv->y; + rmesa->state.scissor.rect.x2 = w + dPriv->x + 1; + rmesa->state.scissor.rect.y2 = h + dPriv->y + 1; + + radeonRecalcScissorRects( rmesa ); + } +} + +/* ============================================================= + * Scissoring + */ + +void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + if (ctx->Scissor.Enabled) { + /* We don't pipeline cliprect changes */ + radeon_firevertices(radeon); + radeonUpdateScissor(ctx); + } +} + + +/* ================================================================ + * SwapBuffers with client-side throttling + */ + +static uint32_t radeonGetLastFrame(radeonContextPtr radeon) +{ + drm_radeon_getparam_t gp; + int ret; + uint32_t frame; + + gp.param = RADEON_PARAM_LAST_FRAME; + gp.value = (int *)&frame; + ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, + ret); + exit(1); + } + + return frame; +} + +uint32_t radeonGetAge(radeonContextPtr radeon) +{ + drm_radeon_getparam_t gp; + int ret; + uint32_t age; + + gp.param = RADEON_PARAM_LAST_CLEAR; + gp.value = (int *)&age; + ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_GETPARAM, + &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, + ret); + exit(1); + } + + return age; +} + +static void radeonEmitIrqLocked(radeonContextPtr radeon) +{ + drm_radeon_irq_emit_t ie; + int ret; + + ie.irq_seq = &radeon->iw.irq_seq; + ret = drmCommandWriteRead(radeon->dri.fd, DRM_RADEON_IRQ_EMIT, + &ie, sizeof(ie)); + if (ret) { + fprintf(stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, + ret); + exit(1); + } +} + +static void radeonWaitIrq(radeonContextPtr radeon) +{ + int ret; + + do { + ret = drmCommandWrite(radeon->dri.fd, DRM_RADEON_IRQ_WAIT, + &radeon->iw, sizeof(radeon->iw)); + } while (ret && (errno == EINTR || errno == EBUSY)); + + if (ret) { + fprintf(stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, + ret); + exit(1); + } +} + +static void radeonWaitForFrameCompletion(radeonContextPtr radeon) +{ + drm_radeon_sarea_t *sarea = radeon->sarea; + + if (radeon->do_irqs) { + if (radeonGetLastFrame(radeon) < sarea->last_frame) { + if (!radeon->irqsEmitted) { + while (radeonGetLastFrame(radeon) < + sarea->last_frame) ; + } else { + UNLOCK_HARDWARE(radeon); + radeonWaitIrq(radeon); + LOCK_HARDWARE(radeon); + } + radeon->irqsEmitted = 10; + } + + if (radeon->irqsEmitted) { + radeonEmitIrqLocked(radeon); + radeon->irqsEmitted--; + } + } else { + while (radeonGetLastFrame(radeon) < sarea->last_frame) { + UNLOCK_HARDWARE(radeon); + if (radeon->do_usleeps) + DO_USLEEP(1); + LOCK_HARDWARE(radeon); + } + } +} + +/* wait for idle */ +void radeonWaitForIdleLocked(radeonContextPtr radeon) +{ + int ret; + int i = 0; + + do { + ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_CP_IDLE); + if (ret) + DO_USLEEP(1); + } while (ret && ++i < 100); + + if (ret < 0) { + UNLOCK_HARDWARE(radeon); + fprintf(stderr, "Error: R300 timed out... exiting\n"); + exit(-1); + } +} + +static void radeonWaitForIdle(radeonContextPtr radeon) +{ + LOCK_HARDWARE(radeon); + radeonWaitForIdleLocked(radeon); + UNLOCK_HARDWARE(radeon); +} + + +/* Copy the back color buffer to the front color buffer. + */ +void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, + const drm_clip_rect_t *rect) +{ + radeonContextPtr rmesa; + GLint nbox, i, ret; + GLboolean missed_target; + int64_t ust; + __DRIscreenPrivate *psp; + + assert(dPriv); + assert(dPriv->driContextPriv); + assert(dPriv->driContextPriv->driverPrivate); + + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); + } + + radeon_firevertices(rmesa); + LOCK_HARDWARE( rmesa ); + + /* Throttle the frame rate -- only allow one pending swap buffers + * request at a time. + */ + radeonWaitForFrameCompletion( rmesa ); + if (!rect) + { + UNLOCK_HARDWARE( rmesa ); + driWaitForVBlank( dPriv, & missed_target ); + LOCK_HARDWARE( rmesa ); + } + + nbox = dPriv->numClipRects; /* must be in locked region */ + + for ( i = 0 ; i < nbox ; ) { + GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); + drm_clip_rect_t *box = dPriv->pClipRects; + drm_clip_rect_t *b = rmesa->sarea->boxes; + GLint n = 0; + + for ( ; i < nr ; i++ ) { + + *b = box[i]; + + if (rect) + { + if (rect->x1 > b->x1) + b->x1 = rect->x1; + if (rect->y1 > b->y1) + b->y1 = rect->y1; + if (rect->x2 < b->x2) + b->x2 = rect->x2; + if (rect->y2 < b->y2) + b->y2 = rect->y2; + + if (b->x1 >= b->x2 || b->y1 >= b->y2) + continue; + } + + b++; + n++; + } + rmesa->sarea->nbox = n; + + if (!n) + continue; + + ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); + + if ( ret ) { + fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); + UNLOCK_HARDWARE( rmesa ); + exit( 1 ); + } + } + + UNLOCK_HARDWARE( rmesa ); + if (!rect) + { + psp = dPriv->driScreenPriv; + rmesa->swap_count++; + (*psp->systemTime->getUST)( & ust ); + if ( missed_target ) { + rmesa->swap_missed_count++; + rmesa->swap_missed_ust = ust - rmesa->swap_ust; + } + + rmesa->swap_ust = ust; + rmesa->hw.all_dirty = GL_TRUE; + + } +} + +void radeonPageFlip( __DRIdrawablePrivate *dPriv ) +{ + radeonContextPtr rmesa; + GLint ret; + GLboolean missed_target; + __DRIscreenPrivate *psp; + struct radeon_renderbuffer *rrb; + GLframebuffer *fb = dPriv->driverPrivate; + + assert(dPriv); + assert(dPriv->driContextPriv); + assert(dPriv->driContextPriv->driverPrivate); + + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + + psp = dPriv->driScreenPriv; + + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, + rmesa->sarea->pfCurrentPage); + } + + radeon_firevertices(rmesa); + + LOCK_HARDWARE( rmesa ); + + if (!dPriv->numClipRects) { + UNLOCK_HARDWARE(rmesa); + usleep(10000); /* throttle invisible client 10ms */ + return; + } + + drm_clip_rect_t *box = dPriv->pClipRects; + drm_clip_rect_t *b = rmesa->sarea->boxes; + b[0] = box[0]; + rmesa->sarea->nbox = 1; + + /* Throttle the frame rate -- only allow a few pending swap buffers + * request at a time. + */ + radeonWaitForFrameCompletion( rmesa ); + UNLOCK_HARDWARE( rmesa ); + driWaitForVBlank( dPriv, & missed_target ); + if ( missed_target ) { + rmesa->swap_missed_count++; + (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); + } + LOCK_HARDWARE( rmesa ); + + ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); + + UNLOCK_HARDWARE( rmesa ); + + if ( ret ) { + fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); + exit( 1 ); + } + + rmesa->swap_count++; + (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); + + /* Get ready for drawing next frame. Update the renderbuffers' + * flippedOffset/Pitch fields so we draw into the right place. + */ + driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, + rmesa->sarea->pfCurrentPage); + + rmesa->state.color.rrb = rrb; + + if (rmesa->vtbl.update_draw_buffer) + rmesa->vtbl.update_draw_buffer(rmesa->glCtx); +} + + +/** + * Swap front and back buffer. + */ +void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) +{ + if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { + radeonContextPtr radeon; + GLcontext *ctx; + + radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + ctx = radeon->glCtx; + + if (ctx->Visual.doubleBufferMode) { + _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ + if (radeon->doPageFlip) { + radeonPageFlip(dPriv); + } else { + radeonCopyBuffer(dPriv, NULL); + } + } + } else { + /* XXX this shouldn't be an error but we can't handle it for now */ + _mesa_problem(NULL, "%s: drawable has no context!", + __FUNCTION__); + } +} + +void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, + int x, int y, int w, int h ) +{ + if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { + radeonContextPtr radeon; + GLcontext *ctx; + + radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + ctx = radeon->glCtx; + + if (ctx->Visual.doubleBufferMode) { + drm_clip_rect_t rect; + rect.x1 = x + dPriv->x; + rect.y1 = (dPriv->h - y - h) + dPriv->y; + rect.x2 = rect.x1 + w; + rect.y2 = rect.y1 + h; + _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ + radeonCopyBuffer(dPriv, &rect); + } + } else { + /* XXX this shouldn't be an error but we can't handle it for now */ + _mesa_problem(NULL, "%s: drawable has no context!", + __FUNCTION__); + } +} + + +static void radeon_print_state_atom( struct radeon_state_atom *state ) +{ + int i; + + fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); + + if (RADEON_DEBUG & DEBUG_VERBOSE) + for (i = 0 ; i < state->cmd_size ; i++) + fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); + +} + +static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) +{ + BATCH_LOCALS(radeon); + struct radeon_state_atom *atom; + int dwords; + + if (radeon->vtbl.pre_emit_atoms) + radeon->vtbl.pre_emit_atoms(radeon); + + /* Emit actual atoms */ + foreach(atom, &radeon->hw.atomlist) { + if ((atom->dirty || radeon->hw.all_dirty) == dirty) { + dwords = (*atom->check) (radeon->glCtx, atom); + if (dwords) { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + radeon_print_state_atom(atom); + } + if (atom->emit) { + (*atom->emit)(radeon->glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } + } + } + } + + COMMIT_BATCH(); +} + +void radeonEmitState(radeonContextPtr radeon) +{ + if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->vtbl.pre_emit_state) + radeon->vtbl.pre_emit_state(radeon); + + /* this code used to return here but now it emits zbs */ + if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) + return; + + /* To avoid going across the entire set of states multiple times, just check + * for enough space for the case of emitting all state, and inline the + * radeonAllocCmdBuf code here without all the checks. + */ + rcommonEnsureCmdBufSpace(radeon, radeon->hw.max_state_size, __FUNCTION__); + + if (!radeon->cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + radeonEmitAtoms(radeon, GL_FALSE); + } + + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + + radeonEmitAtoms(radeon, GL_TRUE); + radeon->hw.is_dirty = GL_FALSE; + radeon->hw.all_dirty = GL_FALSE; + +} + + +void radeonFlush(GLcontext *ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->dma.flush) + radeon->dma.flush( ctx ); + + radeonEmitState(radeon); + + if (radeon->cmdbuf.cs->cdw) + rcommonFlushCmdBuf(radeon, __FUNCTION__); +} + +/* Make sure all commands have been sent to the hardware and have + * completed processing. + */ +void radeonFinish(GLcontext * ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct gl_framebuffer *fb = ctx->DrawBuffer; + int i; + + radeonFlush(ctx); + + if (radeon->radeonScreen->kernel_mm) { + for (i = 0; i < fb->_NumColorDrawBuffers; i++) { + struct radeon_renderbuffer *rrb; + rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; + if (rrb->bo) + radeon_bo_wait(rrb->bo); + } + } else if (radeon->do_irqs) { + LOCK_HARDWARE(radeon); + radeonEmitIrqLocked(radeon); + UNLOCK_HARDWARE(radeon); + radeonWaitIrq(radeon); + } else { + radeonWaitForIdle(radeon); + } +} + +/* cmdbuffer */ +/** + * Send the current command buffer via ioctl to the hardware. + */ +int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) +{ + int ret = 0; + + if (rmesa->cmdbuf.flushing) { + fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n"); + exit(-1); + } + rmesa->cmdbuf.flushing = 1; + if (rmesa->cmdbuf.cs->cdw) { + ret = radeon_cs_emit(rmesa->cmdbuf.cs); + rmesa->hw.all_dirty = GL_TRUE; + } + radeon_cs_erase(rmesa->cmdbuf.cs); + rmesa->cmdbuf.flushing = 0; + return ret; +} + +int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller) +{ + int ret; + + radeonReleaseDmaRegion(rmesa); + + LOCK_HARDWARE(rmesa); + ret = rcommonFlushCmdBufLocked(rmesa, caller); + UNLOCK_HARDWARE(rmesa); + + if (ret) { + fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret); + _mesa_exit(ret); + } + + return ret; +} + +/** + * Make sure that enough space is available in the command buffer + * by flushing if necessary. + * + * \param dwords The number of dwords we need to be free on the command buffer + */ +void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller) +{ + if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size || + radeon_cs_need_flush(rmesa->cmdbuf.cs)) { + rcommonFlushCmdBuf(rmesa, caller); + } +} + +void rcommonInitCmdBuf(radeonContextPtr rmesa) +{ + GLuint size; + /* Initialize command buffer */ + size = 256 * driQueryOptioni(&rmesa->optionCache, + "command_buffer_size"); + if (size < 2 * rmesa->hw.max_state_size) { + size = 2 * rmesa->hw.max_state_size + 65535; + } + if (size > 64 * 256) + size = 64 * 256; + + if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { + fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", + sizeof(drm_r300_cmd_header_t)); + fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%zd\n", + sizeof(drm_radeon_cmd_buffer_t)); + fprintf(stderr, + "Allocating %d bytes command buffer (max state is %d bytes)\n", + size * 4, rmesa->hw.max_state_size * 4); + } + + if (rmesa->radeonScreen->kernel_mm) { + int fd = rmesa->radeonScreen->driScreen->fd; + rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); + } else { + rmesa->cmdbuf.csm = radeon_cs_manager_legacy_ctor(rmesa); + } + if (rmesa->cmdbuf.csm == NULL) { + /* FIXME: fatal error */ + return; + } + rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); + assert(rmesa->cmdbuf.cs != NULL); + rmesa->cmdbuf.size = size; + + if (!rmesa->radeonScreen->kernel_mm) { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } else { + struct drm_radeon_gem_info mminfo; + + if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) + { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_size); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size); + } + } + +} +/** + * Destroy the command buffer + */ +void rcommonDestroyCmdBuf(radeonContextPtr rmesa) +{ + radeon_cs_destroy(rmesa->cmdbuf.cs); + if (rmesa->radeonScreen->driScreen->dri2.enabled || rmesa->radeonScreen->kernel_mm) { + radeon_cs_manager_gem_dtor(rmesa->cmdbuf.csm); + } else { + radeon_cs_manager_legacy_dtor(rmesa->cmdbuf.csm); + } +} + +void rcommonBeginBatch(radeonContextPtr rmesa, int n, + int dostate, + const char *file, + const char *function, + int line) +{ + rcommonEnsureCmdBufSpace(rmesa, n, function); + if (!rmesa->cmdbuf.cs->cdw && dostate) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "Reemit state after flush (from %s)\n", function); + radeonEmitState(rmesa); + } + radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); +} + + + diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h new file mode 100644 index 00000000000..cc9d579ea16 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -0,0 +1,56 @@ +#ifndef COMMON_MISC_H +#define COMMON_MISC_H + +#include "radeon_common_context.h" +#include "radeon_buffer.h" +#include "radeon_dma.h" +#include "radeon_texture.h" + +void radeonRecalcScissorRects(radeonContextPtr radeon); +void radeonSetCliprects(radeonContextPtr radeon); +void radeonUpdateScissor( GLcontext *ctx ); +void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h); + +void radeonWaitForIdleLocked(radeonContextPtr radeon); +extern uint32_t radeonGetAge(radeonContextPtr radeon); +void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, + const drm_clip_rect_t *rect); +void radeonPageFlip( __DRIdrawablePrivate *dPriv ); +void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); +void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, + int x, int y, int w, int h ); + +void radeonUpdatePageFlipping(radeonContextPtr rmesa); + +void radeonFlush(GLcontext *ctx); +void radeonFinish(GLcontext * ctx); +void radeonEmitState(radeonContextPtr radeon); + +static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; + rrb = rmesa->state.depth.rrb; + if (!rrb) + return NULL; + + return rrb; +} + +static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; + GLframebuffer *fb = rmesa->dri.drawable->driverPrivate; + + rrb = rmesa->state.color.rrb; + if (rmesa->radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb) + return NULL; + return rrb; +} + +#include "radeon_cmdbuf.h" + + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c new file mode 100644 index 00000000000..8acde2b90cd --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -0,0 +1,584 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +#include "radeon_common.h" +#include "xmlpool.h" /* for symbolic values of enum-type options */ +#include "utils.h" +#include "drirenderbuffer.h" +#include "vblank.h" + +#define DRIVER_DATE "20090101" + +#ifndef RADEON_DEBUG +int RADEON_DEBUG = (0); +#endif + +/* Return various strings for glGetString(). + */ +static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + static char buffer[128]; + + switch (name) { + case GL_VENDOR: + if (IS_R300_CLASS(radeon->radeonScreen)) + return (GLubyte *) "DRI R300 Project"; + else + return (GLubyte *) "Tungsten Graphics, Inc."; + + case GL_RENDERER: + { + unsigned offset; + GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : + radeon->radeonScreen->AGPMode; + const char* chipname; + + if (IS_R300_CLASS(radeon->radeonScreen)) + chipname = "R300"; + else if (IS_R200_CLASS(radeon->radeonScreen)) + chipname = "R200"; + else + chipname = "R100"; + + offset = driGetRendererString(buffer, chipname, DRIVER_DATE, + agp_mode); + + if (IS_R300_CLASS(radeon->radeonScreen)) { + sprintf(&buffer[offset], " %sTCL", + (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) + ? "" : "NO-"); + } else { + sprintf(&buffer[offset], " %sTCL", + !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) + ? "" : "NO-"); + } + + if (radeon->radeonScreen->driScreen->dri2.enabled) + strcat(buffer, " DRI2"); + + return (GLubyte *) buffer; + } + + default: + return NULL; + } +} + +/* Initialize the driver's misc functions. + */ +static void radeonInitDriverFuncs(struct dd_function_table *functions) +{ + functions->GetString = radeonGetString; +} + +/** + * Create and initialize all common fields of the context, + * including the Mesa context itself. + */ +GLboolean radeonInitContext(radeonContextPtr radeon, + struct dd_function_table* functions, + const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPrivate) +{ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + GLcontext* ctx; + GLcontext* shareCtx; + int fthrottle_mode; + + /* Fill in additional standard functions. */ + radeonInitDriverFuncs(functions); + + radeon->radeonScreen = screen; + /* Allocate and initialize the Mesa context */ + if (sharedContextPrivate) + shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx; + else + shareCtx = NULL; + radeon->glCtx = _mesa_create_context(glVisual, shareCtx, + functions, (void *)radeon); + if (!radeon->glCtx) + return GL_FALSE; + + ctx = radeon->glCtx; + driContextPriv->driverPrivate = radeon; + + /* DRI fields */ + radeon->dri.context = driContextPriv; + radeon->dri.screen = sPriv; + radeon->dri.drawable = NULL; + radeon->dri.readable = NULL; + radeon->dri.hwContext = driContextPriv->hHWContext; + radeon->dri.hwLock = &sPriv->pSAREA->lock; + radeon->dri.fd = sPriv->fd; + radeon->dri.drmMinor = sPriv->drm_version.minor; + + radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + + screen->sarea_priv_offset); + + /* Setup IRQs */ + fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); + radeon->iw.irq_seq = -1; + radeon->irqsEmitted = 0; + radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && + radeon->radeonScreen->irq); + + radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); + + if (!radeon->do_irqs) + fprintf(stderr, + "IRQ's not enabled, falling back to %s: %d %d\n", + radeon->do_usleeps ? "usleeps" : "busy waits", + fthrottle_mode, radeon->radeonScreen->irq); + + (*sPriv->systemTime->getUST) (&radeon->swap_ust); + + return GL_TRUE; +} + +/** + * Cleanup common context fields. + * Called by r200DestroyContext/r300DestroyContext + */ +void radeonCleanupContext(radeonContextPtr radeon) +{ + FILE *track; + struct radeon_renderbuffer *rb; + GLframebuffer *fb; + + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); + + fb = (void*)radeon->dri.drawable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + fb = (void*)radeon->dri.readable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + + /* _mesa_destroy_context() might result in calls to functions that + * depend on the DriverCtx, so don't set it to NULL before. + * + * radeon->glCtx->DriverCtx = NULL; + */ + + + + /* free the option cache */ + driDestroyOptionCache(&radeon->optionCache); + + rcommonDestroyCmdBuf(radeon); + + if (radeon->state.scissor.pClipRects) { + FREE(radeon->state.scissor.pClipRects); + radeon->state.scissor.pClipRects = 0; + } + track = fopen("/tmp/tracklog", "w"); + if (track) { + radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); + fclose(track); + } +} + +/* Force the context `c' to be unbound from its buffer. + */ +GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) +{ + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, + radeon->glCtx); + + return GL_TRUE; +} + + +static void +radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + +static void +radeon_make_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + int size = 4096*4096*4; + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if (radeon->radeonScreen->kernel_mm) { + radeon_make_kernel_renderbuffer_current(radeon, draw); + return; + } + + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + + +void +radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) +{ + unsigned int attachments[10]; + __DRIbuffer *buffers; + __DRIscreen *screen; + struct radeon_renderbuffer *rb; + int i, count; + GLframebuffer *draw; + radeonContextPtr radeon; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); + + draw = drawable->driverPrivate; + screen = context->driScreenPriv; + radeon = (radeonContextPtr) context->driverPrivate; + i = 0; + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_DEPTH; + } + + buffers = (*screen->dri2.loader->getBuffers)(drawable, + &drawable->w, + &drawable->h, + attachments, i, + &count, + drawable->loaderPrivate); + if (buffers == NULL) + return; + + /* set one cliprect to cover the whole drawable */ + drawable->x = 0; + drawable->y = 0; + drawable->backX = 0; + drawable->backY = 0; + drawable->numClipRects = 1; + drawable->pClipRects[0].x1 = 0; + drawable->pClipRects[0].y1 = 0; + drawable->pClipRects[0].x2 = drawable->w; + drawable->pClipRects[0].y2 = drawable->h; + drawable->numBackClipRects = 1; + drawable->pBackClipRects[0].x1 = 0; + drawable->pBackClipRects[0].y1 = 0; + drawable->pBackClipRects[0].x2 = drawable->w; + drawable->pBackClipRects[0].y2 = drawable->h; + for (i = 0; i < count; i++) { + switch (buffers[i].attachment) { + case __DRI_BUFFER_FRONT_LEFT: + rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + if (rb->bo == NULL) { + fprintf(stderr, "failled to attach front %d\n", + buffers[i].name); + } + break; + case __DRI_BUFFER_BACK_LEFT: + rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_DEPTH: + rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_STENCIL: + break; + case __DRI_BUFFER_ACCUM: + default: + fprintf(stderr, + "unhandled buffer attach event, attacment type %d\n", + buffers[i].attachment); + return; + } + } + radeon = (radeonContextPtr) context->driverPrivate; + driUpdateFramebufferSize(radeon->glCtx, drawable); +} + +/* Force the context `c' to be the current context and associate with it + * buffer `b'. + */ +GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, + __DRIdrawablePrivate * driDrawPriv, + __DRIdrawablePrivate * driReadPriv) +{ + radeonContextPtr radeon; + GLframebuffer *dfb, *rfb; + + if (!driContextPriv) { + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx is null\n", __FUNCTION__); + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; + } + radeon = (radeonContextPtr) driContextPriv->driverPrivate; + dfb = driDrawPriv->driverPrivate; + rfb = driReadPriv->driverPrivate; + + if (driContextPriv->driScreenPriv->dri2.enabled) { + radeon_update_renderbuffers(driContextPriv, driDrawPriv); + if (driDrawPriv != driReadPriv) + radeon_update_renderbuffers(driContextPriv, driReadPriv); + radeon->state.color.rrb = + (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon->state.depth.rrb = + (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + } else { + radeon_make_renderbuffer_current(radeon, dfb); + } + + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, dfb, rfb); + + driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); + if (driReadPriv != driDrawPriv) + driUpdateFramebufferSize(radeon->glCtx, driReadPriv); + + + + _mesa_make_current(radeon->glCtx, dfb, rfb); + + if (radeon->dri.drawable != driDrawPriv) { + if (driDrawPriv->swap_interval == (unsigned)-1) { + driDrawPriv->vblFlags = + (radeon->radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; + + driDrawableInitVBlank(driDrawPriv); + } + } + + radeon->dri.readable = driReadPriv; + + if (radeon->dri.drawable != driDrawPriv || + radeon->lastStamp != driDrawPriv->lastStamp) { + radeon->dri.drawable = driDrawPriv; + + radeonSetCliprects(radeon); + radeon->vtbl.update_viewport_offset(radeon->glCtx); + } + + _mesa_update_state(radeon->glCtx); + + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeonUpdatePageFlipping(radeon); + } + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "End %s\n", __FUNCTION__); + return GL_TRUE; +} + diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h new file mode 100644 index 00000000000..b88aeab0518 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -0,0 +1,513 @@ + +#ifndef COMMON_CONTEXT_H +#define COMMON_CONTEXT_H + +#include "main/mm.h" +#include "math/m_vector.h" +#include "texmem.h" +#include "tnl/t_context.h" +#include "main/colormac.h" + +#include "radeon_screen.h" +#include "radeon_drm.h" +#include "dri_util.h" +#include "tnl/t_vertex.h" + +/* This union is used to avoid warnings/miscompilation + with float to uint32_t casts due to strict-aliasing */ +typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; + +struct radeon_context; +typedef struct radeon_context radeonContextRec; +typedef struct radeon_context *radeonContextPtr; + + +#define TEX_0 0x1 +#define TEX_1 0x2 +#define TEX_2 0x4 +#define TEX_3 0x8 +#define TEX_4 0x10 +#define TEX_5 0x20 + +/* Rasterizing fallbacks */ +/* See correponding strings in r200_swtcl.c */ +#define RADEON_FALLBACK_TEXTURE 0x0001 +#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 +#define RADEON_FALLBACK_STENCIL 0x0004 +#define RADEON_FALLBACK_RENDER_MODE 0x0008 +#define RADEON_FALLBACK_BLEND_EQ 0x0010 +#define RADEON_FALLBACK_BLEND_FUNC 0x0020 +#define RADEON_FALLBACK_DISABLE 0x0040 +#define RADEON_FALLBACK_BORDER_MODE 0x0080 + +#define R200_FALLBACK_TEXTURE 0x01 +#define R200_FALLBACK_DRAW_BUFFER 0x02 +#define R200_FALLBACK_STENCIL 0x04 +#define R200_FALLBACK_RENDER_MODE 0x08 +#define R200_FALLBACK_DISABLE 0x10 +#define R200_FALLBACK_BORDER_MODE 0x20 + +#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ +#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ +#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ +#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ +#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ +#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ +#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ +#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ +#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ + +/* The blit width for texture uploads + */ +#define BLIT_WIDTH_BYTES 1024 + +/* Use the templated vertex format: + */ +#define COLOR_IS_RGBA +#define TAG(x) radeon##x +#include "tnl_dd/t_dd_vertex.h" +#undef TAG + +struct radeon_colorbuffer_state { + GLuint clear; + int roundEnable; + struct radeon_renderbuffer *rrb; +}; + +struct radeon_depthbuffer_state { + GLuint clear; + GLfloat scale; + struct radeon_renderbuffer *rrb; +}; + +struct radeon_scissor_state { + drm_clip_rect_t rect; + GLboolean enabled; + + GLuint numClipRects; /* Cliprects active */ + GLuint numAllocedClipRects; /* Cliprects available */ + drm_clip_rect_t *pClipRects; +}; + +struct radeon_stencilbuffer_state { + GLboolean hwBuffer; + GLuint clear; /* rb3d_stencilrefmask value */ +}; + +struct radeon_stipple_state { + GLuint mask[32]; +}; + +struct radeon_state_atom { + struct radeon_state_atom *next, *prev; + const char *name; /* for debug */ + int cmd_size; /* size in bytes */ + GLuint idx; + GLuint is_tcl; + GLuint *cmd; /* one or more cmd's */ + GLuint *lastcmd; /* one or more cmd's */ + GLboolean dirty; /* dirty-mark in emit_state_list */ + int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */ + void (*emit) (GLcontext *, struct radeon_state_atom *atom); +}; + +struct radeon_hw_state { + /* Head of the linked list of state atoms. */ + struct radeon_state_atom atomlist; + int max_state_size; /* Number of bytes necessary for a full state emit. */ + GLboolean is_dirty, all_dirty; +}; + + +/* Texture related */ +typedef struct _radeon_texture_image radeon_texture_image; + +struct _radeon_texture_image { + struct gl_texture_image base; + + /** + * If mt != 0, the image is stored in hardware format in the + * given mipmap tree. In this case, base.Data may point into the + * mapping of the buffer object that contains the mipmap tree. + * + * If mt == 0, the image is stored in normal memory pointed to + * by base.Data. + */ + struct _radeon_mipmap_tree *mt; + struct radeon_bo *bo; + + int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ + int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ +}; + + +static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image) +{ + return (radeon_texture_image*)image; +} + + +typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; + +#define RADEON_TXO_MICRO_TILE (1 << 3) + +/* Texture object in locally shared texture space. + */ +struct radeon_tex_obj { + // driTextureObject base; + struct gl_texture_object base; + struct _radeon_mipmap_tree *mt; + + /** + * This is true if we've verified that the mipmap tree above is complete + * and so on. + */ + GLboolean validated; + + GLuint override_offset; + GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + GLuint tile_bits; /* hw texture tile bits used on this texture */ + struct radeon_bo *bo; + + GLuint bufAddr; /* Offset to start of locally + shared texture block */ + + GLuint dirty_state; /* Flags (1 per texunit) for + whether or not this texobj + has dirty hardware state + (pp_*) that needs to be + brought into the + texunit. */ + + drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; + /* Six, for the cube faces */ + + + + GLuint pp_txfilter; /* hardware register values */ + GLuint pp_txformat; + GLuint pp_txformat_x; + GLuint pp_txoffset; /* Image location in texmem. + All cube faces follow. */ + GLuint pp_txsize; /* npot only */ + GLuint pp_txpitch; /* npot only */ + GLuint pp_border_color; + GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ + + GLuint pp_txfilter_1; /* r300 */ + + GLboolean border_fallback; + + +}; + +static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj) +{ + return (radeonTexObj*)texObj; +} + +/* Need refcounting on dma buffers: + */ +struct radeon_dma_buffer { + int refcount; /* the number of retained regions in buf */ + drmBufPtr buf; +}; + +struct radeon_aos { + struct radeon_bo *bo; /** Buffer object where vertex data is stored */ + int offset; /** Offset into buffer object, in bytes */ + int components; /** Number of components per vertex */ + int stride; /** Stride in dwords (may be 0 for repeating) */ + int count; /** Number of vertices */ +}; + +struct radeon_dma { + /* Active dma region. Allocations for vertices and retained + * regions come from here. Also used for emitting random vertices, + * these may be flushed by calling flush_current(); + */ + struct radeon_bo *current; /** Buffer that DMA memory is allocated from */ + int current_used; /** Number of bytes allocated and forgotten about */ + int current_vertexptr; /** End of active vertex region */ + + /** + * If current_vertexptr != current_used then flush must be non-zero. + * flush must be called before non-active vertex allocations can be + * performed. + */ + void (*flush) (GLcontext *); + + /* Number of "in-flight" DMA buffers, i.e. the number of buffers + * for which a DISCARD command is currently queued in the command buffer +. + */ + GLuint nr_released_bufs; +}; + +/* radeon_swtcl.c + */ +struct radeon_swtcl_info { + + GLuint RenderIndex; + GLuint vertex_size; + GLubyte *verts; + + /* Fallback rasterization functions + */ + GLuint hw_primitive; + GLenum render_primitive; + GLuint numverts; + + struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; + GLuint vertex_attr_count; + +}; + +struct radeon_ioctl { + GLuint vertex_offset; + struct radeon_bo *bo; + GLuint vertex_size; +}; + +#define RADEON_MAX_PRIMS 64 + +struct radeon_prim { + GLuint start; + GLuint end; + GLuint prim; +}; + +static INLINE GLuint radeonPackColor(GLuint cpp, + GLubyte r, GLubyte g, + GLubyte b, GLubyte a) +{ + switch (cpp) { + case 2: + return PACK_COLOR_565(r, g, b); + case 4: + return PACK_COLOR_8888(a, r, g, b); + default: + return 0; + } +} + +#define MAX_CMD_BUF_SZ (16*1024) + +#define MAX_DMA_BUF_SZ (64*1024) + +struct radeon_store { + GLuint statenr; + GLuint primnr; + char cmd_buf[MAX_CMD_BUF_SZ]; + int cmd_used; + int elts_start; +}; + +struct radeon_dri_mirror { + __DRIcontextPrivate *context; /* DRI context */ + __DRIscreenPrivate *screen; /* DRI screen */ + + /** + * DRI drawable bound to this context for drawing. + */ + __DRIdrawablePrivate *drawable; + + /** + * DRI drawable bound to this context for reading. + */ + __DRIdrawablePrivate *readable; + + drm_context_t hwContext; + drm_hw_lock_t *hwLock; + int fd; + int drmMinor; +}; + +#define DEBUG_TEXTURE 0x001 +#define DEBUG_STATE 0x002 +#define DEBUG_IOCTL 0x004 +#define DEBUG_PRIMS 0x008 +#define DEBUG_VERTS 0x010 +#define DEBUG_FALLBACKS 0x020 +#define DEBUG_VFMT 0x040 +#define DEBUG_CODEGEN 0x080 +#define DEBUG_VERBOSE 0x100 +#define DEBUG_DRI 0x200 +#define DEBUG_DMA 0x400 +#define DEBUG_SANITY 0x800 +#define DEBUG_SYNC 0x1000 +#define DEBUG_PIXEL 0x2000 +#define DEBUG_MEMORY 0x4000 + + + +typedef void (*radeon_tri_func) (radeonContextPtr, + radeonVertex *, + radeonVertex *, radeonVertex *); + +typedef void (*radeon_line_func) (radeonContextPtr, + radeonVertex *, radeonVertex *); + +typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); + +struct radeon_state { + struct radeon_colorbuffer_state color; + struct radeon_depthbuffer_state depth; + struct radeon_scissor_state scissor; + struct radeon_stencilbuffer_state stencil; +}; + +/** + * This structure holds the command buffer while it is being constructed. + * + * The first batch of commands in the buffer is always the state that needs + * to be re-emitted when the context is lost. This batch can be skipped + * otherwise. + */ +struct radeon_cmdbuf { + struct radeon_cs_manager *csm; + struct radeon_cs *cs; + int size; /** # of dwords total */ + unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ +}; + +struct radeon_context { + GLcontext *glCtx; + radeonScreenPtr radeonScreen; /* Screen private DRI data */ + + /* Texture object bookkeeping + */ + unsigned nr_heaps; + driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; + driTextureObject swapped; + int texture_depth; + float initialMaxAnisotropy; + + struct radeon_dma dma; + struct radeon_hw_state hw; + /* Rasterization and vertex state: + */ + GLuint TclFallback; + GLuint Fallback; + GLuint NewGLState; + DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ + + /* Page flipping */ + GLuint doPageFlip; + + /* Drawable, cliprect and scissor information */ + GLuint numClipRects; /* Cliprects for the draw buffer */ + drm_clip_rect_t *pClipRects; + unsigned int lastStamp; + GLboolean lost_context; + drm_radeon_sarea_t *sarea; /* Private SAREA data */ + + /* Mirrors of some DRI state */ + struct radeon_dri_mirror dri; + + /* Busy waiting */ + GLuint do_usleeps; + GLuint do_irqs; + GLuint irqsEmitted; + drm_radeon_irq_wait_t iw; + + /* buffer swap */ + int64_t swap_ust; + int64_t swap_missed_ust; + + GLuint swap_count; + GLuint swap_missed_count; + + /* Derived state - for r300 only */ + struct radeon_state state; + + struct radeon_swtcl_info swtcl; + /* Configuration cache + */ + driOptionCache optionCache; + + struct radeon_cmdbuf cmdbuf; + + struct { + void (*get_lock)(radeonContextPtr radeon); + void (*update_viewport_offset)(GLcontext *ctx); + void (*update_draw_buffer)(GLcontext *ctx); + void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); + void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); + void (*pre_emit_atoms)(radeonContextPtr rmesa); + void (*pre_emit_state)(radeonContextPtr rmesa); + } vtbl; +}; + +#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) + +/** + * This function takes a float and packs it into a uint32_t + */ +static INLINE uint32_t radeonPackFloat32(float fl) +{ + union { + float fl; + uint32_t u; + } u; + + u.fl = fl; + return u.u; +} + +/* This is probably wrong for some values, I need to test this + * some more. Range checking would be a good idea also.. + * + * But it works for most things. I'll fix it later if someone + * else with a better clue doesn't + */ +static INLINE uint32_t radeonPackFloat24(float f) +{ + float mantissa; + int exponent; + uint32_t float24 = 0; + + if (f == 0.0) + return 0; + + mantissa = frexpf(f, &exponent); + + /* Handle -ve */ + if (mantissa < 0) { + float24 |= (1 << 23); + mantissa = mantissa * -1.0; + } + /* Handle exponent, bias of 63 */ + exponent += 62; + float24 |= (exponent << 16); + /* Kill 7 LSB of mantissa */ + float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7; + + return float24; +} + +GLboolean radeonInitContext(radeonContextPtr radeon, + struct dd_function_table* functions, + const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPrivate); + +void radeonCleanupContext(radeonContextPtr radeon); +GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); +void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); +GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, + __DRIdrawablePrivate * driDrawPriv, + __DRIdrawablePrivate * driReadPriv); + +/* ================================================================ + * Debugging: + */ +#define DO_DEBUG 1 + +#if DO_DEBUG +extern int RADEON_DEBUG; +#else +#define RADEON_DEBUG 0 +#endif + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index b25f036c442..0296cffc20a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -53,8 +53,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" +#include "radeon_common.h" #include "radeon_context.h" -#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_span.h" @@ -77,36 +77,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ -/* Return various strings for glGetString(). - */ -static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - static char buffer[128]; - unsigned offset; - GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : - rmesa->radeon.radeonScreen->AGPMode; - - switch ( name ) { - case GL_VENDOR: - return (GLubyte *)"Tungsten Graphics, Inc."; - - case GL_RENDERER: - offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE, - agp_mode ); - - sprintf( & buffer[ offset ], " %sTCL", - !(rmesa->radeon.TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) - ? "" : "NO-" ); - - return (GLubyte *)buffer; - - default: - return NULL; - } -} - - /* Extension strings exported by the R100 driver. */ const struct dri_extension card_extensions[] = @@ -163,15 +133,6 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = { NULL, }; - - -/* Initialize the driver's misc functions. - */ -static void radeonInitDriverFuncs( struct dd_function_table *functions ) -{ - functions->GetString = radeonGetString; -} - static const struct dri_debug_control debug_control[] = { { "fall", DEBUG_FALLBACKS }, @@ -292,7 +253,6 @@ radeonCreateContext( const __GLcontextModes *glVisual, * (the texture functions are especially important) */ _mesa_init_driver_functions( &functions ); - radeonInitDriverFuncs( &functions ); radeonInitTextureFuncs( &functions ); if (!radeonInitContext(&rmesa->radeon, &functions, diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index d05e47f16e7..2efabd1f557 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -53,8 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "radeon_screen.h" -#include "common_context.h" -#include "common_misc.h" +#include "radeon_common.h" struct r100_context; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index fbb93a8ba1e..2db3f7a68da 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -31,8 +31,6 @@ */ #include - -#include "common_context.h" #include "radeon_cs.h" #include "radeon_cs_legacy.h" #include "radeon_bo_legacy.h" @@ -234,7 +232,7 @@ static int cs_process_relocs(struct radeon_cs *cs) } cs->packets[relocs[i].indices[j]] += soffset; if (cs->packets[relocs[i].indices[j]] >= eoffset) { - radeon_bo_debug(relocs[i].base.bo, 12); + /* radeon_bo_debug(relocs[i].base.bo, 12); */ fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h index 4da2479eee7..19d904174f6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h @@ -33,7 +33,7 @@ #define RADEON_CS_LEGACY_H #include "radeon_cs.h" -#include "common_context.h" +#include "radeon_common.h" struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm); diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c new file mode 100644 index 00000000000..393b12182d5 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -0,0 +1,323 @@ +/************************************************************************** + +Copyright (C) 2004 Nicolai Haehnle. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +#include "radeon_common.h" + +#if defined(USE_X86_ASM) +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int __tmp; \ + __asm__ __volatile__( "rep ; movsl" \ + : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ + : "0" (nr), \ + "D" ((long)dst), \ + "S" ((long)src) ); \ +} while (0) +#else +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int j; \ + for ( j = 0 ; j < nr ; j++ ) \ + dst[j] = ((int *)src)[j]; \ + dst += nr; \ +} while (0) +#endif + +static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 4) + COPY_DWORDS(out, data, count); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out++; + data += stride; + } +} + +void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 8) + COPY_DWORDS(out, data, count * 2); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out += 2; + data += stride; + } +} + +void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 12) { + COPY_DWORDS(out, data, count * 3); + } + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out += 3; + data += stride; + } +} + +static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 16) + COPY_DWORDS(out, data, count * 4); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out[3] = *(int *)(data + 12); + out += 4; + data += stride; + } +} + +void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, + GLvoid * data, int size, int stride, int count) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + uint32_t *out; + + if (stride == 0) { + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); + count = 1; + aos->stride = 0; + } else { + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); + aos->stride = size; + } + + aos->components = size; + aos->count = count; + + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); + switch (size) { + case 1: radeonEmitVec4(out, data, stride, count); break; + case 2: radeonEmitVec8(out, data, stride, count); break; + case 3: radeonEmitVec12(out, data, stride, count); break; + case 4: radeonEmitVec16(out, data, stride, count); break; + default: + assert(0); + break; + } +} + +void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) +{ + struct radeon_cs_space_check bos[1]; + int flushed = 0, ret; + + size = MAX2(size, MAX_DMA_BUF_SZ * 16); + + if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (rmesa->dma.flush) { + rmesa->dma.flush(rmesa->glCtx); + } + + if (rmesa->dma.nr_released_bufs > 4) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + rmesa->dma.nr_released_bufs = 0; + } + + if (rmesa->dma.current) { + radeon_bo_unmap(rmesa->dma.current); + radeon_bo_unref(rmesa->dma.current); + rmesa->dma.current = 0; + } + +again_alloc: + rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom, + 0, size, 4, RADEON_GEM_DOMAIN_GTT, + 0); + + if (!rmesa->dma.current) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + rmesa->dma.nr_released_bufs = 0; + goto again_alloc; + } + + rmesa->dma.current_used = 0; + rmesa->dma.current_vertexptr = 0; + + bos[0].bo = rmesa->dma.current; + bos[0].read_domains = RADEON_GEM_DOMAIN_GTT; + bos[0].write_domain =0 ; + bos[0].new_accounted = 0; + + ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) { + fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen"); + assert(0); + } else if (ret == RADEON_CS_SPACE_FLUSH) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + if (flushed) { + fprintf(stderr,"flushed but still no space\n"); + assert(0); + } + flushed = 1; + goto again_alloc; + } + radeon_bo_map(rmesa->dma.current, 1); +} + +/* Allocates a region from rmesa->dma.current. If there isn't enough + * space in current, grab a new buffer (and discard what was left of current) + */ +void radeonAllocDmaRegion(radeonContextPtr rmesa, + struct radeon_bo **pbo, int *poffset, + int bytes, int alignment) +{ + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); + + if (rmesa->dma.flush) + rmesa->dma.flush(rmesa->glCtx); + + assert(rmesa->dma.current_used == rmesa->dma.current_vertexptr); + + alignment--; + rmesa->dma.current_used = (rmesa->dma.current_used + alignment) & ~alignment; + + if (!rmesa->dma.current || rmesa->dma.current_used + bytes > rmesa->dma.current->size) + radeonRefillCurrentDmaRegion(rmesa, (bytes + 15) & ~15); + + *poffset = rmesa->dma.current_used; + *pbo = rmesa->dma.current; + radeon_bo_ref(*pbo); + + /* Always align to at least 16 bytes */ + rmesa->dma.current_used = (rmesa->dma.current_used + bytes + 15) & ~15; + rmesa->dma.current_vertexptr = rmesa->dma.current_used; + + assert(rmesa->dma.current_used <= rmesa->dma.current->size); +} + +void radeonReleaseDmaRegion(radeonContextPtr rmesa) +{ + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %p\n", __FUNCTION__, rmesa->dma.current); + if (rmesa->dma.current) { + rmesa->dma.nr_released_bufs++; + radeon_bo_unmap(rmesa->dma.current); + radeon_bo_unref(rmesa->dma.current); + } + rmesa->dma.current = NULL; +} + + +/* Flush vertices in the current dma region. + */ +void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + struct radeon_dma *dma = &rmesa->dma; + + + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s\n", __FUNCTION__); + dma->flush = NULL; + + if (dma->current) { + GLuint current_offset = dma->current_used; + + assert (dma->current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + dma->current_vertexptr); + + if (dma->current_used != dma->current_vertexptr) { + dma->current_used = dma->current_vertexptr; + + rmesa->vtbl.swtcl_flush(ctx, current_offset); + } + rmesa->swtcl.numverts = 0; + } +} +/* Alloc space in the current dma region. + */ +void * +rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) +{ + GLuint bytes = vsize * nverts; + void *head; + + if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) { + radeonRefillCurrentDmaRegion(rmesa, bytes); + } + + if (!rmesa->dma.flush) { + rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->dma.flush = rcommon_flush_last_swtcl_prim; + } + + ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); + ASSERT( rmesa->dma.flush == rcommon_flush_last_swtcl_prim ); + ASSERT( rmesa->dma.current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + rmesa->dma.current_vertexptr ); + + head = (rmesa->dma.current->ptr + rmesa->dma.current_vertexptr); + rmesa->dma.current_vertexptr += bytes; + rmesa->swtcl.numverts += nverts; + return head; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.h b/src/mesa/drivers/dri/radeon/radeon_dma.h new file mode 100644 index 00000000000..cee3744fed1 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_dma.h @@ -0,0 +1,51 @@ +/************************************************************************** + +Copyright (C) 2004 Nicolai Haehnle. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +#ifndef RADEON_DMA_H +#define RADEON_DMA_H + +void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count); +void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count); + +void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, + GLvoid * data, int size, int stride, int count); + +void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size); +void radeonAllocDmaRegion(radeonContextPtr rmesa, + struct radeon_bo **pbo, int *poffset, + int bytes, int alignment); +void radeonReleaseDmaRegion(radeonContextPtr rmesa); + +void rcommon_flush_last_swtcl_prim(GLcontext *ctx); + +void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index d0cd9ce7a60..99b1ef332f0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -43,7 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "radeon_context.h" -#include "common_cmdbuf.h" +#include "radeon_common.h" #include "radeon_cs.h" #include "radeon_state.h" #include "radeon_ioctl.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c new file mode 100644 index 00000000000..9a7e76b245e --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -0,0 +1,124 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Gareth Hughes + * Keith Whitwell + * Kevin E. Martin + */ + +#include "main/glheader.h" +#include "main/mtypes.h" +#include "main/colormac.h" +#include "dri_util.h" +#include "radeon_screen.h" +#include "radeon_common.h" +#include "radeon_lock.h" +#include "drirenderbuffer.h" + +#if DEBUG_LOCKING +char *prevLockFile = NULL; +int prevLockLine = 0; +#endif + +/* Turn on/off page flipping according to the flags in the sarea: + */ +void radeonUpdatePageFlipping(radeonContextPtr rmesa) +{ + int use_back; + __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; + GLframebuffer *fb = drawable->driverPrivate; + + rmesa->doPageFlip = rmesa->sarea->pfState; + if (rmesa->glCtx->WinSysDrawBuffer) { + rmesa->vtbl.update_draw_buffer(rmesa->glCtx); + } + + use_back = rmesa->glCtx->DrawBuffer ? + (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == + BUFFER_BACK_LEFT) : 1; + use_back ^= (rmesa->sarea->pfCurrentPage == 1); + + if (use_back) + rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + else + rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + + rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; +} + +/* Update the hardware state. This is called if another context has + * grabbed the hardware lock, which includes the X server. This + * function also updates the driver's window state after the X server + * moves, resizes or restacks a window -- the change will be reflected + * in the drawable position and clip rects. Since the X server grabs + * the hardware lock when it changes the window state, this routine will + * automatically be called after such a change. + */ +void radeonGetLock(radeonContextPtr rmesa, GLuint flags) +{ + __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; + __DRIdrawablePrivate *const readable = rmesa->dri.readable; + __DRIscreenPrivate *sPriv = rmesa->dri.screen; + drm_radeon_sarea_t *sarea = rmesa->sarea; + + assert(drawable != NULL); + + drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); + + /* The window might have moved, so we might need to get new clip + * rects. + * + * NOTE: This releases and regrabs the hw lock to allow the X server + * to respond to the DRI protocol request for new drawable info. + * Since the hardware state depends on having the latest drawable + * clip rects, all state checking must be done _after_ this call. + */ + DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); + if (drawable != readable) { + DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); + } + + if (rmesa->lastStamp != drawable->lastStamp) { + radeonUpdatePageFlipping(rmesa); + radeonSetCliprects(rmesa); + rmesa->vtbl.update_viewport_offset(rmesa->glCtx); + driUpdateFramebufferSize(rmesa->glCtx, drawable); + } + + rmesa->vtbl.get_lock(rmesa); + + rmesa->lost_context = GL_TRUE; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h index f2d17a54d47..f5ebb8dd54c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.h +++ b/src/mesa/drivers/dri/radeon/radeon_lock.h @@ -39,9 +39,82 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Kevin E. Martin */ -#ifndef __RADEON_LOCK_H__ -#define __RADEON_LOCK_H__ +#ifndef COMMON_LOCK_H +#define COMMON_LOCK_H -#include "common_lock.h" +#include "main/colormac.h" +#include "radeon_screen.h" +#include "radeon_common.h" -#endif /* __RADEON_LOCK_H__ */ +extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); + +/* Turn DEBUG_LOCKING on to find locking conflicts. + */ +#define DEBUG_LOCKING 0 + +#if DEBUG_LOCKING +extern char *prevLockFile; +extern int prevLockLine; + +#define DEBUG_LOCK() \ + do { \ + prevLockFile = (__FILE__); \ + prevLockLine = (__LINE__); \ + } while (0) + +#define DEBUG_RESET() \ + do { \ + prevLockFile = 0; \ + prevLockLine = 0; \ + } while (0) + +#define DEBUG_CHECK_LOCK() \ + do { \ + if ( prevLockFile ) { \ + fprintf( stderr, \ + "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ + prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ + exit( 1 ); \ + } \ + } while (0) + +#else + +#define DEBUG_LOCK() +#define DEBUG_RESET() +#define DEBUG_CHECK_LOCK() + +#endif + +/* + * !!! We may want to separate locks from locks with validation. This + * could be used to improve performance for those things commands that + * do not do any drawing !!! + */ + +/* Lock the hardware and validate our state. + */ +#define LOCK_HARDWARE( rmesa ) \ + do { \ + char __ret = 0; \ + DEBUG_CHECK_LOCK(); \ + if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ + DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ + (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ + if ( __ret ) \ + radeonGetLock( (rmesa), 0 ); \ + } \ + DEBUG_LOCK(); \ + } while (0) + +#define UNLOCK_HARDWARE( rmesa ) \ + do { \ + if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ + DRM_UNLOCK( (rmesa)->dri.fd, \ + (rmesa)->dri.hwLock, \ + (rmesa)->dri.hwContext ); \ + DEBUG_RESET(); \ + } \ + } while (0) + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h index 875e5e5aee6..43dfa48aa71 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h @@ -28,7 +28,7 @@ #ifndef __RADEON_MIPMAP_TREE_H_ #define __RADEON_MIPMAP_TREE_H_ -#include "common_context.h" +#include "radeon_common.h" typedef struct _radeon_mipmap_tree radeon_mipmap_tree; typedef struct _radeon_mipmap_level radeon_mipmap_level; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 7397218fb6c..7f0d526ed2d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -47,7 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_macros.h" #include "radeon_screen.h" #include "radeon_buffer.h" -#include "common_misc.h" +#include "radeon_common.h" #include "radeon_span.h" #if !RADEON_COMMON #include "radeon_context.h" @@ -362,7 +362,7 @@ static const __DRItexBufferExtension r300TexBufferExtension = { }; #endif -int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) +static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) { screen->chip_flags = 0; switch ( device_id ) { diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index bd613f4779c..ebd18a16342 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -43,14 +43,154 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/glheader.h" #include "swrast/swrast.h" -#include "common_context.h" -#include "common_misc.h" +#include "radeon_common.h" +#include "radeon_lock.h" #include "radeon_span.h" #include "radeon_buffer.h" #define DBG 0 +static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + const __DRIdrawablePrivate *dPriv = rrb->dPriv; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + + x += dPriv->x; + y += dPriv->y; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + nmacroblkpl = rrb->pitch >> 5; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x >> 5) << 11; + offset += ((x & 31) >> 2) << 5; + offset += (x & 3) << 2; + } else { + nmacroblkpl = rrb->pitch >> 6; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x >> 6) << 11; + offset += ((x & 63) >> 3) << 5; + offset += (x & 7) << 2; + } + } else { + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x >> 3) << 5; + offset += (x & 7) << 2; + } + } + return &ptr[offset]; +} + +static GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + const __DRIdrawablePrivate *dPriv = rrb->dPriv; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + + x += dPriv->x; + y += dPriv->y; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + nmacroblkpl = rrb->pitch >> 6; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x >> 6) << 11; + offset += ((x & 63) >> 3) << 5; + offset += (x & 7) << 1; + } else { + nmacroblkpl = rrb->pitch >> 7; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x >> 7) << 11; + offset += ((x & 127) >> 4) << 5; + offset += (x & 15) << 2; + } + } else { + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x >> 4) << 5; + offset += (x & 15) << 2; + } + } + return &ptr[offset]; +} + +static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + const __DRIdrawablePrivate *dPriv = rrb->dPriv; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint microblkxs; + GLint macroblkxs; + GLint nmacroblkpl; + GLint nmicroblkpl; + + x += dPriv->x; + y += dPriv->y; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = 0; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) { + microblkxs = 16 / rrb->cpp; + macroblkxs = 128 / rrb->cpp; + nmacroblkpl = rrb->pitch / macroblkxs; + offset += ((y >> 4) * nmacroblkpl) << 11; + offset += ((y & 15) >> 1) << 8; + offset += (y & 1) << 4; + offset += (x / macroblkxs) << 11; + offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } else { + microblkxs = 32 / rrb->cpp; + macroblkxs = 256 / rrb->cpp; + nmacroblkpl = rrb->pitch / macroblkxs; + offset += ((y >> 3) * nmacroblkpl) << 11; + offset += (y & 7) << 8; + offset += (x / macroblkxs) << 11; + offset += ((x & (macroblkxs - 1)) / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } + } else { + microblkxs = 32 / rrb->cpp; + nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5; + offset += (y * nmicroblkpl) << 5; + offset += (x / microblkxs) << 5; + offset += (x & (microblkxs - 1)) * rrb->cpp; + } + } + return &ptr[offset]; +} + + /* * Note that all information needed to access pixels in a renderbuffer * should be obtained through the gl_renderbuffer parameter, not per-context @@ -215,6 +355,88 @@ do { \ #define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" + +static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) +{ + struct radeon_renderbuffer *rrb = (void*)rb; + int r; + + if (rrb->bo) { + r = radeon_bo_map(rrb->bo, write); + if (r) { + fprintf(stderr, "(%s) error(%d) mapping buffer.\n", + __FUNCTION__, r); + } + } +} + +static void unmap_buffer(struct gl_renderbuffer *rb) +{ + struct radeon_renderbuffer *rrb = (void*)rb; + + if (rrb->bo) { + radeon_bo_unmap(rrb->bo); + } +} + +static void radeonSpanRenderStart(GLcontext * ctx) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + int i; + + radeon_firevertices(rmesa); + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + + /* color draw buffers */ + for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { + map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); + } + + map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); + + if (ctx->DrawBuffer->_DepthBuffer) { + map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); + } + if (ctx->DrawBuffer->_StencilBuffer) + map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); + + /* The locking and wait for idle should really only be needed in classic mode. + * In a future memory manager based implementation, this should become + * unnecessary due to the fact that mapping our buffers, textures, etc. + * should implicitly wait for any previous rendering commands that must + * be waited on. */ + LOCK_HARDWARE(rmesa); + radeonWaitForIdleLocked(rmesa); +} + +static void radeonSpanRenderFinish(GLcontext * ctx) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + int i; + _swrast_flush(ctx); + UNLOCK_HARDWARE(rmesa); + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + + /* color draw buffers */ + for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) + unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); + + unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); + + if (ctx->DrawBuffer->_DepthBuffer) + unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); + if (ctx->DrawBuffer->_StencilBuffer) + unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); +} + void radeonInitSpanFuncs(GLcontext * ctx) { struct swrast_device_driver *swdd = diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 7f90bc8090b..86d872030bc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" -#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_tcl.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 1cfb539e713..a397c0824fa 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -38,7 +38,6 @@ #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" -#include "common_cmdbuf.h" #include "radeon_cs.h" #include "radeon_mipmap_tree.h" #include "radeon_ioctl.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 995ab2099e4..af933a35f2b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "radeon_context.h" -#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_swtcl.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 7281800ce2f..5887ab355d2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -42,8 +42,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/tnl.h" #include "tnl/t_pipeline.h" +#include "radeon_common.h" #include "radeon_context.h" -#include "common_cmdbuf.h" #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_tex.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c new file mode 100644 index 00000000000..beb21e7b431 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -0,0 +1,849 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/context.h" +#include "main/mipmap.h" +#include "main/texformat.h" +#include "main/texstore.h" +#include "main/teximage.h" +#include "main/texobj.h" + +#include "xmlpool.h" /* for symbolic values of enum-type options */ + +#include "radeon_common.h" + +#include "radeon_mipmap_tree.h" + +/* textures */ +/** + * Allocate an empty texture image object. + */ +struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx) +{ + return CALLOC(sizeof(radeon_texture_image)); +} + +/** + * Free memory associated with this texture image. + */ +void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) +{ + radeon_texture_image* image = get_radeon_texture_image(timage); + + if (image->mt) { + radeon_miptree_unreference(image->mt); + image->mt = 0; + assert(!image->base.Data); + } else { + _mesa_free_texture_image_data(ctx, timage); + } + if (image->bo) { + radeon_bo_unref(image->bo); + image->bo = NULL; + } + if (timage->Data) { + _mesa_free_texmemory(timage->Data); + timage->Data = NULL; + } +} + +/* Set Data pointer and additional data for mapped texture image */ +static void teximage_set_map_data(radeon_texture_image *image) +{ + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + + image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; + image->base.RowStride = lvl->rowstride / image->mt->bpp; +} + + +/** + * Map a single texture image for glTexImage and friends. + */ +void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable) +{ + if (image->mt) { + assert(!image->base.Data); + + radeon_bo_map(image->mt->bo, write_enable); + teximage_set_map_data(image); + } +} + + +void radeon_teximage_unmap(radeon_texture_image *image) +{ + if (image->mt) { + assert(image->base.Data); + + image->base.Data = 0; + radeon_bo_unmap(image->mt->bo); + } +} + +/** + * Map a validated texture for reading during software rendering. + */ +void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + int face, level; + + /* for r100 3D sw fallbacks don't have mt */ + if (!t->mt) + return; + + radeon_bo_map(t->mt->bo, GL_FALSE); + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level])); + } +} + +void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + int face, level; + + /* for r100 3D sw fallbacks don't have mt */ + if (!t->mt) + return; + + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + texObj->Image[face][level]->Data = 0; + } + radeon_bo_unmap(t->mt->bo); +} + +GLuint radeon_face_for_target(GLenum target) +{ + switch (target) { + case GL_TEXTURE_CUBE_MAP_POSITIVE_X: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: + case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: + case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: + return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; + default: + return 0; + } +} + +/** + * Wraps Mesa's implementation to ensure that the base level image is mapped. + * + * This relies on internal details of _mesa_generate_mipmap, in particular + * the fact that the memory for recreated texture images is always freed. + */ +static void radeon_generate_mipmap(GLcontext *ctx, GLenum target, + struct gl_texture_object *texObj) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; + int i, face; + + + _mesa_generate_mipmap(ctx, target, texObj); + + for (face = 0; face < nr_faces; face++) { + for (i = texObj->BaseLevel + 1; i < texObj->MaxLevel; i++) { + radeon_texture_image *image; + + image = get_radeon_texture_image(texObj->Image[face][i]); + + if (image == NULL) + break; + + image->mtlevel = i; + image->mtface = face; + + radeon_miptree_unreference(image->mt); + image->mt = NULL; + } + } + +} + +void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj) +{ + GLuint face = radeon_face_for_target(target); + radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]); + + radeon_teximage_map(baseimage, GL_FALSE); + radeon_generate_mipmap(ctx, target, texObj); + radeon_teximage_unmap(baseimage); +} + + +/* try to find a format which will only need a memcopy */ +static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, + GLenum srcFormat, + GLenum srcType) +{ + const GLuint ui = 1; + const GLubyte littleEndian = *((const GLubyte *)&ui); + + /* r100 can only do this */ + if (IS_R100_CLASS(rmesa->radeonScreen)) + return _dri_texformat_argb8888; + + if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { + return &_mesa_texformat_rgba8888; + } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { + return &_mesa_texformat_rgba8888_rev; + } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8)) { + return &_mesa_texformat_argb8888_rev; + } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { + return &_mesa_texformat_argb8888; + } else + return _dri_texformat_argb8888; +} + +const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + const GLboolean do32bpt = + (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32); + const GLboolean force16bpt = + (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16); + (void)format; + +#if 0 + fprintf(stderr, "InternalFormat=%s(%d) type=%s format=%s\n", + _mesa_lookup_enum_by_nr(internalFormat), internalFormat, + _mesa_lookup_enum_by_nr(type), _mesa_lookup_enum_by_nr(format)); + fprintf(stderr, "do32bpt=%d force16bpt=%d\n", do32bpt, force16bpt); +#endif + + switch (internalFormat) { + case 4: + case GL_RGBA: + case GL_COMPRESSED_RGBA: + switch (type) { + case GL_UNSIGNED_INT_10_10_10_2: + case GL_UNSIGNED_INT_2_10_10_10_REV: + return do32bpt ? _dri_texformat_argb8888 : + _dri_texformat_argb1555; + case GL_UNSIGNED_SHORT_4_4_4_4: + case GL_UNSIGNED_SHORT_4_4_4_4_REV: + return _dri_texformat_argb4444; + case GL_UNSIGNED_SHORT_5_5_5_1: + case GL_UNSIGNED_SHORT_1_5_5_5_REV: + return _dri_texformat_argb1555; + default: + return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type) : + _dri_texformat_argb4444; + } + + case 3: + case GL_RGB: + case GL_COMPRESSED_RGB: + switch (type) { + case GL_UNSIGNED_SHORT_4_4_4_4: + case GL_UNSIGNED_SHORT_4_4_4_4_REV: + return _dri_texformat_argb4444; + case GL_UNSIGNED_SHORT_5_5_5_1: + case GL_UNSIGNED_SHORT_1_5_5_5_REV: + return _dri_texformat_argb1555; + case GL_UNSIGNED_SHORT_5_6_5: + case GL_UNSIGNED_SHORT_5_6_5_REV: + return _dri_texformat_rgb565; + default: + return do32bpt ? _dri_texformat_argb8888 : + _dri_texformat_rgb565; + } + + case GL_RGBA8: + case GL_RGB10_A2: + case GL_RGBA12: + case GL_RGBA16: + return !force16bpt ? + radeonChoose8888TexFormat(rmesa, format,type) : + _dri_texformat_argb4444; + + case GL_RGBA4: + case GL_RGBA2: + return _dri_texformat_argb4444; + + case GL_RGB5_A1: + return _dri_texformat_argb1555; + + case GL_RGB8: + case GL_RGB10: + case GL_RGB12: + case GL_RGB16: + return !force16bpt ? _dri_texformat_argb8888 : + _dri_texformat_rgb565; + + case GL_RGB5: + case GL_RGB4: + case GL_R3_G3_B2: + return _dri_texformat_rgb565; + + case GL_ALPHA: + case GL_ALPHA4: + case GL_ALPHA8: + case GL_ALPHA12: + case GL_ALPHA16: + case GL_COMPRESSED_ALPHA: + return _dri_texformat_a8; + + case 1: + case GL_LUMINANCE: + case GL_LUMINANCE4: + case GL_LUMINANCE8: + case GL_LUMINANCE12: + case GL_LUMINANCE16: + case GL_COMPRESSED_LUMINANCE: + return _dri_texformat_l8; + + case 2: + case GL_LUMINANCE_ALPHA: + case GL_LUMINANCE4_ALPHA4: + case GL_LUMINANCE6_ALPHA2: + case GL_LUMINANCE8_ALPHA8: + case GL_LUMINANCE12_ALPHA4: + case GL_LUMINANCE12_ALPHA12: + case GL_LUMINANCE16_ALPHA16: + case GL_COMPRESSED_LUMINANCE_ALPHA: + return _dri_texformat_al88; + + case GL_INTENSITY: + case GL_INTENSITY4: + case GL_INTENSITY8: + case GL_INTENSITY12: + case GL_INTENSITY16: + case GL_COMPRESSED_INTENSITY: + return _dri_texformat_i8; + + case GL_YCBCR_MESA: + if (type == GL_UNSIGNED_SHORT_8_8_APPLE || + type == GL_UNSIGNED_BYTE) + return &_mesa_texformat_ycbcr; + else + return &_mesa_texformat_ycbcr_rev; + + case GL_RGB_S3TC: + case GL_RGB4_S3TC: + case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: + return &_mesa_texformat_rgb_dxt1; + + case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: + return &_mesa_texformat_rgba_dxt1; + + case GL_RGBA_S3TC: + case GL_RGBA4_S3TC: + case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: + return &_mesa_texformat_rgba_dxt3; + + case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: + return &_mesa_texformat_rgba_dxt5; + + case GL_ALPHA16F_ARB: + return &_mesa_texformat_alpha_float16; + case GL_ALPHA32F_ARB: + return &_mesa_texformat_alpha_float32; + case GL_LUMINANCE16F_ARB: + return &_mesa_texformat_luminance_float16; + case GL_LUMINANCE32F_ARB: + return &_mesa_texformat_luminance_float32; + case GL_LUMINANCE_ALPHA16F_ARB: + return &_mesa_texformat_luminance_alpha_float16; + case GL_LUMINANCE_ALPHA32F_ARB: + return &_mesa_texformat_luminance_alpha_float32; + case GL_INTENSITY16F_ARB: + return &_mesa_texformat_intensity_float16; + case GL_INTENSITY32F_ARB: + return &_mesa_texformat_intensity_float32; + case GL_RGB16F_ARB: + return &_mesa_texformat_rgba_float16; + case GL_RGB32F_ARB: + return &_mesa_texformat_rgba_float32; + case GL_RGBA16F_ARB: + return &_mesa_texformat_rgba_float16; + case GL_RGBA32F_ARB: + return &_mesa_texformat_rgba_float32; + + case GL_DEPTH_COMPONENT: + case GL_DEPTH_COMPONENT16: + case GL_DEPTH_COMPONENT24: + case GL_DEPTH_COMPONENT32: +#if 0 + switch (type) { + case GL_UNSIGNED_BYTE: + case GL_UNSIGNED_SHORT: + return &_mesa_texformat_z16; + case GL_UNSIGNED_INT: + return &_mesa_texformat_z32; + case GL_UNSIGNED_INT_24_8_EXT: + default: + return &_mesa_texformat_z24_s8; + } +#else + return &_mesa_texformat_z16; +#endif + + default: + _mesa_problem(ctx, + "unexpected internalFormat 0x%x in r300ChooseTextureFormat", + (int)internalFormat); + return NULL; + } + + return NULL; /* never get here */ +} + +/** + * All glTexImage calls go through this function. + */ +static void radeon_teximage( + GLcontext *ctx, int dims, + GLint face, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLsizei imageSize, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj* t = radeon_tex_obj(texObj); + radeon_texture_image* image = get_radeon_texture_image(texImage); + + radeon_firevertices(rmesa); + + t->validated = GL_FALSE; + + /* Choose and fill in the texture format for this image */ + texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type); + _mesa_set_fetch_functions(texImage, dims); + + if (texImage->TexFormat->TexelBytes == 0) { + texImage->IsCompressed = GL_TRUE; + texImage->CompressedSize = + ctx->Driver.CompressedTextureSize(ctx, texImage->Width, + texImage->Height, texImage->Depth, + texImage->TexFormat->MesaFormat); + } else { + texImage->IsCompressed = GL_FALSE; + texImage->CompressedSize = 0; + } + + /* Allocate memory for image */ + radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ + + if (!t->mt) + radeon_try_alloc_miptree(rmesa, t, texImage, face, level); + if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { + image->mt = t->mt; + image->mtlevel = level - t->mt->firstLevel; + image->mtface = face; + radeon_miptree_reference(t->mt); + } else { + int size; + if (texImage->IsCompressed) { + size = texImage->CompressedSize; + } else { + size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; + } + texImage->Data = _mesa_alloc_texmemory(size); + } + + /* Upload texture image; note that the spec allows pixels to be NULL */ + if (compressed) { + pixels = _mesa_validate_pbo_compressed_teximage( + ctx, imageSize, pixels, packing, "glCompressedTexImage"); + } else { + pixels = _mesa_validate_pbo_teximage( + ctx, dims, width, height, depth, + format, type, pixels, packing, "glTexImage"); + } + + if (pixels) { + radeon_teximage_map(image, GL_TRUE); + + if (compressed) { + memcpy(texImage->Data, pixels, imageSize); + } else { + GLuint dstRowStride; + if (image->mt) { + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; + } + if (!texImage->TexFormat->StoreImage(ctx, dims, + texImage->_BaseFormat, + texImage->TexFormat, + texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */ + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); + } + + } + + /* SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + radeon_generate_mipmap(ctx, texObj->Target, texObj); + } + + if (pixels) + radeon_teximage_unmap(image); + + _mesa_unmap_teximage_pbo(ctx, packing); + + +} + +void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_teximage(ctx, 1, 0, level, internalFormat, width, 1, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); +} + +void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) + +{ + GLuint face = radeon_face_for_target(target); + + radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); +} + +void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint internalFormat, + GLint width, GLint height, GLint border, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + GLuint face = radeon_face_for_target(target); + + radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, + imageSize, 0, 0, data, 0, texObj, texImage, 1); +} + +void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_teximage(ctx, 3, 0, level, internalFormat, width, height, depth, + 0, format, type, pixels, packing, texObj, texImage, 0); +} + +/** + * Update a subregion of the given texture image. + */ +static void radeon_texsubimage(GLcontext* ctx, int dims, int level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj* t = radeon_tex_obj(texObj); + radeon_texture_image* image = get_radeon_texture_image(texImage); + + radeon_firevertices(rmesa); + + t->validated = GL_FALSE; + pixels = _mesa_validate_pbo_teximage(ctx, dims, + width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); + + if (pixels) { + GLint dstRowStride; + radeon_teximage_map(image, GL_TRUE); + + if (image->mt) { + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes; + } + + if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, + texImage->TexFormat, texImage->Data, + xoffset, yoffset, zoffset, + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); + + + } + + /* GL_SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + radeon_generate_mipmap(ctx, texObj->Target, texObj); + } + radeon_teximage_unmap(image); + + _mesa_unmap_teximage_pbo(ctx, packing); + + +} + +void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, + GLsizei width, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, + format, type, pixels, packing, texObj, texImage, 0); +} + +void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, + 1, format, type, pixels, packing, texObj, texImage, + 0); +} + +void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint xoffset, + GLint yoffset, GLsizei width, + GLsizei height, GLenum format, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, + format, 0, data, 0, texObj, texImage, 1); +} + + +void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, + format, type, pixels, packing, texObj, texImage, 0); +} + +static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, + GLuint numrows, GLuint rowsize) +{ + assert(rowsize <= dststride); + assert(rowsize <= srcstride); + + if (rowsize == srcstride && rowsize == dststride) { + memcpy(dst, src, numrows*rowsize); + } else { + GLuint i; + for(i = 0; i < numrows; ++i) { + memcpy(dst, src, rowsize); + dst += dststride; + src += srcstride; + } + } +} + + +/** + * Ensure that the given image is stored in the given miptree from now on. + */ +static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level) +{ + radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; + unsigned char *dest; + + assert(image->mt != mt); + assert(dstlvl->width == image->base.Width); + assert(dstlvl->height == image->base.Height); + assert(dstlvl->depth == image->base.Depth); + + + radeon_bo_map(mt->bo, GL_TRUE); + dest = mt->bo->ptr + dstlvl->faces[face].offset; + + if (image->mt) { + /* Format etc. should match, so we really just need a memcpy(). + * In fact, that memcpy() could be done by the hardware in many + * cases, provided that we have a proper memory manager. + */ + radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; + + assert(srclvl->size == dstlvl->size); + assert(srclvl->rowstride == dstlvl->rowstride); + + radeon_bo_map(image->mt->bo, GL_FALSE); + + memcpy(dest, + image->mt->bo->ptr + srclvl->faces[face].offset, + dstlvl->size); + radeon_bo_unmap(image->mt->bo); + + radeon_miptree_unreference(image->mt); + } else { + uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; + +// if (mt->tilebits) +// WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); + + copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, + image->base.Height * image->base.Depth, srcrowstride); + + _mesa_free_texmemory(image->base.Data); + image->base.Data = 0; + } + + radeon_bo_unmap(mt->bo); + + image->mt = mt; + image->mtface = face; + image->mtlevel = level; + radeon_miptree_reference(image->mt); +} + +int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj *t = radeon_tex_obj(texObj); + radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]); + int face, level; + + if (t->validated || t->image_override) + return GL_TRUE; + + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj); + + if (baseimage->base.Border > 0) + return GL_FALSE; + + /* Ensure a matching miptree exists. + * + * Differing mipmap trees can result when the app uses TexImage to + * change texture dimensions. + * + * Prefer to use base image's miptree if it + * exists, since that most likely contains more valid data (remember + * that the base level is usually significantly larger than the rest + * of the miptree, so cubemaps are the only possible exception). + */ + if (baseimage->mt && + baseimage->mt != t->mt && + radeon_miptree_matches_texture(baseimage->mt, &t->base)) { + radeon_miptree_unreference(t->mt); + t->mt = baseimage->mt; + radeon_miptree_reference(t->mt); + } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + } + + if (!t->mt) { + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, " Allocate new miptree\n"); + radeon_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel); + if (!t->mt) { + _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree"); + return GL_FALSE; + } + } + + /* Ensure all images are stored in the single main miptree */ + for(face = 0; face < t->mt->faces; ++face) { + for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { + radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, " face %i, level %i... %p vs %p ", face, level, t->mt, image->mt); + if (t->mt == image->mt) { + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "OK\n"); + continue; + } + + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "migrating\n"); + migrate_image_to_miptree(t->mt, image, face, level); + } + } + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h new file mode 100644 index 00000000000..ff0e1d061ed --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_texture.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RADEON_TEXTURE_H +#define RADEON_TEXTURE_H +struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx); +void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage); + +void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable); +void radeon_teximage_unmap(radeon_texture_image *image); +void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj); +void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); +void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); +int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); +GLuint radeon_face_for_target(GLenum target); +const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type); + +void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint internalFormat, + GLint width, GLint height, GLint border, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, + GLsizei width, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint xoffset, + GLint yoffset, GLsizei width, + GLsizei height, GLenum format, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); + +void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +#endif -- cgit v1.2.3 From 8cb16e6daff40bbfd7b63a43da72862226a4a164 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 22:48:18 +1000 Subject: r200/r300: get up to speed on renamed files --- src/mesa/drivers/dri/r200/Makefile | 39 ++++++++++++-------- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 3 +- src/mesa/drivers/dri/r200/r200_context.h | 7 ++-- src/mesa/drivers/dri/r200/r200_ioctl.c | 5 ++- src/mesa/drivers/dri/r200/r200_ioctl.h | 3 -- src/mesa/drivers/dri/r200/r200_lock.h | 40 --------------------- src/mesa/drivers/dri/r200/r200_state_init.c | 4 +-- src/mesa/drivers/dri/r200/r200_texstate.c | 4 +-- src/mesa/drivers/dri/r300/Makefile | 36 ++++++++++++------- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 4 --- src/mesa/drivers/dri/r300/r300_context.h | 3 +- src/mesa/drivers/dri/r300/r300_ioctl.c | 3 +- src/mesa/drivers/dri/r300/r300_render.c | 3 +- src/mesa/drivers/dri/r300/radeon_lock.h | 48 +------------------------ src/mesa/drivers/dri/r300/radeon_program_pair.c | 2 +- 15 files changed, 63 insertions(+), 141 deletions(-) delete mode 100644 src/mesa/drivers/dri/r200/r200_lock.h mode change 100644 => 120000 src/mesa/drivers/dri/r300/radeon_lock.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index b87e9f206c7..4f626c0584f 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -11,6 +11,17 @@ ifeq ($(USING_EGL), 1) EGL_SOURCES = server/radeon_egl.c endif +RADEON_COMMON_SOURCES = \ + radeon_texture.c \ + radeon_common_context.c \ + radeon_dma.c \ + radeon_lock.c \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ + radeon_mipmap_tree.c \ + radeon_span.c + + DRIVER_SOURCES = r200_context.c \ r200_ioctl.c \ r200_state.c \ @@ -26,13 +37,8 @@ DRIVER_SOURCES = r200_context.c \ r200_fragshader.c \ r200_vertprog.c \ radeon_screen.c \ - common_lock.c \ - common_misc.c \ - radeon_bo_legacy.c \ - radeon_cs_legacy.c \ - radeon_mipmap_tree.c \ - radeon_span.c \ - $(EGL_SOURCES) + $(EGL_SOURCES) \ + $(RADEON_COMMON_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -59,14 +65,19 @@ COMMON_SYMLINKS = \ radeon_span.h \ radeon_span.c \ radeon_buffer.h \ - common_context.h \ - common_lock.c \ - common_lock.h \ - common_misc.h \ - common_misc.c \ - common_cmdbuf.h \ + radeon_lock.c \ + radeon_lock.h \ + radeon_common.c \ + radeon_common_context.c \ + radeon_common_context.h \ + radeon_common.h \ + radeon_cmdbuf.h \ radeon_mipmap_tree.c \ - radeon_mipmap_tree.h + radeon_mipmap_tree.h \ + radeon_texture.c \ + radeon_texture.h \ + radeon_dma.c \ + radeon_dma.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index aa64232a93b..cb1bd8be956 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -38,9 +38,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "main/simple_list.h" -#include "radeon_cs.h" +#include "radeon_common.h" #include "r200_context.h" -#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 96f47ea92bb..fcbe725d6fc 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -54,15 +54,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #include "radeon_screen.h" -#include "common_context.h" -#include "common_misc.h" +#include "radeon_common.h" + +#include "radeon_lock.h" struct r200_context; typedef struct r200_context r200ContextRec; typedef struct r200_context *r200ContextPtr; -#include "r200_lock.h" - #include "main/mm.h" struct r200_vertex_program { diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 8f64c8c6d90..e19ff44bc8e 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -41,10 +41,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" -#include "radeon_cs.h" +#include "radeon_common.h" +#include "radeon_lock.h" #include "r200_context.h" - -#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 6b114971c3d..777fdc38a53 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -37,7 +37,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/simple_list.h" #include "radeon_dri.h" -#include "r200_lock.h" #include "radeon_cs_legacy.h" @@ -45,8 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" -#include "common_cmdbuf.h" - extern void r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, diff --git a/src/mesa/drivers/dri/r200/r200_lock.h b/src/mesa/drivers/dri/r200/r200_lock.h deleted file mode 100644 index 29cad5b226b..00000000000 --- a/src/mesa/drivers/dri/r200/r200_lock.h +++ /dev/null @@ -1,40 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#ifndef __R200_LOCK_H__ -#define __R200_LOCK_H__ - -#include "common_lock.h" - -#endif /* __R200_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index d11baacae95..3cd2dc77512 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -43,10 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" -#include "radeon_buffer.h" +#include "radeon_common.h" #include "radeon_mipmap_tree.h" -#include "radeon_cs.h" -#include "common_misc.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 12b828846f4..03404b6eb19 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -40,7 +40,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/texobj.h" #include "main/enums.h" -#include "common_context.h" +#include "radeon_common.h" #include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_state.h" @@ -1411,7 +1411,7 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object return GL_TRUE; } -GLboolean r200UpdateTextureUnit(GLcontext *ctx, int unit) +static GLboolean r200UpdateTextureUnit(GLcontext *ctx, int unit) { r200ContextPtr rmesa = R200_CONTEXT(ctx); GLuint unitneeded = rmesa->state.texture.unit[unit].unitneeded; diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index abdd1da490e..e9264ce77a2 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -20,13 +20,18 @@ COMMON_SOURCES = \ ../common/xmlconfig.c \ ../common/dri_util.c +RADEON_COMMON_SOURCES = \ + radeon_texture.c \ + radeon_common_context.c \ + radeon_dma.c \ + radeon_lock.c \ + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ + radeon_mipmap_tree.c \ + radeon_span.c + DRIVER_SOURCES = \ - radeon_bo_legacy.c \ - radeon_cs_legacy.c \ radeon_screen.c \ - common_lock.c \ - common_misc.c \ - radeon_span.c \ r300_ioctl.c \ r300_cmdbuf.c \ r300_state.c \ @@ -46,7 +51,7 @@ DRIVER_SOURCES = \ r300_shader.c \ r300_emit.c \ r300_swtcl.c \ - radeon_mipmap_tree.c \ + $(RADEON_COMMON_SOURCES) \ $(EGL_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -75,14 +80,19 @@ COMMON_SYMLINKS = \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ radeon_cs_legacy.h \ - common_context.h \ - common_lock.c \ - common_lock.h \ - common_misc.c \ - common_misc.h \ - common_cmdbuf.h \ + radeon_lock.c \ + radeon_lock.h \ + radeon_common.c \ + radeon_common.h \ + radeon_common_context.c \ + radeon_common_context.h \ + radeon_cmdbuf.h \ + radeon_dma.c \ + radeon_dma.h \ radeon_mipmap_tree.c \ - radeon_mipmap_tree.h + radeon_mipmap_tree.h \ + radeon_texture.c \ + radeon_texture.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index d8a1076e72b..ab5d50f58e8 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -39,10 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "radeon_cs.h" -#include "common_cmdbuf.h" - -extern void r300EmitState(r300ContextPtr r300); - extern void r300InitCmdBuf(r300ContextPtr r300); extern void r300DestroyCmdBuf(r300ContextPtr r300); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 75393bcd14c..0be3657249e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -42,8 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "dri_util.h" #include "texmem.h" -#include "common_context.h" -#include "radeon_context.h" +#include "radeon_common.h" #include "radeon_bo.h" #include "main/macros.h" diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index ee334150951..90b85f0df75 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -46,7 +46,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" -#include "radeon_buffer.h" +#include "radeon_common.h" +#include "radeon_lock.h" #include "r300_context.h" #include "r300_ioctl.h" #include "r300_cmdbuf.h" diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 393bf754ff2..8055952a768 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -334,7 +334,6 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, int start, int end, int prim) { - BATCH_LOCALS(&rmesa->radeon); int type, num_verts; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; @@ -396,7 +395,7 @@ static GLboolean r300RunRender(GLcontext * ctx, r300UpdateShaderStates(rmesa); r300EmitCacheFlush(rmesa); - r300EmitState(rmesa); + radeonEmitState(&rmesa->radeon); for (i = 0; i < vb->PrimitiveCount; i++) { GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h deleted file mode 100644 index f2d17a54d47..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ /dev/null @@ -1,47 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Gareth Hughes - * Keith Whitwell - * Kevin E. Martin - */ - -#ifndef __RADEON_LOCK_H__ -#define __RADEON_LOCK_H__ - -#include "common_lock.h" - -#endif /* __RADEON_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h new file mode 120000 index 00000000000..64bdf94ee7e --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_lock.h @@ -0,0 +1 @@ +../radeon/radeon_lock.h \ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_program_pair.c b/src/mesa/drivers/dri/r300/radeon_program_pair.c index 5ad50d2863a..a6da9f56b5d 100644 --- a/src/mesa/drivers/dri/r300/radeon_program_pair.c +++ b/src/mesa/drivers/dri/r300/radeon_program_pair.c @@ -35,7 +35,7 @@ #include "radeon_program_pair.h" -#include "radeon_context.h" +#include "radeon_common.h" #include "shader/prog_print.h" -- cgit v1.2.3 From dc8a707c672918b88dd4135930bef60ed148d8ce Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 23:52:51 +1000 Subject: radeon/r200/r300: make build with out libdrm_radeon installed for now --- src/mesa/drivers/dri/r200/Makefile | 2 +- src/mesa/drivers/dri/r200/r200_ioctl.h | 2 +- src/mesa/drivers/dri/r200/r200_state.c | 3 +- src/mesa/drivers/dri/r200/r200_swtcl.c | 1 - src/mesa/drivers/dri/r300/Makefile | 2 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 4 +- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 1 - src/mesa/drivers/dri/r300/r300_context.c | 2 +- src/mesa/drivers/dri/r300/r300_context.h | 1 - src/mesa/drivers/dri/r300/r300_state.c | 1 - src/mesa/drivers/dri/r300/r300_texstate.c | 2 - src/mesa/drivers/dri/radeon/radeon_bo_drm.h | 179 +++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 4 +- src/mesa/drivers/dri/radeon/radeon_bo_legacy.h | 1 - src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 35 ++++ src/mesa/drivers/dri/radeon/radeon_buffer.h | 49 ----- src/mesa/drivers/dri/radeon/radeon_cmdbuf.h | 2 +- src/mesa/drivers/dri/radeon/radeon_common.c | 8 +- src/mesa/drivers/dri/radeon/radeon_common.h | 1 - .../drivers/dri/radeon/radeon_common_context.h | 16 ++ src/mesa/drivers/dri/radeon/radeon_cs_drm.h | 198 +++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 5 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.h | 1 - src/mesa/drivers/dri/radeon/radeon_ioctl.c | 1 - src/mesa/drivers/dri/radeon/radeon_ioctl.h | 2 +- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 2 - src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +- src/mesa/drivers/dri/radeon/radeon_screen.h | 1 - src/mesa/drivers/dri/radeon/radeon_span.c | 2 - src/mesa/drivers/dri/radeon/radeon_span.h | 2 - src/mesa/drivers/dri/radeon/radeon_state_init.c | 1 - 31 files changed, 442 insertions(+), 94 deletions(-) create mode 100644 src/mesa/drivers/dri/radeon/radeon_bo_drm.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h delete mode 100644 src/mesa/drivers/dri/radeon/radeon_buffer.h create mode 100644 src/mesa/drivers/dri/radeon/radeon_cs_drm.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 4f626c0584f..7b5fe955776 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -62,9 +62,9 @@ COMMON_SYMLINKS = \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ radeon_cs_legacy.h \ + radeon_bocs_wrapper.h \ radeon_span.h \ radeon_span.c \ - radeon_buffer.h \ radeon_lock.c \ radeon_lock.h \ radeon_common.c \ diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 777fdc38a53..950478e762e 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/simple_list.h" #include "radeon_dri.h" -#include "radeon_cs_legacy.h" +#include "radeon_bocs_wrapper.h" #include "xf86drm.h" #include "drm.h" diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 84b0d90c69f..559985bc3fb 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -47,8 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" -#include "radeon_buffer.h" -#include "radeon_cs.h" +#include "radeon_common.h" #include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_ioctl.h" diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index df786561e17..b006409987a 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -48,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "tnl/t_pipeline.h" -#include "radeon_bo.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index e9264ce77a2..20ee195fe7b 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -75,11 +75,11 @@ COMMON_SYMLINKS = \ radeon_screen.h \ radeon_span.h \ radeon_span.c \ - radeon_buffer.h \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ radeon_cs_legacy.h \ + radeon_bocs_wrapper.h \ radeon_lock.c \ radeon_lock.h \ radeon_common.c \ diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index d6acb39d9f9..29b2c2eb25c 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -44,17 +44,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" -#include "radeon_buffer.h" #include "r300_context.h" #include "r300_ioctl.h" #include "radeon_reg.h" #include "r300_reg.h" #include "r300_cmdbuf.h" #include "r300_emit.h" +#include "radeon_bocs_wrapper.h" #include "radeon_mipmap_tree.h" #include "r300_state.h" -#include "radeon_cs_legacy.h" -#include "radeon_cs_gem.h" #include "radeon_reg.h" #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index ab5d50f58e8..b7798eb97b3 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -37,7 +37,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define __R300_CMDBUF_H__ #include "r300_context.h" -#include "radeon_cs.h" extern void r300InitCmdBuf(r300ContextPtr r300); extern void r300DestroyCmdBuf(r300ContextPtr r300); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index e4dc37debc2..449252a9309 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -63,7 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_tex.h" #include "r300_emit.h" #include "r300_swtcl.h" -#include "radeon_bo_legacy.h" +#include "radeon_bocs_wrapper.h" #include "vblank.h" diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 0be3657249e..6d3472722da 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -43,7 +43,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "dri_util.h" #include "texmem.h" #include "radeon_common.h" -#include "radeon_bo.h" #include "main/macros.h" #include "main/mtypes.h" diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 4258a610000..fe58ac00a8a 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -53,7 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vbo/vbo.h" #include "tnl/tnl.h" -#include "radeon_buffer.h" #include "r300_context.h" #include "r300_ioctl.h" #include "r300_state.h" diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 50ecc570bd1..e5afff0d61c 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -48,10 +48,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_ioctl.h" #include "radeon_mipmap_tree.h" -#include "radeon_cs.h" #include "r300_tex.h" #include "r300_reg.h" -#include "radeon_buffer.h" #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5 \ || ((f) >= MESA_FORMAT_RGBA_FLOAT32 && \ diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h new file mode 100644 index 00000000000..3cabdfc4e81 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h @@ -0,0 +1,179 @@ +/* + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Jérôme Glisse + */ +#ifndef RADEON_BO_H +#define RADEON_BO_H + +#include +#include +#include "radeon_track.h" + +/* bo object */ +#define RADEON_BO_FLAGS_MACRO_TILE 1 +#define RADEON_BO_FLAGS_MICRO_TILE 2 + +struct radeon_bo_manager; + +struct radeon_bo { + uint32_t alignment; + uint32_t handle; + uint32_t size; + uint32_t domains; + uint32_t flags; + unsigned cref; +#ifdef RADEON_BO_TRACK + struct radeon_track *track; +#endif + void *ptr; + struct radeon_bo_manager *bom; + uint32_t space_accounted; +}; + +/* bo functions */ +struct radeon_bo_funcs { + struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t domains, + uint32_t flags); + void (*bo_ref)(struct radeon_bo *bo); + struct radeon_bo *(*bo_unref)(struct radeon_bo *bo); + int (*bo_map)(struct radeon_bo *bo, int write); + int (*bo_unmap)(struct radeon_bo *bo); + int (*bo_wait)(struct radeon_bo *bo); +}; + +struct radeon_bo_manager { + struct radeon_bo_funcs *funcs; + int fd; + struct radeon_tracker tracker; +}; + +static inline void _radeon_bo_debug(struct radeon_bo *bo, + const char *op, + const char *file, + const char *func, + int line) +{ + fprintf(stderr, "%s %p 0x%08X 0x%08X 0x%08X [%s %s %d]\n", + op, bo, bo->handle, bo->size, bo->cref, file, func, line); +} + +static inline struct radeon_bo *_radeon_bo_open(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t domains, + uint32_t flags, + const char *file, + const char *func, + int line) +{ + struct radeon_bo *bo; + + bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags); +#ifdef RADEON_BO_TRACK + if (bo) { + bo->track = radeon_tracker_add_track(&bom->tracker, bo->handle); + radeon_track_add_event(bo->track, file, func, "open", line); + } +#endif + return bo; +} + +static inline void _radeon_bo_ref(struct radeon_bo *bo, + const char *file, + const char *func, + int line) +{ + bo->cref++; +#ifdef RADEON_BO_TRACK + radeon_track_add_event(bo->track, file, func, "ref", line); +#endif + bo->bom->funcs->bo_ref(bo); +} + +static inline struct radeon_bo *_radeon_bo_unref(struct radeon_bo *bo, + const char *file, + const char *func, + int line) +{ + bo->cref--; +#ifdef RADEON_BO_TRACK + radeon_track_add_event(bo->track, file, func, "unref", line); + if (bo->cref <= 0) { + radeon_tracker_remove_track(&bo->bom->tracker, bo->track); + bo->track = NULL; + } +#endif + return bo->bom->funcs->bo_unref(bo); +} + +static inline int _radeon_bo_map(struct radeon_bo *bo, + int write, + const char *file, + const char *func, + int line) +{ + return bo->bom->funcs->bo_map(bo, write); +} + +static inline int _radeon_bo_unmap(struct radeon_bo *bo, + const char *file, + const char *func, + int line) +{ + return bo->bom->funcs->bo_unmap(bo); +} + +static inline int _radeon_bo_wait(struct radeon_bo *bo, + const char *file, + const char *func, + int line) +{ + return bo->bom->funcs->bo_wait(bo); +} + +#define radeon_bo_open(bom, h, s, a, d, f)\ + _radeon_bo_open(bom, h, s, a, d, f, __FILE__, __FUNCTION__, __LINE__) +#define radeon_bo_ref(bo)\ + _radeon_bo_ref(bo, __FILE__, __FUNCTION__, __LINE__) +#define radeon_bo_unref(bo)\ + _radeon_bo_unref(bo, __FILE__, __FUNCTION__, __LINE__) +#define radeon_bo_map(bo, w)\ + _radeon_bo_map(bo, w, __FILE__, __FUNCTION__, __LINE__) +#define radeon_bo_unmap(bo)\ + _radeon_bo_unmap(bo, __FILE__, __FUNCTION__, __LINE__) +#define radeon_bo_debug(bo, opcode)\ + _radeon_bo_debug(bo, opcode, __FILE__, __FUNCTION__, __LINE__) +#define radeon_bo_wait(bo) \ + _radeon_bo_wait(bo, __FILE__, __func__, __LINE__) + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index b7658353af0..1d25887e691 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -45,9 +45,9 @@ #include "drm.h" #include "radeon_drm.h" -#include "radeon_bo.h" -#include "radeon_bo_legacy.h" #include "radeon_common.h" +#include "radeon_bocs_wrapper.h" + struct bo_legacy { struct radeon_bo base; diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h index 575979cbecc..9187cd72013 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h @@ -32,7 +32,6 @@ #ifndef RADEON_BO_LEGACY_H #define RADEON_BO_LEGACY_H -#include "radeon_bo.h" #include "radeon_screen.h" void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending); diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h new file mode 100644 index 00000000000..36dea3be7bd --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -0,0 +1,35 @@ +#ifndef RADEON_CS_WRAPPER_H +#define RADEON_CS_WRAPPER_H + +#ifdef HAVE_LIBDRM_RADEON + +#include "radeon_bo.h" +#include "radeon_bo_gem.h" +#include "radeon_cs.h" +#include "radeon_cs_gem.h" + +#else +/* to be used to build locally in mesa with no libdrm bits */ +#include "../radeon/radeon_bo_drm.h" +#include "../radeon/radeon_cs_drm.h" + +#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain +#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed +#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain + +static inline void *radeon_bo_manager_gem_ctor(int fd) +{ + return NULL; +} + +static inline void radeon_bo_manager_gem_dtor(void *dummy) +{ +} + + +#endif + +#include "radeon_bo_legacy.h" +#include "radeon_cs_legacy.h" + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h deleted file mode 100644 index 62cdfad4a0c..00000000000 --- a/src/mesa/drivers/dri/radeon/radeon_buffer.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2008 Red Hat, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software") - * to deal in the software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * them Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTIBILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES, OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Adam Jackson - */ - -#ifndef RADEON_BUFFER_H -#define RADEON_BUFFER_H - -#include "radeon_bo.h" -#include "dri_util.h" - -struct radeon_renderbuffer -{ - struct gl_renderbuffer base; - struct radeon_bo *bo; - unsigned int cpp; - /* unsigned int offset; */ - unsigned int pitch; - unsigned int width; - unsigned int height; - - /* boo Xorg 6.8.2 compat */ - int has_surface; - - - __DRIdrawablePrivate *dPriv; -}; - -#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h index 5526934209e..4b5116c4741 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -1,7 +1,7 @@ #ifndef COMMON_CMDBUF_H #define COMMON_CMDBUF_H -#include "radeon_cs.h" +#include "radeon_bocs_wrapper.h" void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 87b6dac40bc..80e8e0d86d4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -63,13 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "radeon_common.h" -#include "radeon_common.h" -#include "radeon_bo.h" -#include "radeon_cs.h" -#include "radeon_bo_legacy.h" -#include "radeon_cs_legacy.h" -#include "radeon_bo_gem.h" -#include "radeon_cs_gem.h" +#include "radeon_bocs_wrapper.h" #include "radeon_drm.h" #include "radeon_mipmap_tree.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index cc9d579ea16..ead0f5551b3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -2,7 +2,6 @@ #define COMMON_MISC_H #include "radeon_common_context.h" -#include "radeon_buffer.h" #include "radeon_dma.h" #include "radeon_texture.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index b88aeab0518..c9be104578e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -68,6 +68,22 @@ typedef struct radeon_context *radeonContextPtr; #include "tnl_dd/t_dd_vertex.h" #undef TAG +struct radeon_renderbuffer +{ + struct gl_renderbuffer base; + struct radeon_bo *bo; + unsigned int cpp; + /* unsigned int offset; */ + unsigned int pitch; + unsigned int width; + unsigned int height; + + /* boo Xorg 6.8.2 compat */ + int has_surface; + + __DRIdrawablePrivate *dPriv; +}; + struct radeon_colorbuffer_state { GLuint clear; int roundEnable; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h new file mode 100644 index 00000000000..7cc75d47004 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h @@ -0,0 +1,198 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#ifndef RADEON_CS_H +#define RADEON_CS_H + +#include +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_bo.h" + +struct radeon_cs_reloc { + struct radeon_bo *bo; + uint32_t read_domain; + uint32_t write_domain; + uint32_t flags; +}; + + +#define RADEON_CS_SPACE_OK 0 +#define RADEON_CS_SPACE_OP_TO_BIG 1 +#define RADEON_CS_SPACE_FLUSH 2 + +struct radeon_cs_space_check { + struct radeon_bo *bo; + uint32_t read_domains; + uint32_t write_domain; + uint32_t new_accounted; +}; + +struct radeon_cs_manager; + +struct radeon_cs { + struct radeon_cs_manager *csm; + void *relocs; + uint32_t *packets; + unsigned crelocs; + unsigned relocs_total_size; + unsigned cdw; + unsigned ndw; + int section; + unsigned section_ndw; + unsigned section_cdw; + const char *section_file; + const char *section_func; + int section_line; + +}; + +/* cs functions */ +struct radeon_cs_funcs { + struct radeon_cs *(*cs_create)(struct radeon_cs_manager *csm, + uint32_t ndw); + int (*cs_write_reloc)(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags); + int (*cs_begin)(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, + int line); + int (*cs_end)(struct radeon_cs *cs, + const char *file, + const char *func, + int line); + int (*cs_emit)(struct radeon_cs *cs); + int (*cs_destroy)(struct radeon_cs *cs); + int (*cs_erase)(struct radeon_cs *cs); + int (*cs_need_flush)(struct radeon_cs *cs); + void (*cs_print)(struct radeon_cs *cs, FILE *file); + int (*cs_space_check)(struct radeon_cs *cs, struct radeon_cs_space_check *bos, + int num_bo); +}; + +struct radeon_cs_manager { + struct radeon_cs_funcs *funcs; + int fd; + uint32_t vram_limit, gart_limit; + uint32_t vram_write_used, gart_write_used; + uint32_t read_used; +}; + +static inline struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm, + uint32_t ndw) +{ + return csm->funcs->cs_create(csm, ndw); +} + +static inline int radeon_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags) +{ + return cs->csm->funcs->cs_write_reloc(cs, + bo, + read_domain, + write_domain, + flags); +} + +static inline int radeon_cs_begin(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, + int line) +{ + return cs->csm->funcs->cs_begin(cs, ndw, file, func, line); +} + +static inline int radeon_cs_end(struct radeon_cs *cs, + const char *file, + const char *func, + int line) +{ + return cs->csm->funcs->cs_end(cs, file, func, line); +} + +static inline int radeon_cs_emit(struct radeon_cs *cs) +{ + return cs->csm->funcs->cs_emit(cs); +} + +static inline int radeon_cs_destroy(struct radeon_cs *cs) +{ + return cs->csm->funcs->cs_destroy(cs); +} + +static inline int radeon_cs_erase(struct radeon_cs *cs) +{ + return cs->csm->funcs->cs_erase(cs); +} + +static inline int radeon_cs_need_flush(struct radeon_cs *cs) +{ + return cs->csm->funcs->cs_need_flush(cs); +} + +static inline void radeon_cs_print(struct radeon_cs *cs, FILE *file) +{ + cs->csm->funcs->cs_print(cs, file); +} + +static inline int radeon_cs_space_check(struct radeon_cs *cs, + struct radeon_cs_space_check *bos, + int num_bo) +{ + return cs->csm->funcs->cs_space_check(cs, bos, num_bo); +} + +static inline void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit) +{ + + if (domain == RADEON_GEM_DOMAIN_VRAM) + cs->csm->vram_limit = limit; + else + cs->csm->gart_limit = limit; +} + +static inline void radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword) +{ + cs->packets[cs->cdw++] = dword; + if (cs->section) { + cs->section_cdw++; + } +} + +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 2db3f7a68da..0f73dec1e51 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -31,10 +31,7 @@ */ #include -#include "radeon_cs.h" -#include "radeon_cs_legacy.h" -#include "radeon_bo_legacy.h" - +#include "radeon_bocs_wrapper.h" struct cs_manager_legacy { struct radeon_cs_manager base; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h index 19d904174f6..e177b4bafe2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h @@ -32,7 +32,6 @@ #ifndef RADEON_CS_LEGACY_H #define RADEON_CS_LEGACY_H -#include "radeon_cs.h" #include "radeon_common.h" struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 99b1ef332f0..fb3a236d7c8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -44,7 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" #include "radeon_common.h" -#include "radeon_cs.h" #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_tcl.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index 6d616bf8045..18805d4c571 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/simple_list.h" #include "radeon_lock.h" -#include "radeon_cs_legacy.h" +#include "radeon_bocs_wrapper.h" extern void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 323726c5749..c21d297b22c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -34,8 +34,6 @@ #include "main/texcompress.h" #include "main/texformat.h" -#include "radeon_buffer.h" - static GLuint radeon_compressed_texture_size(GLcontext *ctx, GLsizei width, GLsizei height, GLsizei depth, GLuint mesaFormat) diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 7f0d526ed2d..e8cc3b25a8c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_chipset.h" #include "radeon_macros.h" #include "radeon_screen.h" -#include "radeon_buffer.h" #include "radeon_common.h" #include "radeon_span.h" #if !RADEON_COMMON @@ -66,13 +65,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "drirenderbuffer.h" +#include "radeon_bocs_wrapper.h" + #include "GL/internal/dri_interface.h" /* Radeon configuration */ #include "xmlpool.h" -#include "radeon_bo_legacy.h" -#include "radeon_bo_gem.h" #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 3287e125f45..1c0f5bb9bc7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_reg.h" #include "drm_sarea.h" #include "xmlconfig.h" -#include "radeon_bo.h" typedef struct { diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index ebd18a16342..49ec2c378e5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_lock.h" #include "radeon_span.h" -#include "radeon_buffer.h" - #define DBG 0 static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h index dda542c8d19..dd44ab517af 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h @@ -42,8 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_SPAN_H__ #define __RADEON_SPAN_H__ -#include "radeon_buffer.h" - extern void radeonInitSpanFuncs(GLcontext * ctx); extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index a397c0824fa..fc42318017d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -38,7 +38,6 @@ #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" -#include "radeon_cs.h" #include "radeon_mipmap_tree.h" #include "radeon_ioctl.h" #include "radeon_state.h" -- cgit v1.2.3 From 9314d936e84cc8449d6e200b5d1df51d6d057876 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 23:53:41 +1000 Subject: radeon: remove depends on libdrm_radeon for now. will fixup makefiles later to detect and use libdrm_Radeon in proper places --- src/mesa/drivers/dri/r200/Makefile | 2 +- src/mesa/drivers/dri/r300/Makefile | 2 +- src/mesa/drivers/dri/radeon/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 7b5fe955776..c9f907ec5ba 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -79,7 +79,7 @@ COMMON_SYMLINKS = \ radeon_dma.c \ radeon_dma.h -DRI_LIB_DEPS += -ldrm_radeon +DRI_LIB_DEPS += #-ldrm_radeon ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 20ee195fe7b..1b690feeeee 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -94,7 +94,7 @@ COMMON_SYMLINKS = \ radeon_texture.c \ radeon_texture.h -DRI_LIB_DEPS += -ldrm_radeon +DRI_LIB_DEPS += #-ldrm_radeon ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 16bc063bafd..9eb078ed8d1 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -38,7 +38,7 @@ C_SOURCES = \ DRIVER_DEFINES = -DRADEON_COMMON=0 -DRI_LIB_DEPS += -ldrm_radeon +DRI_LIB_DEPS += #-ldrm_radeon X86_SOURCES = -- cgit v1.2.3 From d513915d27eac8a57ff7f5c1973b4a07fe288c53 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 00:05:39 +1000 Subject: radeon/r200/r300: make build again with tracker changes --- src/mesa/drivers/dri/r200/Makefile | 1 + src/mesa/drivers/dri/r300/Makefile | 1 + src/mesa/drivers/dri/radeon/Makefile | 1 + src/mesa/drivers/dri/radeon/radeon_bo_drm.h | 5 ++++- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 11 +++++++++++ src/mesa/drivers/dri/radeon/radeon_common.c | 1 + src/mesa/drivers/dri/radeon/radeon_common_context.c | 5 +++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 2 ++ 8 files changed, 26 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index c9f907ec5ba..41c7aed3655 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -14,6 +14,7 @@ endif RADEON_COMMON_SOURCES = \ radeon_texture.c \ radeon_common_context.c \ + radeon_common.c \ radeon_dma.c \ radeon_lock.c \ radeon_bo_legacy.c \ diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 1b690feeeee..b3c58cf6f65 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -23,6 +23,7 @@ COMMON_SOURCES = \ RADEON_COMMON_SOURCES = \ radeon_texture.c \ radeon_common_context.c \ + radeon_common.c \ radeon_dma.c \ radeon_lock.c \ radeon_bo_legacy.c \ diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 9eb078ed8d1..0a5775b11c1 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -11,6 +11,7 @@ MINIGLX_SOURCES = server/radeon_dri.c RADEON_COMMON_SOURCES = \ radeon_texture.c \ radeon_common_context.c \ + radeon_common.c \ radeon_dma.c \ radeon_lock.c \ radeon_bo_legacy.c \ diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h index 3cabdfc4e81..1ed13f17955 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h @@ -32,7 +32,7 @@ #include #include -#include "radeon_track.h" +//#include "radeon_track.h" /* bo object */ #define RADEON_BO_FLAGS_MACRO_TILE 1 @@ -73,7 +73,10 @@ struct radeon_bo_funcs { struct radeon_bo_manager { struct radeon_bo_funcs *funcs; int fd; + +#ifdef RADEON_BO_TRACK struct radeon_tracker tracker; +#endif }; static inline void _radeon_bo_debug(struct radeon_bo *bo, diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 36dea3be7bd..b86f31f88a5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -26,7 +26,18 @@ static inline void radeon_bo_manager_gem_dtor(void *dummy) { } +static inline void *radeon_cs_manager_gem_ctor(int fd) +{ + return NULL; +} + +static inline void radeon_cs_manager_gem_dtor(void *dummy) +{ +} +static inline void radeon_tracker_print(void *ptr, int io) +{ +} #endif #include "radeon_bo_legacy.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 80e8e0d86d4..f5f433b2adb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_common.h" #include "radeon_bocs_wrapper.h" +#include "radeon_lock.h" #include "radeon_drm.h" #include "radeon_mipmap_tree.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 8acde2b90cd..1b8a05d045b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -37,6 +37,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "drirenderbuffer.h" #include "vblank.h" +#include "main/state.h" #define DRIVER_DATE "20090101" @@ -175,7 +176,9 @@ GLboolean radeonInitContext(radeonContextPtr radeon, */ void radeonCleanupContext(radeonContextPtr radeon) { +#ifdef RADEON_BO_TRACK FILE *track; +#endif struct radeon_renderbuffer *rb; GLframebuffer *fb; @@ -232,11 +235,13 @@ void radeonCleanupContext(radeonContextPtr radeon) FREE(radeon->state.scissor.pClipRects); radeon->state.scissor.pClipRects = 0; } +#ifdef RADEON_BO_TRACK track = fopen("/tmp/tracklog", "w"); if (track) { radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); fclose(track); } +#endif } /* Force the context `c' to be unbound from its buffer. diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e8cc3b25a8c..8b06fb4d3e9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1115,7 +1115,9 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) return; if (screen->kernel_mm) { +#ifdef RADEON_BO_TRACK radeon_tracker_print(&screen->bom->tracker, stderr); +#endif radeon_bo_manager_gem_dtor(screen->bom); } else { radeon_bo_manager_legacy_dtor(screen->bom); -- cgit v1.2.3 From c83d0bfe0645a58e7dd028b4472dbd54e479ab32 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 14:16:24 +1000 Subject: radeon: make build without libdrm_radeon better --- src/mesa/drivers/dri/radeon/radeon_cs_drm.h | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h index 7cc75d47004..ffda17c11fe 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h @@ -35,7 +35,7 @@ #include #include "drm.h" #include "radeon_drm.h" -#include "radeon_bo.h" +#include "radeon_bocs_wrapper.h" struct radeon_cs_reloc { struct radeon_bo *bo; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 8b06fb4d3e9..133d0d75552 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1016,6 +1016,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return screen; } +#ifndef RADEON_PARAM_DEVICE_ID +#define RADEON_PARAM_DEVICE_ID 17 +#endif + static radeonScreenPtr radeonCreateScreen2(__DRIscreenPrivate *sPriv) { -- cgit v1.2.3 From 56a13a7ca9fcb742352561ee66dddc805676bc5e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 14:36:12 +1000 Subject: r300: make r300 work with latest changes --- src/mesa/drivers/dri/r300/Makefile | 1 + src/mesa/drivers/dri/r300/r300_context.c | 3 ++- src/mesa/drivers/dri/r300/r300_swtcl.c | 3 ++- src/mesa/drivers/dri/r300/radeon_context.h | 1 - 4 files changed, 5 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index b3c58cf6f65..77846a4d676 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -33,6 +33,7 @@ RADEON_COMMON_SOURCES = \ DRIVER_SOURCES = \ radeon_screen.c \ + r300_context.c \ r300_ioctl.c \ r300_cmdbuf.c \ r300_state.c \ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 449252a9309..5226effdd1e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -55,8 +55,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" -#include "radeon_span.h" #include "r300_context.h" +#include "radeon_context.h" +#include "radeon_span.h" #include "r300_cmdbuf.h" #include "r300_state.h" #include "r300_ioctl.h" diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 34e752178af..d73af8650f9 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -56,6 +56,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_ioctl.h" #include "r300_emit.h" +#include "r300_tex.h" void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset); void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr); @@ -628,7 +629,7 @@ void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - r300EmitState(rmesa); + radeonEmitState(&rmesa->radeon); r300EmitVertexAOS(rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index 005edf8448a..250570f6b89 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -50,7 +50,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "dri_util.h" #include "radeon_screen.h" -#include "common_misc.h" #if R200_MERGED extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode); -- cgit v1.2.3 From 1e77f7b55c052de238d46df3454bf2f2eb8d7346 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 14:39:33 +1000 Subject: r200: make build complete --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index b86f31f88a5..2117be71618 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -9,13 +9,14 @@ #include "radeon_cs_gem.h" #else +#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain +#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed +#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain + /* to be used to build locally in mesa with no libdrm bits */ #include "../radeon/radeon_bo_drm.h" #include "../radeon/radeon_cs_drm.h" -#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain -#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed -#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain static inline void *radeon_bo_manager_gem_ctor(int fd) { -- cgit v1.2.3 From ec0939b01370e9272000fcd4d71a023866e767a0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 14:41:16 +1000 Subject: radeon: add defines for future bits --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 8 ++++++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 4 ---- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 2117be71618..a54a3610b95 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -13,6 +13,14 @@ #define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed #define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain +#ifndef DRM_RADEON_GEM_INFO +#define DRM_RADEON_GEM_INFO 0x1c +#endif + +#ifndef RADEON_PARAM_DEVICE_ID +#define RADEON_PARAM_DEVICE_ID 17 +#endif + /* to be used to build locally in mesa with no libdrm bits */ #include "../radeon/radeon_bo_drm.h" #include "../radeon/radeon_cs_drm.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 133d0d75552..8b06fb4d3e9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1016,10 +1016,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return screen; } -#ifndef RADEON_PARAM_DEVICE_ID -#define RADEON_PARAM_DEVICE_ID 17 -#endif - static radeonScreenPtr radeonCreateScreen2(__DRIscreenPrivate *sPriv) { -- cgit v1.2.3 From 899b91b1fb766f2b716c53a350ff2a078655e6c5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 14:43:25 +1000 Subject: radeon: add mminfo struct to wrapper --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index a54a3610b95..6b05337fd33 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -15,6 +15,14 @@ #ifndef DRM_RADEON_GEM_INFO #define DRM_RADEON_GEM_INFO 0x1c + +struct drm_radeon_gem_info { + uint64_t gart_start; + uint64_t gart_size; + uint64_t vram_start; + uint64_t vram_size; + uint64_t vram_visible; +}; #endif #ifndef RADEON_PARAM_DEVICE_ID -- cgit v1.2.3 From dc531ba4063a32e21419cd43cdd9019c64569eb5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 14:44:20 +1000 Subject: radeon: add stdint include --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 6b05337fd33..0f45e9d5a23 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -9,6 +9,8 @@ #include "radeon_cs_gem.h" #else +#include + #define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain #define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed #define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain -- cgit v1.2.3 From 7e104f9cde94279a902b408e8d1cf21779b393a8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 01:04:18 +1000 Subject: r300: fix warning about mesa_lock_context_texture --- src/mesa/drivers/dri/r300/r300_context.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5226effdd1e..8bad6467f2d 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/extensions.h" #include "main/state.h" #include "main/bufferobj.h" +#include "main/texobj.h" #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" -- cgit v1.2.3 From 5ee1dd2133c5514713281f32cd4b05fabf14354a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 01:21:37 +1000 Subject: radeon: fixup include ordering --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 7 ++++--- src/mesa/drivers/dri/radeon/radeon_cs_drm.h | 1 - 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 0f45e9d5a23..97467b22ce9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -15,6 +15,10 @@ #define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed #define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain +/* to be used to build locally in mesa with no libdrm bits */ +#include "../radeon/radeon_bo_drm.h" +#include "../radeon/radeon_cs_drm.h" + #ifndef DRM_RADEON_GEM_INFO #define DRM_RADEON_GEM_INFO 0x1c @@ -31,9 +35,6 @@ struct drm_radeon_gem_info { #define RADEON_PARAM_DEVICE_ID 17 #endif -/* to be used to build locally in mesa with no libdrm bits */ -#include "../radeon/radeon_bo_drm.h" -#include "../radeon/radeon_cs_drm.h" static inline void *radeon_bo_manager_gem_ctor(int fd) diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h index ffda17c11fe..8f0b449e41f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h @@ -35,7 +35,6 @@ #include #include "drm.h" #include "radeon_drm.h" -#include "radeon_bocs_wrapper.h" struct radeon_cs_reloc { struct radeon_bo *bo; -- cgit v1.2.3 From 393c699e219b6cccf0d235749ec7bfaade75f88c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 00:04:11 +1000 Subject: r200: use correct finish interface --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 2 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 2 +- src/mesa/drivers/dri/r200/r200_ioctl.h | 2 -- src/mesa/drivers/dri/r200/r200_pixel.c | 2 +- src/mesa/drivers/dri/r200/r200_state.c | 2 +- 5 files changed, 4 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index cb1bd8be956..6317decf641 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -187,7 +187,7 @@ void r200FlushElts(GLcontext *ctx) if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); - r200Finish( rmesa->radeon.glCtx ); + radeonFinish( rmesa->radeon.glCtx ); } } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index e19ff44bc8e..c08968f7f86 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -213,7 +213,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) return; } - r200Flush( ctx ); + radeonFlush( ctx ); if ( mask & BUFFER_BIT_FRONT_LEFT ) { flags |= RADEON_FRONT; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 950478e762e..2a4b8a11f4c 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -61,8 +61,6 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); -extern void r200Flush( GLcontext *ctx ); -extern void r200Finish( GLcontext *ctx ); extern void r200InitIoctlFuncs( struct dd_function_table *functions ); extern void *r200AllocateMemoryMESA( __DRIscreen *screen, GLsizei size, GLfloat readfreq, diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index eefa2a1e11a..a6c655866ac 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -262,7 +262,7 @@ r200TryReadPixels( GLcontext *ctx, } UNLOCK_HARDWARE( &rmesa->radeon ); - r200Finish( ctx ); /* required by GL */ + radeonFinish( ctx ); /* required by GL */ #endif return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 559985bc3fb..126f78b39ca 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -2380,7 +2380,7 @@ again: if (ret == RADEON_CS_SPACE_OP_TO_BIG) return GL_FALSE; if (ret == RADEON_CS_SPACE_FLUSH) { - r200Flush(ctx); + radeonFlush(ctx); if (flushed) return GL_FALSE; flushed = 1; -- cgit v1.2.3 From ade3660942452985afa1bb67bbeab8fed734089d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 01:27:21 +1000 Subject: r200: fixup some CS emission sizes --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 2 +- src/mesa/drivers/dri/r200/r200_context.c | 1 + src/mesa/drivers/dri/r200/r200_state_init.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 6317decf641..55507be2515 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -259,7 +259,7 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); - BEGIN_BATCH(sz+2); + BEGIN_BATCH(sz+2+ (nr*2)); OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 431bf8235c3..d567bb77df9 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -555,6 +555,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->radeon.dma.current) { + radeonReleaseDmaRegion( &rmesa->radeon ); rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 3cd2dc77512..1a13c9ec13d 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -417,7 +417,7 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; /* output the first 7 bytes of context */ - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2); OUT_BATCH_TABLE(atom->cmd, 5); rrb = r200->radeon.state.depth.rrb; -- cgit v1.2.3 From 695ca1e2be6f222c132a76299fc3a0ac9143d960 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 18:50:57 +1000 Subject: r200: port over state emit fix from r100 --- src/mesa/drivers/dri/r200/r200_state_init.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 1a13c9ec13d..3165f7ec608 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -542,14 +542,16 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) int i = atom->idx; radeonTexObj *t = r200->state.texture.unit[i].texobj; + if (t && t->mt && !t->image_override) + dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 10); if (t && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { - - OUT_BATCH(atom->cmd[10]); + /* workaround for old CS mechanism */ + OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); } END_BATCH(); -- cgit v1.2.3 From 812389761500456d31aab445c194b4bb15dd0d61 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 19:39:21 +1000 Subject: r200: update with changes from r100 driver for texture state --- src/mesa/drivers/dri/r200/r200_texstate.c | 46 +++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 03404b6eb19..e47c7cc0ca9 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -958,6 +958,35 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx ) R200_VOLUME_FILTER_MASK) +static void disable_tex_obj_state( r200ContextPtr rmesa, + int unit ) +{ + + R200_STATECHANGE( rmesa, vtx ); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); + + if (rmesa->radeon.TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<radeon.glCtx, (R200_TCL_FALLBACK_TEXGEN_0<2 texunits. + */ + + { + GLuint tmp = rmesa->TexGenEnabled; + + rmesa->TexGenEnabled &= ~(R200_TEXGEN_TEXMAT_0_ENABLE<TexGenEnabled &= ~(R200_TEXMAT_0_ENABLE<TexGenNeedNormals[unit] = GL_FALSE; + rmesa->TexGenCompSel &= ~(R200_OUTPUT_TEX_0 << unit); + + if (tmp != rmesa->TexGenEnabled) { + rmesa->recheck_texgen[unit] = GL_TRUE; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; + } + } +} static void import_tex_obj_state( r200ContextPtr rmesa, int unit, radeonTexObjPtr texobj ) @@ -1405,10 +1434,20 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object import_tex_obj_state( rmesa, unit, t ); } + if (rmesa->recheck_texgen[unit]) { + GLboolean fallback = !r200_validate_texgen( ctx, unit ); + TCL_FALLBACK( ctx, (R200_TCL_FALLBACK_TEXGEN_0<recheck_texgen[unit] = 0; + rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; + } + t->dirty_state = R200_TEX_ALL; t->validated = GL_TRUE; - return GL_TRUE; + + FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); + + return !t->border_fallback; } static GLboolean r200UpdateTextureUnit(GLcontext *ctx, int unit) @@ -1416,8 +1455,11 @@ static GLboolean r200UpdateTextureUnit(GLcontext *ctx, int unit) r200ContextPtr rmesa = R200_CONTEXT(ctx); GLuint unitneeded = rmesa->state.texture.unit[unit].unitneeded; - if (!unitneeded) + if (!unitneeded) { + /* disable the unit */ + disable_tex_obj_state(rmesa, unit); return GL_TRUE; + } if (!r200_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) { _mesa_warning(ctx, -- cgit v1.2.3 From 9fd8da299b4a62c6baf49f08067d7c1ddebb0ffd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 22:49:06 +1000 Subject: radeon: fix compressed texture upload on all radeons tested on r200, texcmp works. May need more verification --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 42 ++++++++++++++---- src/mesa/drivers/dri/radeon/radeon_texture.c | 55 ++++++++++++++++++------ 2 files changed, 75 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index c21d297b22c..45c1d71be59 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -56,6 +56,29 @@ static GLuint radeon_compressed_texture_size(GLcontext *ctx, return size; } + +static int radeon_compressed_num_bytes(GLuint mesaFormat) +{ + int bytes = 0; + switch(mesaFormat) { + + case MESA_FORMAT_RGB_FXT1: + case MESA_FORMAT_RGBA_FXT1: + case MESA_FORMAT_RGB_DXT1: + case MESA_FORMAT_RGBA_DXT1: + bytes = 2; + break; + + case MESA_FORMAT_RGBA_DXT3: + case MESA_FORMAT_RGBA_DXT5: + bytes = 4; + default: + break; + } + + return bytes; +} + /** * Compute sizes and fill in offset and blit information for the given * image (determined by \p face and \p level). @@ -73,18 +96,14 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, /* TODO: Is this correct? Need test cases for compressed textures! */ GLuint align; - if (mt->target == GL_TEXTURE_RECTANGLE_NV) - align = 64 / mt->bpp; - else - align = 32 / mt->bpp; - lvl->rowstride = (lvl->width + align - 1) & ~(align - 1); + lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, - lvl->width, lvl->height, lvl->depth, mt->compressed); + lvl->width, lvl->height, lvl->depth, mt->compressed); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = lvl->rowstride * lvl->height; } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { - /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, + /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; @@ -160,7 +179,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj * mt->width0 = width0; mt->height0 = height0; mt->depth0 = depth0; - mt->bpp = bpp; + mt->bpp = compressed ? radeon_compressed_num_bytes(compressed) : bpp; mt->tilebits = tilebits; mt->compressed = compressed; @@ -255,7 +274,12 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel) return GL_FALSE; - if (texImage->TexFormat->TexelBytes != mt->bpp) + if (texImage->IsCompressed != mt->compressed) + return GL_FALSE; + + if (!texImage->IsCompressed && + !mt->compressed && + texImage->TexFormat->TexelBytes != mt->bpp) return GL_FALSE; lvl = &mt->levels[level - mt->firstLevel]; diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index beb21e7b431..eb87a0dac5d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -32,6 +32,7 @@ #include "main/imports.h" #include "main/context.h" #include "main/mipmap.h" +#include "main/texcompress.h" #include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" @@ -453,16 +454,26 @@ static void radeon_teximage( radeonContextPtr rmesa = RADEON_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); + GLuint dstRowStride; + GLint postConvWidth = width; + GLint postConvHeight = height; + GLuint texelBytes; radeon_firevertices(rmesa); t->validated = GL_FALSE; + if (ctx->_ImageTransferState & IMAGE_CONVOLUTION_BIT) { + _mesa_adjust_image_for_convolution(ctx, dims, &postConvWidth, + &postConvHeight); + } + /* Choose and fill in the texture format for this image */ texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type); _mesa_set_fetch_functions(texImage, dims); if (texImage->TexFormat->TexelBytes == 0) { + texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, @@ -471,6 +482,16 @@ static void radeon_teximage( } else { texImage->IsCompressed = GL_FALSE; texImage->CompressedSize = 0; + + texelBytes = texImage->TexFormat->TexelBytes; + /* Minimum pitch of 32 bytes */ + if (postConvWidth * texelBytes < 32) { + postConvWidth = 32 / texelBytes; + texImage->RowStride = postConvWidth; + } + if (!image->mt) { + assert(texImage->RowStride == postConvWidth); + } } /* Allocate memory for image */ @@ -479,16 +500,22 @@ static void radeon_teximage( if (!t->mt) radeon_try_alloc_miptree(rmesa, t, texImage, face, level); if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { + radeon_mipmap_level *lvl; image->mt = t->mt; image->mtlevel = level - t->mt->firstLevel; image->mtface = face; radeon_miptree_reference(t->mt); + lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; } else { int size; if (texImage->IsCompressed) { size = texImage->CompressedSize; + dstRowStride = + _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); } else { size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; + dstRowStride = postConvWidth * texelBytes; } texImage->Data = _mesa_alloc_texmemory(size); } @@ -509,13 +536,6 @@ static void radeon_teximage( if (compressed) { memcpy(texImage->Data, pixels, imageSize); } else { - GLuint dstRowStride; - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; - } if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, texImage->TexFormat, @@ -534,11 +554,11 @@ static void radeon_teximage( radeon_generate_mipmap(ctx, texObj->Target, texObj); } - if (pixels) - radeon_teximage_unmap(image); - _mesa_unmap_teximage_pbo(ctx, packing); + if (pixels) + radeon_teximage_unmap(image); + } @@ -579,7 +599,7 @@ void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target, GLuint face = radeon_face_for_target(target); radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1, - imageSize, 0, 0, data, 0, texObj, texImage, 1); + imageSize, 0, 0, data, &ctx->Unpack, texObj, texImage, 1); } void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, @@ -760,13 +780,22 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag radeon_miptree_unreference(image->mt); } else { - uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; + uint32_t srcrowstride; + uint32_t height; + /* need to confirm this value is correct */ + if (mt->compressed) { + height = image->base.Height / 4; + srcrowstride = image->base.RowStride * mt->bpp; + } else { + height = image->base.Height * image->base.Depth; + srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; + } // if (mt->tilebits) // WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, - image->base.Height * image->base.Depth, srcrowstride); + height, srcrowstride); _mesa_free_texmemory(image->base.Data); image->base.Data = 0; -- cgit v1.2.3 From ed8340192ef88bd841966aba10d0043b246805bd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 23:02:12 +1000 Subject: radeon: revert unneeded change to texturing code --- src/mesa/drivers/dri/radeon/radeon_texture.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index eb87a0dac5d..2b04245a39a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -511,11 +511,8 @@ static void radeon_teximage( int size; if (texImage->IsCompressed) { size = texImage->CompressedSize; - dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); } else { size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; - dstRowStride = postConvWidth * texelBytes; } texImage->Data = _mesa_alloc_texmemory(size); } @@ -536,6 +533,14 @@ static void radeon_teximage( if (compressed) { memcpy(texImage->Data, pixels, imageSize); } else { + GLuint dstRowStride; + if (image->mt) { + radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; + dstRowStride = lvl->rowstride; + } else { + dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; + } + if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, texImage->TexFormat, -- cgit v1.2.3 From f363a97d2586a8487bfa64f882fbfc204a56fd05 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 23:29:27 +1000 Subject: radeon/r200: fix set tex offset functions --- src/mesa/drivers/dri/r200/r200_texstate.c | 4 +--- src/mesa/drivers/dri/radeon/radeon_texstate.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index e47c7cc0ca9..e6aff022b3d 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -733,13 +733,11 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, r200ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); - radeonTexObjPtr t; + radeonTexObjPtr t = radeon_tex_obj(tObj); if (!tObj) return; - t = (radeonTexObjPtr) tObj->DriverData; - t->image_override = GL_TRUE; if (!offset) diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index cabac6c13d5..2e064cf0973 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -605,13 +605,11 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, r100ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); - radeonTexObjPtr t; + radeonTexObjPtr t = radeon_tex_obj(tObj); if (tObj == NULL) return; - t = (radeonTexObjPtr) tObj->DriverData; - t->image_override = GL_TRUE; if (!offset) -- cgit v1.2.3 From 2753dd42fd42a3383d2e74ab231d0b1373a2d46d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 23:34:53 +1000 Subject: radeon/r200: make setTexOffset work again --- src/mesa/drivers/dri/r200/r200_state_init.c | 3 ++- src/mesa/drivers/dri/radeon/radeon_common.c | 5 ++--- src/mesa/drivers/dri/radeon/radeon_state_init.c | 5 +++-- src/mesa/drivers/dri/radeon/radeon_texture.c | 1 + 4 files changed, 8 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 3165f7ec608..3d0ebff7c43 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -552,7 +552,8 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); - } + } else if (t->image_override) + OUT_BATCH(atom->cmd[10]); END_BATCH(); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index f5f433b2adb..e816760e66b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -59,7 +59,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "dri_util.h" -#include "drirenderbuffer.h" #include "vblank.h" #include "radeon_common.h" @@ -511,8 +510,8 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) /* Get ready for drawing next frame. Update the renderbuffers' * flippedOffset/Pitch fields so we draw into the right place. */ - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); + // driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, + // rmesa->sarea->pfCurrentPage); rmesa->state.color.rrb = rrb; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index fc42318017d..40317d570a7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -445,11 +445,12 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) if (t && t->mt && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { + } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); // OUT_BATCH(r100->radeon.radeonScreen); - } + } else if (t->image_override) + OUT_BATCH(atom->cmd[4]); OUT_BATCH_TABLE((atom->cmd+4), 5); END_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 2b04245a39a..fe0031e3cdd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -881,3 +881,4 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t return GL_TRUE; } + -- cgit v1.2.3 From cd4e37c8fb7c03e8331a9487d46043eea70fea31 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 14 Feb 2009 05:57:52 +1000 Subject: radeon: add initial cubemap support appears to work --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 40 ++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 40317d570a7..998ae796240 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -362,6 +362,7 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } + static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -430,6 +431,34 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } +static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx, j; + radeonTexObj *t = r100->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; + + if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) + return; + + if (!t) + return; + + if (!t->mt) + return; + + BEGIN_BATCH_NO_AUTOSTATE(dwords + 10); + OUT_BATCH_TABLE(atom->cmd, 3); + lvl = &t->mt->levels[0]; + for (j = 0; j < 5; j++) { + OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + END_BATCH(); +} + static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -437,14 +466,21 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) uint32_t dwords = atom->cmd_size; int i = atom->idx; radeonTexObj *t = r100->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; if (t && t->mt && !t->image_override) dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 3); if (t && t->mt && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { + lvl = &t->mt->levels[0]; + OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); + } } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); @@ -559,6 +595,8 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); + for (i = 0; i < 3; i++) + rmesa->hw.cube[i].emit = cube_emit; } else { -- cgit v1.2.3 From c0ae4d3c55a606ede41399e39e5221b1955ecc22 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 14 Feb 2009 07:49:15 +1000 Subject: radeon/r300: fix warnings --- src/mesa/drivers/dri/r300/r300_tex.h | 3 +++ src/mesa/drivers/dri/radeon/radeon_screen.c | 3 --- src/mesa/drivers/dri/radeon/radeon_texture.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h index c4f42ee621c..baad3fe6c06 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ b/src/mesa/drivers/dri/r300/r300_tex.h @@ -37,6 +37,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r300SetDepthTexMode(struct gl_texture_object *tObj); +extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, + __DRIdrawable *dPriv); + extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 21b94d2e527..086a2683e5b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -357,9 +357,6 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { r300SetTexOffset, }; -void r300SetTexBuffer(__DRIcontext *pDRICtx, - GLint target, - __DRIdrawable *dPriv); static const __DRItexBufferExtension r300TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, r300SetTexBuffer, diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index fe0031e3cdd..55dda29eaf9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -31,6 +31,7 @@ #include "main/glheader.h" #include "main/imports.h" #include "main/context.h" +#include "main/convolve.h" #include "main/mipmap.h" #include "main/texcompress.h" #include "main/texformat.h" -- cgit v1.2.3 From fcc7a691dc968d9d2bc61a8bf18dfbd7ed789598 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 13 Feb 2009 20:34:19 +1000 Subject: radeon: remove old cube code --- src/mesa/drivers/dri/radeon/radeon_texstate.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 2e064cf0973..1aa5f980ce2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -730,21 +730,10 @@ static void import_tex_obj_state( r100ContextPtr rmesa, if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) { uint32_t *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; - // GLuint bytesPerFace = texobj->base.totalSize / 6; - // ASSERT(texobj->base.totalSize % 6 == 0); - GLuint bytesPerFace = 1; // TODO RADEON_STATECHANGE( rmesa, cube[unit] ); cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; - /* dont know if this setup conforms to OpenGL.. - * at least it matches the behavior of mesa software renderer - */ - cube_cmd[CUBE_PP_CUBIC_OFFSET_0] = texobj->pp_txoffset; /* right */ - cube_cmd[CUBE_PP_CUBIC_OFFSET_1] = texobj->pp_txoffset + 1 * bytesPerFace; /* left */ - cube_cmd[CUBE_PP_CUBIC_OFFSET_2] = texobj->pp_txoffset + 2 * bytesPerFace; /* top */ - cube_cmd[CUBE_PP_CUBIC_OFFSET_3] = texobj->pp_txoffset + 3 * bytesPerFace; /* bottom */ - cube_cmd[CUBE_PP_CUBIC_OFFSET_4] = texobj->pp_txoffset + 4 * bytesPerFace; /* front */ - cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset + 5 * bytesPerFace; /* back */ + /* state filled out in the cube_emit */ } } -- cgit v1.2.3 From f3a1f321cfa275eba6186626ee691e8bc9ecfe8c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 14 Feb 2009 12:01:54 +1000 Subject: radeon: check for valid bo in release arrays --- src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index bb90a7b1117..d468a972006 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -438,7 +438,9 @@ void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) int i; for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; + if (rmesa->tcl.aos[i].bo) { + radeon_bo_unref(rmesa->tcl.aos[i].bo); + rmesa->tcl.aos[i].bo = NULL; + } } } -- cgit v1.2.3 From fd81835dc7ac71eac2a5fcc58080b9b4c6944c83 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 14 Feb 2009 19:10:13 +1000 Subject: r200: fix another cmdbuf sizing issue --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 55507be2515..ae31bcb8311 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -135,7 +135,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) BATCH_LOCALS(&rmesa->radeon); if (vertex_count > 0) { - BEGIN_BATCH(8); + BEGIN_BATCH(8+2); OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | ((vertex_count + 0) << 16) | -- cgit v1.2.3 From f8c2beccd4847836dec18849d2d58f3220ff81eb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 14 Feb 2009 20:13:04 +1000 Subject: r200: fixup cube emit debug --- src/mesa/drivers/dri/r200/r200_state_init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 3d0ebff7c43..0366fc0fbe4 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -567,10 +567,9 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) radeonTexObj *t = r200->state.texture.unit[i].texobj; GLuint size; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5)); OUT_BATCH_TABLE(atom->cmd, 3); - fprintf(stderr,"total size is %d\n", t->mt->totalsize); if (t && !t->image_override) { size = t->mt->totalsize / 6; OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0); -- cgit v1.2.3 From b1b7bc66a414d200102a90ed0580c3fd80a45838 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 14 Feb 2009 20:34:20 +1000 Subject: radeon: remove unused radeon_compat.c --- src/mesa/drivers/dri/radeon/radeon_compat.c | 301 ---------------------------- 1 file changed, 301 deletions(-) delete mode 100644 src/mesa/drivers/dri/radeon/radeon_compat.c (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_compat.c b/src/mesa/drivers/dri/radeon/radeon_compat.c deleted file mode 100644 index 46b490d61f7..00000000000 --- a/src/mesa/drivers/dri/radeon/radeon_compat.c +++ /dev/null @@ -1,301 +0,0 @@ -/************************************************************************** - -Copyright 2002 ATI Technologies Inc., Ontario, Canada, and - Tungsten Graphics Inc., Austin, Texas. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - * - */ - -#include "main/glheader.h" -#include "main/imports.h" - -#include "radeon_context.h" -#include "radeon_state.h" -#include "radeon_ioctl.h" - - -static struct { - int start; - int len; - const char *name; -} packet[RADEON_MAX_STATE_PACKETS] = { - { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, - { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, - { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, - { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, - { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, - { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, - { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, - { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, - { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, - { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, - { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, - { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, - { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, - { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, - { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, - { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, - { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, - { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, - { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, - { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, - { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, -}; - - -static void radeonCompatEmitPacket( radeonContextPtr rmesa, - struct radeon_state_atom *state ) -{ - drm_radeon_sarea_t *sarea = rmesa->sarea; - drm_radeon_context_regs_t *ctx = &sarea->context_state; - drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0]; - drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1]; - int i; - int *buf = state->cmd; - - for ( i = 0 ; i < state->cmd_size ; ) { - drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++]; - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id, - packet[(int)header->packet.packet_id].name); - - switch (header->packet.packet_id) { - case RADEON_EMIT_PP_MISC: - ctx->pp_misc = buf[i++]; - ctx->pp_fog_color = buf[i++]; - ctx->re_solid_color = buf[i++]; - ctx->rb3d_blendcntl = buf[i++]; - ctx->rb3d_depthoffset = buf[i++]; - ctx->rb3d_depthpitch = buf[i++]; - ctx->rb3d_zstencilcntl = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_CONTEXT; - break; - case RADEON_EMIT_PP_CNTL: - ctx->pp_cntl = buf[i++]; - ctx->rb3d_cntl = buf[i++]; - ctx->rb3d_coloroffset = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_CONTEXT; - break; - case RADEON_EMIT_RB3D_COLORPITCH: - ctx->rb3d_colorpitch = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_CONTEXT; - break; - case RADEON_EMIT_RE_LINE_PATTERN: - ctx->re_line_pattern = buf[i++]; - ctx->re_line_state = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_LINE; - break; - case RADEON_EMIT_SE_LINE_WIDTH: - ctx->se_line_width = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_LINE; - break; - case RADEON_EMIT_PP_LUM_MATRIX: - ctx->pp_lum_matrix = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_BUMPMAP; - break; - case RADEON_EMIT_PP_ROT_MATRIX_0: - ctx->pp_rot_matrix_0 = buf[i++]; - ctx->pp_rot_matrix_1 = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_BUMPMAP; - break; - case RADEON_EMIT_RB3D_STENCILREFMASK: - ctx->rb3d_stencilrefmask = buf[i++]; - ctx->rb3d_ropcntl = buf[i++]; - ctx->rb3d_planemask = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_MASKS; - break; - case RADEON_EMIT_SE_VPORT_XSCALE: - ctx->se_vport_xscale = buf[i++]; - ctx->se_vport_xoffset = buf[i++]; - ctx->se_vport_yscale = buf[i++]; - ctx->se_vport_yoffset = buf[i++]; - ctx->se_vport_zscale = buf[i++]; - ctx->se_vport_zoffset = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_VIEWPORT; - break; - case RADEON_EMIT_SE_CNTL: - ctx->se_cntl = buf[i++]; - ctx->se_coord_fmt = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_CONTEXT | RADEON_UPLOAD_VERTFMT; - break; - case RADEON_EMIT_SE_CNTL_STATUS: - ctx->se_cntl_status = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_SETUP; - break; - case RADEON_EMIT_RE_MISC: - ctx->re_misc = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_MISC; - break; - case RADEON_EMIT_PP_TXFILTER_0: - tex0->pp_txfilter = buf[i++]; - tex0->pp_txformat = buf[i++]; - tex0->pp_txoffset = buf[i++]; - tex0->pp_txcblend = buf[i++]; - tex0->pp_txablend = buf[i++]; - tex0->pp_tfactor = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_TEX0; - break; - case RADEON_EMIT_PP_BORDER_COLOR_0: - tex0->pp_border_color = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_TEX0; - break; - case RADEON_EMIT_PP_TXFILTER_1: - tex1->pp_txfilter = buf[i++]; - tex1->pp_txformat = buf[i++]; - tex1->pp_txoffset = buf[i++]; - tex1->pp_txcblend = buf[i++]; - tex1->pp_txablend = buf[i++]; - tex1->pp_tfactor = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_TEX1; - break; - case RADEON_EMIT_PP_BORDER_COLOR_1: - tex1->pp_border_color = buf[i++]; - sarea->dirty |= RADEON_UPLOAD_TEX1; - break; - - case RADEON_EMIT_SE_ZBIAS_FACTOR: - i++; - i++; - break; - - case RADEON_EMIT_PP_TXFILTER_2: - case RADEON_EMIT_PP_BORDER_COLOR_2: - case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT: - case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED: - default: - /* These states aren't understood by radeon drm 1.1 */ - fprintf(stderr, "Tried to emit unsupported state\n"); - return; - } - } -} - - - -static void radeonCompatEmitStateLocked( radeonContextPtr rmesa ) -{ - struct radeon_state_atom *atom; - - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty) - return; - - foreach(atom, &rmesa->hw.atomlist) { - if (rmesa->hw.all_dirty) - atom->dirty = GL_TRUE; - if (atom->is_tcl) - atom->dirty = GL_FALSE; - if (atom->dirty) - radeonCompatEmitPacket(rmesa, atom); - } - - rmesa->hw.is_dirty = GL_FALSE; - rmesa->hw.all_dirty = GL_FALSE; -} - - -static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa, - GLuint hw_primitive, - GLuint nverts, - drm_clip_rect_t *pbox, - GLuint nbox ) -{ - int i; - - for ( i = 0 ; i < nbox ; ) { - int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox ); - drm_clip_rect_t *b = rmesa->sarea->boxes; - drm_radeon_vertex_t vtx; - - rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS; - rmesa->sarea->nbox = nr - i; - - for ( ; i < nr ; i++) - *b++ = pbox[i]; - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, - "RadeonFlushVertexBuffer: prim %x buf %d verts %d " - "disc %d nbox %d\n", - hw_primitive, - rmesa->dma.current.buf->buf->idx, - nverts, - nr == nbox, - rmesa->sarea->nbox ); - - vtx.prim = hw_primitive; - vtx.idx = rmesa->dma.current.buf->buf->idx; - vtx.count = nverts; - vtx.discard = (nr == nbox); - - drmCommandWrite( rmesa->dri.fd, - DRM_RADEON_VERTEX, - &vtx, sizeof(vtx)); - } -} - - - -/* No 'start' for 1.1 vertices ioctl: only one vertex prim/buffer! - */ -void radeonCompatEmitPrimitive( radeonContextPtr rmesa, - GLuint vertex_format, - GLuint hw_primitive, - GLuint nrverts ) -{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - LOCK_HARDWARE( rmesa ); - - radeonCompatEmitStateLocked( rmesa ); - rmesa->sarea->vc_format = vertex_format; - - if (rmesa->state.scissor.enabled) { - radeonCompatEmitPrimitiveLocked( rmesa, - hw_primitive, - nrverts, - rmesa->state.scissor.pClipRects, - rmesa->state.scissor.numClipRects ); - } - else { - radeonCompatEmitPrimitiveLocked( rmesa, - hw_primitive, - nrverts, - rmesa->pClipRects, - rmesa->numClipRects ); - } - - - UNLOCK_HARDWARE( rmesa ); -} - -- cgit v1.2.3 From 5f3ab230ea3e971737b733b0c0358c0a85061f5c Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Sat, 14 Feb 2009 20:40:48 +1000 Subject: r300: Fix R300_CMD_SCRATCH on big endian. --- src/mesa/drivers/dri/radeon/radeon_cs_drm.h | 10 ++++++++++ src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 3 +-- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h index 8f0b449e41f..984725a6c9d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h +++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h @@ -33,6 +33,7 @@ #define RADEON_CS_H #include +#include #include "drm.h" #include "radeon_drm.h" @@ -194,4 +195,13 @@ static inline void radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword) } } +static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword) +{ + + memcpy(cs->packets + cs->cdw, &qword, sizeof(qword)); + cs->cdw+=2; + if (cs->section) { + cs->section_cdw+=2; + } +} #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 0f73dec1e51..aa95d86cd48 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -288,8 +288,7 @@ static int cs_emit(struct radeon_cs *cs) age.scratch.n_bufs = 1; age.scratch.flags = 0; radeon_cs_write_dword(cs, age.u); - radeon_cs_write_dword(cs, ull & 0xffffffff); - radeon_cs_write_dword(cs, ull >> 32); + radeon_cs_write_qword(cs, ull); radeon_cs_write_dword(cs, 0); } -- cgit v1.2.3 From 9a26164f3525c31607e3e676e0d41e496dada4c2 Mon Sep 17 00:00:00 2001 From: Nicolai Haehnle Date: Sat, 14 Feb 2009 17:06:06 +0100 Subject: r300: Redirect constant TEX coordinates R3xx/R5xx fragment program texture constants must come from a hardware register instead of the constant file, so we redirect if necessary during the native rewrite phase. The symptoms of this bug started appearing when the Mesa fixed function texenvprogram code started using STATE_CURRENT_ATTRIB constants for texture coordinates when the corresponding attributes were constant across all vertices. Signed-off-by: Nicolai Haehnle --- src/mesa/drivers/dri/r300/r300_fragprog.c | 13 +++++++++++++ src/mesa/drivers/dri/r300/r500_fragprog.c | 19 +++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 4ef7f2bd788..8d030c63fb3 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -163,6 +163,19 @@ static GLboolean transform_TEX( } } + if (inst.SrcReg[0].File != PROGRAM_TEMPORARY && inst.SrcReg[0].File != PROGRAM_INPUT) { + int tmpreg = radeonFindFreeTemporary(t); + tgt = radeonAppendInstructions(t->Program, 1); + tgt->Opcode = OPCODE_MOV; + tgt->DstReg.File = PROGRAM_TEMPORARY; + tgt->DstReg.Index = tmpreg; + tgt->SrcReg[0] = inst.SrcReg[0]; + + reset_srcreg(&inst.SrcReg[0]); + inst.SrcReg[0].File = PROGRAM_TEMPORARY; + inst.SrcReg[0].Index = tmpreg; + } + tgt = radeonAppendInstructions(t->Program, 1); _mesa_copy_instructions(tgt, &inst, 1); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 75dae86fa81..926ddd59644 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -31,6 +31,12 @@ #include "radeon_program_alu.h" +static void reset_srcreg(struct prog_src_register* reg) +{ + _mesa_bzero(reg, sizeof(*reg)); + reg->Swizzle = SWIZZLE_NOOP; +} + static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu) { gl_state_index fail_value_tokens[STATE_LENGTH] = { @@ -99,6 +105,19 @@ static GLboolean transform_TEX( destredirect = GL_TRUE; } + if (inst.SrcReg[0].File != PROGRAM_TEMPORARY && inst.SrcReg[0].File != PROGRAM_INPUT) { + int tmpreg = radeonFindFreeTemporary(t); + tgt = radeonAppendInstructions(t->Program, 1); + tgt->Opcode = OPCODE_MOV; + tgt->DstReg.File = PROGRAM_TEMPORARY; + tgt->DstReg.Index = tmpreg; + tgt->SrcReg[0] = inst.SrcReg[0]; + + reset_srcreg(&inst.SrcReg[0]); + inst.SrcReg[0].File = PROGRAM_TEMPORARY; + inst.SrcReg[0].Index = tmpreg; + } + tgt = radeonAppendInstructions(t->Program, 1); _mesa_copy_instructions(tgt, &inst, 1); -- cgit v1.2.3 From 2d9471b28159b9af952c6a87868ff648a6055c55 Mon Sep 17 00:00:00 2001 From: Nicolai Haehnle Date: Sat, 14 Feb 2009 20:45:01 +0100 Subject: r300: Fix crash in cubemap tree creation The mip tree creation would crash if the first baselevel image to be uploaded was not the positive-x image. Found with Sauerbraten, also added a regression test to Piglit. Signed-off-by: Nicolai Haehnle --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 26 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 45c1d71be59..3203ee1cba7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -213,12 +213,26 @@ void radeon_miptree_unreference(radeon_mipmap_tree *mt) } +/** + * Calculate first and last mip levels for the given texture object, + * where the dimensions are taken from the given texture image at + * the given level. + * + * Note: level is the OpenGL level number, which is not necessarily the same + * as the first level that is actually present. + * + * The base level image of the given texture face must be non-null, + * or this will fail. + */ static void calculate_first_last_level(struct gl_texture_object *tObj, - GLuint *pfirstLevel, GLuint *plastLevel) + GLuint *pfirstLevel, GLuint *plastLevel, + GLuint face, GLuint level) { const struct gl_texture_image * const baseImage = - tObj->Image[0][tObj->BaseLevel]; + tObj->Image[face][level]; + assert(baseImage); + /* These must be signed values. MinLod and MaxLod can be negative numbers, * and having firstLevel and lastLevel as signed prevents the need for * extra sign checks. @@ -240,10 +254,10 @@ static void calculate_first_last_level(struct gl_texture_object *tObj, } else { firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5); firstLevel = MAX2(firstLevel, tObj->BaseLevel); - firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); + firstLevel = MIN2(firstLevel, level + baseImage->MaxLog2); lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); lastLevel = MAX2(lastLevel, tObj->BaseLevel); - lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = MIN2(lastLevel, level + baseImage->MaxLog2); lastLevel = MIN2(lastLevel, tObj->MaxLevel); lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ } @@ -302,7 +316,7 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu GLuint numfaces = 1; GLuint firstLevel, lastLevel; - calculate_first_last_level(texObj, &firstLevel, &lastLevel); + calculate_first_last_level(texObj, &firstLevel, &lastLevel, 0, texObj->BaseLevel); if (texObj->Target == GL_TEXTURE_CUBE_MAP) numfaces = 6; @@ -332,7 +346,7 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, assert(!t->mt); - calculate_first_last_level(&t->base, &firstLevel, &lastLevel); + calculate_first_last_level(&t->base, &firstLevel, &lastLevel, face, level); if (t->base.Target == GL_TEXTURE_CUBE_MAP) numfaces = 6; -- cgit v1.2.3 From 7d19d2768491f4de3b674106e93c24d29712404f Mon Sep 17 00:00:00 2001 From: Nicolai Haehnle Date: Sat, 14 Feb 2009 21:43:30 +0100 Subject: radeon-common: Fix crash in glGetTexImage Since texture images are now stored in miptrees, we cannot usually access them directly via the Data pointer. So we wrap Mesa's implementation by map/unmap calls. This crash was triggered by Sauerbraten, Piglit now contains a regression test. Signed-off-by: Nicolai Haehnle --- src/mesa/drivers/dri/r200/r200_tex.c | 2 ++ src/mesa/drivers/dri/r300/r300_tex.c | 2 ++ src/mesa/drivers/dri/radeon/radeon_tex.c | 2 ++ src/mesa/drivers/dri/radeon/radeon_texture.c | 53 ++++++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_texture.h | 10 ++++++ 5 files changed, 69 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index c0d1723c77c..5daacb8c95a 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -512,6 +512,8 @@ void r200InitTextureFuncs( struct dd_function_table *functions ) #else functions->TexSubImage3D = _mesa_store_texsubimage3d; #endif + functions->GetTexImage = radeonGetTexImage; + functions->GetCompressedTexImage = radeonGetCompressedTexImage; functions->NewTextureObject = r200NewTextureObject; // functions->BindTexture = r200BindTexture; functions->DeleteTexture = r200DeleteTexture; diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index e316e2d822b..27b907019e3 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -325,6 +325,8 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->TexSubImage1D = radeonTexSubImage1D; functions->TexSubImage2D = radeonTexSubImage2D; functions->TexSubImage3D = radeonTexSubImage3D; + functions->GetTexImage = radeonGetTexImage; + functions->GetCompressedTexImage = radeonGetCompressedTexImage; functions->NewTextureObject = r300NewTextureObject; functions->DeleteTexture = r300DeleteTexture; functions->IsTextureResident = driIsTextureResident; diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index e1b988bf4dc..4d98b72612b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -456,6 +456,8 @@ void radeonInitTextureFuncs( struct dd_function_table *functions ) functions->TexImage2D = radeonTexImage2D; functions->TexSubImage1D = radeonTexSubImage1D; functions->TexSubImage2D = radeonTexSubImage2D; + functions->GetTexImage = radeonGetTexImage; + functions->GetCompressedTexImage = radeonGetCompressedTexImage; functions->NewTextureObject = radeonNewTextureObject; // functions->BindTexture = radeonBindTexture; diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 55dda29eaf9..93ab5f72604 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -883,3 +883,56 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t return GL_TRUE; } + +/** + * Need to map texture image into memory before copying image data, + * then unmap it. + */ +static void +radeon_get_tex_image(GLcontext * ctx, GLenum target, GLint level, + GLenum format, GLenum type, GLvoid * pixels, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, int compressed) +{ + radeon_texture_image *image = get_radeon_texture_image(texImage); + + if (image->mt) { + /* Map the texture image read-only */ + radeon_teximage_map(image, GL_FALSE); + } else { + /* Image hasn't been uploaded to a miptree yet */ + assert(image->base.Data); + } + + if (compressed) { + _mesa_get_compressed_teximage(ctx, target, level, pixels, + texObj, texImage); + } else { + _mesa_get_teximage(ctx, target, level, format, type, pixels, + texObj, texImage); + } + + if (image->mt) { + radeon_teximage_unmap(image); + } +} + +void +radeonGetTexImage(GLcontext * ctx, GLenum target, GLint level, + GLenum format, GLenum type, GLvoid * pixels, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_get_tex_image(ctx, target, level, format, type, pixels, + texObj, texImage, 0); +} + +void +radeonGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level, + GLvoid *pixels, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + radeon_get_tex_image(ctx, target, level, 0, 0, pixels, + texObj, texImage, 1); +} diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h index ff0e1d061ed..d90fda7868f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.h +++ b/src/mesa/drivers/dri/radeon/radeon_texture.h @@ -105,4 +105,14 @@ void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, const struct gl_pixelstore_attrib *packing, struct gl_texture_object *texObj, struct gl_texture_image *texImage); + +void radeonGetTexImage(GLcontext * ctx, GLenum target, GLint level, + GLenum format, GLenum type, GLvoid * pixels, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); +void radeonGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level, + GLvoid *pixels, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage); + #endif -- cgit v1.2.3 From b0e8ac8fd2eeb88b5f9299afb36102113a2435d4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 15 Feb 2009 17:03:47 +1000 Subject: radeon: add cflags to decide whether to link libdrm_radeon or not. You don't need libdrm_radeon for the legacy driver to build, only for the experimental mm/cs paths. --- configs/autoconf.in | 2 ++ configure.ac | 9 +++++++++ src/mesa/drivers/dri/r200/Makefile | 4 +++- src/mesa/drivers/dri/r300/Makefile | 4 +++- src/mesa/drivers/dri/radeon/Makefile | 4 +++- 5 files changed, 20 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/configs/autoconf.in b/configs/autoconf.in index b352974a4c5..d7860294eae 100644 --- a/configs/autoconf.in +++ b/configs/autoconf.in @@ -20,6 +20,8 @@ CXXFLAGS = @CPPFLAGS@ @CXXFLAGS@ \ $(OPT_FLAGS) $(PIC_FLAGS) $(ARCH_FLAGS) $(DEFINES) LDFLAGS = @LDFLAGS@ EXTRA_LIB_PATH = @EXTRA_LIB_PATH@ +RADEON_CFLAGS = @RADEON_CFLAGS@ +RADEON_LDFLAGS = @RADEON_LDFLAGS@ # Assembler MESA_ASM_SOURCES = @MESA_ASM_SOURCES@ diff --git a/configure.ac b/configure.ac index a9a8d5ad0be..ea2992d38b0 100644 --- a/configure.ac +++ b/configure.ac @@ -446,6 +446,8 @@ AC_SUBST([GALLIUM_WINSYS_DRM_DIRS]) AC_SUBST([GALLIUM_DRIVER_DIRS]) AC_SUBST([GALLIUM_AUXILIARY_DIRS]) AC_SUBST([GALLIUM_STATE_TRACKERS_DIRS]) +AC_SUBST([RADEON_CFLAGS]) +AC_SUBST([RADEON_LDFLAGS]) dnl dnl User supplied program configuration @@ -573,6 +575,13 @@ dri) GL_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED dri2proto >= $DRI2PROTO_REQUIRED" DRI_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED" + PKG_CHECK_MODULES([LIBDRM_RADEON], [libdrm_radeon], HAVE_LIBDRM_RADEON=yes, HAVE_LIBDRM_RADEON=no) + + if test "$HAVE_LIBDRM_RADEON" = yes; then + RADEON_CFLAGS="-DHAVE_LIBDRM_RADEON=1 $LIBDRM_RADEON_CFLAGS" + RADEON_LDFLAGS=$LIBDRM_RADEON_LIBS + fi + # find the DRI deps for libGL if test "$x11_pkgconfig" = yes; then # add xcb modules if necessary diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 41c7aed3655..e593ed91c58 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -3,6 +3,8 @@ TOP = ../../../../.. include $(TOP)/configs/current +CFLAGS += $(RADEON_CFLAGS) + LIBNAME = r200_dri.so MINIGLX_SOURCES = server/radeon_dri.c @@ -80,7 +82,7 @@ COMMON_SYMLINKS = \ radeon_dma.c \ radeon_dma.h -DRI_LIB_DEPS += #-ldrm_radeon +DRI_LIB_DEPS += $(RADEON_LDFLAGS) ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 77846a4d676..497b1ec528f 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -3,6 +3,8 @@ TOP = ../../../../.. include $(TOP)/configs/current +CFLAGS += $(RADEON_CFLAGS) + LIBNAME = r300_dri.so MINIGLX_SOURCES = server/radeon_dri.c @@ -96,7 +98,7 @@ COMMON_SYMLINKS = \ radeon_texture.c \ radeon_texture.h -DRI_LIB_DEPS += #-ldrm_radeon +DRI_LIB_DEPS += $(RADEON_LDFLAGS) ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index 0a5775b11c1..f469c6f43a1 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -4,6 +4,8 @@ TOP = ../../../../.. include $(TOP)/configs/current +CFLAGS += $(RADEON_CFLAGS) + LIBNAME = radeon_dri.so MINIGLX_SOURCES = server/radeon_dri.c @@ -39,7 +41,7 @@ C_SOURCES = \ DRIVER_DEFINES = -DRADEON_COMMON=0 -DRI_LIB_DEPS += #-ldrm_radeon +DRI_LIB_DEPS += $(RADEON_LDFLAGS) X86_SOURCES = -- cgit v1.2.3 From f069bc4a8e628197a11ff7eb447a88a59d819689 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Feb 2009 17:16:28 +1000 Subject: radeon: fix compressed tex subimage unpack parameter --- src/mesa/drivers/dri/radeon/radeon_texture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 93ab5f72604..a256440a3c5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -714,7 +714,7 @@ void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, struct gl_texture_image *texImage) { radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, - format, 0, data, 0, texObj, texImage, 1); + format, 0, data, &ctx->Unpack, texObj, texImage, 1); } -- cgit v1.2.3 From ecf0a3eac1a4868da83ab0a3c21e2f265f7cf9e2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Feb 2009 09:49:01 +1000 Subject: radeon: fix texcompress2 test. this makes compressed subimages work properly. --- src/mesa/drivers/dri/radeon/radeon_texture.c | 87 +++++++++++++++++----------- 1 file changed, 53 insertions(+), 34 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index a256440a3c5..4aa081ca347 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -45,6 +45,25 @@ #include "radeon_mipmap_tree.h" + +static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, + GLuint numrows, GLuint rowsize) +{ + assert(rowsize <= dststride); + assert(rowsize <= srcstride); + + if (rowsize == srcstride && rowsize == dststride) { + memcpy(dst, src, numrows*rowsize); + } else { + GLuint i; + for(i = 0; i < numrows; ++i) { + memcpy(dst, src, rowsize); + dst += dststride; + src += srcstride; + } + } +} + /* textures */ /** * Allocate an empty texture image object. @@ -627,12 +646,13 @@ void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, static void radeon_texsubimage(GLcontext* ctx, int dims, int level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, + GLsizei imageSize, GLenum format, GLenum type, const GLvoid * pixels, const struct gl_pixelstore_attrib *packing, struct gl_texture_object *texObj, struct gl_texture_image *texImage, - int compressed) + int compressed) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); @@ -641,8 +661,13 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, radeon_firevertices(rmesa); t->validated = GL_FALSE; - pixels = _mesa_validate_pbo_teximage(ctx, dims, - width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); + if (compressed) { + pixels = _mesa_validate_pbo_compressed_teximage( + ctx, imageSize, pixels, packing, "glCompressedTexImage"); + } else { + pixels = _mesa_validate_pbo_teximage(ctx, dims, + width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); + } if (pixels) { GLint dstRowStride; @@ -655,15 +680,26 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes; } - if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, - texImage->TexFormat, texImage->Data, - xoffset, yoffset, zoffset, - dstRowStride, - texImage->ImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); - + if (compressed) { + uint32_t srcRowStride, bytesPerRow, rows; + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width); + srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + bytesPerRow = srcRowStride; + rows = height / 4; + + copy_rows(texImage->Data, dstRowStride, image->base.Data, srcRowStride, rows, + bytesPerRow); + + } else { + if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, + texImage->TexFormat, texImage->Data, + xoffset, yoffset, zoffset, + dstRowStride, + texImage->ImageOffsets, + width, height, depth, + format, type, pixels, packing)) + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); + } } @@ -687,7 +723,7 @@ void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - radeon_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, + radeon_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, 0, format, type, pixels, packing, texObj, texImage, 0); } @@ -700,8 +736,8 @@ void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, - 1, format, type, pixels, packing, texObj, texImage, + radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, + 0, format, type, pixels, packing, texObj, texImage, 0); } @@ -714,7 +750,7 @@ void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target, struct gl_texture_image *texImage) { radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1, - format, 0, data, &ctx->Unpack, texObj, texImage, 1); + imageSize, format, 0, data, &ctx->Unpack, texObj, texImage, 1); } @@ -727,27 +763,10 @@ void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, struct gl_texture_object *texObj, struct gl_texture_image *texImage) { - radeon_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, + radeon_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, 0, format, type, pixels, packing, texObj, texImage, 0); } -static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, - GLuint numrows, GLuint rowsize) -{ - assert(rowsize <= dststride); - assert(rowsize <= srcstride); - - if (rowsize == srcstride && rowsize == dststride) { - memcpy(dst, src, numrows*rowsize); - } else { - GLuint i; - for(i = 0; i < numrows; ++i) { - memcpy(dst, src, rowsize); - dst += dststride; - src += srcstride; - } - } -} /** -- cgit v1.2.3 From 5325f8624093bb1ec30d581b4ff64218ceab99f9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:25:34 +1000 Subject: dri/radeon: export a function to cleanup a texture object. The radeon legacy code want to cleanup not free the texture obj, so export a function to do that and wrap it. --- src/mesa/drivers/dri/common/texmem.c | 16 +++++++++++++--- src/mesa/drivers/dri/common/texmem.h | 1 + src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 4 +++- 3 files changed, 17 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/common/texmem.c b/src/mesa/drivers/dri/common/texmem.c index ff174a251d2..65c3c4e63e2 100644 --- a/src/mesa/drivers/dri/common/texmem.c +++ b/src/mesa/drivers/dri/common/texmem.c @@ -314,11 +314,10 @@ void driSwapOutTextureObject( driTextureObject * t ) * \param t Texture object to be destroyed */ -void driDestroyTextureObject( driTextureObject * t ) +void driCleanupTextureObject( driTextureObject * t ) { driTexHeap * heap; - if ( 0 ) { fprintf( stderr, "[%s:%d] freeing %p (tObj = %p, DriverData = %p)\n", __FILE__, __LINE__, @@ -350,7 +349,6 @@ void driDestroyTextureObject( driTextureObject * t ) } remove_from_list( t ); - FREE( t ); } if ( 0 ) { @@ -359,6 +357,18 @@ void driDestroyTextureObject( driTextureObject * t ) } +void driDestroyTextureObject( driTextureObject * t ) +{ + driTexHeap * heap; + + if (t == NULL) + return; + + driCleanupTextureObject(t); + FREE(t); +} + + /** diff --git a/src/mesa/drivers/dri/common/texmem.h b/src/mesa/drivers/dri/common/texmem.h index 9c065da8b4f..b9beeeadfca 100644 --- a/src/mesa/drivers/dri/common/texmem.h +++ b/src/mesa/drivers/dri/common/texmem.h @@ -272,6 +272,7 @@ void driAgeTextures( driTexHeap * heap ); void driUpdateTextureLRU( driTextureObject * t ); void driSwapOutTextureObject( driTextureObject * t ); +void driCleanupTextureObject( driTextureObject * t ); void driDestroyTextureObject( driTextureObject * t ); int driAllocateTexture( driTexHeap * const * heap_array, unsigned nr_heaps, driTextureObject * t ); diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 1d25887e691..65b0a9a0ce0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -373,11 +373,13 @@ static void bo_free(struct bo_legacy *bo_legacy) /* dma buffers */ bo_dma_free(&bo_legacy->base); } else { + if (bo_legacy->got_dri_texture_obj) + driCleanupTextureObject(&bo_legacy->dri_texture_obj); + /* free backing store */ free(bo_legacy->ptr); } } - memset(bo_legacy, 0 , sizeof(struct bo_legacy)); free(bo_legacy); } -- cgit v1.2.3 From 7a1dbcabf3f2599c90665e7fdbdba8698528841a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:26:33 +1000 Subject: radeon: move YUV on first texunit check after hw state is setup --- src/mesa/drivers/dri/radeon/radeon_texstate.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 1aa5f980ce2..0dc355723ec 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -985,15 +985,14 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec if (!radeon_validate_texture_miptree(ctx, texObj)) return GL_FALSE; - /* yuv conversion only works in first unit */ - if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) - return GL_FALSE; - - ret = setup_hardware_state(rmesa, t, unit); if (ret == GL_FALSE) return GL_FALSE; + /* yuv conversion only works in first unit */ + if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) + return GL_FALSE; + RADEON_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; -- cgit v1.2.3 From 0a8cba9a65e6ec1159a08725d2101e7eabb4526b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:26:58 +1000 Subject: radeon: steal miptree optimisation from intel codebase This replaces a miptree if it won't distrub anything else. --- src/mesa/drivers/dri/radeon/radeon_texture.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 4aa081ca347..6949ee4502c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -517,6 +517,16 @@ static void radeon_teximage( /* Allocate memory for image */ radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ + if (t->mt && + t->mt->firstLevel == level && + t->mt->lastLevel == level && + t->mt->target != GL_TEXTURE_CUBE_MAP_ARB && + !radeon_miptree_matches_image(t->mt, texImage, face, level)) { + fprintf(stderr,"freeing old miptree\n"); + radeon_miptree_unreference(t->mt); + t->mt = NULL; + } + if (!t->mt) radeon_try_alloc_miptree(rmesa, t, texImage, face, level); if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { -- cgit v1.2.3 From 646325a5efb3cf4157623d115d6d8fa36f0b357d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:27:45 +1000 Subject: radeon: fix not emitting texture state correctly this is whole texture dirty bit is probably not needed with the current codebase, need to revisit --- src/mesa/drivers/dri/radeon/radeon_texstate.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 0dc355723ec..2aa1a833420 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -973,6 +973,8 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; } + + t->dirty_state = R100_TEX_ALL; return GL_TRUE; } -- cgit v1.2.3 From a365f9b78bb493a5202c9a4985de40979ed42038 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:28:43 +1000 Subject: r200: align with r100 code --- src/mesa/drivers/dri/r200/r200_texstate.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index e6aff022b3d..eee4475137b 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1398,7 +1398,8 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { t->pp_txformat |= R200_TXFORMAT_NON_POWER2; } - + + t->dirty_state = R200_TEX_ALL; } static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit) @@ -1439,8 +1440,6 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } - t->dirty_state = R200_TEX_ALL; - t->validated = GL_TRUE; FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); -- cgit v1.2.3 From 62d504d818f1ab1836a134658b1661ceabb65f1f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:34:01 +1000 Subject: radeon/r200: drop dirty state from texture object + pp_txoffset this is just more code cleanup for old dead code --- src/mesa/drivers/dri/r200/r200_state_init.c | 2 +- src/mesa/drivers/dri/r200/r200_tex.c | 4 ---- src/mesa/drivers/dri/r200/r200_texstate.c | 23 +++------------------- .../drivers/dri/radeon/radeon_common_context.h | 20 +------------------ src/mesa/drivers/dri/radeon/radeon_state_init.c | 2 +- src/mesa/drivers/dri/radeon/radeon_tex.c | 4 ---- src/mesa/drivers/dri/radeon/radeon_texstate.c | 13 ++++-------- 7 files changed, 10 insertions(+), 58 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 0366fc0fbe4..013064d2b3f 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -553,7 +553,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) /* workaround for old CS mechanism */ OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); } else if (t->image_override) - OUT_BATCH(atom->cmd[10]); + OUT_BATCH(t->override_offset); END_BATCH(); } diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 5daacb8c95a..19a6cad80bd 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -400,10 +400,6 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, default: return; } - - /* Mark this texobj as dirty (one bit per tex unit) - */ - t->dirty_state = R200_TEX_ALL; } diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index eee4475137b..6432068760b 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -743,7 +743,8 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - t->pp_txoffset = offset; + t->bo = NULL; + t->override_offset = offset; t->pp_txpitch = pitch - 32; switch (depth) { @@ -1003,18 +1004,9 @@ static void import_tex_obj_state( r200ContextPtr rmesa, cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */ cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */ cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; - if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { - cmd[TEX_PP_TXOFFSET_NEWDRM] = texobj->pp_txoffset; - } - else { - cmd[TEX_PP_TXOFFSET_OLDDRM] = texobj->pp_txoffset; - } if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) { GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; - // GLuint bytesPerFace = texobj->base.totalSize / 6; - // ASSERT(texobj->base.totalSize % 6 == 0); - GLuint bytesPerFace = 1; // TODO R200_STATECHANGE( rmesa, cube[unit] ); cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; @@ -1023,14 +1015,8 @@ static void import_tex_obj_state( r200ContextPtr rmesa, to not include that command when new drm is used */ cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces; } - cube_cmd[CUBE_PP_CUBIC_OFFSET_F1] = texobj->pp_txoffset + 1 * bytesPerFace; - cube_cmd[CUBE_PP_CUBIC_OFFSET_F2] = texobj->pp_txoffset + 2 * bytesPerFace; - cube_cmd[CUBE_PP_CUBIC_OFFSET_F3] = texobj->pp_txoffset + 3 * bytesPerFace; - cube_cmd[CUBE_PP_CUBIC_OFFSET_F4] = texobj->pp_txoffset + 4 * bytesPerFace; - cube_cmd[CUBE_PP_CUBIC_OFFSET_F5] = texobj->pp_txoffset + 5 * bytesPerFace; } - texobj->dirty_state &= ~(1<pp_txformat |= R200_TXFORMAT_NON_POWER2; } - t->dirty_state = R200_TEX_ALL; } static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit) @@ -1429,9 +1414,7 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); rmesa->recheck_texgen[unit] = GL_TRUE; - if (t->dirty_state & (1<recheck_texgen[unit]) { GLboolean fallback = !r200_validate_texgen( ctx, unit ); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index c9be104578e..7618b3482f3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -170,7 +170,6 @@ typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; /* Texture object in locally shared texture space. */ struct radeon_tex_obj { - // driTextureObject base; struct gl_texture_object base; struct _radeon_mipmap_tree *mt; @@ -185,26 +184,9 @@ struct radeon_tex_obj { GLuint tile_bits; /* hw texture tile bits used on this texture */ struct radeon_bo *bo; - GLuint bufAddr; /* Offset to start of locally - shared texture block */ - - GLuint dirty_state; /* Flags (1 per texunit) for - whether or not this texobj - has dirty hardware state - (pp_*) that needs to be - brought into the - texunit. */ - - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; - /* Six, for the cube faces */ - - - GLuint pp_txfilter; /* hardware register values */ GLuint pp_txformat; - GLuint pp_txformat_x; - GLuint pp_txoffset; /* Image location in texmem. - All cube faces follow. */ + GLuint pp_txformat_x; GLuint pp_txsize; /* npot only */ GLuint pp_txpitch; /* npot only */ GLuint pp_border_color; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 998ae796240..617e731a411 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -486,7 +486,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); // OUT_BATCH(r100->radeon.radeonScreen); } else if (t->image_override) - OUT_BATCH(atom->cmd[4]); + OUT_BATCH(t->override_offset); OUT_BATCH_TABLE((atom->cmd+4), 5); END_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 4d98b72612b..2dfb5042ecc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -362,10 +362,6 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, default: return; } - - /* Mark this texobj as dirty (one bit per tex unit) - */ - t->dirty_state = R100_TEX_ALL; } static void radeonDeleteTexture( GLcontext *ctx, diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 2aa1a833420..6a34f1e3328 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -614,8 +614,9 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - - t->pp_txoffset = offset; + + t->bo = NULL; + t->override_offset = offset; t->pp_txpitch = pitch - 32; switch (depth) { @@ -715,7 +716,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa, cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK; - cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset; cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) { @@ -742,8 +742,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa, rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt; } - texobj->dirty_state &= ~(1<radeon.NewGLState |= _NEW_TEXTURE_MATRIX; } @@ -974,7 +972,6 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; } - t->dirty_state = R100_TEX_ALL; return GL_TRUE; } @@ -1004,9 +1001,7 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec rmesa->recheck_texgen[unit] = GL_TRUE; - if (t->dirty_state & (1<recheck_texgen[unit]) { GLboolean fallback = !radeon_validate_texgen( ctx, unit ); -- cgit v1.2.3 From 43c71a2d40d417cf721656e8b088e375dc4bdedb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 10:42:51 +1000 Subject: radeon: remove leftover debug --- src/mesa/drivers/dri/radeon/radeon_texture.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 6949ee4502c..63680b495c9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -522,7 +522,6 @@ static void radeon_teximage( t->mt->lastLevel == level && t->mt->target != GL_TEXTURE_CUBE_MAP_ARB && !radeon_miptree_matches_image(t->mt, texImage, face, level)) { - fprintf(stderr,"freeing old miptree\n"); radeon_miptree_unreference(t->mt); t->mt = NULL; } -- cgit v1.2.3 From 7c7ff659ce7684f44b064c09cdca6436d2c2bf64 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 11:17:22 +1000 Subject: radeon: fixup destroy texture object exit path and update LRU the destroy path was doing bad things with structure names, make it do less bad things, use container_of instead --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 65b0a9a0ce0..1cc039c8440 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -32,6 +32,7 @@ * Jérôme Glisse */ #include +#include #include #include #include @@ -51,7 +52,6 @@ struct bo_legacy { struct radeon_bo base; - driTextureObject tobj_base; int map_count; uint32_t pending; int is_pending; @@ -85,11 +85,15 @@ struct bo_manager_legacy { unsigned *free_handles; }; +#define container_of(ptr, type, member) ({ \ + const __typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + static void bo_legacy_tobj_destroy(void *data, driTextureObject *t) { - struct bo_legacy *bo_legacy; + struct bo_legacy *bo_legacy = container_of(t, struct bo_legacy, dri_texture_obj); + - bo_legacy = (struct bo_legacy*)((char*)t)-sizeof(struct radeon_bo); bo_legacy->got_dri_texture_obj = 0; bo_legacy->validated = 0; } @@ -535,6 +539,9 @@ static int bo_vram_validate(struct radeon_bo *bo, bo_legacy->got_dri_texture_obj = 1; bo_legacy->dirty = 1; } + + if (bo_legacy->got_dri_texture_obj) + driUpdateTextureLRU(&bo_legacy->dri_texture_obj); if (bo_legacy->dirty) { /* Copy to VRAM using a blit. * All memory is 4K aligned. We're using 1024 pixels wide blits. -- cgit v1.2.3 From 48e7b940ebc2cb3594074ca35fad9c63f6568582 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 13:39:38 +1000 Subject: radeon/r200: fixup texturing aging calls --- src/mesa/drivers/dri/r200/r200_context.c | 5 ++--- src/mesa/drivers/dri/radeon/radeon_context.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index d567bb77df9..a9cb2e2fe91 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -246,11 +246,10 @@ static void r200_get_lock(radeonContextPtr radeon) if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) { sarea->ctx_owner = rmesa->radeon.dri.hwContext; + if (!radeon->radeonScreen->kernel_mm) + radeon_bo_legacy_texture_age(radeon->radeonScreen->bom); } - for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { - DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] ); - } } static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 7db62be7afd..f562876db4b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -164,9 +164,8 @@ static void r100_get_lock(radeonContextPtr radeon) int i; sarea->ctx_owner = rmesa->radeon.dri.hwContext; - for (i = 0; i < rmesa->radeon.nr_heaps; i++) { - DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]); - } + if (!radeon->radeonScreen->kernel_mm) + radeon_bo_legacy_texture_age(radeon->radeonScreen->bom); } } -- cgit v1.2.3 From 2ba4fc3d603ebc9e3210ef96f9fbc2cd488e0a33 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 14:00:24 +1000 Subject: radeon/r200: drop legacy texture heap code --- src/mesa/drivers/dri/r200/r200_context.c | 53 ---------------------- .../drivers/dri/radeon/radeon_common_context.h | 3 -- src/mesa/drivers/dri/radeon/radeon_context.c | 51 --------------------- 3 files changed, 107 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index a9cb2e2fe91..a744469b31c 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -331,25 +331,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, return GL_FALSE; } - - (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); - make_empty_list( & rmesa->radeon.swapped ); - - rmesa->radeon.nr_heaps = 1 /* screen->numTexHeaps */ ; - assert(rmesa->radeon.nr_heaps < RADEON_NR_TEX_HEAPS); -#if 0 - for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { - rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa, - screen->texSize[i], - 12, - RADEON_NR_TEX_REGIONS, - (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i], - & rmesa->radeon.sarea->tex_age[i], - & rmesa->radeon.swapped, - sizeof( radeonTexObj ), - (destroy_texture_object_t *) r200DestroyTexObj ); - } -#endif rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, "texture_depth"); if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) @@ -373,22 +354,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); - driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps, - rmesa->radeon.nr_heaps, - & ctx->Const, - 4, - 11, /* max 2D texture size is 2048x2048 */ -#if ENABLE_HW_3D_TEXTURE - 8, /* max 3D texture size is 256^3 */ -#else - 0, /* 3D textures unsupported */ -#endif - 11, /* max cube texture size is 2048x2048 */ - 11, /* max texture rectangle size is 2048x2048 */ - 12, - GL_FALSE, - i ); - ctx->Const.MaxTextureMaxAnisotropy = 16.0; /* No wide AA points. @@ -541,10 +506,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) /* Free r200 context resources */ assert(rmesa); /* should never be null */ if ( rmesa ) { - GLboolean release_texture_heaps; - - release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1); _swsetup_DestroyContext( rmesa->radeon.glCtx ); _tnl_DestroyContext( rmesa->radeon.glCtx ); _vbo_DestroyContext( rmesa->radeon.glCtx ); @@ -563,21 +525,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) rmesa->radeon.state.scissor.pClipRects = NULL; } - - if ( release_texture_heaps ) { - /* This share group is about to go away, free our private - * texture object data. - */ - int i; - - for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { - driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] ); - rmesa->radeon.texture_heaps[ i ] = NULL; - } - - assert( is_empty_list( & rmesa->radeon.swapped ) ); - } - radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 7618b3482f3..a200e902210 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -375,9 +375,6 @@ struct radeon_context { /* Texture object bookkeeping */ - unsigned nr_heaps; - driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; - driTextureObject swapped; int texture_depth; float initialMaxAnisotropy; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index f562876db4b..e4202c71fc5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -161,7 +161,6 @@ static void r100_get_lock(radeonContextPtr radeon) } if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { - int i; sarea->ctx_owner = rmesa->radeon.dri.hwContext; if (!radeon->radeonScreen->kernel_mm) @@ -255,26 +254,6 @@ radeonCreateContext( const __GLcontextModes *glVisual, return GL_FALSE; } - (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) ); - make_empty_list( & rmesa->radeon.swapped ); - -#if 0 - rmesa->radeon.nr_heaps = screen->numTexHeaps; - for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { - rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa, - screen->texSize[i], - 12, - RADEON_NR_TEX_REGIONS, - (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i], - & rmesa->radeon.sarea->tex_age[i], - & rmesa->radeon.swapped, - sizeof( radeonTexObj ), - (destroy_texture_object_t *) radeonDestroyTexObj ); - - driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i], - & rmesa->c_textureSwaps ); - } -#endif rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, "texture_depth"); if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) @@ -298,19 +277,6 @@ radeonCreateContext( const __GLcontextModes *glVisual, i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); - driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps, - rmesa->radeon.nr_heaps, - & ctx->Const, - 4, - 11, /* max 2D texture size is 2048x2048 */ - 8, /* 256^3 */ - 9, /* \todo: max cube texture size seems to be 512x512(x6) */ - 11, /* max rect texture size is 2048x2048. */ - 12, - GL_FALSE, - i ); - - ctx->Const.MaxTextureMaxAnisotropy = 16.0; /* No wide points. @@ -450,10 +416,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) /* Free radeon context resources */ assert(rmesa); /* should never be null */ if ( rmesa ) { - GLboolean release_texture_heaps; - - release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1); _swsetup_DestroyContext( rmesa->radeon.glCtx ); _tnl_DestroyContext( rmesa->radeon.glCtx ); _vbo_DestroyContext( rmesa->radeon.glCtx ); @@ -473,20 +436,6 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) rmesa->radeon.state.scissor.pClipRects = NULL; } - if ( release_texture_heaps ) { - /* This share group is about to go away, free our private - * texture object data. - */ - int i; - - for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) { - driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] ); - rmesa->radeon.texture_heaps[ i ] = NULL; - } - - assert( is_empty_list( & rmesa->radeon.swapped ) ); - } - radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); -- cgit v1.2.3 From 7ce6af25e56e28a819c38e60b4371caea3c8b5b0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 14:46:12 +1000 Subject: Revert "dri/radeon: export a function to cleanup a texture object." This reverts commit 5325f8624093bb1ec30d581b4ff64218ceab99f9. --- src/mesa/drivers/dri/common/texmem.c | 16 +++------------- src/mesa/drivers/dri/common/texmem.h | 1 - src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 4 +--- 3 files changed, 4 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/common/texmem.c b/src/mesa/drivers/dri/common/texmem.c index 65c3c4e63e2..ff174a251d2 100644 --- a/src/mesa/drivers/dri/common/texmem.c +++ b/src/mesa/drivers/dri/common/texmem.c @@ -314,10 +314,11 @@ void driSwapOutTextureObject( driTextureObject * t ) * \param t Texture object to be destroyed */ -void driCleanupTextureObject( driTextureObject * t ) +void driDestroyTextureObject( driTextureObject * t ) { driTexHeap * heap; + if ( 0 ) { fprintf( stderr, "[%s:%d] freeing %p (tObj = %p, DriverData = %p)\n", __FILE__, __LINE__, @@ -349,6 +350,7 @@ void driCleanupTextureObject( driTextureObject * t ) } remove_from_list( t ); + FREE( t ); } if ( 0 ) { @@ -357,18 +359,6 @@ void driCleanupTextureObject( driTextureObject * t ) } -void driDestroyTextureObject( driTextureObject * t ) -{ - driTexHeap * heap; - - if (t == NULL) - return; - - driCleanupTextureObject(t); - FREE(t); -} - - /** diff --git a/src/mesa/drivers/dri/common/texmem.h b/src/mesa/drivers/dri/common/texmem.h index b9beeeadfca..9c065da8b4f 100644 --- a/src/mesa/drivers/dri/common/texmem.h +++ b/src/mesa/drivers/dri/common/texmem.h @@ -272,7 +272,6 @@ void driAgeTextures( driTexHeap * heap ); void driUpdateTextureLRU( driTextureObject * t ); void driSwapOutTextureObject( driTextureObject * t ); -void driCleanupTextureObject( driTextureObject * t ); void driDestroyTextureObject( driTextureObject * t ); int driAllocateTexture( driTexHeap * const * heap_array, unsigned nr_heaps, driTextureObject * t ); diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 1cc039c8440..93838b5d92f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -377,13 +377,11 @@ static void bo_free(struct bo_legacy *bo_legacy) /* dma buffers */ bo_dma_free(&bo_legacy->base); } else { - if (bo_legacy->got_dri_texture_obj) - driCleanupTextureObject(&bo_legacy->dri_texture_obj); - /* free backing store */ free(bo_legacy->ptr); } } + memset(bo_legacy, 0 , sizeof(struct bo_legacy)); free(bo_legacy); } -- cgit v1.2.3 From 9c040745fe1d8c6cad3ac79030ead13fbcb5ae4d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 14:48:49 +1000 Subject: radeon: legacy texMem interface fixups. The texmem.c interface is wildly messed up it really wants to own the objects so let it, pain in the ass but this code should work a lot better now --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 48 +++++++++++++++----------- 1 file changed, 28 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 93838b5d92f..93ca325e88a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -49,18 +49,23 @@ #include "radeon_common.h" #include "radeon_bocs_wrapper.h" +/* no seriously texmem.c is this screwed up */ +struct bo_legacy_texture_object { + driTextureObject base; + struct bo_legacy *parent; +}; struct bo_legacy { struct radeon_bo base; int map_count; uint32_t pending; int is_pending; - int validated; int static_bo; int got_dri_texture_obj; - int dirty; uint32_t offset; - driTextureObject dri_texture_obj; + struct bo_legacy_texture_object *tobj; + int validated; + int dirty; void *ptr; struct bo_legacy *next, *prev; struct bo_legacy *pnext, *pprev; @@ -85,17 +90,14 @@ struct bo_manager_legacy { unsigned *free_handles; }; -#define container_of(ptr, type, member) ({ \ - const __typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - static void bo_legacy_tobj_destroy(void *data, driTextureObject *t) { - struct bo_legacy *bo_legacy = container_of(t, struct bo_legacy, dri_texture_obj); - - - bo_legacy->got_dri_texture_obj = 0; - bo_legacy->validated = 0; + struct bo_legacy_texture_object *tobj = (struct bo_legacy_texture_object *)t; + + if (tobj->parent) { + tobj->parent->got_dri_texture_obj = 0; + tobj->parent->validated = 0; + } } static void inline clean_handles(struct bo_manager_legacy *bom) @@ -247,7 +249,6 @@ static void legacy_track_pending(struct bo_manager_legacy *boml, int debug) static int legacy_wait_any_pending(struct bo_manager_legacy *boml) { struct bo_legacy *bo_legacy; - struct bo_legacy *next; legacy_get_current_age(boml); bo_legacy = boml->pending_bos.pnext; @@ -377,6 +378,8 @@ static void bo_free(struct bo_legacy *bo_legacy) /* dma buffers */ bo_dma_free(&bo_legacy->base); } else { + driDestroyTextureObject(&bo_legacy->tobj->base); + bo_legacy->tobj = NULL; /* free backing store */ free(bo_legacy->ptr); } @@ -522,10 +525,12 @@ static int bo_vram_validate(struct radeon_bo *bo, int r; if (!bo_legacy->got_dri_texture_obj) { - make_empty_list(&bo_legacy->dri_texture_obj); - bo_legacy->dri_texture_obj.totalSize = bo->size; + bo_legacy->tobj = CALLOC(sizeof(struct bo_legacy_texture_object)); + bo_legacy->tobj->parent = bo_legacy; + make_empty_list(&bo_legacy->tobj->base); + bo_legacy->tobj->base.totalSize = bo->size; r = driAllocateTexture(&boml->texture_heap, 1, - &bo_legacy->dri_texture_obj); + &bo_legacy->tobj->base); if (r) { uint8_t *segfault=NULL; fprintf(stderr, "Ouch! vram_validate failed %d\n", r); @@ -533,14 +538,15 @@ static int bo_vram_validate(struct radeon_bo *bo, return -1; } bo_legacy->offset = boml->texture_offset + - bo_legacy->dri_texture_obj.memBlock->ofs; + bo_legacy->tobj->base.memBlock->ofs; bo_legacy->got_dri_texture_obj = 1; bo_legacy->dirty = 1; } if (bo_legacy->got_dri_texture_obj) - driUpdateTextureLRU(&bo_legacy->dri_texture_obj); - if (bo_legacy->dirty) { + driUpdateTextureLRU(&bo_legacy->tobj->base); + + if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) { /* Copy to VRAM using a blit. * All memory is 4K aligned. We're using 1024 pixels wide blits. */ @@ -578,6 +584,7 @@ static int bo_vram_validate(struct radeon_bo *bo, } } while (ret == -EAGAIN); bo_legacy->dirty = 0; + bo_legacy->tobj->base.dirty_images[0] = 0; } return 0; } @@ -646,6 +653,7 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom) bo_free(bo_legacy); bo_legacy = next; } + driDestroyTextureHeap(boml->texture_heap); free(boml->free_handles); free(boml); } @@ -689,7 +697,7 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc (drmTextureRegionPtr)scrn->sarea->tex_list[0], &scrn->sarea->tex_age[0], &bom->texture_swapped, - sizeof(struct bo_legacy), + sizeof(struct bo_legacy_texture_object), &bo_legacy_tobj_destroy); bom->texture_offset = scrn->texOffset[0]; -- cgit v1.2.3 From 745c78733822573a5791fbae9b3e8fab785f7aca Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 17 Feb 2009 16:01:16 +1000 Subject: radeon: initialise swapped objects pointer --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 93ca325e88a..c40e1401873 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -689,6 +689,8 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc return NULL; } + make_empty_list(&bom->texture_swapped); + bom->texture_heap = driCreateTextureHeap(0, bom, scrn->texSize[0], -- cgit v1.2.3 From e9d6beaab4c4b47576fb422ace0434e0fbbe567a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 18 Feb 2009 10:45:42 +1000 Subject: radeon: move device param id check ifndef --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 97467b22ce9..f80f0f7b226 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -1,6 +1,10 @@ #ifndef RADEON_CS_WRAPPER_H #define RADEON_CS_WRAPPER_H +#ifndef RADEON_PARAM_DEVICE_ID +#define RADEON_PARAM_DEVICE_ID 17 +#endif + #ifdef HAVE_LIBDRM_RADEON #include "radeon_bo.h" @@ -31,9 +35,6 @@ struct drm_radeon_gem_info { }; #endif -#ifndef RADEON_PARAM_DEVICE_ID -#define RADEON_PARAM_DEVICE_ID 17 -#endif -- cgit v1.2.3 From da17b36412155e0ed52b2c23eebd64662f642ac2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 18 Feb 2009 10:46:11 +1000 Subject: r300: make DRI2 not crash on compiz start --- src/mesa/drivers/dri/r300/r300_texstate.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index e5afff0d61c..25cd4d885ed 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -196,8 +196,10 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) */ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) { - const struct gl_texture_image *firstImage = - t->base.Image[0][t->mt->firstLevel]; + const struct gl_texture_image *firstImage; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + + firstImage = t->base.Image[0][firstlevel]; if (!t->image_override && VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { @@ -214,6 +216,14 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) return; } + if (t->image_override) + return; + + t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) + | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT) + | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT) + | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT)); + t->tile_bits = 0; if (t->base.Target == GL_TEXTURE_CUBE_MAP) @@ -221,10 +231,6 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) if (t->base.Target == GL_TEXTURE_3D) t->pp_txformat |= R300_TX_FORMAT_3D; - t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) - | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT) - | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT) - | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT)); if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { unsigned int align = (64 / t->mt->bpp) - 1; @@ -310,7 +316,10 @@ again: i); } t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); - bos[num_bo].bo = t->mt->bo; + if (t->image_override && t->bo) + bos[num_bo].bo = t->bo; + else if (t->mt->bo) + bos[num_bo].bo = t->mt->bo; bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; bos[num_bo].write_domain = 0; bos[num_bo].new_accounted = 0; @@ -440,6 +449,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) rImage->bo = rb->bo; t->bo = rb->bo; + radeon_bo_ref(t->bo); t->tile_bits = 0; t->image_override = GL_TRUE; t->override_offset = 0; -- cgit v1.2.3 From b4a90c62134e7cf3af4ce52baa923a875ff292c1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:32:24 +1000 Subject: radeon: fixup legacy bo/cs out of VRAM waiting. This is similiar to the code from the F10 r300 bufmgr --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 70 +++++++++++++++++++++----- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 4 +- 2 files changed, 60 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index c40e1401873..03a6299ed8a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -61,7 +61,6 @@ struct bo_legacy { uint32_t pending; int is_pending; int static_bo; - int got_dri_texture_obj; uint32_t offset; struct bo_legacy_texture_object *tobj; int validated; @@ -95,8 +94,8 @@ static void bo_legacy_tobj_destroy(void *data, driTextureObject *t) struct bo_legacy_texture_object *tobj = (struct bo_legacy_texture_object *)t; if (tobj->parent) { - tobj->parent->got_dri_texture_obj = 0; - tobj->parent->validated = 0; + tobj->parent->tobj = NULL; + tobj->parent->validated = 0; } } @@ -258,6 +257,23 @@ static int legacy_wait_any_pending(struct bo_manager_legacy *boml) return 0; } +static void legacy_kick_all_buffers(struct bo_manager_legacy *boml) +{ + struct bo_legacy *legacy; + + legacy = boml->bos.next; + while (legacy != &boml->bos) { + if (legacy->tobj) { + if (legacy->validated) { + driDestroyTextureObject(&legacy->tobj->base); + legacy->tobj = 0; + legacy->validated = 0; + } + } + legacy = legacy->next; + } +} + static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, uint32_t size, uint32_t alignment, @@ -286,7 +302,6 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml, bo_legacy->map_count = 0; bo_legacy->next = NULL; bo_legacy->prev = NULL; - bo_legacy->got_dri_texture_obj = 0; bo_legacy->pnext = NULL; bo_legacy->pprev = NULL; bo_legacy->next = boml->bos.next; @@ -523,27 +538,38 @@ static int bo_vram_validate(struct radeon_bo *bo, struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; int r; + int retry_count = 0, pending_retry = 0; - if (!bo_legacy->got_dri_texture_obj) { + if (!bo_legacy->tobj) { bo_legacy->tobj = CALLOC(sizeof(struct bo_legacy_texture_object)); bo_legacy->tobj->parent = bo_legacy; make_empty_list(&bo_legacy->tobj->base); bo_legacy->tobj->base.totalSize = bo->size; + retry: r = driAllocateTexture(&boml->texture_heap, 1, &bo_legacy->tobj->base); if (r) { - uint8_t *segfault=NULL; - fprintf(stderr, "Ouch! vram_validate failed %d\n", r); - *segfault=1; - return -1; - } + pending_retry = 0; + while(boml->cpendings && pending_retry++ < 10000) { + legacy_track_pending(boml, 0); + retry_count++; + if (retry_count > 2) { + free(bo_legacy->tobj); + bo_legacy->tobj = NULL; + fprintf(stderr, "Ouch! vram_validate failed %d\n", r); + return -1; + } + goto retry; + } + } bo_legacy->offset = boml->texture_offset + bo_legacy->tobj->base.memBlock->ofs; - bo_legacy->got_dri_texture_obj = 1; bo_legacy->dirty = 1; } - if (bo_legacy->got_dri_texture_obj) + assert(bo_legacy->tobj->base.memBlock); + + if (bo_legacy->tobj) driUpdateTextureLRU(&bo_legacy->tobj->base); if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) { @@ -589,12 +615,21 @@ static int bo_vram_validate(struct radeon_bo *bo, return 0; } +/* + * radeon_bo_legacy_validate - + * returns: + * 0 - all good + * -EINVAL - mapped buffer can't be validated + * -EAGAIN - restart validation we've kicked all the buffers out + */ int radeon_bo_legacy_validate(struct radeon_bo *bo, uint32_t *soffset, uint32_t *eoffset) { + struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom; struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; int r; + int retries = 0; if (bo_legacy->map_count) { fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n", @@ -607,9 +642,18 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo, return 0; } if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) { + r = bo_vram_validate(bo, soffset, eoffset); if (r) { - return r; + legacy_track_pending(boml, 0); + legacy_kick_all_buffers(boml); + retries++; + if (retries == 2) { + fprintf(stderr,"legacy bo: failed to get relocations into aperture\n"); + assert(0); + exit(-1); + } + return -EAGAIN; } } *soffset = bo_legacy->offset; diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index aa95d86cd48..3acc206a8b9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -216,12 +216,15 @@ static int cs_process_relocs(struct radeon_cs *cs) csm = (struct cs_manager_legacy*)cs->csm; relocs = (struct cs_reloc_legacy *)cs->relocs; + restart: for (i = 0; i < cs->crelocs; i++) { for (j = 0; j < relocs[i].cindices; j++) { uint32_t soffset, eoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); + if (r == -EAGAIN) + goto restart; if (r) { fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); @@ -276,7 +279,6 @@ static int cs_emit(struct radeon_cs *cs) csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); - /* append buffer age */ if (IS_R300_CLASS(csm->ctx->radeonScreen)) { age.scratch.cmd_type = R300_CMD_SCRATCH; -- cgit v1.2.3 From d4bfe34cb9a06f887e243cde936982342d4894c6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:33:05 +1000 Subject: radeon: make state atom print like old r300 code --- src/mesa/drivers/dri/radeon/radeon_common.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index e816760e66b..6b161ef7a60 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -574,14 +574,15 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, } -static void radeon_print_state_atom( struct radeon_state_atom *state ) +static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state ) { int i; + int dwords = (*state->check)(radeon->glCtx, state); - fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); + fprintf(stderr, "emit %s %d/%d\n", state->name, state->cmd_size, dwords); if (RADEON_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < state->cmd_size ; i++) + for (i = 0 ; i < dwords; i++) fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); } @@ -601,7 +602,7 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) dwords = (*atom->check) (radeon->glCtx, atom); if (dwords) { if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(atom); + radeon_print_state_atom(radeon, atom); } if (atom->emit) { (*atom->emit)(radeon->glCtx, atom); -- cgit v1.2.3 From 77161c5ff51a7b8fcd7043b94c2cb86cb1d57d79 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:33:35 +1000 Subject: radeon: add some debugging for flush ioctls --- src/mesa/drivers/dri/radeon/radeon_common.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 6b161ef7a60..3c491d584a0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -715,6 +715,12 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) exit(-1); } rmesa->cmdbuf.flushing = 1; + + if (RADEON_DEBUG & DEBUG_IOCTL) { + fprintf(stderr, "%s from %s - %i cliprects\n", + __FUNCTION__, caller, rmesa->numClipRects); + } + if (rmesa->cmdbuf.cs->cdw) { ret = radeon_cs_emit(rmesa->cmdbuf.cs); rmesa->hw.all_dirty = GL_TRUE; @@ -832,6 +838,11 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n, radeonEmitState(rmesa); } radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); + + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "BEGIN_BATCH(%d) at %d, from %s:%i\n", + n, rmesa->cmdbuf.cs->cdw, function, line); + } -- cgit v1.2.3 From 8c239704792712c246d04450cab8aa167ed8680c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:33:51 +1000 Subject: radeon: stabilise r300 driver like the F10 mesa bufmgr For some reason flushs caused by this CS needs flush hook, caused the chip to lockup on r300 under compiz, whereas the F10 driver was rock solid. --- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 3acc206a8b9..b47b095cf20 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -364,8 +364,9 @@ static int cs_erase(struct radeon_cs *cs) static int cs_need_flush(struct radeon_cs *cs) { - /* FIXME: we should get the texture heap size */ - return (cs->relocs_total_size > (7*1024*1024)); + /* this function used to flush when the BO usage got to + * a certain size, now the higher levels handle this better */ + return 0; } static void cs_print(struct radeon_cs *cs, FILE *file) -- cgit v1.2.3 From 6ffd472b0e44f835c1c8880e3e27bdd33905e08e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:35:10 +1000 Subject: r300: set u to 0 so debug logs are easier to read --- src/mesa/drivers/dri/r300/r300_emit.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 6c026466058..6bc8f8e9449 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -50,6 +50,7 @@ static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, if (!rscrn->kernel_mm) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.packet0.cmd_type = R300_CMD_PACKET0; cmd.packet0.count = count; cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8; @@ -67,6 +68,7 @@ static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.vpu.cmd_type = R300_CMD_VPU; cmd.vpu.count = count; cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8; @@ -80,6 +82,7 @@ static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn, { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.r500fp.cmd_type = R300_CMD_R500FP; cmd.r500fp.count = count; cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8; @@ -94,6 +97,7 @@ static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.packet3.cmd_type = R300_CMD_PACKET3; cmd.packet3.packet = packet; @@ -105,6 +109,8 @@ static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, { drm_r300_cmd_header_t cmd; + cmd.u = 0; + cmd.delay.cmd_type = R300_CMD_CP_DELAY; cmd.delay.count = count; @@ -116,6 +122,7 @@ static INLINE uint32_t cmdwait(struct radeon_screen *rscrn, { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.wait.cmd_type = R300_CMD_WAIT; cmd.wait.flags = flags; @@ -126,6 +133,7 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) { drm_r300_cmd_header_t cmd; + cmd.u = 0; cmd.header.cmd_type = R300_CMD_END3D; return cmd.u; -- cgit v1.2.3 From 13ed7985b245770259681d9dc6bff16354a78be5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:37:23 +1000 Subject: r300: use OUT_BATCH_REGVAL in a few more places --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 24 ++++++++++++------------ src/mesa/drivers/dri/r300/r300_context.c | 3 +-- 2 files changed, 13 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 29b2c2eb25c..ac1c12873b3 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -97,24 +97,20 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; ndw = cmd.vpu.count * 4; if (ndw) { - BEGIN_BATCH_NO_AUTOSTATE(11 + ndw); + BEGIN_BATCH_NO_AUTOSTATE(13 + ndw); /* flush processing vertices */ - OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); - OUT_BATCH(0x0); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH((1 << 15) | (1 << 28)); - OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); - OUT_BATCH(0x00FFFFFF); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); - OUT_BATCH(1); - /* write vpu */ - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0)); - OUT_BATCH(addr); + OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0); + OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff); + OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 1); + OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr); OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); for (i = 0; i < ndw; i++) { OUT_BATCH(atom->cmd[i+1]); } + OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); END_BATCH(); } } @@ -180,6 +176,10 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) END_BATCH(); } else if (!t) { //assert(0); + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + END_BATCH(); } else { if (t->bo) { BEGIN_BATCH_NO_AUTOSTATE(4); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 6d68309d3f0..dd63add8340 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -238,8 +238,7 @@ static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) BATCH_LOCALS(radeon); cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(cmdpacket0(radeon->radeonScreen, R300_TX_INVALTAGS, 1)); - OUT_BATCH(R300_TX_FLUSH); + OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); END_BATCH(); end_3d(radeon); } -- cgit v1.2.3 From 018f5f92cc8f41f6071af4fe16745ccc19231e18 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:48:52 +1000 Subject: r300: revert back autostate change on cacheflush emit --- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 20afae6a097..1512e906e89 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -360,7 +360,7 @@ void r300EmitCacheFlush(r300ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH(4); OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); -- cgit v1.2.3 From f4502f0f8c065f28c257b7be67021d3920e51a99 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 13:49:29 +1000 Subject: radeon: add more debug info to the flush debug --- src/mesa/drivers/dri/radeon/radeon_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 3c491d584a0..f7c0d7d64f5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -663,7 +663,7 @@ void radeonFlush(GLcontext *ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); + fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); if (radeon->dma.flush) radeon->dma.flush( ctx ); -- cgit v1.2.3 From c32a28d86eda3d1984f6a571be0db6c6f5c7f5dc Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Feb 2009 15:41:30 +1000 Subject: r300: fixup old setTexOffset DRI1 extension --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 20 +++++--------------- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 14 ++++++++------ 3 files changed, 14 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index ac1c12873b3..c3a808ca79f 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -97,7 +97,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; ndw = cmd.vpu.count * 4; if (ndw) { - BEGIN_BATCH_NO_AUTOSTATE(13 + ndw); + BEGIN_BATCH_NO_AUTOSTATE(15 + ndw); /* flush processing vertices */ OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0); @@ -166,35 +166,25 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) if (numtmus) { int i; + BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus); for(i = 0; i < numtmus; ++i) { radeonTexObj *t = r300->hw.textures[i]; + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); if (t && !t->image_override) { - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); } else if (!t) { - //assert(0); - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); - END_BATCH(); - } else { + } else { /* override cases */ if (t->bo) { - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); } else if (!r300->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH(t->override_offset); - END_BATCH(); } } } + END_BATCH(); } } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 25cd4d885ed..4f145bdbb4e 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -216,7 +216,7 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) return; } - if (t->image_override) + if (t->image_override && t->bo) return; t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 086a2683e5b..f8de799a6da 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -983,20 +983,22 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->extensions[i++] = &driMediaStreamCounterExtension.base; } + if (!screen->kernel_mm) { #if !RADEON_COMMON - screen->extensions[i++] = &radeonTexOffsetExtension.base; + screen->extensions[i++] = &radeonTexOffsetExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) - if (IS_R200_CLASS(screen)) - screen->extensions[i++] = &r200AllocateExtension.base; + if (IS_R200_CLASS(screen)) + screen->extensions[i++] = &r200AllocateExtension.base; - screen->extensions[i++] = &r200texOffsetExtension.base; + screen->extensions[i++] = &r200texOffsetExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - //screen->extensions[i++] = &r300texOffsetExtension.base; + screen->extensions[i++] = &r300texOffsetExtension.base; #endif + } screen->extensions[i++] = NULL; sPriv->extensions = screen->extensions; @@ -1090,7 +1092,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - screen->extensions[i++] = &r300texOffsetExtension.base; + //screen->extensions[i++] = &r300texOffsetExtension.base; screen->extensions[i++] = &r300TexBufferExtension.base; #endif -- cgit v1.2.3 From 2ebf9b95213b3d1e67dad16442cdd0d8571ef0b3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Feb 2009 12:04:49 +1000 Subject: r300: fix bo ref/unref, plugs DRI handle leaks --- src/mesa/drivers/dri/r300/r300_tex.c | 5 +++++ src/mesa/drivers/dri/r300/r300_texstate.c | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 27b907019e3..0f5afbfa298 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -270,6 +270,11 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) rmesa->hw.textures[i] = 0; } + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + if (t->mt) { radeon_miptree_unreference(t->mt); t->mt = 0; diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 4f145bdbb4e..ef13fed6b22 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -433,9 +433,15 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) _mesa_lock_texture(radeon->glCtx, texObj); if (t->bo) { + radeon_bo_unref(t->bo); t->bo = NULL; } + if (rImage->bo) { + radeon_bo_unref(rImage->bo); + rImage->bo = NULL; + } if (t->mt) { + radeon_miptree_unreference(t->mt); t->mt = NULL; } if (rImage->mt) { @@ -447,7 +453,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) rb->width, rb->height, 1, 0, rb->cpp); texImage->TexFormat = &_mesa_texformat_rgba8888_rev; rImage->bo = rb->bo; - + radeon_bo_ref(rImage->bo); t->bo = rb->bo; radeon_bo_ref(t->bo); t->tile_bits = 0; -- cgit v1.2.3 From 199867bd4585036f19e219562c22a9b499a7b0d2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Feb 2009 18:06:44 +1000 Subject: r300: drop r300Flush for the generic one --- src/mesa/drivers/dri/r300/r300_ioctl.c | 18 +----------------- src/mesa/drivers/dri/r300/r300_ioctl.h | 7 ------- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- 3 files changed, 2 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 90b85f0df75..5e3e529bff6 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -612,25 +612,9 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) COMMIT_BATCH(); } -void r300Flush(GLcontext * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->radeon.dma.flush) { - rmesa->radeon.dma.flush(ctx); - } - - if (rmesa->radeon.cmdbuf.cs->cdw) { - rcommonFlushCmdBuf(&rmesa->radeon, __FUNCTION__); - } -} - void r300InitIoctlFuncs(struct dd_function_table *functions) { functions->Clear = r300Clear; functions->Finish = radeonFinish; - functions->Flush = r300Flush; + functions->Flush = radeonFlush; } diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.h b/src/mesa/drivers/dri/r300/r300_ioctl.h index 5f00264f112..3abfa71a6e8 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.h +++ b/src/mesa/drivers/dri/r300/r300_ioctl.h @@ -39,13 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "radeon_drm.h" -extern void r300Flush(GLcontext * ctx); - -extern void r300AllocDmaRegion(r300ContextPtr rmesa, - struct radeon_bo **pbo, int *poffset, - int bytes, int alignment); - extern void r300InitIoctlFuncs(struct dd_function_table *functions); -extern void r300RefillCurrentDmaRegion(r300ContextPtr rmesa, int size); #endif /* __R300_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index ef13fed6b22..f5b41180f79 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -330,7 +330,7 @@ again: if (ret == RADEON_CS_SPACE_OP_TO_BIG) return GL_FALSE; if (ret == RADEON_CS_SPACE_FLUSH) { - r300Flush(ctx); + radeonFlush(ctx); if (flushed) return GL_FALSE; flushed = 1; -- cgit v1.2.3 From bc5f94c1e1fddcf2b2a50972cb96e2593b288994 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Feb 2009 11:08:14 +1000 Subject: r300: don't flush VAP too often. Flush the VAP the first time for each state atom we upload new VAP data --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 22 ++++++++++++++-------- src/mesa/drivers/dri/r300/r300_context.c | 4 ++++ src/mesa/drivers/dri/r300/r300_context.h | 2 ++ src/mesa/drivers/dri/r300/r300_ioctl.c | 2 ++ 4 files changed, 22 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index c3a808ca79f..3b12d364193 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -97,14 +97,20 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; ndw = cmd.vpu.count * 4; if (ndw) { - BEGIN_BATCH_NO_AUTOSTATE(15 + ndw); - - /* flush processing vertices */ - OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0); - OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff); - OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 1); + + if (r300->vap_flush_needed) { + BEGIN_BATCH_NO_AUTOSTATE(15 + ndw); + + /* flush processing vertices */ + OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0); + OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff); + OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); + r300->vap_flush_needed = GL_FALSE; + } else { + BEGIN_BATCH_NO_AUTOSTATE(5 + ndw); + } OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr); OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); for (i = 0; i < ndw; i++) { diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index dd63add8340..5d497efc9c4 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -235,7 +235,11 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) { + r300ContextPtr r300 = (r300ContextPtr)radeon; BATCH_LOCALS(radeon); + + r300->vap_flush_needed = GL_TRUE; + cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); BEGIN_BATCH_NO_AUTOSTATE(2); OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 6d3472722da..37718f5415d 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -683,7 +683,9 @@ struct r300_context { GLboolean disable_lowimpact_fallback; DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ + struct r300_swtcl_info swtcl; + GLboolean vap_flush_needed; }; struct r300_buffer_object { diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 5e3e529bff6..619d268f387 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -528,6 +528,8 @@ static void r300EmitClearState(GLcontext * ctx) PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); vpu.cmd[8] = 0x0; + + r300->vap_flush_needed = GL_TRUE; emit_vpu(ctx, &vpu); } } -- cgit v1.2.3 From 2c033f3893e808f109807f5e4744b61e79e78055 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Feb 2009 11:09:16 +1000 Subject: r300: don't call page flip on DRI2 --- src/mesa/drivers/dri/r300/r300_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 93ef06fb268..ba1deee23ec 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2742,7 +2742,8 @@ static void r300DrawBuffer( GLcontext *ctx, GLenum mode ) radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ radeonSetCliprects( &rmesa->radeon ); - radeonUpdatePageFlipping(&rmesa->radeon); + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) + radeonUpdatePageFlipping(&rmesa->radeon); } static void r300ReadBuffer( GLcontext *ctx, GLenum mode ) -- cgit v1.2.3 From 158ede35d50faae7cbc8aa2bb9288f93c9e60962 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Feb 2009 11:09:32 +1000 Subject: r300: fixup texture state emission for kms path --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 3b12d364193..068a9f978ba 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -168,10 +168,21 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(&r300->radeon); int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); + int notexture = 0; if (numtmus) { int i; + for(i = 0; i < numtmus; ++i) { + radeonTexObj *t = r300->hw.textures[i]; + + if (!t) + notexture = 1; + } + + if (r300->radeon.radeonScreen->kernel_mm && notexture) { + return; + } BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus); for(i = 0; i < numtmus; ++i) { radeonTexObj *t = r300->hw.textures[i]; @@ -188,6 +199,8 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) } else if (!r300->radeon.radeonScreen->kernel_mm) { OUT_BATCH(t->override_offset); } + else + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); } } END_BATCH(); -- cgit v1.2.3 From 925ea2d9a5096dbad1d82dc1afffb13a650de799 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Feb 2009 19:21:22 +1000 Subject: radeon: move CB/ZB state init into emit code This removes the use of the sarea for this stuff so makes DRI2 easier and emits the CB/ZB info in the correct place --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 133 +++++++++--------------- 1 file changed, 51 insertions(+), 82 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 617e731a411..60dc6bf4111 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -312,37 +312,49 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; - uint32_t zbpitch; + uint32_t zbpitch, depth_fmt; uint32_t dwords = atom->cmd_size; - GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate; /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords + 4); OUT_BATCH_TABLE(atom->cmd, 5); - rrb = r100->radeon.state.depth.rrb; + rrb = radeon_get_depthbuffer(&r100->radeon); if (!rrb) { OUT_BATCH(0); OUT_BATCH(0); } else { zbpitch = (rrb->pitch / rrb->cpp); + if (r100->using_hyperz) + zbpitch |= RADEON_DEPTH_HYPERZ; + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(zbpitch); + if (rrb->cpp == 4) + depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; + else + depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); OUT_BATCH(atom->cmd[CTX_CMD_1]); OUT_BATCH(atom->cmd[CTX_PP_CNTL]); - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - rrb = r100->radeon.state.color.rrb; - if (r100->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } + rrb = radeon_get_colorbuffer(&r100->radeon); if (!rrb || !rrb->bo) { - OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); } else { - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); + if (rrb->cpp == 4) + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; + else + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); } OUT_BATCH(atom->cmd[CTX_CMD_2]); @@ -351,12 +363,8 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); } else { cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->cpp == 4) - ; - else - ; - if (r100->radeon.sarea->tiling_enabled) - cbpitch |= R200_COLOR_TILE_ENABLE; + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) + cbpitch |= RADEON_COLOR_TILE_ENABLE; OUT_BATCH(cbpitch); } @@ -371,23 +379,35 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) uint32_t cbpitch = 0; uint32_t zbpitch = 0; uint32_t dwords = atom->cmd_size; - GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate; + uint32_t depth_fmt; - rrb = r100->radeon.state.color.rrb; - if (r100->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = radeon_get_colorbuffer(&r100->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; } - if (rrb) { - assert(rrb->bo != NULL); - cbpitch = (rrb->pitch / rrb->cpp); - if (r100->radeon.sarea->tiling_enabled) + + atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); + if (rrb->cpp == 4) + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; + else + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; - } - drb = r100->radeon.state.depth.rrb; - if (drb) + drb = radeon_get_depthbuffer(&r100->radeon); + if (drb) { zbpitch = (drb->pitch / drb->cpp); - + if (drb->cpp == 4) + depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; + else + depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; + + } /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -416,10 +436,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) } if (rrb) { - if (rrb->cpp == 4) - ; - else - ; + cbpitch = (rrb->pitch / rrb->cpp); OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH(cbpitch); } @@ -497,20 +514,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) void radeonInitState( r100ContextPtr rmesa ) { GLcontext *ctx = rmesa->radeon.glCtx; - GLuint color_fmt, depth_fmt, i; - GLint drawPitch, drawOffset; - - switch ( rmesa->radeon.radeonScreen->cpp ) { - case 2: - color_fmt = RADEON_COLOR_FORMAT_RGB565; - break; - case 4: - color_fmt = RADEON_COLOR_FORMAT_ARGB8888; - break; - default: - fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); - exit( -1 ); - } + GLuint i; rmesa->radeon.state.color.clear = 0x00000000; @@ -518,13 +522,11 @@ void radeonInitState( r100ContextPtr rmesa ) case 16: rmesa->radeon.state.depth.clear = 0x0000ffff; rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; - depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: rmesa->radeon.state.depth.clear = 0x00ffffff; rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; - depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: @@ -539,13 +541,6 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->radeon.Fallback = 0; - if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) { - drawOffset = rmesa->radeon.radeonScreen->backOffset; - drawPitch = rmesa->radeon.radeonScreen->backPitch; - } else { - drawOffset = rmesa->radeon.radeonScreen->frontOffset; - drawPitch = rmesa->radeon.radeonScreen->frontPitch; - } rmesa->radeon.hw.max_state_size = 0; @@ -708,19 +703,7 @@ void radeonInitState( r100ContextPtr rmesa ) RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO ); - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; - - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = - ((rmesa->radeon.radeonScreen->depthPitch & - RADEON_DEPTHPITCH_MASK) | - RADEON_DEPTH_ENDIAN_NO_SWAP); - - if (rmesa->using_hyperz) - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ; - - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | - RADEON_Z_TEST_LESS | + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS | RADEON_STENCIL_TEST_ALWAYS | RADEON_STENCIL_FAIL_KEEP | RADEON_STENCIL_ZPASS_KEEP | @@ -742,7 +725,6 @@ void radeonInitState( r100ContextPtr rmesa ) RADEON_ANTI_ALIAS_NONE); rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | - color_fmt | RADEON_ZBLOCK16); switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { @@ -764,19 +746,6 @@ void radeonInitState( r100ContextPtr rmesa ) else rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + - rmesa->radeon.radeonScreen->fbLocation) - & RADEON_COLOROFFSET_MASK); - - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & - RADEON_COLORPITCH_MASK) | - RADEON_COLOR_ENDIAN_NO_SWAP); - - - /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; - } rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | RADEON_BFACE_SOLID | -- cgit v1.2.3 From 3ec7137a75f8832bba52f98669b93d4135ae1a3f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Feb 2009 19:22:25 +1000 Subject: radeon: enable DRI2 for r100 --- src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index f8de799a6da..46a946b1c94 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1538,6 +1538,7 @@ const struct __DriverAPIRec driDriverAPI = { .WaitForSBC = NULL, .SwapBuffersMSC = NULL, .CopySubBuffer = radeonCopySubBuffer, + .InitScreen2 = radeonInitScreen2, }; #endif -- cgit v1.2.3 From 6415e64cbc55b2e11b9ed3f3a861e28479f85d68 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Feb 2009 19:22:42 +1000 Subject: radeon: avoid page flip code in DRI2 --- src/mesa/drivers/dri/radeon/radeon_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 86d872030bc..5fffa286fe2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1563,7 +1563,8 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) } radeonSetCliprects( &rmesa->radeon ); - radeonUpdatePageFlipping(&rmesa->radeon); + if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) + radeonUpdatePageFlipping(&rmesa->radeon); /* We'll set the drawing engine's offset/pitch parameters later * when we update other state. */ -- cgit v1.2.3 From 6d7164705b933c754dddea6015b653a3bacc75bf Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Feb 2009 11:45:24 +1000 Subject: r100: fixup kms state emissions --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 40 +++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 60dc6bf4111..d41105e6dd3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -288,7 +288,8 @@ static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->cmd_size; - + + dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); @@ -301,11 +302,26 @@ static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->cmd_size; + dwords += 4; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VEC(atom->cmd[0], atom->cmd+1); END_BATCH(); } + +static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = atom->cmd_size; + + dwords += 6; + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); + OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); + END_BATCH(); +} + static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); @@ -408,7 +424,12 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } + /* output the first 7 bytes of context */ + if (drb) + dwords += 4; + if (rrb) + dwords += 4; BEGIN_BATCH_NO_AUTOSTATE(dwords); /* In the CS case we need to split this up */ @@ -429,7 +450,6 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH(atom->cmd[CTX_PP_CNTL]); OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); @@ -682,6 +702,22 @@ void radeonInitState( r100ContextPtr rmesa ) cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); } + if (rmesa->radeon.radeonScreen->kernel_mm) { + rmesa->hw.grd.emit = scl_emit; + rmesa->hw.fog.emit = vec_emit; + rmesa->hw.glt.emit = vec_emit; + rmesa->hw.eye.emit = vec_emit; + + for (i = 0; i <= 6; i++) + rmesa->hw.mat[i].emit = vec_emit; + + for (i = 0; i < 8; i++) + rmesa->hw.lit[i].emit = lit_emit; + + for (i = 0; i < 6; i++) + rmesa->hw.ucp[i].emit = vec_emit; + } + rmesa->last_ReallyEnabled = -1; /* Initial Harware state: -- cgit v1.2.3 From 2972d065265d38c7902ffeaa1e71706895649bec Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Feb 2009 18:26:22 +1000 Subject: radeon: fixup old packets emission for CS case --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 38 +++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index fb3a236d7c8..b5ab9234df6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -116,13 +116,26 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, #if RADEON_OLD_PACKETS BEGIN_BATCH(8); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); - OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + } else { + OUT_BATCH(rmesa->ioctl.vertex_offset); + } + OUT_BATCH(vertex_nr); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); + + if (rmesa->radeon.radeonScreen->kernel_mm) { + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->ioctl.bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + END_BATCH(); #else @@ -155,7 +168,11 @@ void radeonFlushElts( GLcontext *ctx ) nr = rmesa->tcl.elt_used; - rmesa->radeon.cmdbuf.cs->cdw += dwords; +#if RADEON_OLD_PACKETS + if (rmesa->radeon.radeonScreen->kernel_mm) { + dwords -= 2; + } +#endif #if RADEON_OLD_PACKETS cmd[1] |= (dwords + 3) << 16; @@ -165,7 +182,18 @@ void radeonFlushElts( GLcontext *ctx ) cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #endif + rmesa->radeon.cmdbuf.cs->cdw += dwords; rmesa->radeon.cmdbuf.cs->section_cdw += dwords; + +#if RADEON_OLD_PACKETS + if (rmesa->radeon.radeonScreen->kernel_mm) { + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->ioctl.bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } +#endif + END_BATCH(); if (RADEON_DEBUG & DEBUG_SYNC) { @@ -199,7 +227,11 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, #if RADEON_OLD_PACKETS BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0); - OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + } else { + OUT_BATCH(rmesa->ioctl.vertex_offset); + } OUT_BATCH(0xffff); OUT_BATCH(vertex_format); OUT_BATCH(primitive | -- cgit v1.2.3 From e267a090ab7be5dbd9a40887726e6ae696bc7be3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 27 Feb 2009 03:05:42 +1000 Subject: r200: port over cs emit changes from radeon --- src/mesa/drivers/dri/r200/r200_state_init.c | 136 +++++++++--------------- src/mesa/drivers/dri/radeon/radeon_state_init.c | 1 - 2 files changed, 48 insertions(+), 89 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 013064d2b3f..f73399f6970 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -412,36 +412,47 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; - uint32_t zbpitch; + uint32_t zbpitch, depth_fmt; uint32_t dwords = atom->cmd_size; - GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2); OUT_BATCH_TABLE(atom->cmd, 5); - rrb = r200->radeon.state.depth.rrb; + rrb = radeon_get_depthbuffer(&r200->radeon); if (!rrb) { OUT_BATCH(0); OUT_BATCH(0); } else { zbpitch = (rrb->pitch / rrb->cpp); + if (r200->using_hyperz) + zbpitch |= RADEON_DEPTH_HYPERZ; OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(zbpitch); + if (rrb->cpp == 4) + depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; + else + depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); OUT_BATCH(atom->cmd[CTX_CMD_1]); OUT_BATCH(atom->cmd[CTX_PP_CNTL]); - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - rrb = r200->radeon.state.color.rrb; - if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } + rrb = radeon_get_colorbuffer(&r200->radeon); if (!rrb || !rrb->bo) { + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); } else { + atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); + if (rrb->cpp == 4) + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; + else + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); } @@ -451,11 +462,7 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); } else { cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->cpp == 4) - ; - else - ; - if (r200->radeon.sarea->tiling_enabled) + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; OUT_BATCH(cbpitch); } @@ -474,22 +481,38 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) uint32_t cbpitch = 0; uint32_t zbpitch = 0; uint32_t dwords = atom->cmd_size; - GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; + uint32_t depth_fmt; - rrb = r200->radeon.state.color.rrb; - if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = radeon_get_colorbuffer(&r200->radeon); + if (!rrb || !rrb->bo) { + return; } - if (rrb) { - assert(rrb->bo != NULL); - cbpitch = (rrb->pitch / rrb->cpp); - if (r200->radeon.sarea->tiling_enabled) + + atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); + if (rrb->cpp == 4) + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; + else + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; + + drb = radeon_get_depthbuffer(&r200->radeon); + if (drb) { + zbpitch = (drb->pitch / drb->cpp); + if (drb->cpp == 4) + depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; + else + depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; + atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } - drb = r200->radeon.state.depth.rrb; if (drb) - zbpitch = (drb->pitch / drb->cpp); + dwords += 4; + if (rrb) + dwords += 4; /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -519,10 +542,6 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) } if (rrb) { - if (rrb->cpp == 4) - ; - else - ; OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH(cbpitch); } @@ -586,20 +605,7 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) void r200InitState( r200ContextPtr rmesa ) { GLcontext *ctx = rmesa->radeon.glCtx; - GLuint color_fmt, depth_fmt, i; - GLint drawPitch, drawOffset; - - switch ( rmesa->radeon.radeonScreen->cpp ) { - case 2: - color_fmt = R200_COLOR_FORMAT_RGB565; - break; - case 4: - color_fmt = R200_COLOR_FORMAT_ARGB8888; - break; - default: - fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); - exit( -1 ); - } + GLuint i; rmesa->radeon.state.color.clear = 0x00000000; @@ -607,13 +613,11 @@ void r200InitState( r200ContextPtr rmesa ) case 16: rmesa->radeon.state.depth.clear = 0x0000ffff; rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; - depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z; rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: rmesa->radeon.state.depth.clear = 0x00ffffff; rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; - depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: @@ -628,26 +632,6 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->radeon.Fallback = 0; - if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) { - drawOffset = rmesa->radeon.radeonScreen->backOffset; - drawPitch = rmesa->radeon.radeonScreen->backPitch; - } else { - drawOffset = rmesa->radeon.radeonScreen->frontOffset; - drawPitch = rmesa->radeon.radeonScreen->frontPitch; - } -#if 000 - if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset; - rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch; - } else { - rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset; - rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch; - } - - rmesa->state.pixel.readOffset = rmesa->radeon.state.color.drawOffset; - rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch; -#endif - rmesa->radeon.hw.max_state_size = 0; #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ @@ -1025,8 +1009,7 @@ void r200InitState( r200ContextPtr rmesa ) if (rmesa->using_hyperz) rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | - R200_Z_TEST_LESS | + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS | R200_STENCIL_TEST_ALWAYS | R200_STENCIL_FAIL_KEEP | R200_STENCIL_ZPASS_KEEP | @@ -1043,7 +1026,6 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE | R200_TEX_BLEND_0_ENABLE); - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt; switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; @@ -1063,28 +1045,6 @@ void r200InitState( r200ContextPtr rmesa ) else rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; -#if 000 - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->radeon.state.color.drawOffset + - rmesa->radeon.radeonScreen->fbLocation) - & R200_COLOROFFSET_MASK); - - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->radeon.state.color.drawPitch & - R200_COLORPITCH_MASK) | - R200_COLOR_ENDIAN_NO_SWAP); -#else - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + - rmesa->radeon.radeonScreen->fbLocation) - & R200_COLOROFFSET_MASK); - - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & - R200_COLORPITCH_MASK) | - R200_COLOR_ENDIAN_NO_SWAP); -#endif - /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; - } - rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality"); rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index d41105e6dd3..7ff0eb450ce 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -456,7 +456,6 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) } if (rrb) { - cbpitch = (rrb->pitch / rrb->cpp); OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH(cbpitch); } -- cgit v1.2.3 From 294aab9b713f4646992cf72b19a492285a4bbcdb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 27 Feb 2009 03:37:30 +1000 Subject: r200: fixup emit sizes for kms --- src/mesa/drivers/dri/r200/r200_state_init.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f73399f6970..b40690edb9e 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -342,6 +342,7 @@ static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; + dwords += 6; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); @@ -354,6 +355,7 @@ static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; + dwords += 8; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); @@ -366,6 +368,7 @@ static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; + dwords += 8; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); @@ -378,6 +381,7 @@ static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; + dwords += 4; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); END_BATCH(); @@ -389,6 +393,7 @@ static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; + dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); @@ -401,6 +406,7 @@ static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; + dwords += 4; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VEC(atom->cmd[0], atom->cmd+1); END_BATCH(); -- cgit v1.2.3 From 7f44b62a4a90242ef824f9751affe5c46e401691 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Feb 2009 14:04:38 +1000 Subject: r300: remove depth offset exits in favour of rrb depth changes --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 30 ++++++++++++++++++++++++++++++ src/mesa/drivers/dri/r300/r300_state.c | 27 --------------------------- 2 files changed, 30 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 068a9f978ba..231576fed89 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -263,6 +263,33 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) END_BATCH(); } +static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + struct radeon_renderbuffer *rrb; + uint32_t zbpitch; + uint32_t format; + + rrb = radeon_get_depthbuffer(&r300->radeon); + if (!rrb) + format = 0; + else { + if (rrb->cpp == 2) + format = R300_DEPTHFORMAT_16BIT_INT_Z; + else if (rrb->cpp == 4) + format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; + } + + OUT_BATCH(atom->cmd[0]); + atom->cmd[1] &= ~(3 << 0); + atom->cmd[1] |= format; + OUT_BATCH(atom->cmd[1]); + OUT_BATCH(atom->cmd[2]); + OUT_BATCH(atom->cmd[3]); + OUT_BATCH(atom->cmd[4]); +} + static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; @@ -521,9 +548,12 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); r300->hw.zs.cmd[R300_ZS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); + ALLOC_STATE(zstencil_format, always, 5, 0); r300->hw.zstencil_format.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4); + r300->hw.zstencil_format.emit = emit_zstencil_format; + ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0); r300->hw.zb.emit = emit_zb_offset; ALLOC_STATE(zb_depthclearvalue, always, 2, 0); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index ba1deee23ec..59728a07e5c 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2367,18 +2367,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.zb_depthclearvalue.cmd[1] = 0; - switch (ctx->Visual.depthBits) { - case 16: - r300->hw.zstencil_format.cmd[1] = R300_DEPTHFORMAT_16BIT_INT_Z; - break; - case 24: - r300->hw.zstencil_format.cmd[1] = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; - break; - default: - fprintf(stderr, "Error: Unsupported depth %d... exiting\n", ctx->Visual.depthBits); - _mesa_exit(-1); - } - r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE; r300->hw.zstencil_format.cmd[3] = 0x00000003; r300->hw.zstencil_format.cmd[4] = 0x00000000; @@ -2683,21 +2671,6 @@ void r300InitState(r300ContextPtr r300) GLcontext *ctx = r300->radeon.glCtx; GLuint depth_fmt; - switch (ctx->Visual.depthBits) { - case 16: - r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffff; - depth_fmt = R300_DEPTHFORMAT_16BIT_INT_Z; - break; - case 24: - r300->radeon.state.depth.scale = 1.0 / (GLfloat) 0xffffff; - depth_fmt = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; - break; - default: - fprintf(stderr, "Error: Unsupported depth %d... exiting\n", - ctx->Visual.depthBits); - _mesa_exit(-1); - } - /* Only have hw stencil when depth buffer is 24 bits deep */ r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 && ctx->Visual.depthBits == 24); -- cgit v1.2.3 From 26c1b0af024e4847ce1000ee471ab5b5bdb18a1b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 27 Feb 2009 14:02:23 +1000 Subject: radeon: add more fbconfigs this makes glxgears get its background back when running under DRI2 --- src/mesa/drivers/dri/radeon/radeon_screen.c | 58 ++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 46a946b1c94..c591e9f8820 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1438,6 +1438,7 @@ radeonInitScreen(__DRIscreenPrivate *psp) (dri_priv->bpp == 16) ? 16 : 24, (dri_priv->bpp == 16) ? 0 : 8, 1); } +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) /** * This is the driver specific part of the createNewScreen entry point. @@ -1448,6 +1449,18 @@ radeonInitScreen(__DRIscreenPrivate *psp) static const __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) { + GLenum fb_format[3]; + GLenum fb_type[3]; + /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't + * support pageflipping at all. + */ + static const GLenum back_buffer_modes[] = { + GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ + }; + uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; + int color; + __DRIconfig **configs = NULL; + /* Calling driInitExtensions here, with a NULL context pointer, * does not actually enable the extensions. It just makes sure * that all the dispatch offsets for all the extensions that @@ -1470,9 +1483,50 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) if (!radeonInitDriver(psp)) { return NULL; } + depth_bits[0] = 0; + stencil_bits[0] = 0; + depth_bits[1] = 16; + stencil_bits[1] = 0; + depth_bits[2] = 24; + stencil_bits[2] = 0; + depth_bits[3] = 24; + stencil_bits[3] = 8; + + msaa_samples_array[0] = 0; + + fb_format[0] = GL_RGB; + fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; + + fb_format[1] = GL_BGR; + fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; + + fb_format[2] = GL_BGRA; + fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; + + for (color = 0; color < ARRAY_SIZE(fb_format); color++) { + __DRIconfig **new_configs; + + new_configs = driCreateConfigs(fb_format[color], fb_type[color], + depth_bits, + stencil_bits, + ARRAY_SIZE(depth_bits), + back_buffer_modes, + ARRAY_SIZE(back_buffer_modes), + msaa_samples_array, + ARRAY_SIZE(msaa_samples_array)); + if (configs == NULL) + configs = new_configs; + else + configs = driConcatConfigs(configs, new_configs); + } - /* for now fill in all modes */ - return radeonFillInModes( psp, 24, 24, 8, 1); + if (configs == NULL) { + fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, + __LINE__); + return NULL; + } + + return (const __DRIconfig **)configs; } /** -- cgit v1.2.3 From 0dba8883e3f6d51bf3a2918ac21770326da2664a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 27 Feb 2009 14:03:30 +1000 Subject: r300: make ste text buffer work with > 2048 on r500 --- src/mesa/drivers/dri/r300/r300_texstate.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index f5b41180f79..8a90069a6d0 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -484,6 +484,13 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT); t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; t->pp_txpitch |= pitch_val; + + if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + if (rb->width > 2048) + t->pp_txpitch |= R500_TXWIDTH_BIT11; + if (rb->height > 2048) + t->pp_txpitch |= R500_TXHEIGHT_BIT11; + } t->validated = GL_TRUE; _mesa_unlock_texture(radeon->glCtx, texObj); return; -- cgit v1.2.3 From 5a34ace3e6f507b4a7bd0f99051b64167549672c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Feb 2009 14:31:14 -0500 Subject: R300: set the number of GB pipes on all r3xx-r5xx chips --- src/mesa/drivers/dri/radeon/radeon_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index c591e9f8820..79ab3e2fd85 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -892,7 +892,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->fbLocation = (temp & 0xffff) << 16; } - if (screen->chip_family >= CHIP_FAMILY_RV515) { + if (screen->chip_family >= CHIP_FAMILY_R300) { ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, &temp); if (ret) { -- cgit v1.2.3 From 863c76a7bb0ecf0cd492d9ddb0dcac8e12da75e0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Feb 2009 14:48:24 -0500 Subject: R300: add support for RS600 chips --- src/mesa/drivers/dri/radeon/radeon_chipset.h | 4 ++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h index 55a73eab209..f6bd1eb83fb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_chipset.h +++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h @@ -247,6 +247,9 @@ #define PCI_CHIP_RS350_7835 0x7835 #define PCI_CHIP_RS690_791E 0x791E #define PCI_CHIP_RS690_791F 0x791F +#define PCI_CHIP_RS600_793F 0x793F +#define PCI_CHIP_RS600_7941 0x7941 +#define PCI_CHIP_RS600_7942 0x7942 #define PCI_CHIP_RS740_796C 0x796C #define PCI_CHIP_RS740_796D 0x796D #define PCI_CHIP_RS740_796E 0x796E @@ -270,6 +273,7 @@ enum { CHIP_FAMILY_R420, CHIP_FAMILY_RV410, CHIP_FAMILY_RS400, + CHIP_FAMILY_RS600, CHIP_FAMILY_RS690, CHIP_FAMILY_RS740, CHIP_FAMILY_RV515, diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 79ab3e2fd85..78f0bc25147 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -570,6 +570,12 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) screen->chip_family = CHIP_FAMILY_RS400; break; + case PCI_CHIP_RS600_793F: + case PCI_CHIP_RS600_7941: + case PCI_CHIP_RS600_7942: + screen->chip_family = CHIP_FAMILY_RS600; + break; + case PCI_CHIP_RS690_791E: case PCI_CHIP_RS690_791F: screen->chip_family = CHIP_FAMILY_RS690; @@ -881,7 +887,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { - if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) + if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; else { FREE( screen ); -- cgit v1.2.3 From 2b85fccae5ba33748846f74f90fe0f72c673a4b1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Mar 2009 03:27:59 +1000 Subject: radeon: refactor framebuffer code like intel this is a step towards fbos and should fix pageflipping, but I think the first flip seems broken. --- src/mesa/drivers/dri/r200/r200_context.c | 2 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 2 +- src/mesa/drivers/dri/r200/r200_state.c | 94 +---- src/mesa/drivers/dri/r300/r300_context.c | 39 +- src/mesa/drivers/dri/r300/r300_ioctl.c | 8 +- src/mesa/drivers/dri/r300/r300_render.c | 3 +- src/mesa/drivers/dri/r300/r300_state.c | 71 +--- src/mesa/drivers/dri/r300/r300_texstate.c | 10 +- src/mesa/drivers/dri/radeon/radeon_common.c | 470 ++++++++++++++++----- src/mesa/drivers/dri/radeon/radeon_common.h | 11 +- .../drivers/dri/radeon/radeon_common_context.c | 124 +++--- .../drivers/dri/radeon/radeon_common_context.h | 43 +- src/mesa/drivers/dri/radeon/radeon_context.c | 4 +- src/mesa/drivers/dri/radeon/radeon_lock.c | 78 ++-- src/mesa/drivers/dri/radeon/radeon_lock.h | 69 +-- src/mesa/drivers/dri/radeon/radeon_screen.c | 69 +-- src/mesa/drivers/dri/radeon/radeon_state.c | 80 +--- 17 files changed, 612 insertions(+), 565 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index a744469b31c..10a6362afd2 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -261,9 +261,9 @@ static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; - radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; radeon->vtbl.swtcl_flush = r200_swtcl_flush; + radeon->vtbl.fallback = r200Fallback; } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index c08968f7f86..6076b6d7ea4 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -203,7 +203,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) GLint ret; if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "r200Clear\n"); + fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage); } { diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 126f78b39ca..46baad33f5c 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1639,6 +1639,8 @@ static void r200Viewport( GLcontext *ctx, GLint x, GLint y, * values, or keep the originals hanging around. */ r200UpdateWindow( ctx ); + + radeon_viewport(ctx, x, y, width, height); } static void r200DepthRange( GLcontext *ctx, GLclampd nearval, @@ -1754,47 +1756,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = r200_rop_tab[rop]; } - -static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s %s\n", __FUNCTION__, - _mesa_lookup_enum_by_nr( mode )); - - radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ - - if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { - /* 0 (GL_NONE) buffers or multiple color drawing buffers */ - FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_TRUE ); - return; - } - - switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) { - case BUFFER_FRONT_LEFT: - case BUFFER_BACK_LEFT: - FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_FALSE ); - break; - default: - FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_TRUE ); - return; - } - - radeonSetCliprects( &rmesa->radeon ); - radeonUpdatePageFlipping(&rmesa->radeon); - - /* We'll set the drawing engine's offset/pitch parameters later - * when we update other state. - */ -} - - -static void r200ReadBuffer( GLcontext *ctx, GLenum mode ) -{ - /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */ -} - /* ============================================================= * State enable/disable */ @@ -2289,47 +2250,6 @@ static void update_texturematrix( GLcontext *ctx ) } } - - -/** - * Tell the card where to render (offset, pitch). - * Effected by glDrawBuffer, etc - */ -void -r200UpdateDrawBuffer(GLcontext *ctx) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; - struct radeon_renderbuffer *rrb; - - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } else { - /* drawing to multiple buffers, or none */ - return; - } - - assert(rrb); - assert(rrb->pitch); - - R200_STATECHANGE( rmesa, ctx ); - -#if 0 - /* Note: we used the (possibly) page-flipped values */ - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) - & R200_COLOROFFSET_MASK); - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; - if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; - } -#endif -} - static GLboolean r200ValidateBuffers(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -2395,7 +2315,11 @@ GLboolean r200ValidateState( GLcontext *ctx ) GLuint new_state = rmesa->radeon.NewGLState; if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { - r200UpdateDrawBuffer(ctx); + _mesa_update_framebuffer(ctx); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx); + + R200_STATECHANGE(rmesa, ctx); } if (new_state & (_NEW_TEXTURE | _NEW_PROGRAM)) { @@ -2523,8 +2447,8 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->UpdateState = r200InvalidateState; functions->LightingSpaceChange = r200LightingSpaceChange; - functions->DrawBuffer = r200DrawBuffer; - functions->ReadBuffer = r200ReadBuffer; + functions->DrawBuffer = radeonDrawBuffer; + functions->ReadBuffer = radeonReadBuffer; functions->AlphaFunc = r200AlphaFunc; functions->BlendColor = r200BlendColor; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5d497efc9c4..488fd44740c 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -235,26 +235,35 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - r300ContextPtr r300 = (r300ContextPtr)radeon; - BATCH_LOCALS(radeon); - - r300->vap_flush_needed = GL_TRUE; + r300ContextPtr r300 = (r300ContextPtr)radeon; + BATCH_LOCALS(radeon); + + r300->vap_flush_needed = GL_TRUE; + + cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); + END_BATCH(); + end_3d(radeon); +} - cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); - END_BATCH(); - end_3d(radeon); +static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + if (mode) + r300->radeon.Fallback |= bit; + else + r300->radeon.Fallback &= ~bit; } static void r300_init_vtbl(radeonContextPtr radeon) { - radeon->vtbl.get_lock = r300_get_lock; - radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; - radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; - radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; - radeon->vtbl.swtcl_flush = r300_swtcl_flush; - radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; + radeon->vtbl.get_lock = r300_get_lock; + radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; + radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; + radeon->vtbl.swtcl_flush = r300_swtcl_flush; + radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; + radeon->vtbl.fallback = r300_fallback; } diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 619d268f387..d1cf57959fa 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -541,7 +541,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) { r300ContextPtr r300 = R300_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; - GLframebuffer *fb = dPriv->driverPrivate; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; struct radeon_renderbuffer *rrb; struct radeon_renderbuffer *rrbd; int flags = 0; @@ -594,16 +594,16 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); - rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (flags & BUFFER_BIT_FRONT_LEFT) { - rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (flags & BUFFER_BIT_BACK_LEFT) { - rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index f46477f0f67..402d2d76388 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -427,7 +427,8 @@ static int r300Fallback(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); const unsigned back = ctx->Stencil._BackFace; - + + FALLBACK_IF(r300->radeon.Fallback); /* Do we need to use new-style shaders? * Also is there a better way to do this? */ if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 59728a07e5c..6bb0063bc19 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1083,20 +1083,13 @@ static void r300UpdateWindow(GLcontext * ctx) static void r300Viewport(GLcontext * ctx, GLint x, GLint y, GLsizei width, GLsizei height) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIcontext *driContext = rmesa->radeon.dri.context; /* Don't pipeline viewport changes, conflict with window offset * setting below. Could apply deltas to rescue pipelined viewport * values, or keep the originals hanging around. */ - if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { - radeon_update_renderbuffers(driContext, driContext->driDrawablePriv); - if (driContext->driDrawablePriv != driContext->driReadablePriv) { - radeon_update_renderbuffers(driContext, - driContext->driReadablePriv); - } - } r300UpdateWindow(ctx); + + radeon_viewport(ctx, x, y, width, height); } static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) @@ -1129,34 +1122,6 @@ void r300UpdateViewportOffset(GLcontext * ctx) radeonUpdateScissor(ctx); } -/** - * Tell the card where to render (offset, pitch). - * Effected by glDrawBuffer, etc - */ -void r300UpdateDrawBuffer(GLcontext * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; - struct radeon_renderbuffer *rrb; - - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - rrb = - (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } else { - /* drawing to multiple buffers, or none */ - return; - } - - assert(rrb); - assert(rrb->pitch); - - R300_STATECHANGE(rmesa, cb); -} - static void r300FetchStateParameter(GLcontext * ctx, const gl_state_index state[STATE_LENGTH], @@ -2653,7 +2618,11 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) _ae_invalidate_state(ctx, new_state); if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { - r300UpdateDrawBuffer(ctx); + _mesa_update_framebuffer(ctx); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx); + + R300_STATECHANGE(r300, cb); } r300UpdateStateParameters(ctx, new_state); @@ -2705,28 +2674,6 @@ void r300UpdateClipPlanes( GLcontext *ctx ) } } -static void r300DrawBuffer( GLcontext *ctx, GLenum mode ) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s %s\n", __FUNCTION__, - _mesa_lookup_enum_by_nr( mode )); - - radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ - - radeonSetCliprects( &rmesa->radeon ); - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) - radeonUpdatePageFlipping(&rmesa->radeon); -} - -static void r300ReadBuffer( GLcontext *ctx, GLenum mode ) -{ - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s %s\n", __FUNCTION__, - _mesa_lookup_enum_by_nr( mode )); - -}; - /** * Initialize driver's state callback functions */ @@ -2770,6 +2717,6 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->ClipPlane = r300ClipPlane; functions->Scissor = radeonScissor; - functions->DrawBuffer = r300DrawBuffer; - functions->ReadBuffer = r300ReadBuffer; + functions->DrawBuffer = radeonDrawBuffer; + functions->ReadBuffer = radeonReadBuffer; } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 8a90069a6d0..2d7f392e7c8 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -393,7 +393,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeon_texture_image *rImage; radeonContextPtr radeon; r300ContextPtr rmesa; - GLframebuffer *fb; + struct radeon_framebuffer *rfb; radeonTexObjPtr t; uint32_t pitch_val; @@ -402,7 +402,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeon = pDRICtx->driverPrivate; rmesa = pDRICtx->driverPrivate; - fb = dPriv->driverPrivate; + rfb = dPriv->driverPrivate; texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); @@ -415,17 +415,17 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeon_update_renderbuffers(pDRICtx, dPriv); /* back & depth buffer are useless free them right away */ - rb = (void*)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void*)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb->bo == NULL) { /* Failed to BO for the buffer */ return; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index f7c0d7d64f5..1021f9beec6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -51,7 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/light.h" #include "main/framebuffer.h" #include "main/simple_list.h" - +#include "main/renderbuffer.h" #include "swrast/swrast.h" #include "vbo/vbo.h" #include "tnl/tnl.h" @@ -132,6 +132,38 @@ void radeonRecalcScissorRects(radeonContextPtr radeon) } } +static void radeon_get_cliprects(radeonContextPtr radeon, + struct drm_clip_rect **cliprects, + unsigned int *num_cliprects, + int *x_off, int *y_off) +{ + __DRIdrawablePrivate *dPriv = radeon->dri.drawable; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; + + if (radeon->constant_cliprect) { + radeon->fboRect.x1 = 0; + radeon->fboRect.y1 = 0; + radeon->fboRect.x2 = radeon->glCtx->DrawBuffer->Width; + radeon->fboRect.y2 = radeon->glCtx->DrawBuffer->Height; + + *cliprects = &radeon->fboRect; + *num_cliprects = 1; + *x_off = 0; + *y_off = 0; + } else if (radeon->front_cliprects || + rfb->pf_active || dPriv->numBackClipRects == 0) { + *cliprects = dPriv->pClipRects; + *num_cliprects = dPriv->numClipRects; + *x_off = dPriv->x; + *y_off = dPriv->y; + } else { + *num_cliprects = dPriv->numBackClipRects; + *cliprects = dPriv->pBackClipRects; + *x_off = dPriv->backX; + *y_off = dPriv->backY; + } +} + /** * Update cliprects and scissors. */ @@ -139,49 +171,37 @@ void radeonSetCliprects(radeonContextPtr radeon) { __DRIdrawablePrivate *const drawable = radeon->dri.drawable; __DRIdrawablePrivate *const readable = radeon->dri.readable; - GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; - GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; + struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate; + struct radeon_framebuffer *const read_rfb = readable->driverPrivate; + int x_off, y_off; - if (!radeon->radeonScreen->driScreen->dri2.enabled) { - if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* Can't ignore 2d windows if we are page flipping. */ - if (drawable->numBackClipRects == 0 || radeon->doPageFlip || - radeon->sarea->pfCurrentPage == 1) { - radeon->numClipRects = drawable->numClipRects; - radeon->pClipRects = drawable->pClipRects; - } else { - radeon->numClipRects = drawable->numBackClipRects; - radeon->pClipRects = drawable->pBackClipRects; - } - } else { - /* front buffer (or none, or multiple buffers */ - radeon->numClipRects = drawable->numClipRects; - radeon->pClipRects = drawable->pClipRects; - } - } + fprintf(stderr,"cliprects %d %d\n", radeon->front_cliprects, radeon->constant_cliprect); + radeon_get_cliprects(radeon, &radeon->pClipRects, + &radeon->numClipRects, &x_off, &y_off); - if ((draw_fb->Width != drawable->w) || - (draw_fb->Height != drawable->h)) { - _mesa_resize_framebuffer(radeon->glCtx, draw_fb, + if ((draw_rfb->base.Width != drawable->w) || + (draw_rfb->base.Height != drawable->h)) { + _mesa_resize_framebuffer(radeon->glCtx, &draw_rfb->base, drawable->w, drawable->h); - draw_fb->Initialized = GL_TRUE; + draw_rfb->base.Initialized = GL_TRUE; } if (drawable != readable) { - if ((read_fb->Width != readable->w) || - (read_fb->Height != readable->h)) { - _mesa_resize_framebuffer(radeon->glCtx, read_fb, + if ((read_rfb->base.Width != readable->w) || + (read_rfb->base.Height != readable->h)) { + _mesa_resize_framebuffer(radeon->glCtx, &read_rfb->base, readable->w, readable->h); - read_fb->Initialized = GL_TRUE; + read_rfb->base.Initialized = GL_TRUE; } } if (radeon->state.scissor.enabled) radeonRecalcScissorRects(radeon); - radeon->lastStamp = drawable->lastStamp; } + + void radeonUpdateScissor( GLcontext *ctx ) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -348,6 +368,37 @@ static void radeonWaitForIdle(radeonContextPtr radeon) UNLOCK_HARDWARE(radeon); } +static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb) +{ + int current_page = rfb->pf_current_page; + int next_page = (current_page + 1) % rfb->pf_num_pages; + struct gl_renderbuffer *tmp_rb; + + /* Exchange renderbuffers if necessary but make sure their + * reference counts are preserved. + */ + if (rfb->color_rb[current_page] && + rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer != + &rfb->color_rb[current_page]->base) { + tmp_rb = NULL; + _mesa_reference_renderbuffer(&tmp_rb, + rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer); + tmp_rb = &rfb->color_rb[current_page]->base; + _mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer, tmp_rb); + _mesa_reference_renderbuffer(&tmp_rb, NULL); + } + + if (rfb->color_rb[next_page] && + rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer != + &rfb->color_rb[next_page]->base) { + tmp_rb = NULL; + _mesa_reference_renderbuffer(&tmp_rb, + rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer); + tmp_rb = &rfb->color_rb[next_page]->base; + _mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer, tmp_rb); + _mesa_reference_renderbuffer(&tmp_rb, NULL); + } +} /* Copy the back color buffer to the front color buffer. */ @@ -355,10 +406,8 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, const drm_clip_rect_t *rect) { radeonContextPtr rmesa; + struct radeon_framebuffer *rfb; GLint nbox, i, ret; - GLboolean missed_target; - int64_t ust; - __DRIscreenPrivate *psp; assert(dPriv); assert(dPriv->driContextPriv); @@ -366,24 +415,12 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rfb = dPriv->driverPrivate; + if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); } - radeon_firevertices(rmesa); - LOCK_HARDWARE( rmesa ); - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion( rmesa ); - if (!rect) - { - UNLOCK_HARDWARE( rmesa ); - driWaitForVBlank( dPriv, & missed_target ); - LOCK_HARDWARE( rmesa ); - } - nbox = dPriv->numClipRects; /* must be in locked region */ for ( i = 0 ; i < nbox ; ) { @@ -429,94 +466,76 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, } UNLOCK_HARDWARE( rmesa ); - if (!rect) - { - psp = dPriv->driScreenPriv; - rmesa->swap_count++; - (*psp->systemTime->getUST)( & ust ); - if ( missed_target ) { - rmesa->swap_missed_count++; - rmesa->swap_missed_ust = ust - rmesa->swap_ust; - } +} - rmesa->swap_ust = ust; - rmesa->hw.all_dirty = GL_TRUE; +static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_target) +{ + radeonContextPtr rmesa; + + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + radeon_firevertices(rmesa); + LOCK_HARDWARE( rmesa ); + + if (!dPriv->numClipRects) { + UNLOCK_HARDWARE(rmesa); + usleep(10000); /* throttle invisible client 10ms */ + return 0; } + + radeonWaitForFrameCompletion(rmesa); + + UNLOCK_HARDWARE(rmesa); + driWaitForVBlank(dPriv, missed_target); + LOCK_HARDWARE(rmesa); + + return 0; } -void radeonPageFlip( __DRIdrawablePrivate *dPriv ) +static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) { - radeonContextPtr rmesa; + radeonContextPtr radeon; GLint ret; - GLboolean missed_target; __DRIscreenPrivate *psp; struct radeon_renderbuffer *rrb; - GLframebuffer *fb = dPriv->driverPrivate; - + struct radeon_framebuffer *rfb; + assert(dPriv); assert(dPriv->driContextPriv); assert(dPriv->driContextPriv->driverPrivate); - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + rfb = dPriv->driverPrivate; + rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; psp = dPriv->driScreenPriv; if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); + fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__, + radeon->sarea->pfCurrentPage, radeon->sarea->pfState); } - - radeon_firevertices(rmesa); - - LOCK_HARDWARE( rmesa ); - - if (!dPriv->numClipRects) { - UNLOCK_HARDWARE(rmesa); - usleep(10000); /* throttle invisible client 10ms */ - return; - } - drm_clip_rect_t *box = dPriv->pClipRects; - drm_clip_rect_t *b = rmesa->sarea->boxes; + drm_clip_rect_t *b = radeon->sarea->boxes; b[0] = box[0]; - rmesa->sarea->nbox = 1; - - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ - radeonWaitForFrameCompletion( rmesa ); - UNLOCK_HARDWARE( rmesa ); - driWaitForVBlank( dPriv, & missed_target ); - if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); - } - LOCK_HARDWARE( rmesa ); + radeon->sarea->nbox = 1; - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); + ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP ); - UNLOCK_HARDWARE( rmesa ); + UNLOCK_HARDWARE( radeon ); if ( ret ) { fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); + return GL_FALSE; } - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); - - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. - */ - // driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - // rmesa->sarea->pfCurrentPage); - - rmesa->state.color.rrb = rrb; + if (!rfb->pf_active) + return GL_FALSE; + + rfb->pf_current_page = radeon->sarea->pfCurrentPage; + radeon_flip_renderbuffers(rfb); + radeon_draw_buffer(radeon->glCtx, &rfb->base); - if (rmesa->vtbl.update_draw_buffer) - rmesa->vtbl.update_draw_buffer(rmesa->glCtx); + return GL_TRUE; } @@ -525,6 +544,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) */ void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) { + int64_t ust; + __DRIscreenPrivate *psp; + if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { radeonContextPtr radeon; GLcontext *ctx; @@ -533,12 +555,29 @@ void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) ctx = radeon->glCtx; if (ctx->Visual.doubleBufferMode) { + GLboolean missed_target; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ - if (radeon->doPageFlip) { + + radeonScheduleSwap(dPriv, &missed_target); + + if (rfb->pf_active) { radeonPageFlip(dPriv); } else { radeonCopyBuffer(dPriv, NULL); } + + psp = dPriv->driScreenPriv; + + rfb->swap_count++; + (*psp->systemTime->getUST)( & ust ); + if ( missed_target ) { + rfb->swap_missed_count++; + rfb->swap_missed_ust = ust - rfb->swap_ust; + } + + rfb->swap_ust = ust; + radeon->hw.all_dirty = GL_TRUE; } } else { /* XXX this shouldn't be an error but we can't handle it for now */ @@ -573,7 +612,224 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, } } +void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL, + *rrbColor = NULL; + + + if (!fb) { + /* this can happen during the initial context initialization */ + return; + } + + /* radeons only handle 1 color draw so far */ + if (fb->_NumColorDrawBuffers != 1) { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); + return; + } + + /* Do this here, note core Mesa, since this function is called from + * many places within the driver. + */ + if (ctx->NewState & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { + /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */ + _mesa_update_framebuffer(ctx); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx); + } + + if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) { + /* this may occur when we're called by glBindFrameBuffer() during + * the process of someone setting up renderbuffers, etc. + */ + /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/ + return; + } + + if (fb->Name) + ;/* do something depthy/stencily TODO */ + + + /* none */ + if (fb->Name == 0) { + if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { + rrbColor = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + radeon->front_cliprects = GL_TRUE; + } else { + rrbColor = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon->front_cliprects = GL_FALSE; + } + } else { + /* user FBO in theory */ + struct radeon_renderbuffer *rrb; + rrb = (void *)fb->_ColorDrawBuffers[0]; + rrbColor = rrb; + radeon->constant_cliprect = GL_TRUE; + } + + if (rrbColor == NULL) + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); + else + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); + + + + if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) { + rrbDepth = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; + if (rrbDepth && rrbDepth->bo) { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); + } else { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); + } + } else { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); + rrbDepth = NULL; + } + + /* TODO stencil things */ + if (fb->_StencilBuffer && fb->_StencilBuffer->Wrapped) { + rrbStencil = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; + if (rrbStencil && rrbStencil->bo) { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); + /* need to re-compute stencil hw state */ + if (ctx->Driver.Enable != NULL) + ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); + else + ctx->NewState |= _NEW_STENCIL; + if (!rrbDepth) + rrbDepth = rrbStencil; + } else { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE); + } + } else { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); + if (ctx->Driver.Enable != NULL) + ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); + else + ctx->NewState |= _NEW_STENCIL; + } + + /* Update culling direction which changes depending on the + * orientation of the buffer: + */ + if (ctx->Driver.FrontFace) + ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); + else + ctx->NewState |= _NEW_POLYGON; + + /* + * Update depth test state + */ + if (ctx->Driver.Enable) { + if (ctx->Depth.Test && fb->Visual.depthBits > 0) { + ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE); + } else { + ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE); + } + } else { + ctx->NewState |= _NEW_DEPTH; + } + + radeon->state.depth.rrb = rrbDepth; + + radeon->state.color.rrb = rrbColor; + + /* update viewport since it depends on window size */ + if (ctx->Driver.Viewport) { + ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, + ctx->Viewport.Width, ctx->Viewport.Height); + } else { + ctx->NewState |= _NEW_VIEWPORT; + } + + /* Set state we know depends on drawable parameters: + */ + if (ctx->Driver.Scissor) + ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, + ctx->Scissor.Width, ctx->Scissor.Height); + radeon->NewGLState |= _NEW_SCISSOR; +} + +/** + * Called via glDrawBuffer. + */ +void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s %s\n", __FUNCTION__, + _mesa_lookup_enum_by_nr( mode )); + + radeon_firevertices(radeon); /* don't pipeline cliprect changes */ + + radeon_draw_buffer(ctx, ctx->DrawBuffer); +} + +void radeonReadBuffer( GLcontext *ctx, GLenum mode ) +{ + /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */ + if (ctx->ReadBuffer == ctx->DrawBuffer) { + /* This will update FBO completeness status. + * A framebuffer will be incomplete if the GL_READ_BUFFER setting + * refers to a missing renderbuffer. Calling glReadBuffer can set + * that straight and can make the drawing buffer complete. + */ + radeon_draw_buffer(ctx, ctx->DrawBuffer); + } +} + +/* Turn on/off page flipping according to the flags in the sarea: + */ +void radeonUpdatePageFlipping(radeonContextPtr radeon) +{ + struct radeon_framebuffer *rfb = radeon->dri.drawable->driverPrivate; + + rfb->pf_active = radeon->sarea->pfState; + rfb->pf_current_page = radeon->sarea->pfCurrentPage; + rfb->pf_num_pages = 2; + radeon_flip_renderbuffers(rfb); + radeon_draw_buffer(radeon->glCtx, radeon->glCtx->DrawBuffer); +} + +void radeon_window_moved(radeonContextPtr radeon) +{ + GLcontext *ctx = radeon->glCtx; + __DRIdrawablePrivate *dPriv = radeon->dri.drawable; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; + + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + radeonUpdatePageFlipping(radeon); + } + radeonSetCliprects(radeon); +} + +void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + __DRIcontext *driContext = radeon->dri.context; + void (*old_viewport)(GLcontext *ctx, GLint x, GLint y, + GLsizei w, GLsizei h); + + if (!driContext->driScreenPriv->dri2.enabled) + return; + + radeon_update_renderbuffers(driContext, driContext->driDrawablePriv); + if (driContext->driDrawablePriv != driContext->driReadablePriv) + radeon_update_renderbuffers(driContext, driContext->driReadablePriv); + + old_viewport = ctx->Driver.Viewport; + ctx->Driver.Viewport = NULL; + radeon->dri.drawable = driContext->driDrawablePriv; + radeon_window_moved(radeon); + radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer); + ctx->Driver.Viewport = old_viewport; + + +} static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state ) { int i; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index ead0f5551b3..95b718184b7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -14,7 +14,6 @@ void radeonWaitForIdleLocked(radeonContextPtr radeon); extern uint32_t radeonGetAge(radeonContextPtr radeon); void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, const drm_clip_rect_t *rect); -void radeonPageFlip( __DRIdrawablePrivate *dPriv ); void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h ); @@ -25,6 +24,12 @@ void radeonFlush(GLcontext *ctx); void radeonFinish(GLcontext * ctx); void radeonEmitState(radeonContextPtr radeon); +void radeon_window_moved(radeonContextPtr radeon); +void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb); +void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); +void radeonReadBuffer( GLcontext *ctx, GLenum mode ); +void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); + static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) { struct radeon_renderbuffer *rrb; @@ -38,11 +43,11 @@ static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPt static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) { struct radeon_renderbuffer *rrb; - GLframebuffer *fb = rmesa->dri.drawable->driverPrivate; + struct radeon_framebuffer *rfb = rmesa->dri.drawable->driverPrivate; rrb = rmesa->state.color.rrb; if (rmesa->radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = (struct radeon_renderbuffer *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; } if (!rrb) return NULL; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 1b8a05d045b..4da2055c13d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -35,7 +35,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_common.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ #include "utils.h" -#include "drirenderbuffer.h" #include "vblank.h" #include "main/state.h" @@ -165,8 +164,6 @@ GLboolean radeonInitContext(radeonContextPtr radeon, radeon->do_usleeps ? "usleeps" : "busy waits", fthrottle_mode, radeon->radeonScreen->irq); - (*sPriv->systemTime->getUST) (&radeon->swap_ust); - return GL_TRUE; } @@ -180,39 +177,39 @@ void radeonCleanupContext(radeonContextPtr radeon) FILE *track; #endif struct radeon_renderbuffer *rb; - GLframebuffer *fb; + struct radeon_framebuffer *rfb; /* free the Mesa context */ _mesa_destroy_context(radeon->glCtx); - fb = (void*)radeon->dri.drawable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rfb = (void*)radeon->dri.drawable->driverPrivate; + rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - fb = (void*)radeon->dri.readable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rfb = (void*)radeon->dri.readable->driverPrivate; + rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; @@ -260,12 +257,12 @@ GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) static void radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) + struct radeon_framebuffer *draw) { /* if radeon->fake */ struct radeon_renderbuffer *rb; - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->frontOffset, @@ -277,7 +274,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->backOffset, @@ -289,7 +286,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->depthOffset, @@ -301,7 +298,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; } - if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->depthOffset, @@ -317,7 +314,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, static void radeon_make_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) + struct radeon_framebuffer *draw) { int size = 4096*4096*4; /* if radeon->fake */ @@ -329,7 +326,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, } - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->frontOffset + @@ -342,7 +339,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->backOffset + @@ -355,7 +352,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->depthOffset + @@ -368,7 +365,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, rb->cpp = radeon->radeonScreen->cpp; rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; } - if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) { if (!rb->bo) { rb->bo = radeon_bo_open(radeon->radeonScreen->bom, radeon->radeonScreen->depthOffset + @@ -392,7 +389,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) __DRIscreen *screen; struct radeon_renderbuffer *rb; int i, count; - GLframebuffer *draw; + struct radeon_framebuffer *draw; radeonContextPtr radeon; if (RADEON_DEBUG & DEBUG_DRI) @@ -402,13 +399,13 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) screen = context->driScreenPriv; radeon = (radeonContextPtr) context->driverPrivate; i = 0; - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { attachments[i++] = __DRI_BUFFER_FRONT_LEFT; } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { attachments[i++] = __DRI_BUFFER_BACK_LEFT; } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { attachments[i++] = __DRI_BUFFER_DEPTH; } @@ -439,7 +436,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) for (i = 0; i < count; i++) { switch (buffers[i].attachment) { case __DRI_BUFFER_FRONT_LEFT: - rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; @@ -461,7 +458,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) } break; case __DRI_BUFFER_BACK_LEFT: - rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; @@ -479,7 +476,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) buffers[i].flags); break; case __DRI_BUFFER_DEPTH: - rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; + rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; @@ -518,7 +515,8 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driReadPriv) { radeonContextPtr radeon; - GLframebuffer *dfb, *rfb; + struct radeon_framebuffer *drfb; + struct gl_framebuffer *readfb; if (!driContextPriv) { if (RADEON_DEBUG & DEBUG_DRI) @@ -526,61 +524,65 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, _mesa_make_current(NULL, NULL, NULL); return GL_TRUE; } + radeon = (radeonContextPtr) driContextPriv->driverPrivate; - dfb = driDrawPriv->driverPrivate; - rfb = driReadPriv->driverPrivate; + drfb = driDrawPriv->driverPrivate; + readfb = driReadPriv->driverPrivate; if (driContextPriv->driScreenPriv->dri2.enabled) { radeon_update_renderbuffers(driContextPriv, driDrawPriv); if (driDrawPriv != driReadPriv) radeon_update_renderbuffers(driContextPriv, driReadPriv); radeon->state.color.rrb = - (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + (void *)drfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; radeon->state.depth.rrb = - (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + (void *)drfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; } else { - radeon_make_renderbuffer_current(radeon, dfb); + radeon_make_renderbuffer_current(radeon, drfb); } if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, dfb, rfb); + fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb); driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); if (driReadPriv != driDrawPriv) driUpdateFramebufferSize(radeon->glCtx, driReadPriv); + _mesa_make_current(radeon->glCtx, &drfb->base, readfb); - - _mesa_make_current(radeon->glCtx, dfb, rfb); - - if (radeon->dri.drawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = - (radeon->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&radeon-> - optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank(driDrawPriv); - } - } + _mesa_update_state(radeon->glCtx); - radeon->dri.readable = driReadPriv; + if (radeon->glCtx->DrawBuffer == &drfb->base) { - if (radeon->dri.drawable != driDrawPriv || - radeon->lastStamp != driDrawPriv->lastStamp) { - radeon->dri.drawable = driDrawPriv; + if (radeon->dri.readable != driReadPriv) + radeon->dri.readable = driReadPriv; - radeonSetCliprects(radeon); - radeon->vtbl.update_viewport_offset(radeon->glCtx); + if (radeon->dri.drawable != driDrawPriv) { + if (driDrawPriv->swap_interval == (unsigned)-1) { + int i; + driDrawPriv->vblFlags = + (radeon->radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; + + driDrawableInitVBlank(driDrawPriv); + drfb->vbl_waited = driDrawPriv->vblSeq; + + for (i = 0; i < 2; i++) { + if (drfb->color_rb[i]) + drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq; + } + + } + radeon->dri.drawable = driDrawPriv; + +// radeonWindowMoved(radeon); + } + radeon_draw_buffer(radeon->glCtx, &drfb->base); } - _mesa_update_state(radeon->glCtx); - - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeonUpdatePageFlipping(radeon); - } if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "End %s\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index a200e902210..4aeb50fe68e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -39,6 +39,8 @@ typedef struct radeon_context *radeonContextPtr; #define RADEON_FALLBACK_BLEND_FUNC 0x0020 #define RADEON_FALLBACK_DISABLE 0x0040 #define RADEON_FALLBACK_BORDER_MODE 0x0080 +#define RADEON_FALLBACK_DEPTH_BUFFER 0x0100 +#define RADEON_FALLBACK_STENCIL_BUFFER 0x0200 #define R200_FALLBACK_TEXTURE 0x01 #define R200_FALLBACK_DRAW_BUFFER 0x02 @@ -81,9 +83,34 @@ struct radeon_renderbuffer /* boo Xorg 6.8.2 compat */ int has_surface; + GLuint pf_pending; /**< sequence number of pending flip */ + GLuint vbl_pending; /**< vblank sequence number of pending flip */ __DRIdrawablePrivate *dPriv; }; +struct radeon_framebuffer +{ + struct gl_framebuffer base; + + struct radeon_renderbuffer *color_rb[2]; + + GLuint vbl_waited; + + /* buffer swap */ + int64_t swap_ust; + int64_t swap_missed_ust; + + GLuint swap_count; + GLuint swap_missed_count; + + /* Drawable page flipping state */ + GLboolean pf_active; + GLint pf_current_page; + GLint pf_num_pages; + +}; + + struct radeon_colorbuffer_state { GLuint clear; int roundEnable; @@ -387,9 +414,6 @@ struct radeon_context { GLuint NewGLState; DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ - /* Page flipping */ - GLuint doPageFlip; - /* Drawable, cliprect and scissor information */ GLuint numClipRects; /* Cliprects for the draw buffer */ drm_clip_rect_t *pClipRects; @@ -406,13 +430,6 @@ struct radeon_context { GLuint irqsEmitted; drm_radeon_irq_wait_t iw; - /* buffer swap */ - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; - /* Derived state - for r300 only */ struct radeon_state state; @@ -422,15 +439,19 @@ struct radeon_context { driOptionCache optionCache; struct radeon_cmdbuf cmdbuf; + + drm_clip_rect_t fboRect; + GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ + GLboolean front_cliprects; struct { void (*get_lock)(radeonContextPtr radeon); void (*update_viewport_offset)(GLcontext *ctx); - void (*update_draw_buffer)(GLcontext *ctx); void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); void (*pre_emit_atoms)(radeonContextPtr rmesa); void (*pre_emit_state)(radeonContextPtr rmesa); + void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index e4202c71fc5..47ebe41c6d5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -186,10 +186,10 @@ static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; - radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; radeon->vtbl.swtcl_flush = r100_swtcl_flush; radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; + radeon->vtbl.fallback = radeonFallback; } /* Create the device specific context. @@ -369,8 +369,6 @@ radeonCreateContext( const __GLcontextModes *glVisual, rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); - #if DO_DEBUG RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ), diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index 9a7e76b245e..fb9e5e025ea 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -48,37 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_lock.h" #include "drirenderbuffer.h" -#if DEBUG_LOCKING -char *prevLockFile = NULL; -int prevLockLine = 0; -#endif - -/* Turn on/off page flipping according to the flags in the sarea: - */ -void radeonUpdatePageFlipping(radeonContextPtr rmesa) -{ - int use_back; - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - GLframebuffer *fb = drawable->driverPrivate; - - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - rmesa->vtbl.update_draw_buffer(rmesa->glCtx); - } - - use_back = rmesa->glCtx->DrawBuffer ? - (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == - BUFFER_BACK_LEFT) : 1; - use_back ^= (rmesa->sarea->pfCurrentPage == 1); - - if (use_back) - rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - else - rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - - rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; -} - /* Update the hardware state. This is called if another context has * grabbed the hardware lock, which includes the X server. This * function also updates the driver's window state after the X server @@ -112,13 +81,52 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) } if (rmesa->lastStamp != drawable->lastStamp) { - radeonUpdatePageFlipping(rmesa); - radeonSetCliprects(rmesa); - rmesa->vtbl.update_viewport_offset(rmesa->glCtx); - driUpdateFramebufferSize(rmesa->glCtx, drawable); + radeon_window_moved(rmesa); + rmesa->lastStamp = drawable->lastStamp; } rmesa->vtbl.get_lock(rmesa); rmesa->lost_context = GL_TRUE; } + +static INLINE struct radeon_renderbuffer * +radeon_get_renderbuffer(struct gl_framebuffer *fb, int attIndex) +{ + if (attIndex >= 0) + return (struct radeon_renderbuffer *)fb->Attachment[attIndex].Renderbuffer; + else + return NULL; +} + +void radeon_lock_hardware(radeonContextPtr radeon) +{ + __DRIdrawable *dPriv = radeon->dri.drawable; + char ret = 0; + struct radeon_framebuffer *rfb = NULL; + struct radeon_renderbuffer *rrb = NULL; + + if (radeon->dri.drawable) { + rfb = radeon->dri.drawable->driverPrivate; + + if (rfb) + rrb = radeon_get_renderbuffer(&rfb->base, + rfb->base._ColorDrawBufferIndexes[0]); + } + + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + DRM_CAS(radeon->dri.hwLock, radeon->dri.hwContext, + (DRM_LOCK_HELD | radeon->dri.hwContext), ret ); + if (ret) + radeonGetLock(radeon, 0); + } +} + +void radeon_unlock_hardware(radeonContextPtr radeon) +{ + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + DRM_UNLOCK( radeon->dri.fd, + radeon->dri.hwLock, + radeon->dri.hwContext ); + } +} diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h index f5ebb8dd54c..2817709eed6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.h +++ b/src/mesa/drivers/dri/radeon/radeon_lock.h @@ -48,73 +48,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); -/* Turn DEBUG_LOCKING on to find locking conflicts. - */ -#define DEBUG_LOCKING 0 - -#if DEBUG_LOCKING -extern char *prevLockFile; -extern int prevLockLine; - -#define DEBUG_LOCK() \ - do { \ - prevLockFile = (__FILE__); \ - prevLockLine = (__LINE__); \ - } while (0) - -#define DEBUG_RESET() \ - do { \ - prevLockFile = 0; \ - prevLockLine = 0; \ - } while (0) - -#define DEBUG_CHECK_LOCK() \ - do { \ - if ( prevLockFile ) { \ - fprintf( stderr, \ - "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ - prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ - exit( 1 ); \ - } \ - } while (0) - -#else - -#define DEBUG_LOCK() -#define DEBUG_RESET() -#define DEBUG_CHECK_LOCK() - -#endif - -/* - * !!! We may want to separate locks from locks with validation. This - * could be used to improve performance for those things commands that - * do not do any drawing !!! - */ +void radeon_lock_hardware(radeonContextPtr rmesa); +void radeon_unlock_hardware(radeonContextPtr rmesa); /* Lock the hardware and validate our state. */ -#define LOCK_HARDWARE( rmesa ) \ - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ - if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ - DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ - if ( __ret ) \ - radeonGetLock( (rmesa), 0 ); \ - } \ - DEBUG_LOCK(); \ - } while (0) - -#define UNLOCK_HARDWARE( rmesa ) \ - do { \ - if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ - DRM_UNLOCK( (rmesa)->dri.fd, \ - (rmesa)->dri.hwLock, \ - (rmesa)->dri.hwContext ); \ - DEBUG_RESET(); \ - } \ - } while (0) +#define LOCK_HARDWARE( rmesa ) radeon_lock_hardware(rmesa) +#define UNLOCK_HARDWARE( rmesa ) radeon_unlock_hardware(rmesa) #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 78f0bc25147..bf5f5c98bda 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1262,7 +1262,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { - radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; + radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; const GLboolean swDepth = GL_FALSE; const GLboolean swAlpha = GL_FALSE; @@ -1271,7 +1271,16 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, mesaVis->depthBits != 24; GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); GLenum depthFormat = GL_NONE; - struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); + struct radeon_framebuffer *rfb; + + if (isPixmap) + return GL_FALSE; /* not implemented */ + + rfb = CALLOC_STRUCT(radeon_framebuffer); + if (!rfb) + return GL_FALSE; + + _mesa_initialize_framebuffer(&rfb->base, mesaVis); if (mesaVis->depthBits == 16) depthFormat = GL_DEPTH_COMPONENT16; @@ -1279,26 +1288,22 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, depthFormat = GL_DEPTH_COMPONENT24; /* front color renderbuffer */ - { - struct radeon_renderbuffer *front = - radeon_create_renderbuffer(rgbFormat, driDrawPriv); - _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); - front->has_surface = 1; - } + rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); + _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); + rfb->color_rb[0]->has_surface = 1; /* back color renderbuffer */ if (mesaVis->doubleBufferMode) { - struct radeon_renderbuffer *back = - radeon_create_renderbuffer(rgbFormat, driDrawPriv); - _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); - back->has_surface = 1; + rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); + _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); + rfb->color_rb[1]->has_surface = 1; } /* depth renderbuffer */ if (depthFormat != GL_NONE) { struct radeon_renderbuffer *depth = radeon_create_renderbuffer(depthFormat, driDrawPriv); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); + _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); depth->has_surface = screen->depthHasSurface; } @@ -1306,18 +1311,18 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, if (mesaVis->stencilBits > 0 && !swStencil) { struct radeon_renderbuffer *stencil = radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); + _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base); stencil->has_surface = screen->depthHasSurface; } - _mesa_add_soft_renderbuffers(fb, + _mesa_add_soft_renderbuffers(&rfb->base, GL_FALSE, /* color */ swDepth, swStencil, swAccum, swAlpha, GL_FALSE /* aux */); - driDrawPriv->driverPrivate = (void *) fb; + driDrawPriv->driverPrivate = (void *) rfb; return (driDrawPriv->driverPrivate != NULL); } @@ -1325,21 +1330,21 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) { - struct radeon_renderbuffer *rb; - GLframebuffer *fb; + struct radeon_renderbuffer *rb; + struct radeon_framebuffer *rfb; - fb = (void*)driDrawPriv->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rfb = (void*)driDrawPriv->driverPrivate; + rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; @@ -1541,21 +1546,21 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) { - radeonContextPtr rmesa; + struct radeon_framebuffer *rfb; - if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) - || (dPriv->driContextPriv->driverPrivate == NULL) - || (sInfo == NULL) ) { - return -1; + if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) + || (dPriv->driContextPriv->driverPrivate == NULL) + || (sInfo == NULL) ) { + return -1; } - rmesa = dPriv->driContextPriv->driverPrivate; - sInfo->swap_count = rmesa->swap_count; - sInfo->swap_ust = rmesa->swap_ust; - sInfo->swap_missed_count = rmesa->swap_missed_count; + rfb = dPriv->driverPrivate; + sInfo->swap_count = rfb->swap_count; + sInfo->swap_ust = rfb->swap_ust; + sInfo->swap_missed_count = rfb->swap_missed_count; sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) - ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) + ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) : 0.0; return 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 5fffa286fe2..0c92a6ff086 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1418,6 +1418,8 @@ static void radeonViewport( GLcontext *ctx, GLint x, GLint y, * values, or keep the originals hanging around. */ radeonUpdateWindow( ctx ); + + radeon_viewport(ctx, x, y, width, height); } static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, @@ -1532,50 +1534,6 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = radeon_rop_tab[rop]; } - -/** - * Called via glDrawBuffer. - */ -static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s %s\n", __FUNCTION__, - _mesa_lookup_enum_by_nr( mode )); - - radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ - - if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { - /* 0 (GL_NONE) buffers or multiple color drawing buffers */ - FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE ); - return; - } - - switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) { - case BUFFER_FRONT_LEFT: - case BUFFER_BACK_LEFT: - FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE ); - break; - default: - FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE ); - return; - } - - radeonSetCliprects( &rmesa->radeon ); - if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) - radeonUpdatePageFlipping(&rmesa->radeon); - /* We'll set the drawing engine's offset/pitch parameters later - * when we update other state. - */ -} - -static void radeonReadBuffer( GLcontext *ctx, GLenum mode ) -{ - /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */ -} - - /* ============================================================= * State enable/disable */ @@ -2066,42 +2024,16 @@ static void update_texturematrix( GLcontext *ctx ) } -/** - * Tell the card where to render (offset, pitch). - * Effected by glDrawBuffer, etc - */ -void -radeonUpdateDrawBuffer(GLcontext *ctx) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; - struct radeon_renderbuffer *rrb; - - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } else { - /* drawing to multiple buffers, or none */ - return; - } - - assert(rrb); - assert(rrb->pitch); - - RADEON_STATECHANGE( rmesa, ctx ); -} - - void radeonValidateState( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint new_state = rmesa->radeon.NewGLState; if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { - radeonUpdateDrawBuffer(ctx); + _mesa_update_framebuffer(ctx); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx); + RADEON_STATECHANGE(rmesa, ctx); } if (new_state & _NEW_TEXTURE) { -- cgit v1.2.3 From 54b42c0a4a07c5eab5c5dc4ebce2b947b7b6722e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Mar 2009 03:37:23 +1000 Subject: radeon: remove debugging --- src/mesa/drivers/dri/radeon/radeon_common.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 1021f9beec6..99270c947f3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -175,7 +175,6 @@ void radeonSetCliprects(radeonContextPtr radeon) struct radeon_framebuffer *const read_rfb = readable->driverPrivate; int x_off, y_off; - fprintf(stderr,"cliprects %d %d\n", radeon->front_cliprects, radeon->constant_cliprect); radeon_get_cliprects(radeon, &radeon->pClipRects, &radeon->numClipRects, &x_off, &y_off); -- cgit v1.2.3 From e0de73e8a558db5dfe8e20ed7aa2e9eae28861c1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Mar 2009 18:36:13 +1000 Subject: radeon: fixup some segfaults/exit at startup --- src/mesa/drivers/dri/radeon/radeon_common_context.c | 6 +++--- src/mesa/drivers/dri/radeon/radeon_state_init.c | 4 +--- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 4da2055c13d..73583910970 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -545,6 +545,9 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb); + if (radeon->dri.readable != driReadPriv) + radeon->dri.readable = driReadPriv; + driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); if (driReadPriv != driDrawPriv) driUpdateFramebufferSize(radeon->glCtx, driReadPriv); @@ -555,9 +558,6 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (radeon->glCtx->DrawBuffer == &drfb->base) { - if (radeon->dri.readable != driReadPriv) - radeon->dri.readable = driReadPriv; - if (radeon->dri.drawable != driDrawPriv) { if (driDrawPriv->swap_interval == (unsigned)-1) { int i; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 7ff0eb450ce..26a9c316ce8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -549,9 +549,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: - fprintf( stderr, "Error: Unsupported depth %d... exiting\n", - ctx->Visual.depthBits ); - exit( -1 ); + break; } /* Only have hw stencil when depth buffer is 24 bits deep */ -- cgit v1.2.3 From 940d47de08eedaf5d8471628ba4860663d79a98e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Mar 2009 18:36:46 +1000 Subject: radeon: use swrast clear - fail on depth need to write real hw user clear --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 157 +++++++++++++++++++---------- 1 file changed, 103 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index b5ab9234df6..6a24fc45ae6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -405,71 +405,52 @@ void radeonEmitAOS( r100ContextPtr rmesa, */ #define RADEON_MAX_CLEARS 256 -static void radeonClear( GLcontext *ctx, GLbitfield mask ) +static void radeonUserClear(GLcontext *ctx, GLuint flags) { - r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; - uint32_t clear; - GLuint flags = 0; - GLuint color_mask = 0; - GLint ret, i; - GLint cx, cy, cw, ch; + GLuint mask = 0; - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "radeonClear\n"); - } + if (flags & RADEON_FRONT) + mask |= BUFFER_BIT_FRONT_LEFT; - { - LOCK_HARDWARE( &rmesa->radeon ); - UNLOCK_HARDWARE( &rmesa->radeon ); - if ( dPriv->numClipRects == 0 ) - return; - } - - radeonFlush( ctx ); + if (flags & RADEON_BACK) + mask |= BUFFER_BIT_BACK_LEFT; - if ( mask & BUFFER_BIT_FRONT_LEFT ) { - flags |= RADEON_FRONT; - color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; - mask &= ~BUFFER_BIT_FRONT_LEFT; - } + if (flags & RADEON_DEPTH) + mask |= BUFFER_BIT_DEPTH; - if ( mask & BUFFER_BIT_BACK_LEFT ) { - flags |= RADEON_BACK; - color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; - mask &= ~BUFFER_BIT_BACK_LEFT; - } + if (flags & RADEON_STENCIL) + mask |= BUFFER_BIT_STENCIL; - if ( mask & BUFFER_BIT_DEPTH ) { - flags |= RADEON_DEPTH; - mask &= ~BUFFER_BIT_DEPTH; - } +#if 1 + _swrast_Clear(ctx, mask); +#else + for ( i = 0 ; i < dPriv->numClipRects ; ) { - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { - flags |= RADEON_STENCIL; - mask &= ~BUFFER_BIT_STENCIL; } - if ( mask ) { - if (RADEON_DEBUG & DEBUG_FALLBACKS) - fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); - _swrast_Clear( ctx, mask ); - } + if (flags & (RADEON_FRONT | RADEON_BACK)) { + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH((RADEON_WAIT_3D_IDLECLEAN | + RADEON_WAIT_HOST_IDLECLEAN)); + OUT_BATCH_REGVAL(RADEON_DP_WRITE_MASK, 0); //clear->color_mask); - if ( !flags ) - return; + } + + if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) + && (flags & RADEON_CLEAR_FASTZ)) { - if (rmesa->using_hyperz) { - flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) - flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->radeon.state.stencil.hwBuffer) || - ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && - ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { - flags |= RADEON_CLEAR_FASTZ; - } } +#endif +} + +static void radeonKernelClear(GLcontext *ctx, GLuint flags) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; + uint32_t clear; + GLint ret, i; + GLint cx, cy, cw, ch; LOCK_HARDWARE( &rmesa->radeon ); @@ -580,8 +561,76 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) exit( 1 ); } } - UNLOCK_HARDWARE( &rmesa->radeon ); +} + +static void radeonClear( GLcontext *ctx, GLbitfield mask ) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + GLuint flags = 0; + GLuint color_mask = 0; + + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf( stderr, "radeonClear\n"); + } + + { + LOCK_HARDWARE( &rmesa->radeon ); + UNLOCK_HARDWARE( &rmesa->radeon ); + if ( dPriv->numClipRects == 0 ) + return; + } + + radeonFlush( ctx ); + + if ( mask & BUFFER_BIT_FRONT_LEFT ) { + flags |= RADEON_FRONT; + color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; + mask &= ~BUFFER_BIT_FRONT_LEFT; + } + + if ( mask & BUFFER_BIT_BACK_LEFT ) { + flags |= RADEON_BACK; + color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; + mask &= ~BUFFER_BIT_BACK_LEFT; + } + + if ( mask & BUFFER_BIT_DEPTH ) { + flags |= RADEON_DEPTH; + mask &= ~BUFFER_BIT_DEPTH; + } + + if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { + flags |= RADEON_STENCIL; + mask &= ~BUFFER_BIT_STENCIL; + } + + if ( mask ) { + if (RADEON_DEBUG & DEBUG_FALLBACKS) + fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); + _swrast_Clear( ctx, mask ); + } + + if ( !flags ) + return; + + if (rmesa->using_hyperz) { + flags |= RADEON_USE_COMP_ZBUF; +/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) + flags |= RADEON_USE_HIERZ; */ + if (!(rmesa->radeon.state.stencil.hwBuffer) || + ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && + ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { + flags |= RADEON_CLEAR_FASTZ; + } + } + + if (rmesa->radeon.radeonScreen->kernel_mm) + radeonUserClear(ctx, flags); + else + radeonKernelClear(ctx, flags); + rmesa->radeon.hw.all_dirty = GL_TRUE; } -- cgit v1.2.3 From 26d0172a5bc5b733e839e3ccb8d497cab2bcce98 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Mar 2009 20:24:08 +1000 Subject: radeon: fix texturing for r100 --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 75 ++++++++++++++++++++++--- 1 file changed, 66 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 26a9c316ce8..bff16fa6aa9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -427,9 +427,9 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) /* output the first 7 bytes of context */ if (drb) - dwords += 4; + dwords += 2; if (rrb) - dwords += 4; + dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); /* In the CS case we need to split this up */ @@ -438,7 +438,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (drb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); OUT_BATCH(zbpitch); @@ -507,27 +507,80 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) if (t && t->mt && !t->image_override) dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, 3); if (t && t->mt && !t->image_override) { if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { lvl = &t->mt->levels[0]; OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, - RADEON_GEM_DOMAIN_VRAM, 0, 0); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); // OUT_BATCH(r100->radeon.radeonScreen); - } else if (t->image_override) + } else { OUT_BATCH(t->override_offset); + } OUT_BATCH_TABLE((atom->cmd+4), 5); END_BATCH(); } +static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r100->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; + int hastexture = 1; + + if (!t) + hastexture = 0; + else { + if (!t->mt && !t->bo) + hastexture = 0; + } + dwords += 1; + if (hastexture) + dwords += 2; + else + dwords -= 2; + BEGIN_BATCH_NO_AUTOSTATE(dwords); + + OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); + OUT_BATCH_TABLE((atom->cmd + 1), 2); + + if (hastexture) { + OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); + if (t && t->mt && !t->image_override) { + if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { + lvl = &t->mt->levels[0]; + OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + } else { + if (t->bo) + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + } + + OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1)); + OUT_BATCH_TABLE((atom->cmd+4), 2); + OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0)); + OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR])); + END_BATCH(); +} + /* Initialize the context's hardware state. */ void radeonInitState( r100ContextPtr rmesa ) @@ -598,10 +651,14 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); - ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 ); + ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); - for (i = 0; i < 3; i++) - rmesa->hw.tex[i].emit = tex_emit; + for (i = 0; i < 3; i++) { + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.tex[i].emit = tex_emit_cs; + else + rmesa->hw.tex[i].emit = tex_emit; + } if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) { ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); -- cgit v1.2.3 From 924bf0d8d3db28941efa97911bdcdd01a3f33b7c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Mar 2009 22:26:20 +1000 Subject: radeon: settexbuffer support This gets DRI2 compiz going --- src/mesa/drivers/dri/radeon/radeon_screen.c | 6 ++ src/mesa/drivers/dri/radeon/radeon_state_init.c | 2 +- src/mesa/drivers/dri/radeon/radeon_tex.h | 1 + src/mesa/drivers/dri/radeon/radeon_texstate.c | 111 ++++++++++++++++++++++++ 4 files changed, 119 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index bf5f5c98bda..ecca81f715b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -335,6 +335,11 @@ static const __DRItexOffsetExtension radeonTexOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, radeonSetTexOffset, }; + +static const __DRItexBufferExtension radeonTexBufferExtension = { + { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, + radeonSetTexBuffer, +}; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) @@ -1088,6 +1093,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) #if !RADEON_COMMON screen->extensions[i++] = &radeonTexOffsetExtension.base; + screen->extensions[i++] = &radeonTexBufferExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index bff16fa6aa9..bc4c2214549 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -558,7 +558,7 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (hastexture) { OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); - if (t && t->mt && !t->image_override) { + if (t->mt && !t->image_override) { if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { lvl = &t->mt->levels[0]; OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h index 8c2f9be241d..4c2fba44894 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h @@ -41,6 +41,7 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); +extern void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); extern void radeonUpdateTextureState( GLcontext *ctx ); extern int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 6a34f1e3328..a24b5c88300 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -39,6 +39,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/macros.h" #include "main/texformat.h" +#include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" @@ -636,6 +637,112 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, } } +void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + struct gl_texture_unit *texUnit; + struct gl_texture_object *texObj; + struct gl_texture_image *texImage; + struct radeon_renderbuffer *rb; + radeon_texture_image *rImage; + radeonContextPtr radeon; + r100ContextPtr rmesa; + struct radeon_framebuffer *rfb; + radeonTexObjPtr t; + uint32_t pitch_val; + + target = GL_TEXTURE_RECTANGLE_ARB; + + radeon = pDRICtx->driverPrivate; + rmesa = pDRICtx->driverPrivate; + + rfb = dPriv->driverPrivate; + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + + rImage = get_radeon_texture_image(texImage); + t = radeon_tex_obj(texObj); + if (t == NULL) { + return; + } + + radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ + rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; + } + + _mesa_lock_texture(radeon->glCtx, texObj); + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + if (rImage->bo) { + radeon_bo_unref(rImage->bo); + rImage->bo = NULL; + } + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = NULL; + } + if (rImage->mt) { + radeon_miptree_unreference(rImage->mt); + rImage->mt = NULL; + } + fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->width, rb->height, 1, 0, rb->cpp); + texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + rImage->bo = rb->bo; + radeon_bo_ref(rImage->bo); + t->bo = rb->bo; + radeon_bo_ref(t->bo); + t->tile_bits = 0; + t->image_override = GL_TRUE; + t->override_offset = 0; + t->pp_txpitch &= (1 << 13) -1; + pitch_val = rb->pitch; + switch (rb->cpp) { + case 4: + t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; + t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; + // pitch_val /= 4; + break; + case 3: + default: + t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; + t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter; +// pitch_val /= 4; + break; + case 2: + t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format; + t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; + pitch_val /= 2; + break; + } + t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT) + | ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT); + t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; + t->pp_txpitch = pitch_val; + t->pp_txpitch -= 32; + + t->validated = GL_TRUE; + _mesa_unlock_texture(radeon->glCtx, texObj); + return; +} + #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \ RADEON_MIN_FILTER_MASK | \ RADEON_MAG_FILTER_MASK | \ @@ -899,6 +1006,10 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int const struct gl_texture_image *firstImage; GLint log2Width, log2Height, log2Depth, texelBytes; + if ( t->image_override ) { + return GL_TRUE; + } + firstImage = t->base.Image[0][t->mt->firstLevel]; if (firstImage->Border > 0) { -- cgit v1.2.3 From 31f129880719f75c491fa2ad269055fbc2fb9b95 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Mar 2009 22:26:44 +1000 Subject: radeon: r100 clean up CS packet size calc --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index bc4c2214549..8b6caf19d36 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -426,10 +426,11 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) } /* output the first 7 bytes of context */ + dwords = 10; if (drb) - dwords += 2; + dwords += 6; if (rrb) - dwords += 2; + dwords += 6; BEGIN_BATCH_NO_AUTOSTATE(dwords); /* In the CS case we need to split this up */ @@ -453,9 +454,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - } - if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH(cbpitch); } -- cgit v1.2.3 From 5c80eb7ec13e064b81302da6c672e96a7a7e4e95 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 02:31:00 +1000 Subject: r200: add set tex buffer support --- src/mesa/drivers/dri/r200/r200_tex.h | 1 + src/mesa/drivers/dri/r200/r200_texstate.c | 104 ++++++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 9 ++- 3 files changed, 111 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_tex.h b/src/mesa/drivers/dri/r200/r200_tex.h index 55592ed4f74..886682b36b7 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.h +++ b/src/mesa/drivers/dri/r200/r200_tex.h @@ -35,6 +35,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __R200_TEX_H__ #define __R200_TEX_H__ +extern void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); extern void r200SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 6432068760b..eac95b6659e 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -37,6 +37,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/macros.h" #include "main/texformat.h" +#include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" @@ -764,6 +765,109 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, } } +void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + struct gl_texture_unit *texUnit; + struct gl_texture_object *texObj; + struct gl_texture_image *texImage; + struct radeon_renderbuffer *rb; + radeon_texture_image *rImage; + radeonContextPtr radeon; + r200ContextPtr rmesa; + struct radeon_framebuffer *rfb; + radeonTexObjPtr t; + uint32_t pitch_val; + + target = GL_TEXTURE_RECTANGLE_ARB; + + radeon = pDRICtx->driverPrivate; + rmesa = pDRICtx->driverPrivate; + + rfb = dPriv->driverPrivate; + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + + rImage = get_radeon_texture_image(texImage); + t = radeon_tex_obj(texObj); + if (t == NULL) { + return; + } + + radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ + rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; + } + + _mesa_lock_texture(radeon->glCtx, texObj); + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + if (rImage->bo) { + radeon_bo_unref(rImage->bo); + rImage->bo = NULL; + } + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = NULL; + } + if (rImage->mt) { + radeon_miptree_unreference(rImage->mt); + rImage->mt = NULL; + } + fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->width, rb->height, 1, 0, rb->cpp); + texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + rImage->bo = rb->bo; + radeon_bo_ref(rImage->bo); + t->bo = rb->bo; + radeon_bo_ref(t->bo); + t->tile_bits = 0; + t->image_override = GL_TRUE; + t->override_offset = 0; + t->pp_txpitch &= (1 << 13) -1; + pitch_val = rb->pitch; + switch (rb->cpp) { + case 4: + t->pp_txformat = tx_table_le[MESA_FORMAT_ARGB8888].format; + t->pp_txfilter |= tx_table_le[MESA_FORMAT_ARGB8888].filter; + break; + case 3: + default: + t->pp_txformat = tx_table_le[MESA_FORMAT_RGB888].format; + t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB888].filter; + break; + case 2: + t->pp_txformat = tx_table_le[MESA_FORMAT_RGB565].format; + t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB565].filter; + break; + } + t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT) + | ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT); + t->pp_txformat |= R200_TXFORMAT_NON_POWER2; + t->pp_txpitch = pitch_val; + t->pp_txpitch -= 32; + + t->validated = GL_TRUE; + _mesa_unlock_texture(radeon->glCtx, texObj); + return; +} + #define REF_COLOR 1 #define REF_ALPHA 2 diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ecca81f715b..e90dffd7669 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -354,6 +354,11 @@ static const __DRItexOffsetExtension r200texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, r200SetTexOffset, }; + +static const __DRItexBufferExtension r200TexBufferExtension = { + { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, + r200SetTexBuffer, +}; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) @@ -1092,7 +1097,6 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) } #if !RADEON_COMMON - screen->extensions[i++] = &radeonTexOffsetExtension.base; screen->extensions[i++] = &radeonTexBufferExtension.base; #endif @@ -1100,11 +1104,10 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) if (IS_R200_CLASS(screen)) screen->extensions[i++] = &r200AllocateExtension.base; - screen->extensions[i++] = &r200texOffsetExtension.base; + screen->extensions[i++] = &r200TexBufferExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - //screen->extensions[i++] = &r300texOffsetExtension.base; screen->extensions[i++] = &r300TexBufferExtension.base; #endif -- cgit v1.2.3 From eba8008916503cea47c557398b009e2e2b546cb1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 5 Mar 2009 18:58:48 +1000 Subject: r200: port over state emits for kms from radeon this needs testing on real hw --- src/mesa/drivers/dri/r200/r200_state_init.c | 77 +++++++++++++++++++++++++---- 1 file changed, 67 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index b40690edb9e..096ebad028c 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -515,10 +515,11 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } + dwords = 14; if (drb) - dwords += 4; + dwords += 6; if (rrb) - dwords += 4; + dwords += 6; /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -529,7 +530,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (drb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); OUT_BATCH(zbpitch); @@ -545,9 +546,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - } - if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH(cbpitch); } @@ -571,18 +570,73 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 10); - if (t && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); + + if (t && t->mt && !t->image_override) { + if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { + lvl = &t->mt->levels[0]; + OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); - } else if (t->image_override) + } else { OUT_BATCH(t->override_offset); + } END_BATCH(); } +static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r200->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; + int hastexture = 1; + + if (!t) + hastexture = 0; + else { + if (!t->mt && !t->bo) + hastexture = 0; + } + dwords += 1; + if (hastexture) + dwords += 2; + else + dwords -= 2; + BEGIN_BATCH_NO_AUTOSTATE(dwords); + + OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 8)); + OUT_BATCH_TABLE((atom->cmd + 1), 9); + + if (hastexture) { + OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); + if (t->mt && !t->image_override) { + if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { + lvl = &t->mt->levels[0]; + OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + } else { + if (t->bo) + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + } + END_BATCH(); +} + + static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); @@ -716,7 +770,10 @@ void r200InitState( r200ContextPtr rmesa ) } for (i = 0; i < 5; i++) - rmesa->hw.tex[i].emit = tex_emit; + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.tex[i].emit = tex_emit_cs; + else + rmesa->hw.tex[i].emit = tex_emit; if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) { ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); -- cgit v1.2.3 From 9d72a759170ebf51d8f93fd00d3d9c37bd5dfb27 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 5 Mar 2009 19:00:17 +1000 Subject: radeon: use t->bo to figure out of settexbuffer override is in action --- src/mesa/drivers/dri/r200/r200_texstate.c | 4 ++++ src/mesa/drivers/dri/radeon/radeon_texstate.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index eac95b6659e..4937b0665d1 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1408,6 +1408,10 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) t->base.Image[0][t->mt->firstLevel]; GLint log2Width, log2Height, log2Depth, texelBytes; + if ( t->bo ) { + return; + } + log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index a24b5c88300..42356cd37b8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -1006,7 +1006,7 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int const struct gl_texture_image *firstImage; GLint log2Width, log2Height, log2Depth, texelBytes; - if ( t->image_override ) { + if ( t->bo ) { return GL_TRUE; } -- cgit v1.2.3 From 7ba9eb1e85e1017700a02c4f5d2848e3d997bc5b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 04:47:29 +1000 Subject: r200: temporary sw clear code --- src/mesa/drivers/dri/r200/r200_ioctl.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 6076b6d7ea4..1ab5a82a4db 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -58,6 +58,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static void r200UserClear(GLcontext *ctx, GLuint flags) { + GLuint mask = 0; + + if (flags & RADEON_FRONT) + mask |= BUFFER_BIT_FRONT_LEFT; + + if (flags & RADEON_BACK) + mask |= BUFFER_BIT_BACK_LEFT; + + if (flags & RADEON_DEPTH) + mask |= BUFFER_BIT_DEPTH; + + if (flags & RADEON_STENCIL) + mask |= BUFFER_BIT_STENCIL; + +#if 1 + _swrast_Clear(ctx, mask); +#else if (flags & (RADEON_FRONT | RADEON_BACK)) { @@ -67,7 +84,7 @@ static void r200UserClear(GLcontext *ctx, GLuint flags) && (flags & RADEON_CLEAR_FASTZ)) { } - +#endif } static void r200KernelClear(GLcontext *ctx, GLuint flags) -- cgit v1.2.3 From a03a4dd524b97f43356b830c21df05f82795fe0b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 04:47:45 +1000 Subject: r200: remove depth check for dri2 --- src/mesa/drivers/dri/r200/r200_state_init.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 096ebad028c..f7149c36e20 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -676,14 +676,11 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: + default: rmesa->radeon.state.depth.clear = 0x00ffffff; rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; rmesa->radeon.state.stencil.clear = 0xffff0000; break; - default: - fprintf( stderr, "Error: Unsupported depth %d... exiting\n", - ctx->Visual.depthBits ); - exit( -1 ); } /* Only have hw stencil when depth buffer is 24 bits deep */ -- cgit v1.2.3 From b074aacdb2a9e3520ccd6cfd892b60599ad0d1d8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 05:42:37 +1000 Subject: r200: cs emit state fixups --- src/mesa/drivers/dri/r200/r200_state_init.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f7149c36e20..a71f33ca3bb 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -515,7 +515,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } - dwords = 14; + dwords = 10; if (drb) dwords += 6; if (rrb) @@ -565,6 +565,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) uint32_t dwords = atom->cmd_size; int i = atom->idx; radeonTexObj *t = r200->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; if (t && t->mt && !t->image_override) dwords += 2; @@ -606,15 +607,16 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (!t->mt && !t->bo) hastexture = 0; } - dwords += 1; + + dwords += 2; if (hastexture) dwords += 2; else dwords -= 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 8)); - OUT_BATCH_TABLE((atom->cmd + 1), 9); + OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7)); + OUT_BATCH_TABLE((atom->cmd + 1), 8); if (hastexture) { OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); -- cgit v1.2.3 From c6ac53bc40508ab2f0b9e023eee7ec3793fdf917 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 16:05:22 +1000 Subject: radeon: implement userspace clears This is pretty much Eric Anholts implementation of clear using the GL state machine from the Intel drivers. It works quite well for now for us, probably could do with trying to use Z engine for clears. --- src/mesa/drivers/dri/radeon/radeon_context.h | 15 ++ src/mesa/drivers/dri/radeon/radeon_ioctl.c | 252 ++++++++++++++++++++++++--- 2 files changed, 238 insertions(+), 29 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 2efabd1f557..2015e96a743 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -435,8 +435,23 @@ struct r100_context { GLuint c_textureBytes; GLuint c_vertexBuffers; + struct { + struct gl_fragment_program *bitmap_fp; + struct gl_vertex_program *passthrough_vp; + + struct gl_fragment_program *saved_fp; + GLboolean saved_fp_enable; + struct gl_vertex_program *saved_vp; + GLboolean saved_vp_enable; + + GLint saved_vp_x, saved_vp_y; + GLsizei saved_vp_width, saved_vp_height; + GLenum saved_matrix_mode; + } meta; + }; + #define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 6a24fc45ae6..22584f4817a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -37,6 +37,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include #include +#include "main/attrib.h" +#include "main/enable.h" +#include "main/blend.h" +#include "main/bufferobj.h" +#include "main/buffers.h" +#include "main/depth.h" +#include "main/shaders.h" +#include "main/texstate.h" +#include "main/varray.h" +#include "glapi/dispatch.h" +#include "swrast/swrast.h" +#include "main/stencil.h" +#include "main/matrix.h" + #include "main/glheader.h" #include "main/imports.h" #include "main/simple_list.h" @@ -405,42 +419,221 @@ void radeonEmitAOS( r100ContextPtr rmesa, */ #define RADEON_MAX_CLEARS 256 -static void radeonUserClear(GLcontext *ctx, GLuint flags) + + +static void +r100_meta_set_passthrough_transform(r100ContextPtr r100) { - GLuint mask = 0; + GLcontext *ctx = r100->radeon.glCtx; - if (flags & RADEON_FRONT) - mask |= BUFFER_BIT_FRONT_LEFT; + r100->meta.saved_vp_x = ctx->Viewport.X; + r100->meta.saved_vp_y = ctx->Viewport.Y; + r100->meta.saved_vp_width = ctx->Viewport.Width; + r100->meta.saved_vp_height = ctx->Viewport.Height; + r100->meta.saved_matrix_mode = ctx->Transform.MatrixMode; - if (flags & RADEON_BACK) - mask |= BUFFER_BIT_BACK_LEFT; + _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); - if (flags & RADEON_DEPTH) - mask |= BUFFER_BIT_DEPTH; + _mesa_MatrixMode(GL_PROJECTION); + _mesa_PushMatrix(); + _mesa_LoadIdentity(); + _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); - if (flags & RADEON_STENCIL) - mask |= BUFFER_BIT_STENCIL; + _mesa_MatrixMode(GL_MODELVIEW); + _mesa_PushMatrix(); + _mesa_LoadIdentity(); +} -#if 1 - _swrast_Clear(ctx, mask); -#else - for ( i = 0 ; i < dPriv->numClipRects ; ) { +static void +r100_meta_restore_transform(r100ContextPtr r100) +{ + _mesa_MatrixMode(GL_PROJECTION); + _mesa_PopMatrix(); + _mesa_MatrixMode(GL_MODELVIEW); + _mesa_PopMatrix(); - } + _mesa_MatrixMode(r100->meta.saved_matrix_mode); - if (flags & (RADEON_FRONT | RADEON_BACK)) { - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH((RADEON_WAIT_3D_IDLECLEAN | - RADEON_WAIT_HOST_IDLECLEAN)); - OUT_BATCH_REGVAL(RADEON_DP_WRITE_MASK, 0); //clear->color_mask); + _mesa_Viewport(r100->meta.saved_vp_x, r100->meta.saved_vp_y, + r100->meta.saved_vp_width, r100->meta.saved_vp_height); +} +/** + * Perform glClear where mask contains only color, depth, and/or stencil. + * + * The implementation is based on calling into Mesa to set GL state and + * performing normal triangle rendering. The intent of this path is to + * have as generic a path as possible, so that any driver could make use of + * it. + */ +static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + GLfloat vertices[4][3]; + GLfloat color[4][4]; + GLfloat dst_z; + struct gl_framebuffer *fb = ctx->DrawBuffer; + int i; + GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; + GLboolean saved_shader_program = 0; + unsigned int saved_active_texture; + + assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | + BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); + + _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | + GL_CURRENT_BIT | + GL_DEPTH_BUFFER_BIT | + GL_ENABLE_BIT | + GL_STENCIL_BUFFER_BIT | + GL_TRANSFORM_BIT | + GL_CURRENT_BIT); + _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); + saved_active_texture = ctx->Texture.CurrentUnit; + + /* Disable existing GL state we don't want to apply to a clear. */ + _mesa_Disable(GL_ALPHA_TEST); + _mesa_Disable(GL_BLEND); + _mesa_Disable(GL_CULL_FACE); + _mesa_Disable(GL_FOG); + _mesa_Disable(GL_POLYGON_SMOOTH); + _mesa_Disable(GL_POLYGON_STIPPLE); + _mesa_Disable(GL_POLYGON_OFFSET_FILL); + _mesa_Disable(GL_LIGHTING); + _mesa_Disable(GL_CLIP_PLANE0); + _mesa_Disable(GL_CLIP_PLANE1); + _mesa_Disable(GL_CLIP_PLANE2); + _mesa_Disable(GL_CLIP_PLANE3); + _mesa_Disable(GL_CLIP_PLANE4); + _mesa_Disable(GL_CLIP_PLANE5); + if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { + saved_fp_enable = GL_TRUE; + _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); + } + if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { + saved_vp_enable = GL_TRUE; + _mesa_Disable(GL_VERTEX_PROGRAM_ARB); + } + if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { + saved_shader_program = ctx->Shader.CurrentProgram->Name; + _mesa_UseProgramObjectARB(0); + } + + if (ctx->Texture._EnabledUnits != 0) { + int i; + + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { + _mesa_ActiveTextureARB(GL_TEXTURE0 + i); + _mesa_Disable(GL_TEXTURE_1D); + _mesa_Disable(GL_TEXTURE_2D); + _mesa_Disable(GL_TEXTURE_3D); + if (ctx->Extensions.ARB_texture_cube_map) + _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); + if (ctx->Extensions.NV_texture_rectangle) + _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); + if (ctx->Extensions.MESA_texture_array) { + _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); + _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); + } + } } - - if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) - && (flags & RADEON_CLEAR_FASTZ)) { + + r100_meta_set_passthrough_transform(rmesa); + + for (i = 0; i < 4; i++) { + color[i][0] = ctx->Color.ClearColor[0]; + color[i][1] = ctx->Color.ClearColor[1]; + color[i][2] = ctx->Color.ClearColor[2]; + color[i][3] = ctx->Color.ClearColor[3]; + } + + /* convert clear Z from [0,1] to NDC coord in [-1,1] */ + dst_z = -1.0 + 2.0 * ctx->Depth.Clear; + + /* Prepare the vertices, which are the same regardless of which buffer we're + * drawing to. + */ + vertices[0][0] = fb->_Xmin; + vertices[0][1] = fb->_Ymin; + vertices[0][2] = dst_z; + vertices[1][0] = fb->_Xmax; + vertices[1][1] = fb->_Ymin; + vertices[1][2] = dst_z; + vertices[2][0] = fb->_Xmax; + vertices[2][1] = fb->_Ymax; + vertices[2][2] = dst_z; + vertices[3][0] = fb->_Xmin; + vertices[3][1] = fb->_Ymax; + vertices[3][2] = dst_z; + + _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); + _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); + _mesa_Enable(GL_COLOR_ARRAY); + _mesa_Enable(GL_VERTEX_ARRAY); + + while (mask != 0) { + GLuint this_mask = 0; + + if (mask & BUFFER_BIT_BACK_LEFT) + this_mask = BUFFER_BIT_BACK_LEFT; + else if (mask & BUFFER_BIT_FRONT_LEFT) + this_mask = BUFFER_BIT_FRONT_LEFT; + + /* Clear depth/stencil in the same pass as color. */ + this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); + + /* Select the current color buffer and use the color write mask if + * we have one, otherwise don't write any color channels. + */ + if (this_mask & BUFFER_BIT_FRONT_LEFT) + _mesa_DrawBuffer(GL_FRONT_LEFT); + else if (this_mask & BUFFER_BIT_BACK_LEFT) + _mesa_DrawBuffer(GL_BACK_LEFT); + else + _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); + + /* Control writing of the depth clear value to depth. */ + if (this_mask & BUFFER_BIT_DEPTH) { + _mesa_DepthFunc(GL_ALWAYS); + _mesa_Enable(GL_DEPTH_TEST); + } else { + _mesa_Disable(GL_DEPTH_TEST); + _mesa_DepthMask(GL_FALSE); + } + + /* Control writing of the stencil clear value to stencil. */ + if (this_mask & BUFFER_BIT_STENCIL) { + _mesa_Enable(GL_STENCIL_TEST); + _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); + _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, + ctx->Stencil.WriteMask[0]); + } else { + _mesa_Disable(GL_STENCIL_TEST); + } + + CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); + mask &= ~this_mask; } -#endif + + r100_meta_restore_transform(rmesa); + + _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); + if (saved_fp_enable) + _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); + if (saved_vp_enable) + _mesa_Enable(GL_VERTEX_PROGRAM_ARB); + + if (saved_shader_program) + _mesa_UseProgramObjectARB(saved_shader_program); + + _mesa_PopClientAttrib(); + _mesa_PopAttrib(); +} + +static void radeonUserClear(GLcontext *ctx, GLuint mask) +{ + radeon_clear_tris(ctx, mask); } static void radeonKernelClear(GLcontext *ctx, GLuint flags) @@ -570,6 +763,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLuint flags = 0; GLuint color_mask = 0; + GLuint orig_mask = mask; if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf( stderr, "radeonClear\n"); @@ -582,7 +776,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) return; } - radeonFlush( ctx ); + radeon_firevertices(&rmesa->radeon); if ( mask & BUFFER_BIT_FRONT_LEFT ) { flags |= RADEON_FRONT; @@ -627,11 +821,11 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } if (rmesa->radeon.radeonScreen->kernel_mm) - radeonUserClear(ctx, flags); - else + radeonUserClear(ctx, orig_mask); + else { radeonKernelClear(ctx, flags); - - rmesa->radeon.hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; + } } void radeonInitIoctlFuncs( GLcontext *ctx ) -- cgit v1.2.3 From e0313ef061c2988cc9df9b8a016ba06fd2ba7ce7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 23:42:17 +1100 Subject: r300: fix swtcl codepaths --- src/mesa/drivers/dri/r300/r300_swtcl.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index d73af8650f9..153582ce489 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -203,15 +203,27 @@ static void r300SetVertexFormat( GLcontext *ctx ) } R300_NEWPRIM(rmesa); - R300_STATECHANGE(rmesa, vir[0]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = + if (rmesa->radeon.radeonScreen->kernel_mm) { + R300_STATECHANGE(rmesa, vir[0]); + rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[0].cmd[0] |= + (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + VB->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; + R300_STATECHANGE(rmesa, vir[1]); + rmesa->hw.vir[1].cmd[0] |= + (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + nr) & 0x3FFF) << 16; + } else { + R300_STATECHANGE(rmesa, vir[0]); + ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], VB->AttribPtr, inputs, tab, nr); - R300_STATECHANGE(rmesa, vir[1]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = + R300_STATECHANGE(rmesa, vir[1]); + ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, nr); - + } R300_STATECHANGE(rmesa, vic); rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); @@ -600,7 +612,7 @@ void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_b fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", __FUNCTION__, vertex_size, offset); - BEGIN_BATCH(5); + BEGIN_BATCH(7); OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); -- cgit v1.2.3 From 760068cc8d5b443c4c6545870fa4f7eda7c6e775 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 6 Mar 2009 23:42:35 +1100 Subject: r300: fix uninit variable warning --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 231576fed89..3626b877eb9 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -268,8 +268,7 @@ static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; - uint32_t zbpitch; - uint32_t format; + uint32_t format = 0; rrb = radeon_get_depthbuffer(&r300->radeon); if (!rrb) -- cgit v1.2.3 From f881035fd84add859b3e3dc4721eddd027005f49 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 7 Mar 2009 17:23:40 +1100 Subject: rs690: fix r300 swtcl bug in DMA code. When we finish emitting swtcl objects, we request space in the cmdbuf, and flush if no space exists. However in this case we also flush the DMA buffer we just put the vertices we wanted to send in. This checks in advance if we have space in the buffer. --- src/mesa/drivers/dri/radeon/radeon_dma.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 393b12182d5..92878a5c2e2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -275,7 +275,7 @@ void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); + fprintf(stderr, "%s %p\n", __FUNCTION__, dma->current); dma->flush = NULL; if (dma->current) { @@ -300,12 +300,19 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; void *head; - +restart: if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) { radeonRefillCurrentDmaRegion(rmesa, bytes); } if (!rmesa->dma.flush) { + /* make sure we have enough space to use this in cmdbuf */ + rcommonEnsureCmdBufSpace(&rmesa->radeon, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); + /* if cmdbuf flushed DMA restart */ + if (!rmesa->dma.current) + goto restart; rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->dma.flush = rcommon_flush_last_swtcl_prim; } -- cgit v1.2.3 From 1386e8a6ba9732c578e0122de245abfd578a7d1d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 8 Mar 2009 02:41:30 +1000 Subject: radeon: fix cut-n-paste typo --- src/mesa/drivers/dri/radeon/radeon_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 92878a5c2e2..01fc20bd796 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -307,7 +307,7 @@ restart: if (!rmesa->dma.flush) { /* make sure we have enough space to use this in cmdbuf */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, + rcommonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size + (12*sizeof(int)), __FUNCTION__); /* if cmdbuf flushed DMA restart */ -- cgit v1.2.3 From 778cf80d9e462ca26e660dca1910328f66f6427d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Mar 2009 10:34:41 +1100 Subject: r300: move firevertices out into the main place its needed. This fixes a hang on context destruction on rs690 --- src/mesa/drivers/dri/r200/r200_state.c | 1 - src/mesa/drivers/dri/r300/r300_state.c | 2 +- src/mesa/drivers/dri/radeon/radeon_common_context.c | 2 +- src/mesa/drivers/dri/radeon/radeon_state.c | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 46baad33f5c..5eb61c8804f 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1618,7 +1618,6 @@ void r200UpdateWindow( GLcontext *ctx ) float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - radeon_firevertices(&rmesa->radeon); R200_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 6bb0063bc19..17e7b5227ab 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1069,7 +1069,6 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; - radeon_firevertices(&rmesa->radeon); R300_STATECHANGE(rmesa, vpt); rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); @@ -2137,6 +2136,7 @@ static void r300ResetHwState(r300ContextPtr r300) if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); + radeon_firevertices(&r300->radeon); r300UpdateWindow(ctx); r300ColorMask(ctx, diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 73583910970..b63aba2f894 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -578,7 +578,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, } radeon->dri.drawable = driDrawPriv; -// radeonWindowMoved(radeon); + radeon_window_moved(radeon); } radeon_draw_buffer(radeon->glCtx, &drfb->base); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 0c92a6ff086..42b65cbee65 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1398,7 +1398,6 @@ void radeonUpdateWindow( GLcontext *ctx ) float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - radeon_firevertices(&rmesa->radeon); RADEON_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; -- cgit v1.2.3 From c122cc40979b79a8dc4a529da6b375252b03db3f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 5 Mar 2009 16:45:21 +1000 Subject: r300: emit texture in GTT or VRAM --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 3626b877eb9..2c6618fc608 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -189,13 +189,13 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); if (t && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); } else { /* override cases */ if (t->bo) { OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!r300->radeon.radeonScreen->kernel_mm) { OUT_BATCH(t->override_offset); } -- cgit v1.2.3 From 14c3bddbac8f9fc8e432137772f0c4772fdfb7ab Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Mar 2009 19:03:07 +1000 Subject: r200: enable hw clears --- src/mesa/drivers/dri/r200/r200_context.h | 15 ++ src/mesa/drivers/dri/r200/r200_ioctl.c | 238 ++++++++++++++++++++++++++++--- 2 files changed, 234 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index fcbe725d6fc..f7bad2a2414 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -621,6 +621,21 @@ struct r200_context { GLboolean texmicrotile; struct ati_fragment_shader *afs_loaded; + + struct { + struct gl_fragment_program *bitmap_fp; + struct gl_vertex_program *passthrough_vp; + + struct gl_fragment_program *saved_fp; + GLboolean saved_fp_enable; + struct gl_vertex_program *saved_vp; + GLboolean saved_vp_enable; + + GLint saved_vp_x, saved_vp_y; + GLsizei saved_vp_width, saved_vp_height; + GLenum saved_matrix_mode; + } meta; + }; #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 1ab5a82a4db..96ed49665b2 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -41,6 +41,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" +#include "main/blend.h" +#include "main/bufferobj.h" +#include "main/buffers.h" +#include "main/depth.h" +#include "main/shaders.h" +#include "main/texstate.h" +#include "main/varray.h" +#include "glapi/dispatch.h" +#include "swrast/swrast.h" +#include "main/stencil.h" +#include "main/matrix.h" +#include "main/attrib.h" +#include "main/enable.h" + #include "radeon_common.h" #include "radeon_lock.h" #include "r200_context.h" @@ -56,35 +70,220 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 -static void r200UserClear(GLcontext *ctx, GLuint flags) +static void +r200_meta_set_passthrough_transform(r200ContextPtr r200) { - GLuint mask = 0; + GLcontext *ctx = r200->radeon.glCtx; - if (flags & RADEON_FRONT) - mask |= BUFFER_BIT_FRONT_LEFT; + r200->meta.saved_vp_x = ctx->Viewport.X; + r200->meta.saved_vp_y = ctx->Viewport.Y; + r200->meta.saved_vp_width = ctx->Viewport.Width; + r200->meta.saved_vp_height = ctx->Viewport.Height; + r200->meta.saved_matrix_mode = ctx->Transform.MatrixMode; - if (flags & RADEON_BACK) - mask |= BUFFER_BIT_BACK_LEFT; + _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); - if (flags & RADEON_DEPTH) - mask |= BUFFER_BIT_DEPTH; + _mesa_MatrixMode(GL_PROJECTION); + _mesa_PushMatrix(); + _mesa_LoadIdentity(); + _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); - if (flags & RADEON_STENCIL) - mask |= BUFFER_BIT_STENCIL; + _mesa_MatrixMode(GL_MODELVIEW); + _mesa_PushMatrix(); + _mesa_LoadIdentity(); +} + +static void +r200_meta_restore_transform(r200ContextPtr r200) +{ + _mesa_MatrixMode(GL_PROJECTION); + _mesa_PopMatrix(); + _mesa_MatrixMode(GL_MODELVIEW); + _mesa_PopMatrix(); -#if 1 - _swrast_Clear(ctx, mask); -#else - if (flags & (RADEON_FRONT | RADEON_BACK)) { + _mesa_MatrixMode(r200->meta.saved_matrix_mode); + _mesa_Viewport(r200->meta.saved_vp_x, r200->meta.saved_vp_y, + r200->meta.saved_vp_width, r200->meta.saved_vp_height); +} +/** + * Perform glClear where mask contains only color, depth, and/or stencil. + * + * The implementation is based on calling into Mesa to set GL state and + * performing normal triangle rendering. The intent of this path is to + * have as generic a path as possible, so that any driver could make use of + * it. + */ +static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) +{ + r200ContextPtr rmesa = R200_CONTEXT(ctx); + GLfloat vertices[4][3]; + GLfloat color[4][4]; + GLfloat dst_z; + struct gl_framebuffer *fb = ctx->DrawBuffer; + int i; + GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; + GLboolean saved_shader_program = 0; + unsigned int saved_active_texture; + + assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | + BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); + + _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | + GL_CURRENT_BIT | + GL_DEPTH_BUFFER_BIT | + GL_ENABLE_BIT | + GL_STENCIL_BUFFER_BIT | + GL_TRANSFORM_BIT | + GL_CURRENT_BIT); + _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); + saved_active_texture = ctx->Texture.CurrentUnit; + + /* Disable existing GL state we don't want to apply to a clear. */ + _mesa_Disable(GL_ALPHA_TEST); + _mesa_Disable(GL_BLEND); + _mesa_Disable(GL_CULL_FACE); + _mesa_Disable(GL_FOG); + _mesa_Disable(GL_POLYGON_SMOOTH); + _mesa_Disable(GL_POLYGON_STIPPLE); + _mesa_Disable(GL_POLYGON_OFFSET_FILL); + _mesa_Disable(GL_LIGHTING); + _mesa_Disable(GL_CLIP_PLANE0); + _mesa_Disable(GL_CLIP_PLANE1); + _mesa_Disable(GL_CLIP_PLANE2); + _mesa_Disable(GL_CLIP_PLANE3); + _mesa_Disable(GL_CLIP_PLANE4); + _mesa_Disable(GL_CLIP_PLANE5); + if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { + saved_fp_enable = GL_TRUE; + _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); + } + if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { + saved_vp_enable = GL_TRUE; + _mesa_Disable(GL_VERTEX_PROGRAM_ARB); + } + if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { + saved_shader_program = ctx->Shader.CurrentProgram->Name; + _mesa_UseProgramObjectARB(0); + } + + if (ctx->Texture._EnabledUnits != 0) { + int i; + + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { + _mesa_ActiveTextureARB(GL_TEXTURE0 + i); + _mesa_Disable(GL_TEXTURE_1D); + _mesa_Disable(GL_TEXTURE_2D); + _mesa_Disable(GL_TEXTURE_3D); + if (ctx->Extensions.ARB_texture_cube_map) + _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); + if (ctx->Extensions.NV_texture_rectangle) + _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); + if (ctx->Extensions.MESA_texture_array) { + _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); + _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); + } + } + } + + r200_meta_set_passthrough_transform(rmesa); + + for (i = 0; i < 4; i++) { + color[i][0] = ctx->Color.ClearColor[0]; + color[i][1] = ctx->Color.ClearColor[1]; + color[i][2] = ctx->Color.ClearColor[2]; + color[i][3] = ctx->Color.ClearColor[3]; } - - if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) - && (flags & RADEON_CLEAR_FASTZ)) { + /* convert clear Z from [0,1] to NDC coord in [-1,1] */ + dst_z = -1.0 + 2.0 * ctx->Depth.Clear; + + /* Prepare the vertices, which are the same regardless of which buffer we're + * drawing to. + */ + vertices[0][0] = fb->_Xmin; + vertices[0][1] = fb->_Ymin; + vertices[0][2] = dst_z; + vertices[1][0] = fb->_Xmax; + vertices[1][1] = fb->_Ymin; + vertices[1][2] = dst_z; + vertices[2][0] = fb->_Xmax; + vertices[2][1] = fb->_Ymax; + vertices[2][2] = dst_z; + vertices[3][0] = fb->_Xmin; + vertices[3][1] = fb->_Ymax; + vertices[3][2] = dst_z; + + _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); + _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); + _mesa_Enable(GL_COLOR_ARRAY); + _mesa_Enable(GL_VERTEX_ARRAY); + + while (mask != 0) { + GLuint this_mask = 0; + + if (mask & BUFFER_BIT_BACK_LEFT) + this_mask = BUFFER_BIT_BACK_LEFT; + else if (mask & BUFFER_BIT_FRONT_LEFT) + this_mask = BUFFER_BIT_FRONT_LEFT; + + /* Clear depth/stencil in the same pass as color. */ + this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); + + /* Select the current color buffer and use the color write mask if + * we have one, otherwise don't write any color channels. + */ + if (this_mask & BUFFER_BIT_FRONT_LEFT) + _mesa_DrawBuffer(GL_FRONT_LEFT); + else if (this_mask & BUFFER_BIT_BACK_LEFT) + _mesa_DrawBuffer(GL_BACK_LEFT); + else + _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); + + /* Control writing of the depth clear value to depth. */ + if (this_mask & BUFFER_BIT_DEPTH) { + _mesa_DepthFunc(GL_ALWAYS); + _mesa_Enable(GL_DEPTH_TEST); + } else { + _mesa_Disable(GL_DEPTH_TEST); + _mesa_DepthMask(GL_FALSE); + } + + /* Control writing of the stencil clear value to stencil. */ + if (this_mask & BUFFER_BIT_STENCIL) { + _mesa_Enable(GL_STENCIL_TEST); + _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); + _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, + ctx->Stencil.WriteMask[0]); + } else { + _mesa_Disable(GL_STENCIL_TEST); + } + + CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); + + mask &= ~this_mask; } -#endif + + r200_meta_restore_transform(rmesa); + + _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); + if (saved_fp_enable) + _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); + if (saved_vp_enable) + _mesa_Enable(GL_VERTEX_PROGRAM_ARB); + + if (saved_shader_program) + _mesa_UseProgramObjectARB(saved_shader_program); + + _mesa_PopClientAttrib(); + _mesa_PopAttrib(); +} + + +static void r200UserClear(GLcontext *ctx, GLuint mask) +{ + radeon_clear_tris(ctx, mask); } static void r200KernelClear(GLcontext *ctx, GLuint flags) @@ -218,6 +417,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) GLuint flags = 0; GLuint color_mask = 0; GLint ret; + GLuint orig_mask = mask; if ( R200_DEBUG & DEBUG_IOCTL ) { fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage); @@ -275,7 +475,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } if (rmesa->radeon.radeonScreen->kernel_mm) - r200UserClear(ctx, flags); + r200UserClear(ctx, orig_mask); else r200KernelClear(ctx, flags); -- cgit v1.2.3 From 0fc6c2644cf69fd1851c9387c83b0e43f820bdf2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Mar 2009 13:48:47 +1000 Subject: radeon: remove unused lines --- src/mesa/drivers/dri/radeon/radeon_texstate.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 42356cd37b8..06771a359b9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -718,18 +718,15 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri case 4: t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; - // pitch_val /= 4; break; case 3: default: t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter; -// pitch_val /= 4; break; case 2: t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format; t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; - pitch_val /= 2; break; } t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT) -- cgit v1.2.3 From 9c591c52c7a9a75fc1f5822ed2f5e7e82ab396a5 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 16 Mar 2009 11:33:14 +0100 Subject: radeon: Take the hardware lock for swaps and flips. Otherwise they fail with AIGLX at least. --- src/mesa/drivers/dri/radeon/radeon_common.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 99270c947f3..5ee8627bba7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -420,6 +420,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); } + LOCK_HARDWARE( rmesa ); nbox = dPriv->numClipRects; /* must be in locked region */ for ( i = 0 ; i < nbox ; ) { @@ -509,6 +510,8 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) psp = dPriv->driScreenPriv; + LOCK_HARDWARE( radeon ); + if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__, radeon->sarea->pfCurrentPage, radeon->sarea->pfState); -- cgit v1.2.3 From aa85973f95b8ccce1964c9bbbfb1e411c4b31cbd Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 16 Mar 2009 12:51:50 +0100 Subject: Fixup previous commit. radeonScheduleSwap() already takes the lock in the SwapBuffers case, only the CopySubBuffer case was missing it. --- src/mesa/drivers/dri/radeon/radeon_common.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 5ee8627bba7..1a5d0467d4c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -420,7 +420,6 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); } - LOCK_HARDWARE( rmesa ); nbox = dPriv->numClipRects; /* must be in locked region */ for ( i = 0 ; i < nbox ; ) { @@ -510,8 +509,6 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) psp = dPriv->driScreenPriv; - LOCK_HARDWARE( radeon ); - if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__, radeon->sarea->pfCurrentPage, radeon->sarea->pfState); @@ -605,6 +602,8 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, rect.x2 = rect.x1 + w; rect.y2 = rect.y1 + h; _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ + LOCK_HARDWARE( (radeonContextPtr) + dPriv->driContextPriv->driverPrivate ); radeonCopyBuffer(dPriv, &rect); } } else { -- cgit v1.2.3 From c0c06803fee4d5cd04da03f1984ae99e411e1588 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 19 Mar 2009 14:46:52 +1000 Subject: radeon: fix up locking like the intel driver for pageflip/swaps --- src/mesa/drivers/dri/radeon/radeon_common.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 1a5d0467d4c..5c34ca89fab 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -414,6 +414,8 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + LOCK_HARDWARE(rmesa); + rfb = dPriv->driverPrivate; if ( RADEON_DEBUG & DEBUG_IOCTL ) { @@ -486,8 +488,7 @@ static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_tar UNLOCK_HARDWARE(rmesa); driWaitForVBlank(dPriv, missed_target); - LOCK_HARDWARE(rmesa); - + return 0; } @@ -509,6 +510,8 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) psp = dPriv->driScreenPriv; + LOCK_HARDWARE(radeon); + if ( RADEON_DEBUG & DEBUG_IOCTL ) { fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__, radeon->sarea->pfCurrentPage, radeon->sarea->pfState); @@ -520,7 +523,7 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP ); - UNLOCK_HARDWARE( radeon ); + UNLOCK_HARDWARE(radeon); if ( ret ) { fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); @@ -602,8 +605,6 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, rect.x2 = rect.x1 + w; rect.y2 = rect.y1 + h; _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ - LOCK_HARDWARE( (radeonContextPtr) - dPriv->driContextPriv->driverPrivate ); radeonCopyBuffer(dPriv, &rect); } } else { -- cgit v1.2.3 From bdaa0341caffc353fd26bbd91865c2d86eed11c1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 19 Mar 2009 15:31:03 +1000 Subject: radeon/r200/r300: cleanup some of the renderbuffer code --- src/mesa/drivers/dri/r200/r200_texstate.c | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- src/mesa/drivers/dri/radeon/radeon_common.h | 19 +++- .../drivers/dri/radeon/radeon_common_context.c | 114 +++++++++------------ .../drivers/dri/radeon/radeon_common_context.h | 2 + src/mesa/drivers/dri/radeon/radeon_lock.c | 9 -- src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + src/mesa/drivers/dri/radeon/radeon_texstate.c | 2 +- 8 files changed, 71 insertions(+), 80 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 4937b0665d1..058e0ee5bec 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -806,7 +806,7 @@ void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = rfb->color_rb[0]; if (rb->bo == NULL) { /* Failed to BO for the buffer */ return; diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 2d7f392e7c8..14d470a11c0 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -425,7 +425,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = rfb->color_rb[0]; if (rb->bo == NULL) { /* Failed to BO for the buffer */ return; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index 95b718184b7..814da1b4f5b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -30,6 +30,23 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); void radeonReadBuffer( GLcontext *ctx, GLenum mode ); void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); +static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) +{ + struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb; + if (rrb && rrb->base.ClassID == RADEON_RB_CLASS) + return rrb; + else + return NULL; +} + +static inline struct radeon_renderbuffer *radeon_get_renderbuffer(struct gl_framebuffer *fb, int att_index) +{ + if (att_index >= 0) + return radeon_renderbuffer(fb->Attachment[att_index].Renderbuffer); + else + return NULL; +} + static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) { struct radeon_renderbuffer *rrb; @@ -47,7 +64,7 @@ static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPt rrb = rmesa->state.color.rrb; if (rmesa->radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT); } if (!rrb) return NULL; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index b63aba2f894..a818440faf8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -183,33 +183,33 @@ void radeonCleanupContext(radeonContextPtr radeon) _mesa_destroy_context(radeon->glCtx); rfb = (void*)radeon->dri.drawable->driverPrivate; - rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = rfb->color_rb[0]; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = rfb->color_rb[1]; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } rfb = (void*)radeon->dri.readable->driverPrivate; - rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = rfb->color_rb[0]; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rb = rfb->color_rb[1]; if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); if (rb && rb->bo) { radeon_bo_unref(rb->bo); rb->bo = NULL; @@ -391,6 +391,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) int i, count; struct radeon_framebuffer *draw; radeonContextPtr radeon; + char *regname; if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); @@ -399,15 +400,14 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) screen = context->driScreenPriv; radeon = (radeonContextPtr) context->driverPrivate; i = 0; - if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (draw->color_rb[0]) attachments[i++] = __DRI_BUFFER_FRONT_LEFT; - } - if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (draw->color_rb[1]) attachments[i++] = __DRI_BUFFER_BACK_LEFT; - } - if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH)) attachments[i++] = __DRI_BUFFER_DEPTH; - } + if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL)) + attachments[i++] = __DRI_BUFFER_STENCIL; buffers = (*screen->dri2.loader->getBuffers)(drawable, &drawable->w, @@ -436,64 +436,20 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) for (i = 0; i < count; i++) { switch (buffers[i].attachment) { case __DRI_BUFFER_FRONT_LEFT: - rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - if (rb->bo == NULL) { - fprintf(stderr, "failled to attach front %d\n", - buffers[i].name); - } + rb = draw->color_rb[0]; + regname = "dri2 front buffer"; break; case __DRI_BUFFER_BACK_LEFT: - rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); + rb = draw->color_rb[1]; + regname = "dri2 back buffer"; break; case __DRI_BUFFER_DEPTH: - rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); + rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); + regname = "dri2 depth buffer"; break; case __DRI_BUFFER_STENCIL: + rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); + regname = "dri2 stencil buffer"; break; case __DRI_BUFFER_ACCUM: default: @@ -502,8 +458,32 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) buffers[i].attachment); return; } + + if (rb == NULL) + continue; + + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + if (rb->bo == NULL) { + fprintf(stderr, "failed to attach %s %d\n", + regname, buffers[i].name); + + } } - radeon = (radeonContextPtr) context->driverPrivate; + driUpdateFramebufferSize(radeon->glCtx, drawable); } @@ -534,9 +514,9 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (driDrawPriv != driReadPriv) radeon_update_renderbuffers(driContextPriv, driReadPriv); radeon->state.color.rrb = - (void *)drfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT); radeon->state.depth.rrb = - (void *)drfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH); } else { radeon_make_renderbuffer_current(radeon, drfb); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 4aeb50fe68e..e5ada622b0f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -70,6 +70,8 @@ typedef struct radeon_context *radeonContextPtr; #include "tnl_dd/t_dd_vertex.h" #undef TAG +#define RADEON_RB_CLASS 0xdeadbeef + struct radeon_renderbuffer { struct gl_renderbuffer base; diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index fb9e5e025ea..e1bb2cd6e21 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -90,15 +90,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) rmesa->lost_context = GL_TRUE; } -static INLINE struct radeon_renderbuffer * -radeon_get_renderbuffer(struct gl_framebuffer *fb, int attIndex) -{ - if (attIndex >= 0) - return (struct radeon_renderbuffer *)fb->Attachment[attIndex].Renderbuffer; - else - return NULL; -} - void radeon_lock_hardware(radeonContextPtr radeon) { __DRIdrawable *dPriv = radeon->dri.drawable; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e90dffd7669..02101978ac4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1197,6 +1197,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) return NULL; _mesa_init_renderbuffer(&ret->base, 0); + ret->base.ClassID = RADEON_RB_CLASS; /* XXX format junk */ switch (format) { diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 06771a359b9..b9adab18d49 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -678,7 +678,7 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri radeon_bo_unref(rb->bo); rb->bo = NULL; } - rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rb = rfb->color_rb[0]; if (rb->bo == NULL) { /* Failed to BO for the buffer */ return; -- cgit v1.2.3 From fabce837f9740df2553b6cc0dd991b2cb8b8fc5b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 20 Mar 2009 18:23:38 +1000 Subject: radeon: initial couch code copy from radeon --- src/mesa/drivers/dri/r300/Makefile | 6 +- src/mesa/drivers/dri/radeon/radeon_common.h | 2 + src/mesa/drivers/dri/radeon/radeon_fbo.c | 193 ++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+), 2 deletions(-) create mode 100644 src/mesa/drivers/dri/radeon/radeon_fbo.c (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 497b1ec528f..0dff9a12731 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -31,7 +31,8 @@ RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_mipmap_tree.c \ - radeon_span.c + radeon_span.c \ + radeon_fbo.c DRIVER_SOURCES = \ radeon_screen.c \ @@ -96,7 +97,8 @@ COMMON_SYMLINKS = \ radeon_mipmap_tree.c \ radeon_mipmap_tree.h \ radeon_texture.c \ - radeon_texture.h + radeon_texture.h \ + radeon_fbo.c DRI_LIB_DEPS += $(RADEON_LDFLAGS) diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index 814da1b4f5b..d3eee7d8885 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -30,6 +30,8 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); void radeonReadBuffer( GLcontext *ctx, GLenum mode ); void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); +void radeon_fbo_init(struct radeon_context *radeon); + static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) { struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c new file mode 100644 index 00000000000..56e5cbcbc81 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -0,0 +1,193 @@ +/************************************************************************** + * + * Copyright 2008 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#include "main/imports.h" +#include "main/macros.h" +#include "main/mtypes.h" +#include "main/fbobject.h" +#include "main/framebuffer.h" +#include "main/renderbuffer.h" +#include "main/context.h" +#include "main/texformat.h" +#include "main/texrender.h" + +#include "radeon_common.h" + +static struct gl_framebuffer * +radeon_new_framebuffer(GLcontext *ctx, GLuint name) +{ + return _mesa_new_framebuffer(ctx, name); +} + +static void +radeon_delete_renderbuffer(struct gl_renderbuffer *rb) +{ + GET_CURRENT_CONTEXT(ctx); + struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); + + ASSERT(rrb); + + if (rrb && rrb->bo) { + radeon_bo_unref(rrb->bo); + } + + + _mesa_free(rrb); +} + +static void +radeon_resize_buffers(GLcontext *ctx, struct gl_framebuffer *fb, + GLuint width, GLuint height) +{ + +} + +static void * +radeon_get_pointer(GLcontext *ctx, struct gl_renderbuffer *rb, + GLint x, GLint y) +{ + return NULL; +} + +/** + * Called via glRenderbufferStorageEXT() to set the format and allocate + * storage for a user-created renderbuffer. + */ +static GLboolean +radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, + GLenum internalFormat, + GLuint width, GLuint height) +{ + struct radeon_context *radeon = RADEON_CONTEXT(ctx); + struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); + GLboolean software_buffer = GL_FALSE; + int cpp; + + ASSERT(rb->Name != 0); + + if (software_buffer) { + return _mesa_soft_renderbuffer_storage(ctx, rb, internalFormat, + width, height); + } + else { + /* TODO Alloc a BO */ + return GL_TRUE; + } + +} + +static struct gl_renderbuffer * +radeon_new_renderbuffer(GLcontext * ctx, GLuint name) +{ + struct radeon_renderbuffer *rrb; + + rrb = CALLOC_STRUCT(radeon_renderbuffer); + if (!rrb) + return NULL; + + _mesa_init_renderbuffer(&rrb->base, name); + rrb->base.ClassID = RADEON_RB_CLASS; + + rrb->base.Delete = radeon_delete_renderbuffer; + rrb->base.AllocStorage = radeon_alloc_renderbuffer_storage; + rrb->base.GetPointer = radeon_get_pointer; + + return &rrb->base; +} + +static void +radeon_bind_framebuffer(GLcontext * ctx, GLenum target, + struct gl_framebuffer *fb, struct gl_framebuffer *fbread) +{ + if (target == GL_FRAMEBUFFER_EXT || target == GL_DRAW_FRAMEBUFFER_EXT) { + radeon_draw_buffer(ctx, fb); + } + else { + /* don't need to do anything if target == GL_READ_FRAMEBUFFER_EXT */ + } +} + +static void +radeon_framebuffer_renderbuffer(GLcontext * ctx, + struct gl_framebuffer *fb, + GLenum attachment, struct gl_renderbuffer *rb) +{ + + radeonFlush(ctx); + + _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb); + radeon_draw_buffer(ctx, fb); +} + +static struct radeon_renderbuffer * +radeon_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage) +{ + +} +static void +radeon_render_texture(GLcontext * ctx, + struct gl_framebuffer *fb, + struct gl_renderbuffer_attachment *att) +{ + +} + +static void +radeon_finish_render_texture(GLcontext * ctx, + struct gl_renderbuffer_attachment *att) +{ + +} +static void +radeon_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) +{ +} + +static void +radeon_blit_framebuffer(GLcontext *ctx, + GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, + GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, + GLbitfield mask, GLenum filter) +{ +} + +void radeon_fbo_init(struct radeon_context *radeon) +{ + radeon->glCtx->Driver.NewFramebuffer = radeon_new_framebuffer; + radeon->glCtx->Driver.NewRenderbuffer = radeon_new_renderbuffer; + radeon->glCtx->Driver.BindFramebuffer = radeon_bind_framebuffer; + radeon->glCtx->Driver.FramebufferRenderbuffer = radeon_framebuffer_renderbuffer; + radeon->glCtx->Driver.RenderTexture = radeon_render_texture; + radeon->glCtx->Driver.FinishRenderTexture = radeon_finish_render_texture; + radeon->glCtx->Driver.ResizeBuffers = radeon_resize_buffers; + radeon->glCtx->Driver.ValidateFramebuffer = radeon_validate_framebuffer; + radeon->glCtx->Driver.BlitFramebuffer = radeon_blit_framebuffer; +} + + + -- cgit v1.2.3 From 230abc06f817b5d9868f7e6a094f56bb3294b476 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 20 Mar 2009 22:07:05 +1000 Subject: radeon: some more fbo work --- src/mesa/drivers/dri/radeon/radeon_common.h | 3 +- src/mesa/drivers/dri/radeon/radeon_fbo.c | 302 +++++++++++++++++++++++++++- src/mesa/drivers/dri/radeon/radeon_screen.c | 95 +-------- 3 files changed, 303 insertions(+), 97 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index d3eee7d8885..a3fea28a299 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -31,7 +31,8 @@ void radeonReadBuffer( GLcontext *ctx, GLenum mode ); void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); void radeon_fbo_init(struct radeon_context *radeon); - +struct gl_renderbuffer * +radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv); static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) { struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 56e5cbcbc81..649f88a061c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -38,6 +38,12 @@ #include "radeon_common.h" +#define FILE_DEBUG_FLAG DEBUG_TEXTURE +#define DBG(...) do { \ + if (RADEON_DEBUG & FILE_DEBUG_FLAG) \ + _mesa_printf(__VA_ARGS__); \ +} while(0) + static struct gl_framebuffer * radeon_new_framebuffer(GLcontext *ctx, GLuint name) { @@ -60,13 +66,6 @@ radeon_delete_renderbuffer(struct gl_renderbuffer *rb) _mesa_free(rrb); } -static void -radeon_resize_buffers(GLcontext *ctx, struct gl_framebuffer *fb, - GLuint width, GLuint height) -{ - -} - static void * radeon_get_pointer(GLcontext *ctx, struct gl_renderbuffer *rb, GLint x, GLint y) @@ -89,18 +88,236 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, int cpp; ASSERT(rb->Name != 0); + switch (internalFormat) { + case GL_R3_G3_B2: + case GL_RGB4: + case GL_RGB5: + rb->_ActualFormat = GL_RGB5; + rb->DataType = GL_UNSIGNED_BYTE; + rb->RedBits = 5; + rb->GreenBits = 6; + rb->BlueBits = 5; + cpp = 2; + break; + case GL_RGB: + case GL_RGB8: + case GL_RGB10: + case GL_RGB12: + case GL_RGB16: + rb->_ActualFormat = GL_RGB8; + rb->DataType = GL_UNSIGNED_BYTE; + rb->RedBits = 8; + rb->GreenBits = 8; + rb->BlueBits = 8; + rb->AlphaBits = 0; + cpp = 4; + break; + case GL_RGBA: + case GL_RGBA2: + case GL_RGBA4: + case GL_RGB5_A1: + case GL_RGBA8: + case GL_RGB10_A2: + case GL_RGBA12: + case GL_RGBA16: + rb->_ActualFormat = GL_RGBA8; + rb->DataType = GL_UNSIGNED_BYTE; + rb->RedBits = 8; + rb->GreenBits = 8; + rb->BlueBits = 8; + rb->AlphaBits = 8; + cpp = 4; + break; + case GL_STENCIL_INDEX: + case GL_STENCIL_INDEX1_EXT: + case GL_STENCIL_INDEX4_EXT: + case GL_STENCIL_INDEX8_EXT: + case GL_STENCIL_INDEX16_EXT: + /* alloc a depth+stencil buffer */ + rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rb->DataType = GL_UNSIGNED_INT_24_8_EXT; + rb->StencilBits = 8; + cpp = 4; + break; + case GL_DEPTH_COMPONENT16: + rb->_ActualFormat = GL_DEPTH_COMPONENT16; + rb->DataType = GL_UNSIGNED_SHORT; + rb->DepthBits = 16; + cpp = 2; + break; + case GL_DEPTH_COMPONENT: + case GL_DEPTH_COMPONENT24: + case GL_DEPTH_COMPONENT32: + rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rb->DataType = GL_UNSIGNED_INT_24_8_EXT; + rb->DepthBits = 24; + cpp = 4; + break; + case GL_DEPTH_STENCIL_EXT: + case GL_DEPTH24_STENCIL8_EXT: + rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rb->DataType = GL_UNSIGNED_INT_24_8_EXT; + rb->DepthBits = 24; + rb->StencilBits = 8; + cpp = 4; + break; + default: + _mesa_problem(ctx, + "Unexpected format in intel_alloc_renderbuffer_storage"); + return GL_FALSE; + } + radeonFlush(ctx); + + if (rrb->bo) + radeon_bo_unref(rrb->bo); + + if (software_buffer) { return _mesa_soft_renderbuffer_storage(ctx, rb, internalFormat, width, height); } else { /* TODO Alloc a BO */ + + // rrb->bo = radeon_bo_open(); + rb->Width = width; + rb->Height = height; return GL_TRUE; } } + +/** + * Called for each hardware renderbuffer when a _window_ is resized. + * Just update fields. + * Not used for user-created renderbuffers! + */ +static GLboolean +radeon_alloc_window_storage(GLcontext * ctx, struct gl_renderbuffer *rb, + GLenum internalFormat, GLuint width, GLuint height) +{ + ASSERT(rb->Name == 0); + rb->Width = width; + rb->Height = height; + rb->_ActualFormat = internalFormat; + + return GL_TRUE; +} + + +static void +radeon_resize_buffers(GLcontext *ctx, struct gl_framebuffer *fb, + GLuint width, GLuint height) +{ + struct radeon_framebuffer *radeon_fb = (struct radeon_framebuffer*)fb; + int i; + + _mesa_resize_framebuffer(ctx, fb, width, height); + + fb->Initialized = GL_TRUE; /* XXX remove someday */ + + if (fb->Name != 0) { + return; + } + + /* Make sure all window system renderbuffers are up to date */ + for (i = 0; i < 2; i++) { + struct gl_renderbuffer *rb = &radeon_fb->color_rb[i]->base; + + /* only resize if size is changing */ + if (rb && (rb->Width != width || rb->Height != height)) { + rb->AllocStorage(ctx, rb, rb->InternalFormat, width, height); + } + } +} + + +/** Dummy function for gl_renderbuffer::AllocStorage() */ +static GLboolean +radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb, + GLenum internalFormat, GLuint width, GLuint height) +{ + _mesa_problem(ctx, "radeon_op_alloc_storage should never be called."); + return GL_FALSE; +} + +struct gl_renderbuffer * +radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) +{ + struct radeon_renderbuffer *rrb; + + rrb = CALLOC_STRUCT(radeon_renderbuffer); + if (!rrb) + return NULL; + + _mesa_init_renderbuffer(&rrb->base, 0); + rrb->base.ClassID = RADEON_RB_CLASS; + + /* XXX format junk */ + switch (format) { + case GL_RGB5: + rrb->base._ActualFormat = GL_RGB5; + rrb->base._BaseFormat = GL_RGBA; + rrb->base.RedBits = 5; + rrb->base.GreenBits = 6; + rrb->base.BlueBits = 5; + rrb->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_RGBA8: + rrb->base._ActualFormat = GL_RGBA8; + rrb->base._BaseFormat = GL_RGBA; + rrb->base.RedBits = 8; + rrb->base.GreenBits = 8; + rrb->base.BlueBits = 8; + rrb->base.AlphaBits = 8; + rrb->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_STENCIL_INDEX8_EXT: + rrb->base._ActualFormat = GL_STENCIL_INDEX8_EXT; + rrb->base._BaseFormat = GL_STENCIL_INDEX; + rrb->base.StencilBits = 8; + rrb->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_DEPTH_COMPONENT16: + rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; + rrb->base._BaseFormat = GL_DEPTH_COMPONENT; + rrb->base.DepthBits = 16; + rrb->base.DataType = GL_UNSIGNED_SHORT; + break; + case GL_DEPTH_COMPONENT24: + rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rrb->base._BaseFormat = GL_DEPTH_COMPONENT; + rrb->base.DepthBits = 24; + rrb->base.DataType = GL_UNSIGNED_INT; + break; + case GL_DEPTH24_STENCIL8_EXT: + rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; + rrb->base.DepthBits = 24; + rrb->base.StencilBits = 8; + rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; + break; + default: + fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); + _mesa_delete_renderbuffer(&rrb->base); + return NULL; + } + + rrb->dPriv = driDrawPriv; + rrb->base.InternalFormat = format; + + rrb->base.Delete = radeon_delete_renderbuffer; + rrb->base.AllocStorage = radeon_alloc_window_storage; + rrb->base.GetPointer = radeon_get_pointer; + + radeonSetSpanFunctions(rrb); + + rrb->bo = NULL; + return &rrb->base; +} + static struct gl_renderbuffer * radeon_new_renderbuffer(GLcontext * ctx, GLuint name) { @@ -120,6 +337,7 @@ radeon_new_renderbuffer(GLcontext * ctx, GLuint name) return &rrb->base; } + static void radeon_bind_framebuffer(GLcontext * ctx, GLenum target, struct gl_framebuffer *fb, struct gl_framebuffer *fbread) @@ -144,10 +362,80 @@ radeon_framebuffer_renderbuffer(GLcontext * ctx, radeon_draw_buffer(ctx, fb); } + +static GLboolean +radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, + struct gl_texture_image *texImage) +{ + if (texImage->TexFormat == &_mesa_texformat_argb8888) { + rrb->base._ActualFormat = GL_RGBA8; + rrb->base._BaseFormat = GL_RGBA; + rrb->base.DataType = GL_UNSIGNED_BYTE; + DBG("Render to RGBA8 texture OK\n"); + } + else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + rrb->base._ActualFormat = GL_RGB5; + rrb->base._BaseFormat = GL_RGB; + rrb->base.DataType = GL_UNSIGNED_SHORT; + DBG("Render to RGB5 texture OK\n"); + } + else if (texImage->TexFormat == &_mesa_texformat_z16) { + rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; + rrb->base._BaseFormat = GL_DEPTH_COMPONENT; + rrb->base.DataType = GL_UNSIGNED_SHORT; + DBG("Render to DEPTH16 texture OK\n"); + } + else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; + rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; + DBG("Render to DEPTH_STENCIL texture OK\n"); + } + else { + DBG("Render to texture BAD FORMAT %d\n", + texImage->TexFormat->MesaFormat); + return GL_FALSE; + } + + rrb->base.InternalFormat = rrb->base._ActualFormat; + rrb->base.Width = texImage->Width; + rrb->base.Height = texImage->Height; + rrb->base.RedBits = texImage->TexFormat->RedBits; + rrb->base.GreenBits = texImage->TexFormat->GreenBits; + rrb->base.BlueBits = texImage->TexFormat->BlueBits; + rrb->base.AlphaBits = texImage->TexFormat->AlphaBits; + rrb->base.DepthBits = texImage->TexFormat->DepthBits; + + rrb->base.Delete = radeon_delete_renderbuffer; + rrb->base.AllocStorage = radeon_nop_alloc_storage; + + return GL_TRUE; +} + + static struct radeon_renderbuffer * radeon_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage) { + const GLuint name = ~0; /* not significant, but distinct for debugging */ + struct radeon_renderbuffer *rrb; + + /* make an radeon_renderbuffer to wrap the texture image */ + rrb = CALLOC_STRUCT(radeon_renderbuffer); + if (!rrb) { + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glFramebufferTexture"); + return NULL; + } + _mesa_init_renderbuffer(&rrb->base, name); + rrb->base.ClassID = RADEON_RB_CLASS; + + if (!radeon_update_wrapper(ctx, rrb, texImage)) { + _mesa_free(rrb); + return NULL; + } + + return rrb; + } static void radeon_render_texture(GLcontext * ctx, diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 1d4f008cbc7..a14a0c3cb28 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1175,90 +1175,7 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) return GL_TRUE; } -static GLboolean -radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, - GLenum intFormat, GLuint w, GLuint h) -{ - rb->Width = w; - rb->Height = h; - rb->_ActualFormat = intFormat; - - return GL_TRUE; -} - - -static struct radeon_renderbuffer * -radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) -{ - struct radeon_renderbuffer *ret; - ret = CALLOC_STRUCT(radeon_renderbuffer); - if (!ret) - return NULL; - - _mesa_init_renderbuffer(&ret->base, 0); - ret->base.ClassID = RADEON_RB_CLASS; - - /* XXX format junk */ - switch (format) { - case GL_RGB5: - ret->base._ActualFormat = GL_RGB5; - ret->base._BaseFormat = GL_RGBA; - ret->base.RedBits = 5; - ret->base.GreenBits = 6; - ret->base.BlueBits = 5; - ret->base.DataType = GL_UNSIGNED_BYTE; - break; - case GL_RGBA8: - ret->base._ActualFormat = GL_RGBA8; - ret->base._BaseFormat = GL_RGBA; - ret->base.RedBits = 8; - ret->base.GreenBits = 8; - ret->base.BlueBits = 8; - ret->base.AlphaBits = 8; - ret->base.DataType = GL_UNSIGNED_BYTE; - break; - case GL_STENCIL_INDEX8_EXT: - ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; - ret->base._BaseFormat = GL_STENCIL_INDEX; - ret->base.StencilBits = 8; - ret->base.DataType = GL_UNSIGNED_BYTE; - break; - case GL_DEPTH_COMPONENT16: - ret->base._ActualFormat = GL_DEPTH_COMPONENT16; - ret->base._BaseFormat = GL_DEPTH_COMPONENT; - ret->base.DepthBits = 16; - ret->base.DataType = GL_UNSIGNED_SHORT; - break; - case GL_DEPTH_COMPONENT24: - ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - ret->base._BaseFormat = GL_DEPTH_COMPONENT; - ret->base.DepthBits = 24; - ret->base.DataType = GL_UNSIGNED_INT; - break; - case GL_DEPTH24_STENCIL8_EXT: - ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; - ret->base.DepthBits = 24; - ret->base.StencilBits = 8; - ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; - break; - default: - fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); - _mesa_delete_renderbuffer(&ret->base); - return NULL; - } - - ret->dPriv = driDrawPriv; - ret->base.InternalFormat = format; - - ret->base.AllocStorage = radeon_alloc_window_storage; - - radeonSetSpanFunctions(ret); - - ret->bo = NULL; - return ret; -} /** * Create the Mesa framebuffer and renderbuffers for a given window/drawable. @@ -1298,29 +1215,29 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, depthFormat = GL_DEPTH_COMPONENT24; /* front color renderbuffer */ - rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); + rfb->color_rb[0] = radeon_renderbuffer(radeon_create_renderbuffer(rgbFormat, driDrawPriv)); _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); rfb->color_rb[0]->has_surface = 1; /* back color renderbuffer */ if (mesaVis->doubleBufferMode) { - rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); + rfb->color_rb[1] = radeon_renderbuffer(radeon_create_renderbuffer(rgbFormat, driDrawPriv)); _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); rfb->color_rb[1]->has_surface = 1; } /* depth renderbuffer */ if (depthFormat != GL_NONE) { - struct radeon_renderbuffer *depth = - radeon_create_renderbuffer(depthFormat, driDrawPriv); + struct radeon_renderbuffer *depth = radeon_renderbuffer( + radeon_create_renderbuffer(depthFormat, driDrawPriv)); _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); depth->has_surface = screen->depthHasSurface; } /* stencil renderbuffer */ if (mesaVis->stencilBits > 0 && !swStencil) { - struct radeon_renderbuffer *stencil = - radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); + struct radeon_renderbuffer *stencil = radeon_renderbuffer( + radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv)); _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base); stencil->has_surface = screen->depthHasSurface; } -- cgit v1.2.3 From e3faf5b51d76975fb54a2b4eada3e0042a182096 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 20 Mar 2009 22:15:22 +1000 Subject: r300: enable FBO for a test --- src/mesa/drivers/dri/r300/r300_context.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5bae37e1b1e..9c9a270558f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -82,14 +82,17 @@ int hw_tcl_on = 1; #define need_GL_EXT_blend_equation_separate #define need_GL_EXT_blend_func_separate #define need_GL_EXT_blend_minmax +#define need_GL_EXT_framebuffer_object #define need_GL_EXT_fog_coord #define need_GL_EXT_gpu_program_parameters #define need_GL_EXT_secondary_color #define need_GL_EXT_stencil_two_side #define need_GL_ATI_separate_stencil #define need_GL_NV_vertex_program + #include "extension_helper.h" + const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ {"GL_ARB_depth_texture", NULL}, @@ -110,6 +113,7 @@ const struct dri_extension card_extensions[] = { {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions}, {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions}, {"GL_EXT_blend_subtract", NULL}, + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions}, {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions}, -- cgit v1.2.3 From ba890ad35b3ff52603665bdb576f9efcbb3a108a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 20 Mar 2009 22:29:15 +1000 Subject: more fbo fillin --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 649f88a061c..01978ec2933 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -37,6 +37,7 @@ #include "main/texrender.h" #include "radeon_common.h" +#include "radeon_mipmap_tree.h" #define FILE_DEBUG_FLAG DEBUG_TEXTURE #define DBG(...) do { \ @@ -442,7 +443,74 @@ radeon_render_texture(GLcontext * ctx, struct gl_framebuffer *fb, struct gl_renderbuffer_attachment *att) { + struct gl_texture_image *newImage + = att->Texture->Image[att->CubeMapFace][att->TextureLevel]; + struct radeon_renderbuffer *rrb = radeon_renderbuffer(att->Renderbuffer); + radeon_texture_image *radeon_image; + GLuint imageOffset; + + (void) fb; + + ASSERT(newImage); + + if (newImage->Border != 0) { + /* Fallback on drawing to a texture with a border, which won't have a + * miptree. + */ + _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); + _mesa_render_texture(ctx, fb, att); + return; + } + else if (!rrb) { + rrb = radeon_wrap_texture(ctx, newImage); + if (rrb) { + /* bind the wrapper to the attachment point */ + _mesa_reference_renderbuffer(&att->Renderbuffer, &rrb->base); + } + else { + /* fallback to software rendering */ + _mesa_render_texture(ctx, fb, att); + return; + } + } + + if (!radeon_update_wrapper(ctx, rrb, newImage)) { + _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); + _mesa_render_texture(ctx, fb, att); + return; + } + DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", + _glthread_GetID(), + att->Texture->Name, newImage->Width, newImage->Height, + rrb->base.RefCount); + + /* point the renderbufer's region to the texture image region */ + radeon_image = (radeon_texture_image *)newImage; + if (rrb->bo != radeon_image->mt->bo) { + if (rrb->bo) + radeon_bo_unref(rrb->bo); + rrb->bo = radeon_image->mt->bo; + radeon_bo_ref(rrb->bo); + } + +#if 0 + /* compute offset of the particular 2D image within the texture region */ + imageOffset = radeon_miptree_image_offset(radeon_image->mt, + att->CubeMapFace, + att->TextureLevel); + + if (att->Texture->Target == GL_TEXTURE_3D) { + const GLuint *offsets = radeon_miptree_depth_offsets(radeon_image->mt, + att->TextureLevel); + imageOffset += offsets[att->Zoffset]; + } + + /* store that offset in the region */ + radeon_image->mt->draw_offset = imageOffset; +#endif + /* update drawing region, etc */ + radeon_draw_buffer(ctx, fb); } static void -- cgit v1.2.3 From 22443d5cc036ddebfd97ade17711cd1306721754 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 20 Mar 2009 22:34:30 +1000 Subject: r300: init fbos --- src/mesa/drivers/dri/r300/r300_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 9c9a270558f..cf0557d6a27 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -439,7 +439,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, r300->disable_lowimpact_fallback = driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); - + radeon_fbo_init(&r300->radeon); radeonInitSpanFuncs( ctx ); r300InitCmdBuf(r300); r300InitState(r300); -- cgit v1.2.3 From ffde891a0390a915716087ca7d99b3ddf7f1ef89 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 14:31:14 +1000 Subject: radeon: fix up span function setting --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 12 ++++++++---- src/mesa/drivers/dri/radeon/radeon_span.c | 8 +++++++- src/mesa/drivers/dri/radeon/radeon_span.h | 1 - 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 01978ec2933..0e3ac9c4057 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -180,7 +180,14 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, } else { /* TODO Alloc a BO */ - + uint32_t size = width * height * cpp; + + rrb->bo = radeon_bo_open(radeon->radeonScreen->bom, + 0, + size, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); // rrb->bo = radeon_bo_open(); rb->Width = width; rb->Height = height; @@ -313,8 +320,6 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) rrb->base.AllocStorage = radeon_alloc_window_storage; rrb->base.GetPointer = radeon_get_pointer; - radeonSetSpanFunctions(rrb); - rrb->bo = NULL; return &rrb->base; } @@ -338,7 +343,6 @@ radeon_new_renderbuffer(GLcontext * ctx, GLuint name) return &rrb->base; } - static void radeon_bind_framebuffer(GLcontext * ctx, GLenum target, struct gl_framebuffer *fb, struct gl_framebuffer *fbread) diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 49ec2c378e5..503a1e0b869 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -49,6 +49,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DBG 0 +static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); + static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { @@ -366,6 +368,8 @@ static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) __FUNCTION__, r); } } + + radeonSetSpanFunctions(rrb); } static void unmap_buffer(struct gl_renderbuffer *rb) @@ -375,6 +379,8 @@ static void unmap_buffer(struct gl_renderbuffer *rb) if (rrb->bo) { radeon_bo_unmap(rrb->bo); } + rb->GetRow = NULL; + rb->PutRow = NULL; } static void radeonSpanRenderStart(GLcontext * ctx) @@ -446,7 +452,7 @@ void radeonInitSpanFuncs(GLcontext * ctx) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) +static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { if (rrb->base.InternalFormat == GL_RGB5) { radeonInitPointers_RGB565(&rrb->base); diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h index dd44ab517af..ea6a2e7fb4e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h @@ -44,5 +44,4 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void radeonInitSpanFuncs(GLcontext * ctx); -extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); #endif -- cgit v1.2.3 From fbda2ad4457cf47494ae3eee28d417afb262c5c2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 15:05:34 +1000 Subject: r300: hw clear buffer 0 hopefully --- src/mesa/drivers/dri/r300/r300_ioctl.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index d1cf57959fa..d4acbd7e997 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -583,6 +583,11 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) mask &= ~BUFFER_BIT_STENCIL; } + if (mask & BUFFER_BIT_COLOR0) { + flags |= BUFFER_BIT_COLOR0; + mask &= ~BUFFER_BIT_COLOR0; + } + if (mask) { if (RADEON_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "%s: swrast clear, mask: %x\n", @@ -596,6 +601,12 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) r300EmitClearState(ctx); rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (flags & BUFFER_BIT_COLOR0) { + rrb = (void *)rfb->base.Attachment[BUFFER_COLOR0].Renderbuffer; + r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); + bits = 0; + } + if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); -- cgit v1.2.3 From 9368dcb426a97e8fb628b712ac74c7c808a79b9b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 16:08:20 +1000 Subject: radeon: fixup span code for FBOs --- src/mesa/drivers/dri/radeon/radeon_common.c | 8 ++--- src/mesa/drivers/dri/radeon/radeon_common.h | 4 +++ src/mesa/drivers/dri/radeon/radeon_span.c | 47 ++++++++++++++++++++++------- 3 files changed, 44 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 840233ff896..4d7f91e356c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -132,10 +132,10 @@ void radeonRecalcScissorRects(radeonContextPtr radeon) } } -static void radeon_get_cliprects(radeonContextPtr radeon, - struct drm_clip_rect **cliprects, - unsigned int *num_cliprects, - int *x_off, int *y_off) +void radeon_get_cliprects(radeonContextPtr radeon, + struct drm_clip_rect **cliprects, + unsigned int *num_cliprects, + int *x_off, int *y_off) { __DRIdrawablePrivate *dPriv = radeon->dri.drawable; struct radeon_framebuffer *rfb = dPriv->driverPrivate; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index a3fea28a299..528ea9dce4a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -29,6 +29,10 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb); void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); void radeonReadBuffer( GLcontext *ctx, GLenum mode ); void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); +void radeon_get_cliprects(radeonContextPtr radeon, + struct drm_clip_rect **cliprects, + unsigned int *num_cliprects, + int *x_off, int *y_off); void radeon_fbo_init(struct radeon_context *radeon); struct gl_renderbuffer * diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 503a1e0b869..7ad170a939c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -197,25 +197,48 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, * information. */ #define LOCAL_VARS \ + struct radeon_context *radeon = RADEON_CONTEXT(ctx); \ struct radeon_renderbuffer *rrb = (void *) rb; \ - const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ + const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \ + const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\ + unsigned int num_cliprects; \ + struct drm_clip_rect *cliprects; \ + int x_off, y_off; \ GLuint p; \ - (void)p; + (void)p; \ + radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off); #define LOCAL_DEPTH_VARS \ + struct radeon_context *radeon = RADEON_CONTEXT(ctx); \ struct radeon_renderbuffer *rrb = (void *) rb; \ - const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; + const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \ + const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\ + unsigned int num_cliprects; \ + struct drm_clip_rect *cliprects; \ + int x_off, y_off; \ + radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off); #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS -#define Y_FLIP(Y) (bottom - (Y)) +#define Y_FLIP(_y) ((_y) * yScale + yBias) #define HW_LOCK() #define HW_UNLOCK() +/* XXX FBO: this is identical to the macro in spantmp2.h except we get + * the cliprect info from the context, not the driDrawable. + * Move this into spantmp2.h someday. + */ +#define HW_CLIPLOOP() \ + do { \ + int _nc = num_cliprects; \ + while ( _nc-- ) { \ + int minx = cliprects[_nc].x1 - x_off; \ + int miny = cliprects[_nc].y1 - y_off; \ + int maxx = cliprects[_nc].x2 - x_off; \ + int maxy = cliprects[_nc].y2 - y_off; + /* ================================================================ * Color buffer */ @@ -454,15 +477,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) */ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (rrb->base.InternalFormat == GL_RGB5) { + if (rrb->base._ActualFormat == GL_RGB5) { radeonInitPointers_RGB565(&rrb->base); - } else if (rrb->base.InternalFormat == GL_RGBA8) { + } else if (rrb->base._ActualFormat == GL_RGB8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base._ActualFormat == GL_RGBA8) { radeonInitPointers_ARGB8888(&rrb->base); - } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT16) { radeonInitDepthPointers_z16(&rrb->base); - } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) { radeonInitDepthPointers_z24_s8(&rrb->base); - } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + } else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) { radeonInitStencilPointers_z24_s8(&rrb->base); } } -- cgit v1.2.3 From 86dcbb545729627e09115cc0d416af697f2c2832 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 16:51:46 +1000 Subject: radeon: dPriv handling is now in cliprects code --- src/mesa/drivers/dri/radeon/radeon_span.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 7ad170a939c..cb20379c91f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -55,15 +55,11 @@ static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { GLubyte *ptr = rrb->bo->ptr; - const __DRIdrawablePrivate *dPriv = rrb->dPriv; uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; GLint offset; GLint nmacroblkpl; GLint nmicroblkpl; - x += dPriv->x; - y += dPriv->y; - if (rrb->has_surface || !(rrb->bo->flags & mask)) { offset = x * rrb->cpp + y * rrb->pitch; } else { @@ -99,15 +95,11 @@ static GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { GLubyte *ptr = rrb->bo->ptr; - const __DRIdrawablePrivate *dPriv = rrb->dPriv; uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; GLint offset; GLint nmacroblkpl; GLint nmicroblkpl; - x += dPriv->x; - y += dPriv->y; - if (rrb->has_surface || !(rrb->bo->flags & mask)) { offset = x * rrb->cpp + y * rrb->pitch; } else { @@ -143,7 +135,6 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, GLint x, GLint y) { GLubyte *ptr = rrb->bo->ptr; - const __DRIdrawablePrivate *dPriv = rrb->dPriv; uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; GLint offset; GLint microblkxs; @@ -151,9 +142,6 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, GLint nmacroblkpl; GLint nmicroblkpl; - x += dPriv->x; - y += dPriv->y; - if (rrb->has_surface || !(rrb->bo->flags & mask)) { offset = x * rrb->cpp + y * rrb->pitch; } else { -- cgit v1.2.3 From e795bd3c9090443a5e52ff79356c253022de8538 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 18:05:54 +1000 Subject: radeon/fbo: add x_off and y_off in correct places --- src/mesa/drivers/dri/radeon/radeon_span.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index cb20379c91f..71aeb5ea6bd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -270,10 +270,10 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, #define VALUE_TYPE GLushort #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)radeon_ptr(rrb, _x, _y) = d + *(GLushort *)radeon_ptr(rrb, _x + x_off, _y + y_off) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)radeon_ptr(rrb, _x, _y) + d = *(GLushort *)radeon_ptr(rrb, _x + x_off, _y + y_off) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -288,7 +288,7 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ GLuint tmp = *_ptr; \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ @@ -297,7 +297,7 @@ do { \ #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \_ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ @@ -308,11 +308,11 @@ do { \ #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0xffffff00) >> 8; \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint*)(radeon_ptr32(rrb, _x, _y )) & 0x00ffffff; + d = *(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off )) & 0x00ffffff; #endif /* fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\ @@ -330,7 +330,7 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + x_off, _y + y_off); \ GLuint tmp = *_ptr; \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ @@ -339,7 +339,7 @@ do { \ #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ + GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + x_off, _y + y_off); \ GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ @@ -350,14 +350,14 @@ do { \ #ifdef COMPILE_R300 #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ GLuint tmp = *_ptr; \ d = tmp & 0x000000ff; \ } while (0) #else #define READ_STENCIL( d, _x, _y ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ GLuint tmp = *_ptr; \ d = (tmp & 0xff000000) >> 24; \ } while (0) -- cgit v1.2.3 From 8a600836766716df684f2ab1eeafdcbec4b0f019 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 18:07:33 +1000 Subject: radeon: add cpp/pitch to rrb --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 0e3ac9c4057..110afb74507 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -182,6 +182,8 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, /* TODO Alloc a BO */ uint32_t size = width * height * cpp; + rrb->pitch = width * cpp; + rrb->cpp = cpp; rrb->bo = radeon_bo_open(radeon->radeonScreen->bom, 0, size, -- cgit v1.2.3 From 56c5df33de1e34b606bb771db27742af78be30f3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 18:16:02 +1000 Subject: radeon: fixup last missing x_off/y_off --- src/mesa/drivers/dri/radeon/radeon_span.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 71aeb5ea6bd..096ac2f8949 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -238,7 +238,7 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) +#define GET_PTR(X,Y) radeon_ptr16(rrb, (X) + x_off, (Y) + y_off) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -248,7 +248,7 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) +#define GET_PTR(X,Y) radeon_ptr32(rrb, (X) + x_off, (Y) + y_off) #include "spantmp2.h" /* ================================================================ @@ -297,8 +297,8 @@ do { \ #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \_ - GLuint tmp = *_ptr; \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ *_ptr = tmp; \ -- cgit v1.2.3 From 8ab7c77dc2a29ad3edc1fab4e0c9fb01a15665fa Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 18:16:21 +1000 Subject: radeon: align FBO pitch --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 110afb74507..2125a651833 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -179,10 +179,13 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, width, height); } else { - /* TODO Alloc a BO */ uint32_t size = width * height * cpp; + uint32_t pitch = ((cpp * width + 63) & ~63) / cpp; - rrb->pitch = width * cpp; + fprintf(stderr,"Allocating %d x %d radeon RBO (pitch %d)\n", width, + height, pitch); + + rrb->pitch = pitch * cpp; rrb->cpp = cpp; rrb->bo = radeon_bo_open(radeon->radeonScreen->bom, 0, @@ -190,7 +193,6 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, 0, RADEON_GEM_DOMAIN_VRAM, 0); - // rrb->bo = radeon_bo_open(); rb->Width = width; rb->Height = height; return GL_TRUE; -- cgit v1.2.3 From 712478cfdd4a6ec0d0a85d1eaf5907e937c5dfe5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 22:27:01 +1100 Subject: r300: fix viewport inversion for FBOs --- src/mesa/drivers/dri/r300/r300_state.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index f423029ee68..02f29a0a2f1 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -933,11 +933,21 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; + const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); + GLfloat y_scale, y_bias; + + if (render_to_fbo) { + y_scale = 1.0; + y_bias = 0; + } else { + y_scale = -1.0; + y_bias = yoffset; + } GLfloat sx = v[MAT_SX]; GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; - GLfloat sy = -v[MAT_SY]; - GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; + GLfloat sy = v[MAT_SY] * y_scale; + GLfloat ty = (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y; GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; -- cgit v1.2.3 From 6c48c93a5358ab04d6779afb14203bd1680a37a0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 22:36:18 +1100 Subject: radeon/r200: add fbo state changes --- src/mesa/drivers/dri/r200/r200_state.c | 14 ++++++++++++-- src/mesa/drivers/dri/radeon/radeon_state.c | 14 ++++++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 5eb61c8804f..74824b8d249 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1610,11 +1610,21 @@ void r200UpdateWindow( GLcontext *ctx ) GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; + const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); + GLfloat y_scale, y_bias; + + if (render_to_fbo) { + y_scale = 1.0; + y_bias = 0; + } else { + y_scale = -1.0; + y_bias = yoffset; + } float_ui32_type sx = { v[MAT_SX] }; float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; - float_ui32_type sy = { - v[MAT_SY] }; - float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; + float_ui32_type sy = { v[MAT_SY] * y_scale }; + float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y }; float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 42b65cbee65..635fe43ce4b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1390,11 +1390,21 @@ void radeonUpdateWindow( GLcontext *ctx ) GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; + const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); + GLfloat y_scale, y_bias; + + if (render_to_fbo) { + y_scale = 1.0; + y_bias = 0; + } else { + y_scale = -1.0; + y_bias = yoffset; + } float_ui32_type sx = { v[MAT_SX] }; float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; - float_ui32_type sy = { - v[MAT_SY] }; - float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; + float_ui32_type sy = { v[MAT_SY] * y_scale }; + float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y }; float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; -- cgit v1.2.3 From 98f1b1e6f99c690645c3cb5093005fc41f436225 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 22:38:11 +1100 Subject: radeon/r200: add fbo init --- src/mesa/drivers/dri/r200/r200_context.c | 1 + src/mesa/drivers/dri/radeon/radeon_context.c | 1 + 2 files changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 10a6362afd2..e29a7a73a54 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -453,6 +453,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, #endif /* plug in a few more device driver functions */ /* XXX these should really go right after _mesa_init_driver_functions() */ + radeon_fbo_init(&r300->radeon); radeonInitSpanFuncs( ctx ); r200InitPixelFuncs( ctx ); r200InitTnlFuncs( ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 47ebe41c6d5..933c76daab2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -352,6 +352,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); /* XXX these should really go right after _mesa_init_driver_functions() */ + radeon_fbo_init(&r300->radeon); radeonInitSpanFuncs( ctx ); radeonInitIoctlFuncs( ctx ); radeonInitStateFuncs( ctx ); -- cgit v1.2.3 From 218083c542138dc2271b83450f556a6146144f75 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 22:38:28 +1100 Subject: radeon: dri2 is hooked up elsewhere now --- src/mesa/drivers/dri/radeon/radeon_common.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index 528ea9dce4a..c97492d742a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -67,12 +67,8 @@ static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPt static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) { struct radeon_renderbuffer *rrb; - struct radeon_framebuffer *rfb = rmesa->dri.drawable->driverPrivate; rrb = rmesa->state.color.rrb; - if (rmesa->radeonScreen->driScreen->dri2.enabled) { - rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT); - } if (!rrb) return NULL; return rrb; -- cgit v1.2.3 From 9f7a03d94586091ef6c38187e0c8a4564143fd7a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 21:41:25 +1000 Subject: radeon: add xRGB span functions same as ARGB need to add a parameter to get ptr32 --- src/mesa/drivers/dri/radeon/radeon_span.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 096ac2f8949..768a51b51d5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -241,6 +241,16 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, #define GET_PTR(X,Y) radeon_ptr16(rrb, (X) + x_off, (Y) + y_off) #include "spantmp2.h" +/* 32 bit, xRGB8888 color spanline and pixel functions + */ +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV + +#define TAG(x) radeon##x##_xRGB8888 +#define TAG2(x,y) radeon##x##_xRGB8888##y +#define GET_PTR(X,Y) radeon_ptr32(rrb, (X) + x_off, (Y) + y_off) +#include "spantmp2.h" + /* 32 bit, ARGB8888 color spanline and pixel functions */ #define SPANTMP_PIXEL_FMT GL_BGRA @@ -468,7 +478,7 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) if (rrb->base._ActualFormat == GL_RGB5) { radeonInitPointers_RGB565(&rrb->base); } else if (rrb->base._ActualFormat == GL_RGB8) { - radeonInitPointers_ARGB8888(&rrb->base); + radeonInitPointers_xRGB8888(&rrb->base); } else if (rrb->base._ActualFormat == GL_RGBA8) { radeonInitPointers_ARGB8888(&rrb->base); } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT16) { -- cgit v1.2.3 From 4bd5ee2d9741a74e28f29e48a4c144206f78fd41 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 22:35:01 +1000 Subject: radeon/r200: oops make correct fbo init calls --- src/mesa/drivers/dri/r200/r200_context.c | 2 +- src/mesa/drivers/dri/radeon/radeon_context.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index e29a7a73a54..57852a0a67b 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -453,7 +453,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, #endif /* plug in a few more device driver functions */ /* XXX these should really go right after _mesa_init_driver_functions() */ - radeon_fbo_init(&r300->radeon); + radeon_fbo_init(&r200->radeon); radeonInitSpanFuncs( ctx ); r200InitPixelFuncs( ctx ); r200InitTnlFuncs( ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 933c76daab2..3f69de8d274 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -352,7 +352,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); /* XXX these should really go right after _mesa_init_driver_functions() */ - radeon_fbo_init(&r300->radeon); + radeon_fbo_init(&rmesa->radeon); radeonInitSpanFuncs( ctx ); radeonInitIoctlFuncs( ctx ); radeonInitStateFuncs( ctx ); -- cgit v1.2.3 From c73f4fdb65a6bae4b02348d73f2efdb8f2c5583a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 21 Mar 2009 22:41:42 +1000 Subject: r200: fix for sure --- src/mesa/drivers/dri/r200/r200_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 57852a0a67b..bf06c419d16 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -453,7 +453,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, #endif /* plug in a few more device driver functions */ /* XXX these should really go right after _mesa_init_driver_functions() */ - radeon_fbo_init(&r200->radeon); + radeon_fbo_init(&rmesa->radeon); radeonInitSpanFuncs( ctx ); r200InitPixelFuncs( ctx ); r200InitTnlFuncs( ctx ); -- cgit v1.2.3 From 0968512f8f4abc5bce84c200bd99f8a522d56122 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 22 Mar 2009 11:56:41 +1000 Subject: radeon: add miptree offset functions --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 26 ++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h | 6 ++++-- 2 files changed, 30 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 3203ee1cba7..228629e3c45 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -358,3 +358,29 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, texImage->Width, texImage->Height, texImage->Depth, texImage->TexFormat->TexelBytes, t->tile_bits, compressed); } + +/* Although we use the image_offset[] array to store relative offsets + * to cube faces, Mesa doesn't know anything about this and expects + * each cube face to be treated as a separate image. + * + * These functions present that view to mesa: + */ +const GLuint * +radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level) +{ + static const GLuint zero = 0; + if (mt->target != GL_TEXTURE_3D || mt->faces == 1) + return &zero; + else + return mt->levels[level].faces[0].offset; +} + +GLuint +radeon_miptree_image_offset(radeon_mipmap_tree *mt, + GLuint face, GLuint level) +{ + if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) + return (mt->levels[level].faces[face].offset); + else + return mt->levels[level].faces[0].offset; +} diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h index 43dfa48aa71..d9ad5ad39a3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h @@ -92,6 +92,8 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj); void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, struct gl_texture_image *texImage, GLuint face, GLuint level); - - +GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt, + GLuint face, GLuint level); +const GLuint * +radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level); #endif /* __RADEON_MIPMAP_TREE_H_ */ -- cgit v1.2.3 From 06cb6f7aa799e25b4a53f8c547a8f4ca909fe245 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 22 Mar 2009 11:57:03 +1000 Subject: radeon: use mipmap fns in FBO code --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 2125a651833..a55a563340b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -502,7 +502,6 @@ radeon_render_texture(GLcontext * ctx, radeon_bo_ref(rrb->bo); } -#if 0 /* compute offset of the particular 2D image within the texture region */ imageOffset = radeon_miptree_image_offset(radeon_image->mt, att->CubeMapFace, @@ -515,8 +514,8 @@ radeon_render_texture(GLcontext * ctx, } /* store that offset in the region */ - radeon_image->mt->draw_offset = imageOffset; -#endif + //TODO radeon_image->mt->draw_offset = imageOffset; + /* update drawing region, etc */ radeon_draw_buffer(ctx, fb); } -- cgit v1.2.3 From 4a2cb696cc3b9e151ea902fc976ee025fb614309 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 22 Mar 2009 12:03:24 +1000 Subject: radeon/r200/r300: add support for new tfp interface also fixup old interface, gets rid of white boxes in compiz --- src/mesa/drivers/dri/r200/r200_tex.h | 2 ++ src/mesa/drivers/dri/r200/r200_texstate.c | 19 ++++++++++++++++--- src/mesa/drivers/dri/r300/r300_tex.h | 3 +++ src/mesa/drivers/dri/r300/r300_texstate.c | 18 ++++++++++++++---- src/mesa/drivers/dri/radeon/radeon_screen.c | 3 +++ src/mesa/drivers/dri/radeon/radeon_tex.h | 3 +++ src/mesa/drivers/dri/radeon/radeon_texstate.c | 20 ++++++++++++++++---- 7 files changed, 57 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_tex.h b/src/mesa/drivers/dri/r200/r200_tex.h index 886682b36b7..e122de6e5ed 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.h +++ b/src/mesa/drivers/dri/r200/r200_tex.h @@ -36,6 +36,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define __R200_TEX_H__ extern void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); +extern void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, + __DRIdrawable *dPriv); extern void r200SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index e9cee1a637d..2212fe64a6d 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -765,7 +765,8 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, } } -void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, + __DRIdrawable *dPriv) { struct gl_texture_unit *texUnit; struct gl_texture_object *texObj; @@ -777,8 +778,11 @@ void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) struct radeon_framebuffer *rfb; radeonTexObjPtr t; uint32_t pitch_val; + uint32_t internalFormat, type, format; - target = GL_TEXTURE_RECTANGLE_ARB; + type = GL_BGRA; + format = GL_UNSIGNED_BYTE; + internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4); radeon = pDRICtx->driverPrivate; rmesa = pDRICtx->driverPrivate; @@ -832,7 +836,9 @@ void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); - texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, + internalFormat, + type, format); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; @@ -868,6 +874,13 @@ void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) return; } + +void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + r200SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); +} + + #define REF_COLOR 1 #define REF_ALPHA 2 diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h index baad3fe6c06..8a653ea2d11 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ b/src/mesa/drivers/dri/r300/r300_tex.h @@ -40,6 +40,9 @@ extern void r300SetDepthTexMode(struct gl_texture_object *tObj); extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); +extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, + GLint format, __DRIdrawable *dPriv); + extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 14d470a11c0..d16cf688ed5 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -384,7 +384,7 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, t->pp_txpitch |= pitch_val; } -void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv) { struct gl_texture_unit *texUnit; struct gl_texture_object *texObj; @@ -396,8 +396,11 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) struct radeon_framebuffer *rfb; radeonTexObjPtr t; uint32_t pitch_val; + uint32_t internalFormat, type, format; - target = GL_TEXTURE_RECTANGLE_ARB; + type = GL_BGRA; + format = GL_UNSIGNED_BYTE; + internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4); radeon = pDRICtx->driverPrivate; rmesa = pDRICtx->driverPrivate; @@ -448,10 +451,12 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) radeon_miptree_unreference(rImage->mt); rImage->mt = NULL; } - fprintf(stderr,"settexbuf %dx%d@%d\n", rb->width, rb->height, rb->cpp); + fprintf(stderr,"settexbuf %dx%d@%d targ %x format %x\n", rb->width, rb->height, rb->cpp, target, format); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); - texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, + internalFormat, + type, format); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; @@ -495,3 +500,8 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) _mesa_unlock_texture(radeon->glCtx, texObj); return; } + +void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + r300SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); +} diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 1d4f008cbc7..bbcf19cceef 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -339,6 +339,7 @@ static const __DRItexOffsetExtension radeonTexOffsetExtension = { static const __DRItexBufferExtension radeonTexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, radeonSetTexBuffer, + radeonSetTexBuffer2, }; #endif @@ -358,6 +359,7 @@ static const __DRItexOffsetExtension r200texOffsetExtension = { static const __DRItexBufferExtension r200TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, r200SetTexBuffer, + r200SetTexBuffer2, }; #endif @@ -370,6 +372,7 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { static const __DRItexBufferExtension r300TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, r300SetTexBuffer, + r300SetTexBuffer2, }; #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h index 4c2fba44894..8d8afb43436 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h @@ -42,6 +42,9 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, GLuint pitch); extern void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); +externvoid radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, + __DRIdrawable *dPriv); + extern void radeonUpdateTextureState( GLcontext *ctx ); extern int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 0ece1acbeb2..78e2a08559b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -637,7 +637,8 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, } } -void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, + __DRIdrawable *dPriv) { struct gl_texture_unit *texUnit; struct gl_texture_object *texObj; @@ -649,8 +650,11 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri struct radeon_framebuffer *rfb; radeonTexObjPtr t; uint32_t pitch_val; + uint32_t internalFormat, type, format; - target = GL_TEXTURE_RECTANGLE_ARB; + type = GL_BGRA; + format = GL_UNSIGNED_BYTE; + internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4); radeon = pDRICtx->driverPrivate; rmesa = pDRICtx->driverPrivate; @@ -701,10 +705,11 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri radeon_miptree_unreference(rImage->mt); rImage->mt = NULL; } - fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); - texImage->TexFormat = &_mesa_texformat_rgba8888_rev; + texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, + internalFormat, + type, format); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; @@ -740,6 +745,13 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri return; } + +void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + radeonSetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); +} + + #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \ RADEON_MIN_FILTER_MASK | \ RADEON_MAG_FILTER_MASK | \ -- cgit v1.2.3 From c607a664dd005c001afda1fff1a68d41925fa86e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 22 Mar 2009 19:11:46 +1000 Subject: radeon fbo: add draw offset calcs --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 3 ++- src/mesa/drivers/dri/radeon/radeon_common.c | 3 +++ src/mesa/drivers/dri/radeon/radeon_common_context.h | 2 ++ src/mesa/drivers/dri/radeon/radeon_fbo.c | 9 +++++++-- 4 files changed, 14 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 2c6618fc608..d85f106c112 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -213,6 +213,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; + uint32_t offset = r300->radeon.state.color.draw_offset; rrb = radeon_get_colorbuffer(&r300->radeon); if (!rrb || !rrb->bo) { @@ -231,7 +232,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); OUT_BATCH(cbpitch); END_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 4d7f91e356c..4fd54c06c3a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -619,6 +619,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL, *rrbColor = NULL; + uint32_t offset = 0; if (!fb) { @@ -667,6 +668,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) /* user FBO in theory */ struct radeon_renderbuffer *rrb; rrb = (void *)fb->_ColorDrawBuffers[0]; + offset = rrb->draw_offset; rrbColor = rrb; radeon->constant_cliprect = GL_TRUE; } @@ -737,6 +739,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) radeon->state.depth.rrb = rrbDepth; radeon->state.color.rrb = rrbColor; + radeon->state.color.draw_offset = offset; /* update viewport since it depends on window size */ if (ctx->Driver.Viewport) { diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index e5ada622b0f..612cc97f255 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -82,6 +82,7 @@ struct radeon_renderbuffer unsigned int width; unsigned int height; + uint32_t draw_offset; /* FBO */ /* boo Xorg 6.8.2 compat */ int has_surface; @@ -117,6 +118,7 @@ struct radeon_colorbuffer_state { GLuint clear; int roundEnable; struct radeon_renderbuffer *rrb; + uint32_t draw_offset; /* offset into color renderbuffer - FBOs */ }; struct radeon_depthbuffer_state { diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index a55a563340b..7342f2295ea 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -377,24 +377,28 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, struct gl_texture_image *texImage) { if (texImage->TexFormat == &_mesa_texformat_argb8888) { + rrb->cpp = 4; rrb->base._ActualFormat = GL_RGBA8; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5; rrb->base._BaseFormat = GL_RGB; rrb->base.DataType = GL_UNSIGNED_SHORT; DBG("Render to RGB5 texture OK\n"); } else if (texImage->TexFormat == &_mesa_texformat_z16) { + rrb->cpp = 2; rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; rrb->base._BaseFormat = GL_DEPTH_COMPONENT; rrb->base.DataType = GL_UNSIGNED_SHORT; DBG("Render to DEPTH16 texture OK\n"); } else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + rrb->cpp = 4; rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; @@ -406,6 +410,7 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, return GL_FALSE; } + rrb->pitch = texImage->Width * rrb->cpp; rrb->base.InternalFormat = rrb->base._ActualFormat; rrb->base.Width = texImage->Width; rrb->base.Height = texImage->Height; @@ -488,7 +493,7 @@ radeon_render_texture(GLcontext * ctx, return; } - DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", + fprintf(stderr,"Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", _glthread_GetID(), att->Texture->Name, newImage->Width, newImage->Height, rrb->base.RefCount); @@ -514,7 +519,7 @@ radeon_render_texture(GLcontext * ctx, } /* store that offset in the region */ - //TODO radeon_image->mt->draw_offset = imageOffset; + rrb->draw_offset = imageOffset; /* update drawing region, etc */ radeon_draw_buffer(ctx, fb); -- cgit v1.2.3 From 8c7e30fb950c83f5e9e29e60735e999ac608145a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Mar 2009 18:27:49 +1000 Subject: raedon/r200/r300: mega-FBO commits. Re work depth issues. Do a lot more FBO abstactions fixup depth/stencil buffer interactions --- src/mesa/drivers/dri/r200/r200_context.c | 10 + src/mesa/drivers/dri/r200/r200_context.h | 15 -- src/mesa/drivers/dri/r200/r200_ioctl.c | 230 +--------------- src/mesa/drivers/dri/r200/r200_state.c | 31 ++- src/mesa/drivers/dri/r200/r200_state_init.c | 6 - src/mesa/drivers/dri/r300/r300_context.c | 9 +- src/mesa/drivers/dri/r300/r300_ioctl.c | 139 ++++++---- src/mesa/drivers/dri/r300/r300_state.c | 31 +-- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 5 +- src/mesa/drivers/dri/radeon/radeon_common.c | 297 +++++++++++++++++++-- src/mesa/drivers/dri/radeon/radeon_common.h | 19 +- .../drivers/dri/radeon/radeon_common_context.c | 49 +++- .../drivers/dri/radeon/radeon_common_context.h | 22 +- src/mesa/drivers/dri/radeon/radeon_context.c | 9 + src/mesa/drivers/dri/radeon/radeon_context.h | 14 - src/mesa/drivers/dri/radeon/radeon_fbo.c | 27 +- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 217 +-------------- src/mesa/drivers/dri/radeon/radeon_screen.c | 40 +-- src/mesa/drivers/dri/radeon/radeon_span.c | 83 +++--- src/mesa/drivers/dri/radeon/radeon_state.c | 31 ++- src/mesa/drivers/dri/radeon/radeon_state_init.c | 6 - 21 files changed, 605 insertions(+), 685 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index bf06c419d16..6fd0575898f 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -72,6 +72,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_EXT_blend_func_separate #define need_GL_NV_vertex_program #define need_GL_ARB_point_parameters +#define need_GL_EXT_framebuffer_object #include "extension_helper.h" #define DRIVER_DATE "20060602" @@ -124,6 +125,7 @@ const struct dri_extension card_extensions[] = { "GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions }, { "GL_EXT_blend_subtract", NULL }, { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, + { "GL_EXT_packed_depth_stencil", NULL}, { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions }, { "GL_EXT_stencil_wrap", NULL }, { "GL_EXT_texture_edge_clamp", NULL }, @@ -165,6 +167,11 @@ const struct dri_extension point_extensions[] = { { NULL, NULL } }; +const struct dri_extension mm_extensions[] = { + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, + { NULL, NULL } +}; + extern const struct tnl_pipeline_stage _r200_render_stage; extern const struct tnl_pipeline_stage _r200_tcl_stage; @@ -418,6 +425,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, _math_matrix_set_identity( &rmesa->tmpmat ); driInitExtensions( ctx, card_extensions, GL_TRUE ); + + if (rmesa->radeon.radeonScreen->kernel_mm) + driInitExtensions(ctx, mm_extensions, GL_FALSE); if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { /* yuv textures don't work with some chips - R200 / rv280 okay so far others get the bit ordering right but don't actually do YUV-RGB conversion */ diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index f7bad2a2414..fcbe725d6fc 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -621,21 +621,6 @@ struct r200_context { GLboolean texmicrotile; struct ati_fragment_shader *afs_loaded; - - struct { - struct gl_fragment_program *bitmap_fp; - struct gl_vertex_program *passthrough_vp; - - struct gl_fragment_program *saved_fp; - GLboolean saved_fp_enable; - struct gl_vertex_program *saved_vp; - GLboolean saved_vp_enable; - - GLint saved_vp_x, saved_vp_y; - GLsizei saved_vp_width, saved_vp_height; - GLenum saved_matrix_mode; - } meta; - }; #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 96ed49665b2..ccb56202f6d 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -41,19 +41,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" -#include "main/blend.h" -#include "main/bufferobj.h" -#include "main/buffers.h" -#include "main/depth.h" -#include "main/shaders.h" -#include "main/texstate.h" -#include "main/varray.h" -#include "glapi/dispatch.h" -#include "swrast/swrast.h" -#include "main/stencil.h" -#include "main/matrix.h" -#include "main/attrib.h" -#include "main/enable.h" + #include "radeon_common.h" #include "radeon_lock.h" @@ -70,217 +58,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 -static void -r200_meta_set_passthrough_transform(r200ContextPtr r200) -{ - GLcontext *ctx = r200->radeon.glCtx; - - r200->meta.saved_vp_x = ctx->Viewport.X; - r200->meta.saved_vp_y = ctx->Viewport.Y; - r200->meta.saved_vp_width = ctx->Viewport.Width; - r200->meta.saved_vp_height = ctx->Viewport.Height; - r200->meta.saved_matrix_mode = ctx->Transform.MatrixMode; - - _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); - - _mesa_MatrixMode(GL_PROJECTION); - _mesa_PushMatrix(); - _mesa_LoadIdentity(); - _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); - - _mesa_MatrixMode(GL_MODELVIEW); - _mesa_PushMatrix(); - _mesa_LoadIdentity(); -} - -static void -r200_meta_restore_transform(r200ContextPtr r200) -{ - _mesa_MatrixMode(GL_PROJECTION); - _mesa_PopMatrix(); - _mesa_MatrixMode(GL_MODELVIEW); - _mesa_PopMatrix(); - - _mesa_MatrixMode(r200->meta.saved_matrix_mode); - - _mesa_Viewport(r200->meta.saved_vp_x, r200->meta.saved_vp_y, - r200->meta.saved_vp_width, r200->meta.saved_vp_height); -} - -/** - * Perform glClear where mask contains only color, depth, and/or stencil. - * - * The implementation is based on calling into Mesa to set GL state and - * performing normal triangle rendering. The intent of this path is to - * have as generic a path as possible, so that any driver could make use of - * it. - */ -static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLfloat vertices[4][3]; - GLfloat color[4][4]; - GLfloat dst_z; - struct gl_framebuffer *fb = ctx->DrawBuffer; - int i; - GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; - GLboolean saved_shader_program = 0; - unsigned int saved_active_texture; - - assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | - BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); - - _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | - GL_CURRENT_BIT | - GL_DEPTH_BUFFER_BIT | - GL_ENABLE_BIT | - GL_STENCIL_BUFFER_BIT | - GL_TRANSFORM_BIT | - GL_CURRENT_BIT); - _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); - saved_active_texture = ctx->Texture.CurrentUnit; - - /* Disable existing GL state we don't want to apply to a clear. */ - _mesa_Disable(GL_ALPHA_TEST); - _mesa_Disable(GL_BLEND); - _mesa_Disable(GL_CULL_FACE); - _mesa_Disable(GL_FOG); - _mesa_Disable(GL_POLYGON_SMOOTH); - _mesa_Disable(GL_POLYGON_STIPPLE); - _mesa_Disable(GL_POLYGON_OFFSET_FILL); - _mesa_Disable(GL_LIGHTING); - _mesa_Disable(GL_CLIP_PLANE0); - _mesa_Disable(GL_CLIP_PLANE1); - _mesa_Disable(GL_CLIP_PLANE2); - _mesa_Disable(GL_CLIP_PLANE3); - _mesa_Disable(GL_CLIP_PLANE4); - _mesa_Disable(GL_CLIP_PLANE5); - if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { - saved_fp_enable = GL_TRUE; - _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); - } - if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { - saved_vp_enable = GL_TRUE; - _mesa_Disable(GL_VERTEX_PROGRAM_ARB); - } - if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { - saved_shader_program = ctx->Shader.CurrentProgram->Name; - _mesa_UseProgramObjectARB(0); - } - - if (ctx->Texture._EnabledUnits != 0) { - int i; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - _mesa_ActiveTextureARB(GL_TEXTURE0 + i); - _mesa_Disable(GL_TEXTURE_1D); - _mesa_Disable(GL_TEXTURE_2D); - _mesa_Disable(GL_TEXTURE_3D); - if (ctx->Extensions.ARB_texture_cube_map) - _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); - if (ctx->Extensions.NV_texture_rectangle) - _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); - if (ctx->Extensions.MESA_texture_array) { - _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); - _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); - } - } - } - - r200_meta_set_passthrough_transform(rmesa); - - for (i = 0; i < 4; i++) { - color[i][0] = ctx->Color.ClearColor[0]; - color[i][1] = ctx->Color.ClearColor[1]; - color[i][2] = ctx->Color.ClearColor[2]; - color[i][3] = ctx->Color.ClearColor[3]; - } - - /* convert clear Z from [0,1] to NDC coord in [-1,1] */ - dst_z = -1.0 + 2.0 * ctx->Depth.Clear; - - /* Prepare the vertices, which are the same regardless of which buffer we're - * drawing to. - */ - vertices[0][0] = fb->_Xmin; - vertices[0][1] = fb->_Ymin; - vertices[0][2] = dst_z; - vertices[1][0] = fb->_Xmax; - vertices[1][1] = fb->_Ymin; - vertices[1][2] = dst_z; - vertices[2][0] = fb->_Xmax; - vertices[2][1] = fb->_Ymax; - vertices[2][2] = dst_z; - vertices[3][0] = fb->_Xmin; - vertices[3][1] = fb->_Ymax; - vertices[3][2] = dst_z; - - _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); - _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); - _mesa_Enable(GL_COLOR_ARRAY); - _mesa_Enable(GL_VERTEX_ARRAY); - - while (mask != 0) { - GLuint this_mask = 0; - - if (mask & BUFFER_BIT_BACK_LEFT) - this_mask = BUFFER_BIT_BACK_LEFT; - else if (mask & BUFFER_BIT_FRONT_LEFT) - this_mask = BUFFER_BIT_FRONT_LEFT; - - /* Clear depth/stencil in the same pass as color. */ - this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); - - /* Select the current color buffer and use the color write mask if - * we have one, otherwise don't write any color channels. - */ - if (this_mask & BUFFER_BIT_FRONT_LEFT) - _mesa_DrawBuffer(GL_FRONT_LEFT); - else if (this_mask & BUFFER_BIT_BACK_LEFT) - _mesa_DrawBuffer(GL_BACK_LEFT); - else - _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); - - /* Control writing of the depth clear value to depth. */ - if (this_mask & BUFFER_BIT_DEPTH) { - _mesa_DepthFunc(GL_ALWAYS); - _mesa_Enable(GL_DEPTH_TEST); - } else { - _mesa_Disable(GL_DEPTH_TEST); - _mesa_DepthMask(GL_FALSE); - } - - /* Control writing of the stencil clear value to stencil. */ - if (this_mask & BUFFER_BIT_STENCIL) { - _mesa_Enable(GL_STENCIL_TEST); - _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); - _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, - ctx->Stencil.WriteMask[0]); - } else { - _mesa_Disable(GL_STENCIL_TEST); - } - - CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); - - mask &= ~this_mask; - } - - r200_meta_restore_transform(rmesa); - - _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); - if (saved_fp_enable) - _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); - if (saved_vp_enable) - _mesa_Enable(GL_VERTEX_PROGRAM_ARB); - - if (saved_shader_program) - _mesa_UseProgramObjectARB(saved_shader_program); - - _mesa_PopClientAttrib(); - _mesa_PopAttrib(); -} - - static void r200UserClear(GLcontext *ctx, GLuint mask) { radeon_clear_tris(ctx, mask); @@ -449,7 +226,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) mask &= ~BUFFER_BIT_DEPTH; } - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { + if ( (mask & BUFFER_BIT_STENCIL) ) { flags |= RADEON_STENCIL; mask &= ~BUFFER_BIT_STENCIL; } @@ -467,8 +244,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) flags |= RADEON_USE_COMP_ZBUF; /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->radeon.state.stencil.hwBuffer) || - ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && + if (!((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { flags |= RADEON_CLEAR_FASTZ; } diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 74824b8d249..ca4dee8a5bc 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -740,7 +740,8 @@ static void r200PolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - float_ui32_type constant = { units * rmesa->radeon.state.depth.scale }; + const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; + float_ui32_type constant = { units * depthScale }; float_ui32_type factoru = { factor }; /* factor *= 2; */ @@ -1611,6 +1612,7 @@ void r200UpdateWindow( GLcontext *ctx ) GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); + const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; GLfloat y_scale, y_bias; if (render_to_fbo) { @@ -1625,8 +1627,8 @@ void r200UpdateWindow( GLcontext *ctx ) float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; float_ui32_type sy = { v[MAT_SY] * y_scale }; float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y }; - float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; - float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; + float_ui32_type sz = { v[MAT_SZ] * depthScale }; + float_ui32_type tz = { v[MAT_TZ] * depthScale }; R200_STATECHANGE( rmesa, vpt ); @@ -2014,15 +2016,24 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) break; case GL_STENCIL_TEST: - if ( rmesa->radeon.state.stencil.hwBuffer ) { - R200_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; + { + GLboolean hw_stencil = GL_FALSE; + if (ctx->DrawBuffer) { + struct radeon_renderbuffer *rrbStencil + = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); + hw_stencil = (rrbStencil && rrbStencil->bo); + } + + if (hw_stencil) { + R200_STATECHANGE( rmesa, ctx ); + if ( state ) { + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; + } else { + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE; + } } else { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE; + FALLBACK( rmesa, R200_FALLBACK_STENCIL, state ); } - } else { - FALLBACK( rmesa, R200_FALLBACK_STENCIL, state ); } break; diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index a71f33ca3bb..30326c29601 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -674,21 +674,15 @@ void r200InitState( r200ContextPtr rmesa ) switch ( ctx->Visual.depthBits ) { case 16: rmesa->radeon.state.depth.clear = 0x0000ffff; - rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: default: rmesa->radeon.state.depth.clear = 0x00ffffff; - rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; rmesa->radeon.state.stencil.clear = 0xffff0000; break; } - /* Only have hw stencil when depth buffer is 24 bits deep */ - rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24 ); - rmesa->radeon.Fallback = 0; rmesa->radeon.hw.max_state_size = 0; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index cf0557d6a27..c6bd69ed146 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -113,7 +113,7 @@ const struct dri_extension card_extensions[] = { {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions}, {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions}, {"GL_EXT_blend_subtract", NULL}, - { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, + {"GL_EXT_packed_depth_stencil", NULL}, {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions}, {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions}, @@ -141,6 +141,11 @@ const struct dri_extension card_extensions[] = { }; +const struct dri_extension mm_extensions[] = { + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, + { NULL, NULL } +}; + /** * The GL 2.0 functions are needed to make display lists work with * functions added by GL_ATI_separate_stencil. @@ -421,6 +426,8 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; driInitExtensions(ctx, card_extensions, GL_TRUE); + if (r300->radeon.radeonScreen->kernel_mm) + driInitExtensions(ctx, mm_extensions, GL_FALSE); if (driQueryOptionb (&r300->radeon.optionCache, "disable_stencil_two_side")) diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index d4acbd7e997..71661eef19c 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -66,6 +66,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define CLEARBUFFER_DEPTH 0x2 #define CLEARBUFFER_STENCIL 0x4 +static void r300EmitClearState(GLcontext * ctx); + +static void r300UserClear(GLcontext *ctx, GLuint mask) +{ + radeon_clear_tris(ctx, mask); +} + static void r300ClearBuffer(r300ContextPtr r300, int flags, struct radeon_renderbuffer *rrb, struct radeon_renderbuffer *rrbd) @@ -534,6 +541,47 @@ static void r300EmitClearState(GLcontext * ctx) } } +static void r300KernelClear(GLcontext *ctx, GLuint flags) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; + struct radeon_renderbuffer *rrb; + struct radeon_renderbuffer *rrbd; + int bits = 0; + + /* Make sure it fits there. */ + rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); + if (flags || bits) + r300EmitClearState(ctx); + rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); + if (rrbd && (flags & BUFFER_BIT_DEPTH)) + bits |= CLEARBUFFER_DEPTH; + + if (flags & BUFFER_BIT_COLOR0) { + rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0); + r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); + bits = 0; + } + + if (flags & BUFFER_BIT_FRONT_LEFT) { + rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT); + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); + bits = 0; + } + + if (flags & BUFFER_BIT_BACK_LEFT) { + rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT); + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); + bits = 0; + } + + if (bits) + r300ClearBuffer(r300, bits, NULL, rrbd); + + COMMIT_BATCH(); +} + /** * Buffer clear */ @@ -541,16 +589,15 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) { r300ContextPtr r300 = R300_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; - struct radeon_framebuffer *rfb = dPriv->driverPrivate; - struct radeon_renderbuffer *rrb; - struct radeon_renderbuffer *rrbd; - int flags = 0; - int bits = 0; + const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask); + GLbitfield swrast_mask = 0, tri_mask = 0; + int i; + struct gl_framebuffer *fb = ctx->DrawBuffer; if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r300Clear\n"); - { + if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { LOCK_HARDWARE(&r300->radeon); UNLOCK_HARDWARE(&r300->radeon); if (dPriv->numClipRects == 0) @@ -563,68 +610,52 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) */ R300_NEWPRIM(r300); - if (mask & BUFFER_BIT_FRONT_LEFT) { - flags |= BUFFER_BIT_FRONT_LEFT; - mask &= ~BUFFER_BIT_FRONT_LEFT; - } + if (colorMask == ~0) + tri_mask |= (mask & BUFFER_BITS_COLOR); - if (mask & BUFFER_BIT_BACK_LEFT) { - flags |= BUFFER_BIT_BACK_LEFT; - mask &= ~BUFFER_BIT_BACK_LEFT; - } - if (mask & BUFFER_BIT_DEPTH) { - bits |= CLEARBUFFER_DEPTH; - mask &= ~BUFFER_BIT_DEPTH; + /* HW stencil */ + if (mask & BUFFER_BIT_STENCIL) { + tri_mask |= BUFFER_BIT_STENCIL; } - if ((mask & BUFFER_BIT_STENCIL) && r300->radeon.state.stencil.hwBuffer) { - bits |= CLEARBUFFER_STENCIL; - mask &= ~BUFFER_BIT_STENCIL; + /* HW depth */ + if (mask & BUFFER_BIT_DEPTH) { + tri_mask |= BUFFER_BIT_DEPTH; } - if (mask & BUFFER_BIT_COLOR0) { - flags |= BUFFER_BIT_COLOR0; - mask &= ~BUFFER_BIT_COLOR0; - } + /* If we're doing a tri pass for depth/stencil, include a likely color + * buffer with it. + */ - if (mask) { - if (RADEON_DEBUG & DEBUG_FALLBACKS) - fprintf(stderr, "%s: swrast clear, mask: %x\n", - __FUNCTION__, mask); - _swrast_Clear(ctx, mask); + for (i = 0; i < BUFFER_COUNT; i++) { + GLuint bufBit = 1 << i; + if ((tri_mask) & bufBit) { + if (!fb->Attachment[i].Renderbuffer->ClassID) { + tri_mask &= ~bufBit; + swrast_mask |= bufBit; + } + } } - /* Make sure it fits there. */ - rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); - if (flags || bits) - r300EmitClearState(ctx); - rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + /* SW fallback clearing */ + swrast_mask = mask & ~tri_mask; - if (flags & BUFFER_BIT_COLOR0) { - rrb = (void *)rfb->base.Attachment[BUFFER_COLOR0].Renderbuffer; - r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); - bits = 0; - } - - if (flags & BUFFER_BIT_FRONT_LEFT) { - rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); - bits = 0; + if (tri_mask) { + if (r300->radeon.radeonScreen->kernel_mm) + r300UserClear(ctx, tri_mask); + else + r300KernelClear(ctx, tri_mask); } - - if (flags & BUFFER_BIT_BACK_LEFT) { - rrb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); - bits = 0; + if (swrast_mask) { + if (RADEON_DEBUG & DEBUG_FALLBACKS) + fprintf(stderr, "%s: swrast clear, mask: %x\n", + __FUNCTION__, swrast_mask); + _swrast_Clear(ctx, swrast_mask); } - - if (bits) - r300ClearBuffer(r300, bits, NULL, rrbd); - - COMMIT_BATCH(); } + void r300InitIoctlFuncs(struct dd_function_table *functions) { functions->Clear = r300Clear; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 02f29a0a2f1..f49b43c2070 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -587,8 +587,14 @@ static void r300SetDepthState(GLcontext * ctx) static void r300SetStencilState(GLcontext * ctx, GLboolean state) { r300ContextPtr r300 = R300_CONTEXT(ctx); + GLboolean hw_stencil = GL_FALSE; + if (ctx->DrawBuffer) { + struct radeon_renderbuffer *rrbStencil + = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); + hw_stencil = (rrbStencil && rrbStencil->bo); + } - if (r300->radeon.state.stencil.hwBuffer) { + if (hw_stencil) { R300_STATECHANGE(r300, zs); if (state) { r300->hw.zs.cmd[R300_ZS_CNTL_0] |= @@ -933,7 +939,8 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; - const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); + const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; + const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0); GLfloat y_scale, y_bias; if (render_to_fbo) { @@ -948,8 +955,8 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; GLfloat sy = v[MAT_SY] * y_scale; GLfloat ty = (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y; - GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; - GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; + GLfloat sz = v[MAT_SZ] * depthScale; + GLfloat tz = v[MAT_TZ] * depthScale; R300_STATECHANGE(rmesa, vpt); @@ -2032,7 +2039,7 @@ static void r300ResetHwState(r300ContextPtr r300) fprintf(stderr, "%s\n", __FUNCTION__); radeon_firevertices(&r300->radeon); - r300UpdateWindow(ctx); + //r300UpdateWindow(ctx); r300ColorMask(ctx, ctx->Color.ColorMask[RCOMP], @@ -2207,16 +2214,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - rrb = r300->radeon.state.depth.rrb; - if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { - /* XXX: Turn off when clearing buffers ? */ - r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; - - if (ctx->Visual.depthBits == 24) - r300->hw.zb.cmd[R300_ZB_PITCH] |= - R300_DEPTHMICROTILE_TILED; - } - r300->hw.zb_depthclearvalue.cmd[1] = 0; r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE; @@ -2530,10 +2527,6 @@ void r300InitState(r300ContextPtr r300) GLcontext *ctx = r300->radeon.glCtx; GLuint depth_fmt; - /* Only have hw stencil when depth buffer is 24 bits deep */ - r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24); - memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); r300ResetHwState(r300); diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index f80f0f7b226..42607df9676 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -36,7 +36,10 @@ struct drm_radeon_gem_info { #endif - +uint32_t radeon_gem_bo_name(struct radeon_bo *dummy) +{ + return 0; +} static inline void *radeon_bo_manager_gem_ctor(int fd) { diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 4fd54c06c3a..9f646c4386c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -58,6 +58,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "main/blend.h" +#include "main/bufferobj.h" +#include "main/buffers.h" +#include "main/depth.h" +#include "main/shaders.h" +#include "main/texstate.h" +#include "main/varray.h" +#include "glapi/dispatch.h" +#include "swrast/swrast.h" +#include "main/stencil.h" +#include "main/matrix.h" +#include "main/attrib.h" +#include "main/enable.h" +#include "main/viewport.h" + #include "dri_util.h" #include "vblank.h" @@ -658,18 +673,20 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) /* none */ if (fb->Name == 0) { if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - rrbColor = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer); radeon->front_cliprects = GL_TRUE; } else { - rrbColor = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer); radeon->front_cliprects = GL_FALSE; } } else { /* user FBO in theory */ struct radeon_renderbuffer *rrb; - rrb = (void *)fb->_ColorDrawBuffers[0]; - offset = rrb->draw_offset; - rrbColor = rrb; + rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[0]); + if (rrb) { + offset = rrb->draw_offset; + rrbColor = rrb; + } radeon->constant_cliprect = GL_TRUE; } @@ -679,9 +696,8 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); - if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) { - rrbDepth = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; + rrbDepth = radeon_renderbuffer(fb->_DepthBuffer->Wrapped); if (rrbDepth && rrbDepth->bo) { radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); } else { @@ -692,16 +708,11 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) rrbDepth = NULL; } - /* TODO stencil things */ if (fb->_StencilBuffer && fb->_StencilBuffer->Wrapped) { - rrbStencil = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; + rrbStencil = radeon_renderbuffer(fb->_DepthBuffer->Wrapped); if (rrbStencil && rrbStencil->bo) { radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); /* need to re-compute stencil hw state */ - if (ctx->Driver.Enable != NULL) - ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); - else - ctx->NewState |= _NEW_STENCIL; if (!rrbDepth) rrbDepth = rrbStencil; } else { @@ -727,27 +738,28 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) * Update depth test state */ if (ctx->Driver.Enable) { - if (ctx->Depth.Test && fb->Visual.depthBits > 0) { - ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE); - } else { - ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE); - } + ctx->Driver.Enable(ctx, GL_DEPTH_TEST, + (ctx->Depth.Test && fb->Visual.depthBits > 0)); + ctx->Driver.Enable(ctx, GL_STENCIL_TEST, + (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0)); } else { - ctx->NewState |= _NEW_DEPTH; + ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL); } radeon->state.depth.rrb = rrbDepth; - radeon->state.color.rrb = rrbColor; radeon->state.color.draw_offset = offset; +#if 0 /* update viewport since it depends on window size */ if (ctx->Driver.Viewport) { ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, ctx->Viewport.Width, ctx->Viewport.Height); } else { - ctx->NewState |= _NEW_VIEWPORT; + } +#endif + ctx->NewState |= _NEW_VIEWPORT; /* Set state we know depends on drawable parameters: */ @@ -755,6 +767,19 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, ctx->Scissor.Width, ctx->Scissor.Height); radeon->NewGLState |= _NEW_SCISSOR; + + if (ctx->Driver.DepthRange) + ctx->Driver.DepthRange(ctx, + ctx->Viewport.Near, + ctx->Viewport.Far); + + /* Update culling direction which changes depending on the + * orientation of the buffer: + */ + if (ctx->Driver.FrontFace) + ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); + else + ctx->NewState |= _NEW_POLYGON; } /** @@ -802,10 +827,6 @@ void radeonUpdatePageFlipping(radeonContextPtr radeon) void radeon_window_moved(radeonContextPtr radeon) { - GLcontext *ctx = radeon->glCtx; - __DRIdrawablePrivate *dPriv = radeon->dri.drawable; - struct radeon_framebuffer *rfb = dPriv->driverPrivate; - if (!radeon->radeonScreen->driScreen->dri2.enabled) { radeonUpdatePageFlipping(radeon); } @@ -949,8 +970,14 @@ void radeonFinish(GLcontext * ctx) if (radeon->radeonScreen->kernel_mm) { for (i = 0; i < fb->_NumColorDrawBuffers; i++) { struct radeon_renderbuffer *rrb; - rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; - if (rrb->bo) + rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[i]); + if (rrb && rrb->bo) + radeon_bo_wait(rrb->bo); + } + { + struct radeon_renderbuffer *rrb; + rrb = radeon_get_depthbuffer(radeon); + if (rrb && rrb->bo) radeon_bo_wait(rrb->bo); } } else if (radeon->do_irqs) { @@ -1108,3 +1135,219 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n, +static void +radeon_meta_set_passthrough_transform(radeonContextPtr radeon) +{ + GLcontext *ctx = radeon->glCtx; + + radeon->meta.saved_vp_x = ctx->Viewport.X; + radeon->meta.saved_vp_y = ctx->Viewport.Y; + radeon->meta.saved_vp_width = ctx->Viewport.Width; + radeon->meta.saved_vp_height = ctx->Viewport.Height; + radeon->meta.saved_matrix_mode = ctx->Transform.MatrixMode; + + _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); + + _mesa_MatrixMode(GL_PROJECTION); + _mesa_PushMatrix(); + _mesa_LoadIdentity(); + _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); + + _mesa_MatrixMode(GL_MODELVIEW); + _mesa_PushMatrix(); + _mesa_LoadIdentity(); +} + +static void +radeon_meta_restore_transform(radeonContextPtr radeon) +{ + _mesa_MatrixMode(GL_PROJECTION); + _mesa_PopMatrix(); + _mesa_MatrixMode(GL_MODELVIEW); + _mesa_PopMatrix(); + + _mesa_MatrixMode(radeon->meta.saved_matrix_mode); + + _mesa_Viewport(radeon->meta.saved_vp_x, radeon->meta.saved_vp_y, + radeon->meta.saved_vp_width, radeon->meta.saved_vp_height); +} + + +/** + * Perform glClear where mask contains only color, depth, and/or stencil. + * + * The implementation is based on calling into Mesa to set GL state and + * performing normal triangle rendering. The intent of this path is to + * have as generic a path as possible, so that any driver could make use of + * it. + */ + + +void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + GLfloat vertices[4][3]; + GLfloat color[4][4]; + GLfloat dst_z; + struct gl_framebuffer *fb = ctx->DrawBuffer; + int i; + GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; + GLboolean saved_shader_program = 0; + unsigned int saved_active_texture; + + assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH | + BUFFER_BIT_STENCIL)) == 0); + + _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | + GL_CURRENT_BIT | + GL_DEPTH_BUFFER_BIT | + GL_ENABLE_BIT | + GL_STENCIL_BUFFER_BIT | + GL_TRANSFORM_BIT | + GL_CURRENT_BIT); + _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); + saved_active_texture = ctx->Texture.CurrentUnit; + + /* Disable existing GL state we don't want to apply to a clear. */ + _mesa_Disable(GL_ALPHA_TEST); + _mesa_Disable(GL_BLEND); + _mesa_Disable(GL_CULL_FACE); + _mesa_Disable(GL_FOG); + _mesa_Disable(GL_POLYGON_SMOOTH); + _mesa_Disable(GL_POLYGON_STIPPLE); + _mesa_Disable(GL_POLYGON_OFFSET_FILL); + _mesa_Disable(GL_LIGHTING); + _mesa_Disable(GL_CLIP_PLANE0); + _mesa_Disable(GL_CLIP_PLANE1); + _mesa_Disable(GL_CLIP_PLANE2); + _mesa_Disable(GL_CLIP_PLANE3); + _mesa_Disable(GL_CLIP_PLANE4); + _mesa_Disable(GL_CLIP_PLANE5); + if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { + saved_fp_enable = GL_TRUE; + _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); + } + if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { + saved_vp_enable = GL_TRUE; + _mesa_Disable(GL_VERTEX_PROGRAM_ARB); + } + if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { + saved_shader_program = ctx->Shader.CurrentProgram->Name; + _mesa_UseProgramObjectARB(0); + } + + if (ctx->Texture._EnabledUnits != 0) { + int i; + + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { + _mesa_ActiveTextureARB(GL_TEXTURE0 + i); + _mesa_Disable(GL_TEXTURE_1D); + _mesa_Disable(GL_TEXTURE_2D); + _mesa_Disable(GL_TEXTURE_3D); + if (ctx->Extensions.ARB_texture_cube_map) + _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); + if (ctx->Extensions.NV_texture_rectangle) + _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); + if (ctx->Extensions.MESA_texture_array) { + _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); + _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); + } + } + } + + radeon_meta_set_passthrough_transform(rmesa); + + for (i = 0; i < 4; i++) { + color[i][0] = ctx->Color.ClearColor[0]; + color[i][1] = ctx->Color.ClearColor[1]; + color[i][2] = ctx->Color.ClearColor[2]; + color[i][3] = ctx->Color.ClearColor[3]; + } + + /* convert clear Z from [0,1] to NDC coord in [-1,1] */ + + dst_z = -1.0 + 2.0 * ctx->Depth.Clear; + /* Prepare the vertices, which are the same regardless of which buffer we're + * drawing to. + */ + vertices[0][0] = fb->_Xmin; + vertices[0][1] = fb->_Ymin; + vertices[0][2] = dst_z; + vertices[1][0] = fb->_Xmax; + vertices[1][1] = fb->_Ymin; + vertices[1][2] = dst_z; + vertices[2][0] = fb->_Xmax; + vertices[2][1] = fb->_Ymax; + vertices[2][2] = dst_z; + vertices[3][0] = fb->_Xmin; + vertices[3][1] = fb->_Ymax; + vertices[3][2] = dst_z; + + _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); + _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); + _mesa_Enable(GL_COLOR_ARRAY); + _mesa_Enable(GL_VERTEX_ARRAY); + + while (mask != 0) { + GLuint this_mask = 0; + GLuint color_bit; + + color_bit = _mesa_ffs(mask & TRI_CLEAR_COLOR_BITS); + if (color_bit != 0) + this_mask |= (1 << (color_bit - 1)); + + /* Clear depth/stencil in the same pass as color. */ + this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); + + /* Select the current color buffer and use the color write mask if + * we have one, otherwise don't write any color channels. + */ + if (this_mask & BUFFER_BIT_FRONT_LEFT) + _mesa_DrawBuffer(GL_FRONT_LEFT); + else if (this_mask & BUFFER_BIT_BACK_LEFT) + _mesa_DrawBuffer(GL_BACK_LEFT); + else if (color_bit != 0) + _mesa_DrawBuffer(GL_COLOR_ATTACHMENT0 + + (color_bit - BUFFER_COLOR0 - 1)); + else + _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); + + /* Control writing of the depth clear value to depth. */ + if (this_mask & BUFFER_BIT_DEPTH) { + _mesa_DepthFunc(GL_ALWAYS); + _mesa_DepthMask(GL_TRUE); + _mesa_Enable(GL_DEPTH_TEST); + } else { + _mesa_Disable(GL_DEPTH_TEST); + _mesa_DepthMask(GL_FALSE); + } + + /* Control writing of the stencil clear value to stencil. */ + if (this_mask & BUFFER_BIT_STENCIL) { + _mesa_Enable(GL_STENCIL_TEST); + _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); + _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, + ctx->Stencil.WriteMask[0]); + } else { + _mesa_Disable(GL_STENCIL_TEST); + } + + CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); + + mask &= ~this_mask; + } + + radeon_meta_restore_transform(rmesa); + + _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); + if (saved_fp_enable) + _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); + if (saved_vp_enable) + _mesa_Enable(GL_VERTEX_PROGRAM_ARB); + + if (saved_shader_program) + _mesa_UseProgramObjectARB(saved_shader_program); + + _mesa_PopClientAttrib(); + _mesa_PopAttrib(); +} diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index c97492d742a..f3e2290cab8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -5,6 +5,18 @@ #include "radeon_dma.h" #include "radeon_texture.h" + +#define TRI_CLEAR_COLOR_BITS (BUFFER_BIT_BACK_LEFT | \ + BUFFER_BIT_FRONT_LEFT | \ + BUFFER_BIT_COLOR0 | \ + BUFFER_BIT_COLOR1 | \ + BUFFER_BIT_COLOR2 | \ + BUFFER_BIT_COLOR3 | \ + BUFFER_BIT_COLOR4 | \ + BUFFER_BIT_COLOR5 | \ + BUFFER_BIT_COLOR6 | \ + BUFFER_BIT_COLOR7) + void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); @@ -24,6 +36,8 @@ void radeonFlush(GLcontext *ctx); void radeonFinish(GLcontext * ctx); void radeonEmitState(radeonContextPtr radeon); +void radeon_clear_tris(GLcontext *ctx, GLbitfield mask); + void radeon_window_moved(radeonContextPtr radeon); void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb); void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); @@ -35,7 +49,10 @@ void radeon_get_cliprects(radeonContextPtr radeon, int *x_off, int *y_off); void radeon_fbo_init(struct radeon_context *radeon); -struct gl_renderbuffer * +void +radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, + struct radeon_bo *bo); +struct radeon_renderbuffer * radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv); static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) { diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index a818440faf8..f335eb0313e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -392,6 +392,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) struct radeon_framebuffer *draw; radeonContextPtr radeon; char *regname; + struct radeon_bo *depth_bo, *bo; if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); @@ -448,7 +449,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) regname = "dri2 depth buffer"; break; case __DRI_BUFFER_STENCIL: - rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); + rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL); regname = "dri2 stencil buffer"; break; case __DRI_BUFFER_ACCUM: @@ -463,25 +464,49 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) continue; if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; + uint32_t name = radeon_gem_name_bo(rb->bo); + if (name == buffers[i].name) + continue; } + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, + "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n", + regname, buffers[i].name, buffers[i].attachment, + buffers[i].cpp, buffers[i].pitch); + rb->cpp = buffers[i].cpp; rb->pitch = buffers[i].pitch; rb->width = drawable->w; rb->height = drawable->h; rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - if (rb->bo == NULL) { - fprintf(stderr, "failed to attach %s %d\n", - regname, buffers[i].name); + if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) { + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "(reusing depth buffer as stencil)\n"); + bo = depth_bo; + radeon_bo_ref(bo); + } else { + bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + if (bo == NULL) { + + fprintf(stderr, "failed to attach %s %d\n", + regname, buffers[i].name); + + } } + + if (buffers[i].attachment == __DRI_BUFFER_DEPTH) + depth_bo = bo; + + radeon_renderbuffer_set_bo(rb, bo); + radeon_bo_unref(bo); + } driUpdateFramebufferSize(radeon->glCtx, drawable); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 612cc97f255..0ce72c91985 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -123,7 +123,6 @@ struct radeon_colorbuffer_state { struct radeon_depthbuffer_state { GLuint clear; - GLfloat scale; struct radeon_renderbuffer *rrb; }; @@ -137,7 +136,6 @@ struct radeon_scissor_state { }; struct radeon_stencilbuffer_state { - GLboolean hwBuffer; GLuint clear; /* rb3d_stencilrefmask value */ }; @@ -444,9 +442,23 @@ struct radeon_context { struct radeon_cmdbuf cmdbuf; - drm_clip_rect_t fboRect; - GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ - GLboolean front_cliprects; + drm_clip_rect_t fboRect; + GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ + GLboolean front_cliprects; + + struct { + struct gl_fragment_program *bitmap_fp; + struct gl_vertex_program *passthrough_vp; + + struct gl_fragment_program *saved_fp; + GLboolean saved_fp_enable; + struct gl_vertex_program *saved_vp; + GLboolean saved_vp_enable; + + GLint saved_vp_x, saved_vp_y; + GLsizei saved_vp_width, saved_vp_height; + GLenum saved_matrix_mode; + } meta; struct { void (*get_lock)(radeonContextPtr radeon); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 3f69de8d274..ac945ecc4d3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -66,6 +66,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_EXT_blend_minmax #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color +#define need_GL_EXT_framebuffer_object #include "extension_helper.h" #define DRIVER_DATE "20061018" @@ -88,6 +89,7 @@ const struct dri_extension card_extensions[] = { "GL_EXT_blend_logic_op", NULL }, { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions }, { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, + { "GL_EXT_packed_depth_stencil", NULL}, { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions }, { "GL_EXT_stencil_wrap", NULL }, { "GL_EXT_texture_edge_clamp", NULL }, @@ -104,6 +106,11 @@ const struct dri_extension card_extensions[] = { NULL, NULL } }; +const struct dri_extension mm_extensions[] = { + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, + { NULL, NULL } +}; + extern const struct tnl_pipeline_stage _radeon_render_stage; extern const struct tnl_pipeline_stage _radeon_tcl_stage; @@ -338,6 +345,8 @@ radeonCreateContext( const __GLcontextModes *glVisual, } driInitExtensions( ctx, card_extensions, GL_TRUE ); + if (rmesa->radeon.radeonScreen->kernel_mm) + driInitExtensions(ctx, mm_extensions, GL_FALSE); if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" ); if (rmesa->radeon.glCtx->Mesa_DXTn) { diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 2015e96a743..5235a6e374c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -435,20 +435,6 @@ struct r100_context { GLuint c_textureBytes; GLuint c_vertexBuffers; - struct { - struct gl_fragment_program *bitmap_fp; - struct gl_vertex_program *passthrough_vp; - - struct gl_fragment_program *saved_fp; - GLboolean saved_fp_enable; - struct gl_vertex_program *saved_vp; - GLboolean saved_vp_enable; - - GLint saved_vp_x, saved_vp_y; - GLsizei saved_vp_width, saved_vp_height; - GLenum saved_matrix_mode; - } meta; - }; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 7342f2295ea..f914c8c8d07 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -54,7 +54,6 @@ radeon_new_framebuffer(GLcontext *ctx, GLuint name) static void radeon_delete_renderbuffer(struct gl_renderbuffer *rb) { - GET_CURRENT_CONTEXT(ctx); struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); ASSERT(rrb); @@ -62,8 +61,6 @@ radeon_delete_renderbuffer(struct gl_renderbuffer *rb) if (rrb && rrb->bo) { radeon_bo_unref(rrb->bo); } - - _mesa_free(rrb); } @@ -255,7 +252,7 @@ radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb, return GL_FALSE; } -struct gl_renderbuffer * +struct radeon_renderbuffer * radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) { struct radeon_renderbuffer *rrb; @@ -325,7 +322,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) rrb->base.GetPointer = radeon_get_pointer; rrb->bo = NULL; - return &rrb->base; + return rrb; } static struct gl_renderbuffer * @@ -383,6 +380,13 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } + else if (texImage->TexFormat == &_mesa_texformat_argb4444) { + rrb->cpp = 2; + rrb->base._ActualFormat = GL_RGBA4; + rrb->base._BaseFormat = GL_RGBA; + rrb->base.DataType = GL_UNSIGNED_BYTE; + DBG("Render to RGBA4 texture OK\n"); + } else if (texImage->TexFormat == &_mesa_texformat_rgb565) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5; @@ -493,7 +497,7 @@ radeon_render_texture(GLcontext * ctx, return; } - fprintf(stderr,"Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", + DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", _glthread_GetID(), att->Texture->Name, newImage->Width, newImage->Height, rrb->base.RefCount); @@ -558,4 +562,13 @@ void radeon_fbo_init(struct radeon_context *radeon) } - +void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, + struct radeon_bo *bo) +{ + struct radeon_bo *old; + old = rb->bo; + rb->bo = bo; + radeon_bo_ref(bo); + if (old) + radeon_bo_unref(old); +} diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 22584f4817a..f18aa1a4dae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -419,218 +419,6 @@ void radeonEmitAOS( r100ContextPtr rmesa, */ #define RADEON_MAX_CLEARS 256 - - -static void -r100_meta_set_passthrough_transform(r100ContextPtr r100) -{ - GLcontext *ctx = r100->radeon.glCtx; - - r100->meta.saved_vp_x = ctx->Viewport.X; - r100->meta.saved_vp_y = ctx->Viewport.Y; - r100->meta.saved_vp_width = ctx->Viewport.Width; - r100->meta.saved_vp_height = ctx->Viewport.Height; - r100->meta.saved_matrix_mode = ctx->Transform.MatrixMode; - - _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); - - _mesa_MatrixMode(GL_PROJECTION); - _mesa_PushMatrix(); - _mesa_LoadIdentity(); - _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); - - _mesa_MatrixMode(GL_MODELVIEW); - _mesa_PushMatrix(); - _mesa_LoadIdentity(); -} - -static void -r100_meta_restore_transform(r100ContextPtr r100) -{ - _mesa_MatrixMode(GL_PROJECTION); - _mesa_PopMatrix(); - _mesa_MatrixMode(GL_MODELVIEW); - _mesa_PopMatrix(); - - _mesa_MatrixMode(r100->meta.saved_matrix_mode); - - _mesa_Viewport(r100->meta.saved_vp_x, r100->meta.saved_vp_y, - r100->meta.saved_vp_width, r100->meta.saved_vp_height); -} - -/** - * Perform glClear where mask contains only color, depth, and/or stencil. - * - * The implementation is based on calling into Mesa to set GL state and - * performing normal triangle rendering. The intent of this path is to - * have as generic a path as possible, so that any driver could make use of - * it. - */ -static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - GLfloat vertices[4][3]; - GLfloat color[4][4]; - GLfloat dst_z; - struct gl_framebuffer *fb = ctx->DrawBuffer; - int i; - GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; - GLboolean saved_shader_program = 0; - unsigned int saved_active_texture; - - assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | - BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); - - _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | - GL_CURRENT_BIT | - GL_DEPTH_BUFFER_BIT | - GL_ENABLE_BIT | - GL_STENCIL_BUFFER_BIT | - GL_TRANSFORM_BIT | - GL_CURRENT_BIT); - _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); - saved_active_texture = ctx->Texture.CurrentUnit; - - /* Disable existing GL state we don't want to apply to a clear. */ - _mesa_Disable(GL_ALPHA_TEST); - _mesa_Disable(GL_BLEND); - _mesa_Disable(GL_CULL_FACE); - _mesa_Disable(GL_FOG); - _mesa_Disable(GL_POLYGON_SMOOTH); - _mesa_Disable(GL_POLYGON_STIPPLE); - _mesa_Disable(GL_POLYGON_OFFSET_FILL); - _mesa_Disable(GL_LIGHTING); - _mesa_Disable(GL_CLIP_PLANE0); - _mesa_Disable(GL_CLIP_PLANE1); - _mesa_Disable(GL_CLIP_PLANE2); - _mesa_Disable(GL_CLIP_PLANE3); - _mesa_Disable(GL_CLIP_PLANE4); - _mesa_Disable(GL_CLIP_PLANE5); - if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { - saved_fp_enable = GL_TRUE; - _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); - } - if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { - saved_vp_enable = GL_TRUE; - _mesa_Disable(GL_VERTEX_PROGRAM_ARB); - } - if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { - saved_shader_program = ctx->Shader.CurrentProgram->Name; - _mesa_UseProgramObjectARB(0); - } - - if (ctx->Texture._EnabledUnits != 0) { - int i; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - _mesa_ActiveTextureARB(GL_TEXTURE0 + i); - _mesa_Disable(GL_TEXTURE_1D); - _mesa_Disable(GL_TEXTURE_2D); - _mesa_Disable(GL_TEXTURE_3D); - if (ctx->Extensions.ARB_texture_cube_map) - _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); - if (ctx->Extensions.NV_texture_rectangle) - _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); - if (ctx->Extensions.MESA_texture_array) { - _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); - _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); - } - } - } - - r100_meta_set_passthrough_transform(rmesa); - - for (i = 0; i < 4; i++) { - color[i][0] = ctx->Color.ClearColor[0]; - color[i][1] = ctx->Color.ClearColor[1]; - color[i][2] = ctx->Color.ClearColor[2]; - color[i][3] = ctx->Color.ClearColor[3]; - } - - /* convert clear Z from [0,1] to NDC coord in [-1,1] */ - dst_z = -1.0 + 2.0 * ctx->Depth.Clear; - - /* Prepare the vertices, which are the same regardless of which buffer we're - * drawing to. - */ - vertices[0][0] = fb->_Xmin; - vertices[0][1] = fb->_Ymin; - vertices[0][2] = dst_z; - vertices[1][0] = fb->_Xmax; - vertices[1][1] = fb->_Ymin; - vertices[1][2] = dst_z; - vertices[2][0] = fb->_Xmax; - vertices[2][1] = fb->_Ymax; - vertices[2][2] = dst_z; - vertices[3][0] = fb->_Xmin; - vertices[3][1] = fb->_Ymax; - vertices[3][2] = dst_z; - - _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); - _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); - _mesa_Enable(GL_COLOR_ARRAY); - _mesa_Enable(GL_VERTEX_ARRAY); - - while (mask != 0) { - GLuint this_mask = 0; - - if (mask & BUFFER_BIT_BACK_LEFT) - this_mask = BUFFER_BIT_BACK_LEFT; - else if (mask & BUFFER_BIT_FRONT_LEFT) - this_mask = BUFFER_BIT_FRONT_LEFT; - - /* Clear depth/stencil in the same pass as color. */ - this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); - - /* Select the current color buffer and use the color write mask if - * we have one, otherwise don't write any color channels. - */ - if (this_mask & BUFFER_BIT_FRONT_LEFT) - _mesa_DrawBuffer(GL_FRONT_LEFT); - else if (this_mask & BUFFER_BIT_BACK_LEFT) - _mesa_DrawBuffer(GL_BACK_LEFT); - else - _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); - - /* Control writing of the depth clear value to depth. */ - if (this_mask & BUFFER_BIT_DEPTH) { - _mesa_DepthFunc(GL_ALWAYS); - _mesa_Enable(GL_DEPTH_TEST); - } else { - _mesa_Disable(GL_DEPTH_TEST); - _mesa_DepthMask(GL_FALSE); - } - - /* Control writing of the stencil clear value to stencil. */ - if (this_mask & BUFFER_BIT_STENCIL) { - _mesa_Enable(GL_STENCIL_TEST); - _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); - _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, - ctx->Stencil.WriteMask[0]); - } else { - _mesa_Disable(GL_STENCIL_TEST); - } - - CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); - - mask &= ~this_mask; - } - - r100_meta_restore_transform(rmesa); - - _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); - if (saved_fp_enable) - _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); - if (saved_vp_enable) - _mesa_Enable(GL_VERTEX_PROGRAM_ARB); - - if (saved_shader_program) - _mesa_UseProgramObjectARB(saved_shader_program); - - _mesa_PopClientAttrib(); - _mesa_PopAttrib(); -} - static void radeonUserClear(GLcontext *ctx, GLuint mask) { radeon_clear_tris(ctx, mask); @@ -795,7 +583,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) mask &= ~BUFFER_BIT_DEPTH; } - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { + if ( (mask & BUFFER_BIT_STENCIL) ) { flags |= RADEON_STENCIL; mask &= ~BUFFER_BIT_STENCIL; } @@ -813,8 +601,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) flags |= RADEON_USE_COMP_ZBUF; /* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->radeon.state.stencil.hwBuffer) || - ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && + if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { flags |= RADEON_CLEAR_FASTZ; } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index a14a0c3cb28..4725f38ae83 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1086,6 +1086,9 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) else screen->chip_flags |= RADEON_CLASS_R300; + if (getenv("R300_NO_TCL")) + screen->chip_flags &= ~RADEON_CHIPSET_TCL; + i = 0; screen->extensions[i++] = &driCopySubBufferExtension.base; screen->extensions[i++] = &driFrameTrackingExtension.base; @@ -1197,7 +1200,6 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, const GLboolean swStencil = mesaVis->stencilBits > 0 && mesaVis->depthBits != 24; GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); - GLenum depthFormat = GL_NONE; struct radeon_framebuffer *rfb; if (isPixmap) @@ -1209,37 +1211,35 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, _mesa_initialize_framebuffer(&rfb->base, mesaVis); - if (mesaVis->depthBits == 16) - depthFormat = GL_DEPTH_COMPONENT16; - else if (mesaVis->depthBits == 24) - depthFormat = GL_DEPTH_COMPONENT24; - /* front color renderbuffer */ - rfb->color_rb[0] = radeon_renderbuffer(radeon_create_renderbuffer(rgbFormat, driDrawPriv)); + rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); rfb->color_rb[0]->has_surface = 1; /* back color renderbuffer */ if (mesaVis->doubleBufferMode) { - rfb->color_rb[1] = radeon_renderbuffer(radeon_create_renderbuffer(rgbFormat, driDrawPriv)); + rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); rfb->color_rb[1]->has_surface = 1; } - /* depth renderbuffer */ - if (depthFormat != GL_NONE) { - struct radeon_renderbuffer *depth = radeon_renderbuffer( - radeon_create_renderbuffer(depthFormat, driDrawPriv)); + if (mesaVis->depthBits == 24) { + if (mesaVis->stencilBits == 8) { + struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); + _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); + _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); + depthStencilRb->has_surface = screen->depthHasSurface; + } else { + /* depth renderbuffer */ + struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); + _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); + depth->has_surface = screen->depthHasSurface; + } + } else if (mesaVis->depthBits == 16) { + /* just 16-bit depth buffer, no hw stencil */ + struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); depth->has_surface = screen->depthHasSurface; - } - - /* stencil renderbuffer */ - if (mesaVis->stencilBits > 0 && !swStencil) { - struct radeon_renderbuffer *stencil = radeon_renderbuffer( - radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv)); - _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base); - stencil->has_surface = screen->depthHasSurface; } _mesa_add_soft_renderbuffers(&rfb->base, diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 768a51b51d5..3d2c5da4c06 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -377,33 +377,64 @@ do { \ #include "stenciltmp.h" -static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) +void map_unmap_rb(struct gl_renderbuffer *rb, int flag) { - struct radeon_renderbuffer *rrb = (void*)rb; + struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); int r; - if (rrb->bo) { - r = radeon_bo_map(rrb->bo, write); + if (rrb == NULL || !rrb->bo) + return; + + if (flag) { + r = radeon_bo_map(rrb->bo, 1); if (r) { fprintf(stderr, "(%s) error(%d) mapping buffer.\n", __FUNCTION__, r); } - } - radeonSetSpanFunctions(rrb); + radeonSetSpanFunctions(rrb); + } else { + radeon_bo_unmap(rrb->bo); + rb->GetRow = NULL; + rb->PutRow = NULL; + } } -static void unmap_buffer(struct gl_renderbuffer *rb) +static void +radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map) { - struct radeon_renderbuffer *rrb = (void*)rb; + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + GLuint i, j; - if (rrb->bo) { - radeon_bo_unmap(rrb->bo); + /* color draw buffers */ + for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) + map_unmap_rb(ctx->DrawBuffer->_ColorDrawBuffers[j], map); + + /* check for render to textures */ + for (i = 0; i < BUFFER_COUNT; i++) { + struct gl_renderbuffer_attachment *att = + ctx->DrawBuffer->Attachment + i; + struct gl_texture_object *tex = att->Texture; + if (tex) { + /* render to texture */ + ASSERT(att->Renderbuffer); + if (map) + ctx->Driver.MapTexture(ctx, tex); + else + ctx->Driver.UnmapTexture(ctx, tex); + } } - rb->GetRow = NULL; - rb->PutRow = NULL; -} + + map_unmap_rb(ctx->ReadBuffer->_ColorReadBuffer, map); + + /* depth buffer (Note wrapper!) */ + if (ctx->DrawBuffer->_DepthBuffer) + map_unmap_rb(ctx->DrawBuffer->_DepthBuffer->Wrapped, map); + + if (ctx->DrawBuffer->_StencilBuffer) + map_unmap_rb(ctx->DrawBuffer->_StencilBuffer->Wrapped, map); +} static void radeonSpanRenderStart(GLcontext * ctx) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -416,18 +447,7 @@ static void radeonSpanRenderStart(GLcontext * ctx) ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); } - /* color draw buffers */ - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { - map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); - } - - map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); - - if (ctx->DrawBuffer->_DepthBuffer) { - map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); - } - if (ctx->DrawBuffer->_StencilBuffer) - map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); + radeon_map_unmap_buffers(ctx, 1); /* The locking and wait for idle should really only be needed in classic mode. * In a future memory manager based implementation, this should become @@ -450,16 +470,7 @@ static void radeonSpanRenderFinish(GLcontext * ctx) ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); } - /* color draw buffers */ - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) - unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); - - unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); - - if (ctx->DrawBuffer->_DepthBuffer) - unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); - if (ctx->DrawBuffer->_StencilBuffer) - unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); + radeon_map_unmap_buffers(ctx, 0); } void radeonInitSpanFuncs(GLcontext * ctx) @@ -485,6 +496,8 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) radeonInitDepthPointers_z16(&rrb->base); } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) { radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base._ActualFormat == GL_DEPTH24_STENCIL8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); } else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) { radeonInitStencilPointers_z24_s8(&rrb->base); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 635fe43ce4b..19ff2688e6e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -528,7 +528,8 @@ static void radeonPolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - float_ui32_type constant = { units * rmesa->radeon.state.depth.scale }; + const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; + float_ui32_type constant = { units * depthScale }; float_ui32_type factoru = { factor }; RADEON_STATECHANGE( rmesa, zbs ); @@ -1391,6 +1392,7 @@ void radeonUpdateWindow( GLcontext *ctx ) GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); + const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; GLfloat y_scale, y_bias; if (render_to_fbo) { @@ -1405,8 +1407,8 @@ void radeonUpdateWindow( GLcontext *ctx ) float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; float_ui32_type sy = { v[MAT_SY] * y_scale }; float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y }; - float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; - float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; + float_ui32_type sz = { v[MAT_SZ] * depthScale }; + float_ui32_type tz = { v[MAT_TZ] * depthScale }; RADEON_STATECHANGE( rmesa, vpt ); @@ -1800,15 +1802,24 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) break; case GL_STENCIL_TEST: - if ( rmesa->radeon.state.stencil.hwBuffer ) { - RADEON_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; + { + GLboolean hw_stencil = GL_FALSE; + if (ctx->DrawBuffer) { + struct radeon_renderbuffer *rrbStencil + = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); + hw_stencil = (rrbStencil && rrbStencil->bo); + } + + if (hw_stencil) { + RADEON_STATECHANGE( rmesa, ctx ); + if ( state ) { + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; + } else { + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE; + } } else { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE; + FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state ); } - } else { - FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state ); } break; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 8b6caf19d36..3d0cd8d3f86 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -592,22 +592,16 @@ void radeonInitState( r100ContextPtr rmesa ) switch ( ctx->Visual.depthBits ) { case 16: rmesa->radeon.state.depth.clear = 0x0000ffff; - rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: rmesa->radeon.state.depth.clear = 0x00ffffff; - rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: break; } - /* Only have hw stencil when depth buffer is 24 bits deep */ - rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24 ); - rmesa->radeon.Fallback = 0; -- cgit v1.2.3 From f9d3de06bdc609d2c7cb189d220977968894c7ed Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Mar 2009 19:32:10 +1000 Subject: radeon: fixup wrapper bo name --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 42607df9676..cb354c5117b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -36,7 +36,7 @@ struct drm_radeon_gem_info { #endif -uint32_t radeon_gem_bo_name(struct radeon_bo *dummy) +static inline uint32_t radeon_gem_name_bo(struct radeon_bo *dummy) { return 0; } -- cgit v1.2.3 From 9f11b3311e9f65bc19a3fde10f1ee4d6fbb7ead2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 09:26:31 +1000 Subject: radeon: stupid mesa extension fail --- src/mesa/drivers/dri/radeon/radeon_screen.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 2d3bb619cda..78f769e3ed2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -241,6 +241,7 @@ static const struct dri_debug_control debug_control[] = { #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ extern const struct dri_extension card_extensions[]; +extern const struct dri_extension mm_extensions[]; static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); @@ -1413,6 +1414,7 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) * Hello chicken. Hello egg. How are you two today? */ driInitExtensions( NULL, card_extensions, GL_FALSE ); + driInitExtensions( NULL, mm_extensions, GL_FALSE ); #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) driInitExtensions( NULL, blend_extensions, GL_FALSE ); driInitSingleExtension( NULL, ARB_vp_extension ); -- cgit v1.2.3 From 28e082197d158206b58da62940cf57796abe565a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 09:28:52 +1000 Subject: radeon: setup pipes for r300 --- src/mesa/drivers/dri/radeon/radeon_screen.c | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 78f769e3ed2..3817007e9e5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1047,6 +1047,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) int i; int ret; uint32_t device_id; + uint32_t temp = 0; /* Allocate the private area */ screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); @@ -1083,6 +1084,36 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) if (ret == -1) return NULL; + if (screen->chip_family >= CHIP_FAMILY_R300) { + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, + &temp); + if (ret) { + fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); + switch (screen->chip_family) { + case CHIP_FAMILY_R300: + case CHIP_FAMILY_R350: + screen->num_gb_pipes = 2; + break; + case CHIP_FAMILY_R420: + case CHIP_FAMILY_R520: + case CHIP_FAMILY_R580: + case CHIP_FAMILY_RV560: + case CHIP_FAMILY_RV570: + screen->num_gb_pipes = 4; + break; + case CHIP_FAMILY_RV350: + case CHIP_FAMILY_RV515: + case CHIP_FAMILY_RV530: + case CHIP_FAMILY_RV410: + default: + screen->num_gb_pipes = 1; + break; + } + } else { + screen->num_gb_pipes = temp; + } + } + if (screen->chip_family <= CHIP_FAMILY_RS200) screen->chip_flags |= RADEON_CLASS_R100; else if (screen->chip_family <= CHIP_FAMILY_RV280) -- cgit v1.2.3 From 2aa097f963d7be12b538469f61214b8ddaa535fb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 09:45:18 +1000 Subject: radeon: fix typo --- src/mesa/drivers/dri/radeon/radeon_tex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h index 8d8afb43436..a4aaddc74fa 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h @@ -42,7 +42,7 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, GLuint pitch); extern void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); -externvoid radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, +extern void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv); extern void radeonUpdateTextureState( GLcontext *ctx ); -- cgit v1.2.3 From ccd18f462cccd238ff0d839004d43a3102f09ff3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 09:45:26 +1000 Subject: radeon: actual format is rgba8 --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index f914c8c8d07..2c30f9ddfde 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -382,7 +382,7 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, } else if (texImage->TexFormat == &_mesa_texformat_argb4444) { rrb->cpp = 2; - rrb->base._ActualFormat = GL_RGBA4; + rrb->base._ActualFormat = GL_RGBA8; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA4 texture OK\n"); -- cgit v1.2.3 From 0a725db10c1491539d48370df7207206538bf945 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 11:19:09 +1000 Subject: radeon/r200/r300: set the texture depth correctly for DRI2 --- src/mesa/drivers/dri/r200/r200_context.c | 6 ------ src/mesa/drivers/dri/r300/r300_context.c | 6 ------ src/mesa/drivers/dri/radeon/radeon_common_context.c | 6 ++++++ src/mesa/drivers/dri/radeon/radeon_context.c | 6 ------ 4 files changed, 6 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 6fd0575898f..d3898d0900d 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -338,12 +338,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, return GL_FALSE; } - rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, - "texture_depth"); - if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? - DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->radeon.hw.all_dirty = 1; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index c6bd69ed146..87ec68a2cd8 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -328,12 +328,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, } /* Init r300 context data */ - r300->radeon.texture_depth = driQueryOptioni(&r300->radeon.optionCache, - "texture_depth"); - if (r300->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - r300->radeon.texture_depth = (screen->cpp == 4) ? - DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have them both in * texturable memory at once. diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index f335eb0313e..5b23473ab37 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -163,6 +163,12 @@ GLboolean radeonInitContext(radeonContextPtr radeon, "IRQ's not enabled, falling back to %s: %d %d\n", radeon->do_usleeps ? "usleeps" : "busy waits", fthrottle_mode, radeon->radeonScreen->irq); + + radeon->texture_depth = driQueryOptioni (&radeon->optionCache, + "texture_depth"); + if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) + radeon->texture_depth = ( glVisual->rgbBits > 16 ) ? + DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index ac945ecc4d3..cad2c3e0c1f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -261,12 +261,6 @@ radeonCreateContext( const __GLcontextModes *glVisual, return GL_FALSE; } - rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, - "texture_depth"); - if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? - DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->radeon.hw.all_dirty = GL_TRUE; -- cgit v1.2.3 From 20981c0a0bd43aff4972c1300f990b06dfa789d1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 15:06:19 +1000 Subject: radeon: fixup some issue with fbos and sw fallbacks --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 7 ------- src/mesa/drivers/dri/radeon/radeon_texture.c | 5 ++++- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 2c30f9ddfde..40945855d96 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -380,13 +380,6 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb4444) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_RGBA8; - rrb->base._BaseFormat = GL_RGBA; - rrb->base.DataType = GL_UNSIGNED_BYTE; - DBG("Render to RGBA4 texture OK\n"); - } else if (texImage->TexFormat == &_mesa_texformat_rgb565) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5; diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 63680b495c9..d212898acd8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -139,9 +139,12 @@ void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeonTexObj* t = radeon_tex_obj(texObj); int face, level; + if (!radeon_validate_texture_miptree(ctx, texObj)) + return; + /* for r100 3D sw fallbacks don't have mt */ if (!t->mt) - return; + return; radeon_bo_map(t->mt->bo, GL_FALSE); for(face = 0; face < t->mt->faces; ++face) { -- cgit v1.2.3 From 5021b47dd307377be30140e3a0d1c2caf0d71665 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 15:21:49 +1000 Subject: r300: remove lock.h link --- src/mesa/drivers/dri/r300/radeon_lock.h | 1 - 1 file changed, 1 deletion(-) delete mode 120000 src/mesa/drivers/dri/r300/radeon_lock.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h deleted file mode 120000 index 64bdf94ee7e..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_lock.h \ No newline at end of file -- cgit v1.2.3 From f577c8e462fc924ea436d129ad64c8a1226b5f9c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 18:32:46 +1000 Subject: radeon/r200/r300: fix warnings --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 15 +-------------- src/mesa/drivers/dri/r200/r200_context.c | 1 - src/mesa/drivers/dri/r200/r200_ioctl.c | 1 - src/mesa/drivers/dri/r300/r300_state.c | 6 +----- src/mesa/drivers/dri/radeon/radeon_common_context.c | 3 ++- src/mesa/drivers/dri/radeon/radeon_fbo.c | 5 +++-- src/mesa/drivers/dri/radeon/radeon_lock.c | 2 -- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 16 ++++++++-------- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h | 3 +-- src/mesa/drivers/dri/radeon/radeon_span.c | 3 +-- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 2 -- src/mesa/drivers/dri/radeon/radeon_texstate.c | 7 ------- 12 files changed, 17 insertions(+), 47 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index ae31bcb8311..83375c88a70 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -112,7 +112,6 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ) { - drm_radeon_cmd_header_t *cmd; BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & R200_VF_PRIM_WALK_IND)); @@ -164,8 +163,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) void r200FlushElts(GLcontext *ctx) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - int dwords; + r200ContextPtr rmesa = R200_CONTEXT(ctx); int nr, elt_used = rmesa->tcl.elt_used; if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) @@ -345,14 +343,3 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) } END_BATCH(); } - -void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type) -{ - BATCH_LOCALS(&rmesa->radeon); - - BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type); - END_BATCH(); -} - diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index d3898d0900d..564e168290c 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -243,7 +243,6 @@ static void r200_get_lock(radeonContextPtr radeon) { r200ContextPtr rmesa = (r200ContextPtr)radeon; drm_radeon_sarea_t *sarea = radeon->sarea; - int i; R200_STATECHANGE( rmesa, ctx ); if (rmesa->radeon.sarea->tiling_enabled) { diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index ccb56202f6d..b8e40da475c 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -193,7 +193,6 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLuint flags = 0; GLuint color_mask = 0; - GLint ret; GLuint orig_mask = mask; if ( R200_DEBUG & DEBUG_IOCTL ) { diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index f49b43c2070..6796d36d4cd 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/macros.h" #include "main/context.h" #include "main/dd.h" +#include "main/framebuffer.h" #include "main/simple_list.h" #include "main/api_arrayelt.h" #include "main/texformat.h" @@ -2029,7 +2030,6 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) static void r300ResetHwState(r300ContextPtr r300) { GLcontext *ctx = r300->radeon.glCtx; - struct radeon_renderbuffer *rrb; int has_tcl = 1; if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) @@ -2039,7 +2039,6 @@ static void r300ResetHwState(r300ContextPtr r300) fprintf(stderr, "%s\n", __FUNCTION__); radeon_firevertices(&r300->radeon); - //r300UpdateWindow(ctx); r300ColorMask(ctx, ctx->Color.ColorMask[RCOMP], @@ -2524,9 +2523,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) */ void r300InitState(r300ContextPtr r300) { - GLcontext *ctx = r300->radeon.glCtx; - GLuint depth_fmt; - memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); r300ResetHwState(r300); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 5b23473ab37..9964de7c7cc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -36,6 +36,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" /* for symbolic values of enum-type options */ #include "utils.h" #include "vblank.h" +#include "drirenderbuffer.h" #include "main/state.h" #define DRIVER_DATE "20090101" @@ -398,7 +399,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) struct radeon_framebuffer *draw; radeonContextPtr radeon; char *regname; - struct radeon_bo *depth_bo, *bo; + struct radeon_bo *depth_bo = NULL, *bo; if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 40945855d96..96ba5d3c60e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -510,8 +510,9 @@ radeon_render_texture(GLcontext * ctx, att->TextureLevel); if (att->Texture->Target == GL_TEXTURE_3D) { - const GLuint *offsets = radeon_miptree_depth_offsets(radeon_image->mt, - att->TextureLevel); + GLuint offsets[6]; + radeon_miptree_depth_offsets(radeon_image->mt, att->TextureLevel, + offsets); imageOffset += offsets[att->Zoffset]; } diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index e1bb2cd6e21..fe19218d7ae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -61,7 +61,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; __DRIdrawablePrivate *const readable = rmesa->dri.readable; __DRIscreenPrivate *sPriv = rmesa->dri.screen; - drm_radeon_sarea_t *sarea = rmesa->sarea; assert(drawable != NULL); @@ -92,7 +91,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) void radeon_lock_hardware(radeonContextPtr radeon) { - __DRIdrawable *dPriv = radeon->dri.drawable; char ret = 0; struct radeon_framebuffer *rfb = NULL; struct radeon_renderbuffer *rrb = NULL; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 228629e3c45..34d62617068 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -94,8 +94,6 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, /* Find image size in bytes */ if (mt->compressed) { /* TODO: Is this correct? Need test cases for compressed textures! */ - GLuint align; - lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, lvl->width, lvl->height, lvl->depth, mt->compressed); @@ -365,14 +363,16 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, * * These functions present that view to mesa: */ -const GLuint * -radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level) +void +radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets) { - static const GLuint zero = 0; if (mt->target != GL_TEXTURE_3D || mt->faces == 1) - return &zero; - else - return mt->levels[level].faces[0].offset; + offsets[0] = 0; + else { + int i; + for (i = 0; i < 6; i++) + offsets[i] = mt->levels[level].faces[i].offset; + } } GLuint diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h index d9ad5ad39a3..697010bc022 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h @@ -94,6 +94,5 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, struct gl_texture_image *texImage, GLuint face, GLuint level); GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt, GLuint face, GLuint level); -const GLuint * -radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level); +void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets); #endif /* __RADEON_MIPMAP_TREE_H_ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 3d2c5da4c06..0b4eaae02bf 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -377,7 +377,7 @@ do { \ #include "stenciltmp.h" -void map_unmap_rb(struct gl_renderbuffer *rb, int flag) +static void map_unmap_rb(struct gl_renderbuffer *rb, int flag) { struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); int r; @@ -403,7 +403,6 @@ void map_unmap_rb(struct gl_renderbuffer *rb, int flag) static void radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); GLuint i, j; /* color draw buffers */ diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index af933a35f2b..2484006f1c4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -825,6 +825,4 @@ void radeonInitSwtcl( GLcontext *ctx ) void radeonDestroySwtcl( GLcontext *ctx ) { - r100ContextPtr rmesa = R100_CONTEXT(ctx); - } diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 78e2a08559b..9931f01b636 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -775,11 +775,6 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri static void disable_tex_obj_state( r100ContextPtr rmesa, int unit ) { - /* do not use RADEON_DB_STATE to avoid stale texture caches */ - uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; - GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; - GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] ); - RADEON_STATECHANGE( rmesa, tex[unit] ); RADEON_STATECHANGE( rmesa, tcl ); @@ -1142,8 +1137,6 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) { return GL_FALSE; -- cgit v1.2.3 From 4d36a19c90fcc3f6e09dd01072b8b279cc8baef2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 26 Mar 2009 11:15:07 +1000 Subject: r200: add fbo files to the compile --- src/mesa/drivers/dri/r200/Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index e593ed91c58..6a246edf7cb 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -22,7 +22,8 @@ RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_mipmap_tree.c \ - radeon_span.c + radeon_span.c \ + radeon_fbo.c DRIVER_SOURCES = r200_context.c \ @@ -80,7 +81,8 @@ COMMON_SYMLINKS = \ radeon_texture.c \ radeon_texture.h \ radeon_dma.c \ - radeon_dma.h + radeon_dma.h \ + radeon_fbo.c DRI_LIB_DEPS += $(RADEON_LDFLAGS) -- cgit v1.2.3 From 258686a973d7aef4bf956f540e99e65dc5bbee9c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Mar 2009 17:01:37 +1000 Subject: radeon: fixup map/unmap texture to work with override BOs if you hit this you've already failed but we shouldn't crash --- src/mesa/drivers/dri/radeon/radeon_texture.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index d212898acd8..a38d76ac2c1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -131,6 +131,25 @@ void radeon_teximage_unmap(radeon_texture_image *image) } } +static void map_override(GLcontext *ctx, radeonTexObj *t) +{ + radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]); + + radeon_bo_map(t->bo, GL_FALSE); + + img->base.Data = t->bo->ptr; + _mesa_set_fetch_functions(&img->base, 2); +} + +static void unmap_override(GLcontext *ctx, radeonTexObj *t) +{ + radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]); + + radeon_bo_unmap(t->bo); + + img->base.Data = NULL; +} + /** * Map a validated texture for reading during software rendering. */ @@ -143,8 +162,11 @@ void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) return; /* for r100 3D sw fallbacks don't have mt */ + if (t->image_override && t->bo) + map_override(ctx, t); + if (!t->mt) - return; + return; radeon_bo_map(t->mt->bo, GL_FALSE); for(face = 0; face < t->mt->faces; ++face) { @@ -158,6 +180,8 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeonTexObj* t = radeon_tex_obj(texObj); int face, level; + if (t->image_override && t->bo) + unmap_override(ctx, t); /* for r100 3D sw fallbacks don't have mt */ if (!t->mt) return; -- cgit v1.2.3 From e757bf964f4fd9ddbaa23ebaa47f743725aaf2c5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Mar 2009 17:02:32 +1000 Subject: r300: check buffer sizes in non-tcl case + set correct VRAM limits --- src/mesa/drivers/dri/r300/r300_render.c | 3 +++ src/mesa/drivers/dri/radeon/radeon_common.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 402d2d76388..829d088033a 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -490,6 +490,9 @@ static GLboolean r300RunNonTCLRender(GLcontext * ctx, if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) return GL_TRUE; + if (!r300ValidateBuffers(ctx)) + return GL_TRUE; + return r300RunRender(ctx, stage); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 9f646c4386c..3ce868d2cf3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -1094,7 +1094,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa) if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) { - radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_size); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_visible); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size); } } -- cgit v1.2.3 From 8ed405cd3716a9a578bf2bdd46eabd6c90400074 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Mar 2009 17:59:33 +1000 Subject: radeon/r200/r300: set correct row stride for rbs --- src/mesa/drivers/dri/r200/r200_texstate.c | 1 + src/mesa/drivers/dri/r300/r300_texstate.c | 3 ++- src/mesa/drivers/dri/radeon/radeon_texstate.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 2212fe64a6d..72b7f3dafa2 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -836,6 +836,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); + texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, type, format); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index d16cf688ed5..0c6d092df36 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -451,9 +451,10 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo radeon_miptree_unreference(rImage->mt); rImage->mt = NULL; } - fprintf(stderr,"settexbuf %dx%d@%d targ %x format %x\n", rb->width, rb->height, rb->cpp, target, format); + fprintf(stderr,"settexbuf %dx%d@%d %d targ %x format %x\n", rb->width, rb->height, rb->cpp, rb->pitch, target, format); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); + texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, type, format); diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 9931f01b636..dab0df0ff3b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -707,6 +707,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ } _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); + texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, type, format); -- cgit v1.2.3 From 3b09f6544aee880687cd82de33205ae2fa652e10 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 30 Mar 2009 12:02:08 +1000 Subject: radeon: fix readback problem for piglit tests --- src/mesa/drivers/dri/radeon/radeon_span.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 0b4eaae02bf..961bbaba5b2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -441,13 +441,6 @@ static void radeonSpanRenderStart(GLcontext * ctx) radeon_firevertices(rmesa); - for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) - ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); - } - - radeon_map_unmap_buffers(ctx, 1); - /* The locking and wait for idle should really only be needed in classic mode. * In a future memory manager based implementation, this should become * unnecessary due to the fact that mapping our buffers, textures, etc. @@ -455,6 +448,16 @@ static void radeonSpanRenderStart(GLcontext * ctx) * be waited on. */ LOCK_HARDWARE(rmesa); radeonWaitForIdleLocked(rmesa); + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { + if (ctx->Texture.Unit[i]._ReallyEnabled) + ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + + radeon_map_unmap_buffers(ctx, 1); + + + } static void radeonSpanRenderFinish(GLcontext * ctx) -- cgit v1.2.3 From 1570bde279362d95a58d120e42e68cb307d00dde Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 10:35:16 +1000 Subject: r200: fix veclinear emission --- src/mesa/drivers/dri/r200/r200_state_init.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 30326c29601..2400abe838b 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -305,11 +305,12 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9 OUT_BATCH_TABLE((data), h.vectors.count); \ } while(0) -#define OUT_VECLINEAR(hdr, data) do { \ - drm_radeon_cmd_header_t h; \ - uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ - uint32_t _sz = h.veclinear.count * 4; \ +#define OUT_VECLINEAR(hdr, data) do { \ + drm_radeon_cmd_header_t h; \ + uint32_t _start, _sz; \ h.i = hdr; \ + _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ + _sz = h.veclinear.count * 4; \ OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ OUT_BATCH(0); \ OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ -- cgit v1.2.3 From e1d16574932be24da573a93e3302418dc6e855f1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 10:36:06 +1000 Subject: radeon/r200: fix glean failures on readPixSanity since EXT_DEPTH_STENCIL support --- src/mesa/drivers/dri/radeon/radeon_span.c | 63 +++++++++++++++++++++++++--- src/mesa/drivers/dri/radeon/radeon_texture.c | 22 +++------- 2 files changed, 63 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 961bbaba5b2..d2211bcbcc6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -178,6 +178,19 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, return &ptr[offset]; } +#ifndef COMPILE_R300 +static uint32_t +z24s8_to_s8z24(uint32_t val) +{ + return (val << 24) | (val >> 8); +} + +static uint32_t +s8z24_to_z24s8(uint32_t val) +{ + return (val >> 24) | (val << 8); +} +#endif /* * Note that all information needed to access pixels in a renderbuffer @@ -288,7 +301,7 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb, #define TAG(x) radeon##x##_z16 #include "depthtmp.h" -/* 24 bit depth, 8 bit stencil depthbuffer functions +/* 24 bit depth * * Careful: It looks like the R300 uses ZZZS byte order while the R200 * uses SZZZ for 24 bit depth, 8 bit stencil mode. @@ -317,12 +330,52 @@ do { \ #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ - do { \ + do { \ d = (*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \ }while(0) #else +#define READ_DEPTH( d, _x, _y ) \ + d = *(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) & 0x00ffffff; +#endif +/* + fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\ + d = *(GLuint*)(radeon_ptr(rrb, _x, _y )) & 0x00ffffff; +*/ +#define TAG(x) radeon##x##_z24 +#include "depthtmp.h" + +/* 24 bit depth, 8 bit stencil depthbuffer functions + * EXT_depth_stencil + * + * Careful: It looks like the R300 uses ZZZS byte order while the R200 + * uses SZZZ for 24 bit depth, 8 bit stencil mode. + */ +#define VALUE_TYPE GLuint + +#ifdef COMPILE_R300 +#define WRITE_DEPTH( _x, _y, d ) \ +do { \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + *_ptr = d; \ +} while (0) +#else +#define WRITE_DEPTH( _x, _y, d ) \ +do { \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = z24s8_to_s8z24(d); \ + *_ptr = tmp; \ +} while (0) +#endif + +#ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off )) & 0x00ffffff; + do { \ + d = (*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off))); \ + }while(0) +#else +#define READ_DEPTH( d, _x, _y ) do { \ + d = s8z24_to_z24s8(*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off ))); \ + } while (0) #endif /* fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\ @@ -497,9 +550,9 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT16) { radeonInitDepthPointers_z16(&rrb->base); } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) { - radeonInitDepthPointers_z24_s8(&rrb->base); + radeonInitDepthPointers_z24(&rrb->base); } else if (rrb->base._ActualFormat == GL_DEPTH24_STENCIL8_EXT) { - radeonInitStencilPointers_z24_s8(&rrb->base); + radeonInitDepthPointers_z24_s8(&rrb->base); } else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) { radeonInitStencilPointers_z24_s8(&rrb->base); } diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index a38d76ac2c1..5808633b7b0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -458,25 +458,13 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_DEPTH_COMPONENT16: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: -#if 0 - switch (type) { - case GL_UNSIGNED_BYTE: - case GL_UNSIGNED_SHORT: - return &_mesa_texformat_z16; - case GL_UNSIGNED_INT: - return &_mesa_texformat_z32; - case GL_UNSIGNED_INT_24_8_EXT: - default: - return &_mesa_texformat_z24_s8; - } -#else - return &_mesa_texformat_z16; -#endif - + case GL_DEPTH_STENCIL_EXT: + case GL_DEPTH24_STENCIL8_EXT: + return &_mesa_texformat_s8_z24; default: _mesa_problem(ctx, - "unexpected internalFormat 0x%x in r300ChooseTextureFormat", - (int)internalFormat); + "unexpected internalFormat 0x%x in %s", + (int)internalFormat, __func__); return NULL; } -- cgit v1.2.3 From 226c876a52c1bd51d5f16ff58df5c4144355e2a3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 10:46:27 +1000 Subject: r200: only set all dirty on kernel clears --- src/mesa/drivers/dri/r200/r200_ioctl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index b8e40da475c..0262aea880e 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -251,10 +251,10 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) if (rmesa->radeon.radeonScreen->kernel_mm) r200UserClear(ctx, orig_mask); - else + else { r200KernelClear(ctx, flags); - - rmesa->radeon.hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; + } } /* This version of AllocateMemoryMESA allocates only GART memory, and -- cgit v1.2.3 From 5c7fc1cb8e59d1603df17db8c7c63a92441ac820 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 20:10:48 +1000 Subject: r300: fix stencil clears --- src/mesa/drivers/dri/r300/r300_ioctl.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 71661eef19c..1314550e544 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -558,6 +558,9 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags) if (rrbd && (flags & BUFFER_BIT_DEPTH)) bits |= CLEARBUFFER_DEPTH; + if (rrbd && (flags & BUFFER_BIT_STENCIL)) + bits |= CLEARBUFFER_STENCIL; + if (flags & BUFFER_BIT_COLOR0) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0); r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); -- cgit v1.2.3 From 5ad32cfd21bc9c798d05f5202cc75d37cc258354 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 13:38:39 +1000 Subject: r200: fix glean pixelFormats regression --- src/mesa/drivers/dri/radeon/radeon_texture.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 5808633b7b0..21529f62fa5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -276,6 +276,8 @@ static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPt (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { return &_mesa_texformat_rgba8888_rev; + } else if (IS_R200_CLASS(rmesa->radeonScreen)) { + return _dri_texformat_argb8888; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8)) { return &_mesa_texformat_argb8888_rev; @@ -376,8 +378,12 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return _dri_texformat_a8; - + /* r200: can't use a8 format since interpreting hw I8 as a8 would result + in wrong rgb values (same as alpha value instead of 0). */ + if (IS_R200_CLASS(rmesa->radeonScreen)) + return _dri_texformat_al88; + else + return _dri_texformat_a8; case 1: case GL_LUMINANCE: case GL_LUMINANCE4: -- cgit v1.2.3 From 2f3be8ab14d6f4a3cc44817f6f55bc640faadde0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 14:43:14 +1000 Subject: radeon: fix pixel readback for RGB8 tests --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 9 +++++++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 9 ++++++++- src/mesa/drivers/dri/radeon/radeon_span.c | 6 +++++- 3 files changed, 22 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 96ba5d3c60e..d17835bb12c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -274,6 +274,15 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) rrb->base.BlueBits = 5; rrb->base.DataType = GL_UNSIGNED_BYTE; break; + case GL_RGB8: + rrb->base._ActualFormat = GL_RGB8; + rrb->base._BaseFormat = GL_RGB; + rrb->base.RedBits = 8; + rrb->base.GreenBits = 8; + rrb->base.BlueBits = 8; + rrb->base.AlphaBits = 8; + rrb->base.DataType = GL_UNSIGNED_BYTE; + break; case GL_RGBA8: rrb->base._ActualFormat = GL_RGBA8; rrb->base._BaseFormat = GL_RGBA; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 3817007e9e5..98fa1417f9a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1234,7 +1234,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, const GLboolean swAccum = mesaVis->accumRedBits > 0; const GLboolean swStencil = mesaVis->stencilBits > 0 && mesaVis->depthBits != 24; - GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); + GLenum rgbFormat; struct radeon_framebuffer *rfb; if (isPixmap) @@ -1246,6 +1246,13 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, _mesa_initialize_framebuffer(&rfb->base, mesaVis); + if (mesaVis->redBits == 5) + rgbFormat = GL_RGB5; + else if (mesaVis->alphaBits == 0) + rgbFormat = GL_RGB8; + else + rgbFormat = GL_RGBA8; + /* front color renderbuffer */ rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index d2211bcbcc6..b0c77be7bd3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -261,7 +261,11 @@ s8z24_to_z24s8(uint32_t val) #define TAG(x) radeon##x##_xRGB8888 #define TAG2(x,y) radeon##x##_xRGB8888##y -#define GET_PTR(X,Y) radeon_ptr32(rrb, (X) + x_off, (Y) + y_off) +#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) | 0xff000000)) +#define PUT_VALUE(_x, _y, d) { \ + GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + *_ptr = d; \ +} while (0) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions -- cgit v1.2.3 From d81a48757a9bde35299fd7c3cfbe83885238409a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 31 Mar 2009 15:50:19 +1000 Subject: radeon/dri2: if the depth buffer is 16-bit force cpp == 2 This is because the DDX always allocates using the drawable sizes. which gives me twice the depth buffer I asked for, dumb. --- src/mesa/drivers/dri/radeon/radeon_common_context.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 9964de7c7cc..5766c9ec7bc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -508,8 +508,11 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) } } - if (buffers[i].attachment == __DRI_BUFFER_DEPTH) + if (buffers[i].attachment == __DRI_BUFFER_DEPTH) { + if (draw->base.Visual.depthBits == 16) + rb->cpp = 2; depth_bo = bo; + } radeon_renderbuffer_set_bo(rb, bo); radeon_bo_unref(bo); -- cgit v1.2.3 From 6e30fe4873f30ccf9edec9ab6113ea647dccb9b7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 1 Apr 2009 15:41:58 +1000 Subject: radeon: fixup render buffer cleanups this fixes qtdemo-qt4 starting and a leak in glxgears exit --- .../drivers/dri/radeon/radeon_common_context.c | 40 +++--------------- src/mesa/drivers/dri/radeon/radeon_screen.c | 47 +++++++++++++--------- src/mesa/drivers/dri/radeon/radeon_screen.h | 1 + 3 files changed, 35 insertions(+), 53 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 5766c9ec7bc..9103c8c0f66 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -37,6 +37,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "vblank.h" #include "drirenderbuffer.h" +#include "main/framebuffer.h" #include "main/state.h" #define DRIVER_DATE "20090101" @@ -183,45 +184,14 @@ void radeonCleanupContext(radeonContextPtr radeon) #ifdef RADEON_BO_TRACK FILE *track; #endif - struct radeon_renderbuffer *rb; struct radeon_framebuffer *rfb; + radeonDestroyBuffer(radeon->dri.drawable); + radeonDestroyBuffer(radeon->dri.readable); + /* free the Mesa context */ _mesa_destroy_context(radeon->glCtx); - - rfb = (void*)radeon->dri.drawable->driverPrivate; - rb = rfb->color_rb[0]; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = rfb->color_rb[1]; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rfb = (void*)radeon->dri.readable->driverPrivate; - rb = rfb->color_rb[0]; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = rfb->color_rb[1]; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - + /* _mesa_destroy_context() might result in calls to functions that * depend on the DriverCtx, so don't set it to NULL before. * diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 98fa1417f9a..ea400a672dd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1296,28 +1296,39 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, return (driDrawPriv->driverPrivate != NULL); } -static void + +static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) +{ + struct radeon_renderbuffer *rb; + + rb = rfb->color_rb[0]; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = rfb->color_rb[1]; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } +} + +void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) { - struct radeon_renderbuffer *rb; struct radeon_framebuffer *rfb; - + if (!driDrawPriv) + return; + rfb = (void*)driDrawPriv->driverPrivate; - rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } + if (!rfb) + return; + radeon_cleanup_renderbuffers(rfb); _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 1c0f5bb9bc7..8605eb4f075 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -118,4 +118,5 @@ typedef struct radeon_screen { #define IS_R300_CLASS(screen) \ ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300) +extern void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv); #endif /* __RADEON_SCREEN_H__ */ -- cgit v1.2.3 From f9d272fa414ec04d9cc608840436f29e6adf84bc Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 1 Apr 2009 16:13:30 +1000 Subject: radeon: go back and repick texture formats. This might trip up some serious FBO users, will have to see, but it avoids the slow paths for all the demos I have. --- src/mesa/drivers/dri/r200/r200_tex.c | 2 +- src/mesa/drivers/dri/r200/r200_texstate.c | 2 +- src/mesa/drivers/dri/r300/r300_tex.c | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- src/mesa/drivers/dri/radeon/radeon_fbo.c | 107 ++++++++++++++------------ src/mesa/drivers/dri/radeon/radeon_tex.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texture.c | 21 +++-- src/mesa/drivers/dri/radeon/radeon_texture.h | 6 +- 9 files changed, 85 insertions(+), 61 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 19a6cad80bd..fc2caabb5ac 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -493,7 +493,7 @@ void r200InitTextureFuncs( struct dd_function_table *functions ) /* Note: we only plug in the functions we implement in the driver * since _mesa_init_driver_functions() was already called. */ - functions->ChooseTextureFormat = radeonChooseTextureFormat; + functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; functions->TexImage1D = radeonTexImage1D; functions->TexImage2D = radeonTexImage2D; #if ENABLE_HW_3D_TEXTURE diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 72b7f3dafa2..9797f77ec4f 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -839,7 +839,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, - type, format); + type, format, 0); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 0f5afbfa298..0cbb2bcf3f1 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -323,7 +323,7 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->MapTexture = radeonMapTexture; functions->UnmapTexture = radeonUnmapTexture; - functions->ChooseTextureFormat = radeonChooseTextureFormat; + functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; functions->TexImage1D = radeonTexImage1D; functions->TexImage2D = radeonTexImage2D; functions->TexImage3D = radeonTexImage3D; diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 0c6d092df36..baaca5f1e59 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -457,7 +457,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, - type, format); + type, format, 0); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index d17835bb12c..f62ca7f9eb3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -382,54 +382,65 @@ static GLboolean radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, struct gl_texture_image *texImage) { - if (texImage->TexFormat == &_mesa_texformat_argb8888) { - rrb->cpp = 4; - rrb->base._ActualFormat = GL_RGBA8; - rrb->base._BaseFormat = GL_RGBA; - rrb->base.DataType = GL_UNSIGNED_BYTE; - DBG("Render to RGBA8 texture OK\n"); - } - else if (texImage->TexFormat == &_mesa_texformat_rgb565) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_RGB5; - rrb->base._BaseFormat = GL_RGB; - rrb->base.DataType = GL_UNSIGNED_SHORT; - DBG("Render to RGB5 texture OK\n"); - } - else if (texImage->TexFormat == &_mesa_texformat_z16) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; - rrb->base._BaseFormat = GL_DEPTH_COMPONENT; - rrb->base.DataType = GL_UNSIGNED_SHORT; - DBG("Render to DEPTH16 texture OK\n"); - } - else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { - rrb->cpp = 4; - rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; - rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; - DBG("Render to DEPTH_STENCIL texture OK\n"); - } - else { - DBG("Render to texture BAD FORMAT %d\n", - texImage->TexFormat->MesaFormat); - return GL_FALSE; - } - - rrb->pitch = texImage->Width * rrb->cpp; - rrb->base.InternalFormat = rrb->base._ActualFormat; - rrb->base.Width = texImage->Width; - rrb->base.Height = texImage->Height; - rrb->base.RedBits = texImage->TexFormat->RedBits; - rrb->base.GreenBits = texImage->TexFormat->GreenBits; - rrb->base.BlueBits = texImage->TexFormat->BlueBits; - rrb->base.AlphaBits = texImage->TexFormat->AlphaBits; - rrb->base.DepthBits = texImage->TexFormat->DepthBits; - - rrb->base.Delete = radeon_delete_renderbuffer; - rrb->base.AllocStorage = radeon_nop_alloc_storage; - - return GL_TRUE; + int retry = 0; +restart: + if (texImage->TexFormat == &_mesa_texformat_argb8888) { + rrb->cpp = 4; + rrb->base._ActualFormat = GL_RGBA8; + rrb->base._BaseFormat = GL_RGBA; + rrb->base.DataType = GL_UNSIGNED_BYTE; + DBG("Render to RGBA8 texture OK\n"); + } + else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + rrb->cpp = 2; + rrb->base._ActualFormat = GL_RGB5; + rrb->base._BaseFormat = GL_RGB; + rrb->base.DataType = GL_UNSIGNED_SHORT; + DBG("Render to RGB5 texture OK\n"); + } + else if (texImage->TexFormat == &_mesa_texformat_z16) { + rrb->cpp = 2; + rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; + rrb->base._BaseFormat = GL_DEPTH_COMPONENT; + rrb->base.DataType = GL_UNSIGNED_SHORT; + DBG("Render to DEPTH16 texture OK\n"); + } + else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + rrb->cpp = 4; + rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; + rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; + DBG("Render to DEPTH_STENCIL texture OK\n"); + } + else { + /* try redoing the FBO */ + if (retry == 1) { + DBG("Render to texture BAD FORMAT %d\n", + texImage->TexFormat->MesaFormat); + return GL_FALSE; + } + texImage->TexFormat = radeonChooseTextureFormat(ctx, texImage->InternalFormat, 0, + texImage->TexFormat->DataType, + 1); + + retry++; + goto restart; + } + + rrb->pitch = texImage->Width * rrb->cpp; + rrb->base.InternalFormat = rrb->base._ActualFormat; + rrb->base.Width = texImage->Width; + rrb->base.Height = texImage->Height; + rrb->base.RedBits = texImage->TexFormat->RedBits; + rrb->base.GreenBits = texImage->TexFormat->GreenBits; + rrb->base.BlueBits = texImage->TexFormat->BlueBits; + rrb->base.AlphaBits = texImage->TexFormat->AlphaBits; + rrb->base.DepthBits = texImage->TexFormat->DepthBits; + + rrb->base.Delete = radeon_delete_renderbuffer; + rrb->base.AllocStorage = radeon_nop_alloc_storage; + + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 2dfb5042ecc..21509c6e5e7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -447,7 +447,7 @@ radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target ) void radeonInitTextureFuncs( struct dd_function_table *functions ) { - functions->ChooseTextureFormat = radeonChooseTextureFormat; + functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; functions->TexImage1D = radeonTexImage1D; functions->TexImage2D = radeonTexImage2D; functions->TexSubImage1D = radeonTexSubImage1D; diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index dab0df0ff3b..e4df33766eb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -710,7 +710,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, - type, format); + type, format, 0); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 21529f62fa5..35ed5424311 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -257,13 +257,13 @@ void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_objec /* try to find a format which will only need a memcopy */ static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, GLenum srcFormat, - GLenum srcType) + GLenum srcType, GLboolean fbo) { const GLuint ui = 1; const GLubyte littleEndian = *((const GLubyte *)&ui); /* r100 can only do this */ - if (IS_R100_CLASS(rmesa->radeonScreen)) + if (IS_R100_CLASS(rmesa->radeonScreen) || fbo) return _dri_texformat_argb8888; if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || @@ -288,10 +288,19 @@ static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPt return _dri_texformat_argb8888; } -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, +const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, GLint internalFormat, GLenum format, GLenum type) +{ + return radeonChooseTextureFormat(ctx, internalFormat, format, + type, 0); +} + +const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); const GLboolean do32bpt = @@ -323,7 +332,7 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_UNSIGNED_SHORT_1_5_5_5_REV: return _dri_texformat_argb1555; default: - return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type) : + return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type, fbo) : _dri_texformat_argb4444; } @@ -350,7 +359,7 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_RGBA12: case GL_RGBA16: return !force16bpt ? - radeonChoose8888TexFormat(rmesa, format,type) : + radeonChoose8888TexFormat(rmesa, format, type, fbo) : _dri_texformat_argb4444; case GL_RGBA4: @@ -510,7 +519,7 @@ static void radeon_teximage( } /* Choose and fill in the texture format for this image */ - texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type); + texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); _mesa_set_fetch_functions(texImage, dims); if (texImage->TexFormat->TexelBytes == 0) { diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h index d90fda7868f..888a55ba911 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.h +++ b/src/mesa/drivers/dri/radeon/radeon_texture.h @@ -40,10 +40,14 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); GLuint radeon_face_for_target(GLenum target); -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, +const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, GLint internalFormat, GLenum format, GLenum type); +const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo); void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, GLint internalFormat, -- cgit v1.2.3 From 617c5262c68b5fd4d26eff758b6447880478f83b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Apr 2009 11:30:03 +1100 Subject: r300: fix qtdemo qt4 startup --- src/mesa/drivers/dri/r300/r300_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 87ec68a2cd8..5e271c60104 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -498,7 +498,7 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) _vbo_DestroyContext(r300->radeon.glCtx); _swrast_DestroyContext(r300->radeon.glCtx); - rcommonFlushCmdBuf(&r300->radeon, __FUNCTION__); + radeon_firevertices(&r300->radeon); if (radeon->state.scissor.pClipRects) { FREE(radeon->state.scissor.pClipRects); -- cgit v1.2.3 From 104d5422052d0c03b121d196f7c0a8ef0af4ecab Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Apr 2009 13:35:09 +1000 Subject: radeon: tiling support --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 6 +++--- src/mesa/drivers/dri/r300/r300_ioctl.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index d85f106c112..fc8a2e74315 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -230,11 +230,11 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R300_COLOR_TILE_ENABLE; - BEGIN_BATCH_NO_AUTOSTATE(6); + BEGIN_BATCH_NO_AUTOSTATE(8); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); - OUT_BATCH(cbpitch); + OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); } @@ -282,7 +282,7 @@ static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom } OUT_BATCH(atom->cmd[0]); - atom->cmd[1] &= ~(3 << 0); + atom->cmd[1] &= ~0xf; atom->cmd[1] |= format; OUT_BATCH(atom->cmd[1]); OUT_BATCH(atom->cmd[2]); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 1314550e544..a7f5121da74 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -624,7 +624,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) /* HW depth */ if (mask & BUFFER_BIT_DEPTH) { - tri_mask |= BUFFER_BIT_DEPTH; + tri_mask |= BUFFER_BIT_DEPTH; } /* If we're doing a tri pass for depth/stencil, include a likely color -- cgit v1.2.3 From e00ef43d796f0ae0247b1072bf0aa8cdd8e3034d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Apr 2009 14:25:07 +1000 Subject: radeon/r200/r300: collapse context destruction down to a common path. Context destruction was nearly the same over all the drivers, so collapse it down. --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 96 ++++++++++----------- src/mesa/drivers/dri/r200/r200_context.c | 58 ------------- src/mesa/drivers/dri/r200/r200_context.h | 6 -- src/mesa/drivers/dri/r200/r200_maos.h | 1 - src/mesa/drivers/dri/r200/r200_maos_arrays.c | 24 ++---- src/mesa/drivers/dri/r200/r200_state.h | 4 - src/mesa/drivers/dri/r200/r200_state_init.c | 16 ---- src/mesa/drivers/dri/r200/r200_swtcl.c | 4 - src/mesa/drivers/dri/r200/r200_swtcl.h | 1 - src/mesa/drivers/dri/r200/r200_tcl.c | 16 ++-- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 13 --- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 2 - src/mesa/drivers/dri/r300/r300_context.c | 48 ----------- src/mesa/drivers/dri/r300/r300_context.h | 4 - src/mesa/drivers/dri/r300/r300_emit.c | 21 +---- src/mesa/drivers/dri/r300/r300_emit.h | 1 - src/mesa/drivers/dri/r300/r300_render.c | 98 +++++++++++----------- src/mesa/drivers/dri/radeon/Makefile | 3 +- .../drivers/dri/radeon/radeon_common_context.c | 90 +++++++++++++++----- .../drivers/dri/radeon/radeon_common_context.h | 12 ++- src/mesa/drivers/dri/radeon/radeon_context.c | 54 ++---------- src/mesa/drivers/dri/radeon/radeon_context.h | 24 ++---- src/mesa/drivers/dri/radeon/radeon_dma.c | 17 ++++ src/mesa/drivers/dri/radeon/radeon_dma.h | 1 + src/mesa/drivers/dri/radeon/radeon_ioctl.c | 76 ++++++++--------- src/mesa/drivers/dri/radeon/radeon_maos.h | 1 - src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 13 --- src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 29 ++----- src/mesa/drivers/dri/radeon/radeon_screen.c | 46 +++------- src/mesa/drivers/dri/radeon/radeon_state.h | 3 - src/mesa/drivers/dri/radeon/radeon_state_init.c | 16 ---- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 4 - src/mesa/drivers/dri/radeon/radeon_swtcl.h | 1 - src/mesa/drivers/dri/radeon/radeon_tcl.c | 8 +- 34 files changed, 286 insertions(+), 525 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 83375c88a70..3a11a448eca 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -143,18 +143,18 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset, - rmesa->tcl.elt_dma_bo, - rmesa->tcl.elt_dma_offset, + OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset, + rmesa->radeon.tcl.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count/2); } else { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH(rmesa->tcl.elt_dma_offset); + OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); OUT_BATCH(vertex_count/2); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); @@ -176,12 +176,12 @@ void r200FlushElts(GLcontext *ctx) nr = elt_used / 2; - radeon_bo_unmap(rmesa->tcl.elt_dma_bo); + radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); - radeon_bo_unref(rmesa->tcl.elt_dma_bo); - rmesa->tcl.elt_dma_bo = NULL; + radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo); + rmesa->radeon.tcl.elt_dma_bo = NULL; if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); @@ -203,14 +203,14 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, radeonEmitState(&rmesa->radeon); - rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, R200_ELT_BUF_SZ, 4, RADEON_GEM_DOMAIN_GTT, 0); - rmesa->tcl.elt_dma_offset = 0; + rmesa->radeon.tcl.elt_dma_offset = 0; rmesa->tcl.elt_used = min_nr * 2; - radeon_bo_map(rmesa->tcl.elt_dma_bo, 1); - retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; + radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); + retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; if (R200_DEBUG & DEBUG_PRIMS) @@ -264,79 +264,79 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i].bo, + rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[nr - 1].bo, + rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+0].bo, + rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[nr-1].bo, + rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 564e168290c..f80f0d8ac73 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -491,61 +491,3 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, } -/* Destroy the device specific context. - */ -/* Destroy the Mesa and driver specific context data. - */ -void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) -{ - GET_CURRENT_CONTEXT(ctx); - r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate; - r200ContextPtr current = ctx ? R200_CONTEXT(ctx) : NULL; - - /* check if we're deleting the currently bound context */ - if (rmesa == current) { - radeon_firevertices(&rmesa->radeon); - _mesa_make_current(NULL, NULL, NULL); - } - - /* Free r200 context resources */ - assert(rmesa); /* should never be null */ - if ( rmesa ) { - - _swsetup_DestroyContext( rmesa->radeon.glCtx ); - _tnl_DestroyContext( rmesa->radeon.glCtx ); - _vbo_DestroyContext( rmesa->radeon.glCtx ); - _swrast_DestroyContext( rmesa->radeon.glCtx ); - - r200DestroySwtcl( rmesa->radeon.glCtx ); - r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); - - if (rmesa->radeon.dma.current) { - radeonReleaseDmaRegion( &rmesa->radeon ); - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - } - - if (rmesa->radeon.state.scissor.pClipRects) { - FREE(rmesa->radeon.state.scissor.pClipRects); - rmesa->radeon.state.scissor.pClipRects = NULL; - } - - radeonCleanupContext(&rmesa->radeon); - - FREE( rmesa ); - } -} - - - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean -r200UnbindContext( __DRIcontextPrivate *driContextPriv ) -{ - r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate; - - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx); - - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index fcbe725d6fc..6267293817d 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -526,14 +526,8 @@ struct r200_state { struct r200_tcl_info { GLuint hw_primitive; -/* hw can handle 12 components max */ - struct radeon_aos aos[12]; - GLuint nr_aos_components; - GLuint *Elts; - struct radeon_bo *elt_dma_bo; - int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; }; diff --git a/src/mesa/drivers/dri/r200/r200_maos.h b/src/mesa/drivers/dri/r200/r200_maos.h index d3ed06d4021..16a70475e18 100644 --- a/src/mesa/drivers/dri/r200/r200_maos.h +++ b/src/mesa/drivers/dri/r200/r200_maos.h @@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_context.h" extern void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ); -extern void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ); #endif diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 5dbc202330b..383a0c4b0d3 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -142,17 +142,17 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) case 3: /* special handling to fix up fog. Will get us into trouble with vbos...*/ assert(attrib == VERT_ATTRIB_FOG); - if (!rmesa->tcl.aos[i].bo) { + if (!rmesa->radeon.tcl.aos[i].bo) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[nr]), + &(rmesa->radeon.tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, 1, VB->AttribPtr[attrib]->stride, count); else r200_emit_vecfog( ctx, - &(rmesa->tcl.aos[nr]), + &(rmesa->radeon.tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, VB->AttribPtr[attrib]->stride, count); @@ -199,9 +199,9 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) default: assert(0); } - if (!rmesa->tcl.aos[nr].bo) { + if (!rmesa->radeon.tcl.aos[nr].bo) { rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[nr]), + &(rmesa->radeon.tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, emitsize, VB->AttribPtr[attrib]->stride, @@ -220,18 +220,6 @@ after_emit: rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1; } - rmesa->tcl.nr_aos_components = nr; + rmesa->radeon.tcl.aos_count = nr; } - -void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - int i; - for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - if (rmesa->tcl.aos[i].bo) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; - } - } -} diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h index 1dddbfdbfed..23cf8aea667 100644 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ b/src/mesa/drivers/dri/r200/r200_state.h @@ -49,10 +49,6 @@ extern void r200UpdateDrawBuffer(GLcontext *ctx); extern GLboolean r200ValidateState( GLcontext *ctx ); -extern void r200PrintDirty( r200ContextPtr rmesa, - const char *msg ); - - extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define FALLBACK( rmesa, bit, mode ) do { \ if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \ diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 2400abe838b..75262e46bd8 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -166,22 +166,6 @@ static struct { /* ============================================================= * State initialization */ - -void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) -{ - struct radeon_state_atom *l; - - fprintf(stderr, msg); - fprintf(stderr, ": "); - - foreach(l, &rmesa->radeon.hw.atomlist) { - if (l->dirty || rmesa->radeon.hw.all_dirty) - fprintf(stderr, "%s, ", l->name); - } - - fprintf(stderr, "\n"); -} - static int cmdpkt( r200ContextPtr rmesa, int id ) { drm_radeon_cmd_header_t h; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index b006409987a..712da980775 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -908,7 +908,3 @@ void r200InitSwtcl( GLcontext *ctx ) rmesa->radeon.swtcl.hw_primitive = 0; } - -void r200DestroySwtcl( GLcontext *ctx ) -{ -} diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index a4051a4b768..b0905879d7a 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_context.h" extern void r200InitSwtcl( GLcontext *ctx ); -extern void r200DestroySwtcl( GLcontext *ctx ); extern void r200ChooseRenderState( GLcontext *ctx ); extern void r200ChooseVertexState( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 8e0fb14e70e..580370933ee 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -145,7 +145,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + + GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->tcl.elt_used); rmesa->tcl.elt_used += nr*2; @@ -156,10 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); + rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__); r200EmitAOS( rmesa, - rmesa->tcl.nr_aos_components, 0 ); + rmesa->radeon.tcl.aos_count, 0 ); return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); } @@ -186,13 +186,13 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); + // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count); rcommonEnsureCmdBufSpace( &rmesa->radeon, - AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + AOS_BUFSZ(rmesa->radeon.tcl.aos_count) + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); r200EmitAOS( rmesa, - rmesa->tcl.nr_aos_components, + rmesa->radeon.tcl.aos_count, start ); /* Why couldn't this packet have taken an offset param? @@ -481,7 +481,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Do the actual work: */ - r200ReleaseArrays( ctx, ~0 /* stage->changed_inputs */ ); + radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ ); r200EmitArrays( ctx, vimap_rev ); rmesa->tcl.Elts = VB->Elts; @@ -545,7 +545,7 @@ static void transition_to_swtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = _mesa_validate_all_lighting_tables; - r200ReleaseArrays( ctx, ~0 ); + radeonReleaseArrays( ctx, ~0 ); /* Still using the D3D based hardware-rasterizer from the radeon; * need to put the card into D3D mode to make it work: diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index fc8a2e74315..1ecbeea489f 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -649,16 +649,3 @@ void r300InitCmdBuf(r300ContextPtr r300) rcommonInitCmdBuf(&r300->radeon); } - -/** - * Destroy the command buffer and state atoms. - */ -void r300DestroyCmdBuf(r300ContextPtr r300) -{ - struct radeon_state_atom *atom; - - foreach(atom, &r300->radeon.hw.atomlist) { - FREE(atom->cmd); - } - -} diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index b7798eb97b3..3786813de36 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -39,8 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" extern void r300InitCmdBuf(r300ContextPtr r300); -extern void r300DestroyCmdBuf(r300ContextPtr r300); - void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5e271c60104..06db7ab8ff4 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -470,51 +470,3 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } -/* Destroy the device specific context. - */ -void r300DestroyContext(__DRIcontextPrivate * driContextPriv) -{ - GET_CURRENT_CONTEXT(ctx); - r300ContextPtr r300 = (r300ContextPtr) driContextPriv->driverPrivate; - radeonContextPtr radeon = (radeonContextPtr) r300; - radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; - - if (RADEON_DEBUG & DEBUG_DRI) { - fprintf(stderr, "Destroying context !\n"); - } - - /* check if we're deleting the currently bound context */ - if (&r300->radeon == current) { - radeonFlush(r300->radeon.glCtx); - _mesa_make_current(NULL, NULL, NULL); - } - - /* Free r300 context resources */ - assert(r300); /* should never be null */ - - if (r300) { - _swsetup_DestroyContext(r300->radeon.glCtx); - _tnl_DestroyContext(r300->radeon.glCtx); - _vbo_DestroyContext(r300->radeon.glCtx); - _swrast_DestroyContext(r300->radeon.glCtx); - - radeon_firevertices(&r300->radeon); - - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = NULL; - } - - r300DestroyCmdBuf(r300); - - radeonCleanupContext(&r300->radeon); - - - /* the memory manager might be accessed when Mesa frees the shared - * state, so don't destroy it earlier - */ - - - FREE(r300); - } -} diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 37718f5415d..5ef59d258e8 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -633,11 +633,7 @@ struct r300_state { struct r300_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; struct r300_vertex_shader_state vertex_shader; - struct radeon_aos aos[R300_MAX_AOS_ARRAYS]; - int aos_count; - struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ - int elt_dma_offset; /** Offset into this buffer object, in bytes */ DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. They are the same as tnl->render_inputs for fixed pipeline */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4bf0e7a1898..3ce0ba68c99 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -302,7 +302,7 @@ int r300EmitArrays(GLcontext * ctx) for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] = ci; } - rcommon_emit_vector(ctx, &rmesa->state.aos[i], + rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i], vb->AttribPtr[tab[i]]->data, vb->AttribPtr[tab[i]]->size, vb->AttribPtr[tab[i]]->stride, count); @@ -343,28 +343,11 @@ int r300EmitArrays(GLcontext * ctx) rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); - rmesa->state.aos_count = nr; + rmesa->radeon.tcl.aos_count = nr; return R300_FALLBACK_NONE; } -void r300ReleaseArrays(GLcontext * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - int i; - - if (rmesa->state.elt_dma_bo) { - radeon_bo_unref(rmesa->state.elt_dma_bo); - rmesa->state.elt_dma_bo = NULL; - } - for (i = 0; i < rmesa->state.aos_count; i++) { - if (rmesa->state.aos[i].bo) { - radeon_bo_unref(rmesa->state.aos[i].bo); - rmesa->state.aos[i].bo = NULL; - } - } -} - void r300EmitCacheFlush(r300ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 6bc8f8e9449..80c22d5e9ab 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -218,7 +218,6 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) extern int r300EmitArrays(GLcontext * ctx); -extern void r300ReleaseArrays(GLcontext * ctx); extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 829d088033a..924305dd128 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -175,12 +175,12 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) r300ContextPtr rmesa = R300_CONTEXT(ctx); void *out; - radeonAllocDmaRegion(&rmesa->radeon, &rmesa->state.elt_dma_bo, - &rmesa->state.elt_dma_offset, n_elts * 4, 4); - radeon_bo_map(rmesa->state.elt_dma_bo, 1); - out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; + radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, + &rmesa->radeon.tcl.elt_dma_offset, n_elts * 4, 4); + radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); + out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; memcpy(out, elts, n_elts * 4); - radeon_bo_unmap(rmesa->state.elt_dma_bo); + radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); } static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) @@ -199,19 +199,19 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | (R300_VAP_PORT_IDX0 >> 2)); - OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, - rmesa->state.elt_dma_bo, - rmesa->state.elt_dma_offset, + OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset, + rmesa->radeon.tcl.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count); } else { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | (R300_VAP_PORT_IDX0 >> 2)); - OUT_BATCH(rmesa->state.elt_dma_offset); + OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); OUT_BATCH(vertex_count); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); @@ -236,34 +236,34 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i].bo, + rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | - (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->state.aos[nr - 1].bo, + rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -276,45 +276,45 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | - (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+0].bo, + rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[nr-1].bo, + rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } @@ -370,10 +370,10 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, * arrays. *sigh* */ r300EmitElts(ctx, vb->Elts, num_verts); - r300EmitAOS(rmesa, rmesa->state.aos_count, start); + r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); r300FireEB(rmesa, num_verts, type); } else { - r300EmitAOS(rmesa, rmesa->state.aos_count, start); + r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); r300FireAOS(rmesa, num_verts, type); } COMMIT_BATCH(); @@ -408,7 +408,7 @@ static GLboolean r300RunRender(GLcontext * ctx, r300EmitCacheFlush(rmesa); - r300ReleaseArrays(ctx); + radeonReleaseArrays(ctx, ~0); return GL_FALSE; } diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index f469c6f43a1..ba409ba8130 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -19,7 +19,8 @@ RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_mipmap_tree.c \ - radeon_span.c + radeon_span.c \ + radeon_fbo.c DRIVER_SOURCES = \ radeon_context.c \ diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 9103c8c0f66..4d61b003454 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -37,8 +37,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "vblank.h" #include "drirenderbuffer.h" +#include "main/context.h" #include "main/framebuffer.h" #include "main/state.h" +#include "main/simple_list.h" +#include "swrast/swrast.h" +#include "swrast_setup/swrast_setup.h" +#include "tnl/tnl.h" #define DRIVER_DATE "20090101" @@ -175,39 +180,81 @@ GLboolean radeonInitContext(radeonContextPtr radeon, return GL_TRUE; } + + +/** + * Destroy the command buffer and state atoms. + */ +static void radeon_destroy_atom_list(radeonContextPtr radeon) +{ + struct radeon_state_atom *atom; + + foreach(atom, &radeon->hw.atomlist) { + FREE(atom->cmd); + if (atom->lastcmd) + FREE(atom->lastcmd); + } + +} + /** * Cleanup common context fields. * Called by r200DestroyContext/r300DestroyContext */ -void radeonCleanupContext(radeonContextPtr radeon) +void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) { #ifdef RADEON_BO_TRACK FILE *track; #endif - struct radeon_framebuffer *rfb; - - radeonDestroyBuffer(radeon->dri.drawable); - radeonDestroyBuffer(radeon->dri.readable); - - /* free the Mesa context */ - _mesa_destroy_context(radeon->glCtx); - - /* _mesa_destroy_context() might result in calls to functions that - * depend on the DriverCtx, so don't set it to NULL before. - * - * radeon->glCtx->DriverCtx = NULL; - */ - + GET_CURRENT_CONTEXT(ctx); + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; + if (radeon == current) { + radeon_firevertices(radeon); + _mesa_make_current(NULL, NULL, NULL); + } + + assert(radeon); + if (radeon) { - /* free the option cache */ - driDestroyOptionCache(&radeon->optionCache); + if (radeon->dma.current) { + radeonReleaseDmaRegion( radeon ); + rcommonFlushCmdBuf( radeon, __FUNCTION__ ); + } - rcommonDestroyCmdBuf(radeon); + radeonReleaseArrays(ctx, ~0); - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = 0; + if (radeon->vtbl.free_context) + radeon->vtbl.free_context(radeon->glCtx); + _swsetup_DestroyContext( radeon->glCtx ); + _tnl_DestroyContext( radeon->glCtx ); + _vbo_DestroyContext( radeon->glCtx ); + _swrast_DestroyContext( radeon->glCtx ); + + radeonDestroyBuffer(radeon->dri.drawable); + radeonDestroyBuffer(radeon->dri.readable); + + /* free atom list */ + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); + + /* _mesa_destroy_context() might result in calls to functions that + * depend on the DriverCtx, so don't set it to NULL before. + * + * radeon->glCtx->DriverCtx = NULL; + */ + /* free the option cache */ + driDestroyOptionCache(&radeon->optionCache); + + rcommonDestroyCmdBuf(radeon); + + radeon_destroy_atom_list(radeon); + + if (radeon->state.scissor.pClipRects) { + FREE(radeon->state.scissor.pClipRects); + radeon->state.scissor.pClipRects = 0; + } } #ifdef RADEON_BO_TRACK track = fopen("/tmp/tracklog", "w"); @@ -216,6 +263,7 @@ void radeonCleanupContext(radeonContextPtr radeon) fclose(track); } #endif + FREE(radeon); } /* Force the context `c' to be unbound from its buffer. diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 0ce72c91985..c6e6be74840 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -290,6 +290,14 @@ struct radeon_swtcl_info { }; +#define RADEON_MAX_AOS_ARRAYS 16 +struct radeon_tcl_info { + struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS]; + GLuint aos_count; + struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ + int elt_dma_offset; /** Offset into this buffer object, in bytes */ +}; + struct radeon_ioctl { GLuint vertex_offset; struct radeon_bo *bo; @@ -367,7 +375,6 @@ struct radeon_dri_mirror { #define DEBUG_MEMORY 0x4000 - typedef void (*radeon_tri_func) (radeonContextPtr, radeonVertex *, radeonVertex *, radeonVertex *); @@ -436,6 +443,7 @@ struct radeon_context { struct radeon_state state; struct radeon_swtcl_info swtcl; + struct radeon_tcl_info tcl; /* Configuration cache */ driOptionCache optionCache; @@ -468,6 +476,7 @@ struct radeon_context { void (*pre_emit_atoms)(radeonContextPtr rmesa); void (*pre_emit_state)(radeonContextPtr rmesa); void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode); + void (*free_context)(GLcontext *ctx); } vtbl; }; @@ -530,6 +539,7 @@ void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv); +extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); /* ================================================================ * Debugging: diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index cad2c3e0c1f..2600c78df39 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -188,6 +188,11 @@ static void r100_vtbl_pre_emit_state(radeonContextPtr radeon) radeon->hw.is_dirty = 1; } +static void r100_vtbl_free_context(GLcontext *ctx) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + _mesa_vector4f_free( &rmesa->tcl.ObjClean ); +} static void r100_init_vtbl(radeonContextPtr radeon) { @@ -202,7 +207,7 @@ static void r100_init_vtbl(radeonContextPtr radeon) /* Create the device specific context. */ GLboolean -radeonCreateContext( const __GLcontextModes *glVisual, +r100CreateContext( const __GLcontextModes *glVisual, __DRIcontextPrivate *driContextPriv, void *sharedContextPrivate) { @@ -397,50 +402,3 @@ radeonCreateContext( const __GLcontextModes *glVisual, } return GL_TRUE; } - - -/* Destroy the device specific context. - */ -/* Destroy the Mesa and driver specific context data. - */ -void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) -{ - GET_CURRENT_CONTEXT(ctx); - r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate; - r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL; - - /* check if we're deleting the currently bound context */ - if (rmesa == current) { - radeon_firevertices(&rmesa->radeon); - _mesa_make_current(NULL, NULL, NULL); - } - - /* Free radeon context resources */ - assert(rmesa); /* should never be null */ - if ( rmesa ) { - - _swsetup_DestroyContext( rmesa->radeon.glCtx ); - _tnl_DestroyContext( rmesa->radeon.glCtx ); - _vbo_DestroyContext( rmesa->radeon.glCtx ); - _swrast_DestroyContext( rmesa->radeon.glCtx ); - - radeonDestroySwtcl( rmesa->radeon.glCtx ); - radeonReleaseArrays( rmesa->radeon.glCtx, ~0 ); - if (rmesa->radeon.dma.current) { - radeonReleaseDmaRegion( &rmesa->radeon ); - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - } - - _mesa_vector4f_free( &rmesa->tcl.ObjClean ); - - if (rmesa->radeon.state.scissor.pClipRects) { - FREE(rmesa->radeon.state.scissor.pClipRects); - rmesa->radeon.state.scissor.pClipRects = NULL; - } - - radeonCleanupContext(&rmesa->radeon); - - FREE( rmesa ); - } -} - diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 5235a6e374c..1795d8bdb6d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -332,7 +332,7 @@ struct r100_state { #define R200_ELT_BUF_SZ (8*1024) /* radeon_tcl.c */ -struct radeon_tcl_info { +struct r100_tcl_info { GLuint vertex_format; GLuint hw_primitive; @@ -341,14 +341,9 @@ struct radeon_tcl_info { */ GLvector4f ObjClean; - struct radeon_aos aos[8]; - GLuint nr_aos_components; - GLuint *Elts; - struct radeon_bo *indexed_bo; - - int elt_cmd_offset; /** Offset into the cmdbuf */ + int elt_cmd_offset; int elt_cmd_start; int elt_used; }; @@ -416,7 +411,7 @@ struct r100_context { /* radeon_tcl.c */ - struct radeon_tcl_info tcl; + struct r100_tcl_info tcl; /* radeon_swtcl.c */ @@ -443,15 +438,10 @@ struct r100_context { #define RADEON_OLD_PACKETS 1 -extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); -extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate); -extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); -extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); - +extern GLboolean r100CreateContext( const __GLcontextModes *glVisual, + __DRIcontextPrivate *driContextPriv, + void *sharedContextPrivate); + #endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 01fc20bd796..47f789e9cd0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -328,3 +328,20 @@ restart: rmesa->swtcl.numverts += nverts; return head; } + +void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) +{ + radeonContextPtr radeon = RADEON_CONTEXT( ctx ); + int i; + + if (radeon->tcl.elt_dma_bo) { + radeon_bo_unref(radeon->tcl.elt_dma_bo); + radeon->tcl.elt_dma_bo = NULL; + } + for (i = 0; i < radeon->tcl.aos_count; i++) { + if (radeon->tcl.aos[i].bo) { + radeon_bo_unref(radeon->tcl.aos[i].bo); + radeon->tcl.aos[i].bo = NULL; + } + } +} diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.h b/src/mesa/drivers/dri/radeon/radeon_dma.h index cee3744fed1..06e388fc1de 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.h +++ b/src/mesa/drivers/dri/radeon/radeon_dma.h @@ -48,4 +48,5 @@ void radeonReleaseDmaRegion(radeonContextPtr rmesa); void rcommon_flush_last_swtcl_prim(GLcontext *ctx); void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index f18aa1a4dae..b5fde6d3de5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -313,9 +313,9 @@ void radeonEmitAOS( r100ContextPtr rmesa, { #if RADEON_OLD_PACKETS assert( nr == 1 ); - rmesa->ioctl.bo = rmesa->tcl.aos[0].bo; + rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; rmesa->ioctl.vertex_offset = - (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4); + (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); #else BATCH_LOCALS(&rmesa->radeon); uint32_t voffset; @@ -332,79 +332,79 @@ void radeonEmitAOS( r100ContextPtr rmesa, if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i].bo, + rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[nr - 1].bo, + rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+0].bo, + rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[nr-1].bo, + rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } diff --git a/src/mesa/drivers/dri/radeon/radeon_maos.h b/src/mesa/drivers/dri/radeon/radeon_maos.h index b8935e84a05..b88eb198d57 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos.h +++ b/src/mesa/drivers/dri/radeon/radeon_maos.h @@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" extern void radeonEmitArrays( GLcontext *ctx, GLuint inputs ); -extern void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index 7f5da16b03d..7c6ea0530e0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -324,16 +324,3 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) rmesa->tcl.vertex_format = vfmt; } - -void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) -{ - r100ContextPtr rmesa = R100_CONTEXT( ctx ); - int i; - - for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - if (rmesa->tcl.aos[i].bo) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; - } - } -} diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index d468a972006..78ec1193026 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -374,15 +374,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) break; if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && - rmesa->tcl.aos[0].bo) + rmesa->radeon.tcl.aos[0].bo) return; - if (rmesa->tcl.aos[0].bo) + if (rmesa->radeon.tcl.aos[0].bo) radeonReleaseArrays( ctx, ~0 ); radeonAllocDmaRegion( &rmesa->radeon, - &rmesa->tcl.aos[0].bo, - &rmesa->tcl.aos[0].offset, + &rmesa->radeon.tcl.aos[0].bo, + &rmesa->radeon.tcl.aos[0].offset, VB->Count * setup_tab[i].vertex_size * 4, 4); @@ -422,25 +422,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) setup_tab[i].emit( ctx, 0, VB->Count, - rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset); + rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset); - // rmesa->tcl.aos[0].size = setup_tab[i].vertex_size; - rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size; + // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size; + rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size; rmesa->tcl.vertex_format = setup_tab[i].vertex_format; - rmesa->tcl.nr_aos_components = 1; + rmesa->radeon.tcl.aos_count = 1; } - -void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) -{ - r100ContextPtr rmesa = R100_CONTEXT( ctx ); - int i; - - for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - if (rmesa->tcl.aos[i].bo) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; - } - } -} diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ea400a672dd..ecfdce9d014 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1332,7 +1332,6 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) /** * Choose the appropriate CreateContext function based on the chipset. * Eventually, all drivers will go through this process. @@ -1343,25 +1342,21 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, { __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); - +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) if (IS_R300_CLASS(screen)) return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); - return GL_FALSE; -} - -/** - * Choose the appropriate DestroyContext function based on the chipset. - */ -static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) -{ - radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; - - if (IS_R300_CLASS(radeon->radeonScreen)) - return r300DestroyContext(driContextPriv); -} +#endif +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) + return r200CreateContext(glVisual, driContextPriv, sharedContextPriv); +#endif +#if !RADEON_COMMON + return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); #endif + return GL_FALSE; +} /** @@ -1547,7 +1542,6 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) return 0; } -#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) const struct __DriverAPIRec driDriverAPI = { .InitScreen = radeonInitScreen, .DestroyScreen = radeonDestroyScreen, @@ -1567,24 +1561,4 @@ const struct __DriverAPIRec driDriverAPI = { /* DRI2 */ .InitScreen2 = radeonInitScreen2, }; -#else -const struct __DriverAPIRec driDriverAPI = { - .InitScreen = radeonInitScreen, - .DestroyScreen = radeonDestroyScreen, - .CreateContext = r200CreateContext, - .DestroyContext = r200DestroyContext, - .CreateBuffer = radeonCreateBuffer, - .DestroyBuffer = radeonDestroyBuffer, - .SwapBuffers = radeonSwapBuffers, - .MakeCurrent = radeonMakeCurrent, - .UnbindContext = radeonUnbindContext, - .GetSwapInfo = getSwapInfo, - .GetDrawableMSC = driDrawableGetMSC32, - .WaitForMSC = driWaitForMSC32, - .WaitForSBC = NULL, - .SwapBuffersMSC = NULL, - .CopySubBuffer = radeonCopySubBuffer, - .InitScreen2 = radeonInitScreen2, -}; -#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h index 17c2b112225..f05fa827d72 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.h +++ b/src/mesa/drivers/dri/radeon/radeon_state.h @@ -52,9 +52,6 @@ extern void radeonUploadTexMatrix( r100ContextPtr rmesa, extern void radeonValidateState( GLcontext *ctx ); -extern void radeonPrintDirty( r100ContextPtr rmesa, - const char *msg ); - extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define FALLBACK( rmesa, bit, mode ) do { \ diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 3d0cd8d3f86..174a7e1862f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -161,22 +161,6 @@ static struct { /* ============================================================= * State initialization */ - -void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) -{ - struct radeon_state_atom *l; - - fprintf(stderr, msg); - fprintf(stderr, ": "); - - foreach(l, &rmesa->radeon.hw.atomlist) { - if (l->dirty || rmesa->radeon.hw.all_dirty) - fprintf(stderr, "%s, ", l->name); - } - - fprintf(stderr, "\n"); -} - static int cmdpkt( r100ContextPtr rmesa, int id ) { drm_radeon_cmd_header_t h; diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 2484006f1c4..e31f045991c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -822,7 +822,3 @@ void radeonInitSwtcl( GLcontext *ctx ) rmesa->radeon.swtcl.hw_primitive = 0; } - -void radeonDestroySwtcl( GLcontext *ctx ) -{ -} diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.h b/src/mesa/drivers/dri/radeon/radeon_swtcl.h index 3ada9890b37..da89158eeb9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.h +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.h @@ -40,7 +40,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" extern void radeonInitSwtcl( GLcontext *ctx ); -extern void radeonDestroySwtcl( GLcontext *ctx ); extern void radeonChooseRenderState( GLcontext *ctx ); extern void radeonChooseVertexState( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 5887ab355d2..df6708f05e3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -150,10 +150,10 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) + - AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); + AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__); radeonEmitAOS( rmesa, - rmesa->tcl.nr_aos_components, 0 ); + rmesa->radeon.tcl.aos_count, 0 ); return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, rmesa->tcl.hw_primitive, nr ); @@ -177,11 +177,11 @@ static void radeonEmitPrim( GLcontext *ctx, radeonTclPrimitive( ctx, prim, hwprim ); rcommonEnsureCmdBufSpace( &rmesa->radeon, - AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + AOS_BUFSZ(rmesa->radeon.tcl.aos_count) + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); radeonEmitAOS( rmesa, - rmesa->tcl.nr_aos_components, + rmesa->radeon.tcl.aos_count, start ); /* Why couldn't this packet have taken an offset param? -- cgit v1.2.3 From 41702160090a4c1325afc07c56682f3e1c4fcaf0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Apr 2009 14:47:51 +1000 Subject: radeon/common: use glCtx not ctx --- src/mesa/drivers/dri/radeon/radeon_common_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 4d61b003454..ef67c86f0b8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -223,7 +223,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) rcommonFlushCmdBuf( radeon, __FUNCTION__ ); } - radeonReleaseArrays(ctx, ~0); + radeonReleaseArrays(radeon->glCtx, ~0); if (radeon->vtbl.free_context) radeon->vtbl.free_context(radeon->glCtx); -- cgit v1.2.3 From 05304d41f2d9ab7a66a8b976580c156b7b93a9d3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Apr 2009 18:58:49 +1000 Subject: radeon/r200/r300: fix up the whole buffer space checking. This fixes up the buffer validation scheme, so that we keep a list of buffers to validate so cmdbuf flushes during a pipeline get all the buffers revalidated on the next emit. This also fixes radeonFlush to not flush unless we have something useful to send to the GPU, like a DMA buffer or something not state --- src/mesa/drivers/dri/r200/r200_state.c | 48 ++++++------------- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 46 +++++------------- src/mesa/drivers/dri/radeon/radeon_common.c | 56 ++++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_common.h | 3 ++ .../drivers/dri/radeon/radeon_common_context.c | 1 - .../drivers/dri/radeon/radeon_common_context.h | 8 ++++ src/mesa/drivers/dri/radeon/radeon_dma.c | 25 ++-------- src/mesa/drivers/dri/radeon/radeon_state.c | 50 ++++++++++++++++++- src/mesa/drivers/dri/radeon/radeon_state.h | 2 +- 10 files changed, 149 insertions(+), 92 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index ca4dee8a5bc..f040713980f 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -2273,33 +2273,24 @@ static void update_texturematrix( GLcontext *ctx ) static GLboolean r200ValidateBuffers(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct radeon_cs_space_check bos[8]; struct radeon_renderbuffer *rrb; - int num_bo = 0; int i; - int flushed = 0, ret; -again: - num_bo = 0; + + radeon_validate_reset_bos(&rmesa->radeon); rrb = radeon_get_colorbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { - bos[num_bo].bo = rrb->bo; - bos[num_bo].read_domains = 0; - bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; - bos[num_bo].new_accounted = 0; - num_bo++; + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); } /* depth buffer */ rrb = radeon_get_depthbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { - bos[num_bo].bo = rrb->bo; - bos[num_bo].read_domains = 0; - bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; - bos[num_bo].new_accounted = 0; - num_bo++; + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); } for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { @@ -2307,26 +2298,17 @@ again: if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; - + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); - bos[num_bo].bo = t->mt->bo; - bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; - bos[num_bo].write_domain = 0; - bos[num_bo].new_accounted = 0; - num_bo++; + if (t->image_override && t->bo) + radeon_validate_bo(&rmesa->radeon, t->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + else if (t->mt->bo) + radeon_validate_bo(&rmesa->radeon, t->mt->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); } - - ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); - if (ret == RADEON_CS_SPACE_OP_TO_BIG) - return GL_FALSE; - if (ret == RADEON_CS_SPACE_FLUSH) { - radeonFlush(ctx); - if (flushed) - return GL_FALSE; - flushed = 1; - goto again; - } - return GL_TRUE; + + return radeon_revalidate_bos(ctx); } GLboolean r200ValidateState( GLcontext *ctx ) diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 3ce0ba68c99..bcf88038759 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -352,7 +352,7 @@ void r300EmitCacheFlush(r300ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); - BEGIN_BATCH(4); + BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index baaca5f1e59..5a87b5da43d 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -268,40 +268,29 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object return GL_TRUE; } - /** * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ GLboolean r300ValidateBuffers(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct radeon_cs_space_check bos[16]; struct radeon_renderbuffer *rrb; - int num_bo = 0; int i; - int flushed = 0, ret; -again: - num_bo = 0; + + radeon_validate_reset_bos(&rmesa->radeon); rrb = radeon_get_colorbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { - bos[num_bo].bo = rrb->bo; - bos[num_bo].read_domains = 0; - bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; - bos[num_bo].new_accounted = 0; - num_bo++; + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); } /* depth buffer */ rrb = radeon_get_depthbuffer(&rmesa->radeon); - /* color buffer */ if (rrb && rrb->bo) { - bos[num_bo].bo = rrb->bo; - bos[num_bo].read_domains = 0; - bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; - bos[num_bo].new_accounted = 0; - num_bo++; + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); } for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { @@ -317,26 +306,15 @@ again: } t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); if (t->image_override && t->bo) - bos[num_bo].bo = t->bo; + radeon_validate_bo(&rmesa->radeon, t->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + else if (t->mt->bo) - bos[num_bo].bo = t->mt->bo; - bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; - bos[num_bo].write_domain = 0; - bos[num_bo].new_accounted = 0; - num_bo++; + radeon_validate_bo(&rmesa->radeon, t->mt->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); } - ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); - if (ret == RADEON_CS_SPACE_OP_TO_BIG) - return GL_FALSE; - if (ret == RADEON_CS_SPACE_FLUSH) { - radeonFlush(ctx); - if (flushed) - return GL_FALSE; - flushed = 1; - goto again; - } - return GL_TRUE; + return radeon_revalidate_bos(ctx); } void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 3ce868d2cf3..4f7bfebf04f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -906,6 +906,49 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) COMMIT_BATCH(); } +GLboolean radeon_revalidate_bos(GLcontext *ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + int flushed = 0; + int ret; +again: + ret = radeon_cs_space_check(radeon->cmdbuf.cs, radeon->state.bos, radeon->state.validated_bo_count); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) + return GL_FALSE; + if (ret == RADEON_CS_SPACE_FLUSH) { + radeonFlush(ctx); + if (flushed) + return GL_FALSE; + flushed = 1; + goto again; + } + return GL_TRUE; +} + +void radeon_validate_reset_bos(radeonContextPtr radeon) +{ + int i; + + for (i = 0; i < radeon->state.validated_bo_count; i++) { + radeon->state.bos[i].bo = NULL; + radeon->state.bos[i].read_domains = 0; + radeon->state.bos[i].write_domain = 0; + radeon->state.bos[i].new_accounted = 0; + } + radeon->state.validated_bo_count = 0; +} + +void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) +{ + radeon->state.bos[radeon->state.validated_bo_count].bo = bo; + radeon->state.bos[radeon->state.validated_bo_count].read_domains = read_domains; + radeon->state.bos[radeon->state.validated_bo_count].write_domain = write_domain; + radeon->state.bos[radeon->state.validated_bo_count].new_accounted = 0; + radeon->state.validated_bo_count++; + + assert(radeon->state.validated_bo_count < RADEON_MAX_BOS); +} + void radeonEmitState(radeonContextPtr radeon) { if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) @@ -947,6 +990,14 @@ void radeonFlush(GLcontext *ctx) if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); + /* okay if we have no cmds in the buffer && + we have no DMA flush && + we have no DMA buffer allocated. + then no point flushing anything at all. + */ + if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && !radeon->dma.current) + return; + if (radeon->dma.flush) radeon->dma.flush( ctx ); @@ -1015,6 +1066,11 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) } radeon_cs_erase(rmesa->cmdbuf.cs); rmesa->cmdbuf.flushing = 0; + + if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE) { + fprintf(stderr,"failed to revalidate buffers\n"); + } + return ret; } diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index f3e2290cab8..c2fbb0950d5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -47,6 +47,9 @@ void radeon_get_cliprects(radeonContextPtr radeon, struct drm_clip_rect **cliprects, unsigned int *num_cliprects, int *x_off, int *y_off); +GLboolean radeon_revalidate_bos(GLcontext *ctx); +void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain); +void radeon_validate_reset_bos(radeonContextPtr radeon); void radeon_fbo_init(struct radeon_context *radeon); void diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index ef67c86f0b8..ba74c97f2cb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -219,7 +219,6 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) if (radeon) { if (radeon->dma.current) { - radeonReleaseDmaRegion( radeon ); rcommonFlushCmdBuf( radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index c6e6be74840..d32e5af5441 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -13,6 +13,10 @@ #include "dri_util.h" #include "tnl/t_vertex.h" +struct radeon_context; + +#include "radeon_bocs_wrapper.h" + /* This union is used to avoid warnings/miscompilation with float to uint32_t casts due to strict-aliasing */ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; @@ -384,11 +388,15 @@ typedef void (*radeon_line_func) (radeonContextPtr, typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); +#define RADEON_MAX_BOS 24 struct radeon_state { struct radeon_colorbuffer_state color; struct radeon_depthbuffer_state depth; struct radeon_scissor_state scissor; struct radeon_stencilbuffer_state stencil; + + struct radeon_cs_space_check bos[RADEON_MAX_BOS]; + int validated_bo_count; }; /** diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 47f789e9cd0..5ffee86e5a3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -163,8 +163,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) { - struct radeon_cs_space_check bos[1]; - int flushed = 0, ret; size = MAX2(size, MAX_DMA_BUF_SZ * 16); @@ -200,24 +198,11 @@ again_alloc: rmesa->dma.current_used = 0; rmesa->dma.current_vertexptr = 0; - bos[0].bo = rmesa->dma.current; - bos[0].read_domains = RADEON_GEM_DOMAIN_GTT; - bos[0].write_domain =0 ; - bos[0].new_accounted = 0; - - ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1); - if (ret == RADEON_CS_SPACE_OP_TO_BIG) { - fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen"); - assert(0); - } else if (ret == RADEON_CS_SPACE_FLUSH) { - rcommonFlushCmdBuf(rmesa, __FUNCTION__); - if (flushed) { - fprintf(stderr,"flushed but still no space\n"); - assert(0); - } - flushed = 1; - goto again_alloc; - } + radeon_validate_bo(rmesa, rmesa->dma.current, RADEON_GEM_DOMAIN_GTT, 0); + + if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE) + fprintf(stderr,"failure to revalidate BOs - badness\n"); + radeon_bo_map(rmesa->dma.current, 1); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 19ff2688e6e..dcca326c667 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" +#include "radeon_mipmap_tree.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_tcl.h" @@ -2043,8 +2044,48 @@ static void update_texturematrix( GLcontext *ctx ) } } +static GLboolean r100ValidateBuffers(GLcontext *ctx) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + struct radeon_renderbuffer *rrb; + int i; + + radeon_validate_reset_bos(&rmesa->radeon); + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); + } + + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); + } -void radeonValidateState( GLcontext *ctx ) + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + + if (!ctx->Texture.Unit[i]._ReallyEnabled) + continue; + + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + if (t->image_override && t->bo) + radeon_validate_bo(&rmesa->radeon, t->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + else if (t->mt->bo) + radeon_validate_bo(&rmesa->radeon, t->mt->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + } + + return radeon_revalidate_bos(ctx); +} + +GLboolean radeonValidateState( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint new_state = rmesa->radeon.NewGLState; @@ -2061,6 +2102,10 @@ void radeonValidateState( GLcontext *ctx ) new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */ } + /* we need to do a space check here */ + if (!r100ValidateBuffers(ctx)) + return GL_FALSE; + /* Need an event driven matrix update? */ if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) @@ -2136,7 +2181,8 @@ static void radeonWrapRunPipeline( GLcontext *ctx ) /* Validate state: */ if (rmesa->radeon.NewGLState) - radeonValidateState( ctx ); + if (!radeonValidateState( ctx )) + FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE); has_material = (ctx->Light.Enabled && check_material( ctx )); diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h index f05fa827d72..a7c8eef32a5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.h +++ b/src/mesa/drivers/dri/radeon/radeon_state.h @@ -50,7 +50,7 @@ extern void radeonUpdateDrawBuffer( GLcontext *ctx ); extern void radeonUploadTexMatrix( r100ContextPtr rmesa, int unit, GLboolean swapcols ); -extern void radeonValidateState( GLcontext *ctx ); +extern GLboolean radeonValidateState( GLcontext *ctx ); extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ); -- cgit v1.2.3 From 741aaaa2881e5ab60cfa55f081f7b9ca6f4de46b Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 3 Apr 2009 15:15:22 +0200 Subject: radeon: add support for new ttm --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 18 +++++++++++ src/mesa/drivers/dri/radeon/radeon_common.c | 8 +++-- src/mesa/drivers/dri/radeon/radeon_screen.c | 50 +++++++++++++++++------------ src/mesa/drivers/dri/radeon/radeon_span.c | 12 ++++--- 4 files changed, 60 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 1ecbeea489f..2dd2c6a4df1 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -236,6 +236,24 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); + OUT_BATCH(0); + OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) | + (rrb->height << R300_SCISSORS_Y_SHIFT)); + END_BATCH(); + } else { + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); + OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) | + (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) | + ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT)); + END_BATCH(); + } + } } static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 4f7bfebf04f..a5b8d3253f8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -377,9 +377,11 @@ void radeonWaitForIdleLocked(radeonContextPtr radeon) static void radeonWaitForIdle(radeonContextPtr radeon) { - LOCK_HARDWARE(radeon); - radeonWaitForIdleLocked(radeon); - UNLOCK_HARDWARE(radeon); + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + LOCK_HARDWARE(radeon); + radeonWaitForIdleLocked(radeon); + UNLOCK_HARDWARE(radeon); + } } static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb) diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ecfdce9d014..49c7eae6d2c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -246,15 +246,31 @@ extern const struct dri_extension mm_extensions[]; static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); static int -radeonGetParam(int fd, int param, void *value) +radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) { int ret; drm_radeon_getparam_t gp; + struct drm_radeon_info info; + + if (sPriv->drm_version.major >= 2) { + info.value = (uint64_t)value; + switch (param) { + case RADEON_PARAM_DEVICE_ID: + info.request = RADEON_INFO_DEVICE_ID; + break; + case RADEON_PARAM_NUM_GB_PIPES: + info.request = RADEON_INFO_NUM_GB_PIPES; + break; + default: + return -EINVAL; + } + ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); + } else { + gp.param = param; + gp.value = value; - gp.param = param; - gp.value = value; - - ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + } return ret; } @@ -767,8 +783,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) int ret; #ifdef RADEON_PARAM_KERNEL_MM - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, - &screen->kernel_mm); + ret = radeonGetParam(sPriv, RADEON_PARAM_KERNEL_MM, &screen->kernel_mm); if (ret && ret != -EINVAL) { FREE( screen ); @@ -780,7 +795,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->kernel_mm = 0; #endif - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, + ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, &screen->gart_buffer_offset); if (ret) { @@ -789,7 +804,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return NULL; } - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, + ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, &screen->gart_base); if (ret) { FREE( screen ); @@ -797,7 +812,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return NULL; } - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, + ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq); if (ret) { FREE( screen ); @@ -898,8 +913,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->cpp = dri_priv->bpp / 8; screen->AGPMode = dri_priv->AGPMode; - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, - &temp); + ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; @@ -913,8 +927,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) } if (screen->chip_family >= CHIP_FAMILY_R300) { - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, - &temp); + ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); if (ret) { fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); switch (screen->chip_family) { @@ -1069,11 +1082,9 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) screen->kernel_mm = 1; screen->chip_flags = 0; - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, - &screen->irq); + ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq); - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, - &device_id); + ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); if (ret) { FREE( screen ); fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); @@ -1085,8 +1096,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) return NULL; if (screen->chip_family >= CHIP_FAMILY_R300) { - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, - &temp); + ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); if (ret) { fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); switch (screen->chip_family) { diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index b0c77be7bd3..e28f28662b4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -503,9 +503,10 @@ static void radeonSpanRenderStart(GLcontext * ctx) * unnecessary due to the fact that mapping our buffers, textures, etc. * should implicitly wait for any previous rendering commands that must * be waited on. */ - LOCK_HARDWARE(rmesa); - radeonWaitForIdleLocked(rmesa); - + if (!rmesa->radeonScreen->driScreen->dri2.enabled) { + LOCK_HARDWARE(rmesa); + radeonWaitForIdleLocked(rmesa); + } for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); @@ -522,8 +523,9 @@ static void radeonSpanRenderFinish(GLcontext * ctx) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); int i; _swrast_flush(ctx); - UNLOCK_HARDWARE(rmesa); - + if (!rmesa->radeonScreen->driScreen->dri2.enabled) { + UNLOCK_HARDWARE(rmesa); + } for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); -- cgit v1.2.3 From 23478f1c037c3c97ebf3a5f53f2dfbfa31a9b197 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 6 Apr 2009 20:37:11 +1000 Subject: radeon: fix bocs wrapper --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index cb354c5117b..9921d350e30 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -2,7 +2,7 @@ #define RADEON_CS_WRAPPER_H #ifndef RADEON_PARAM_DEVICE_ID -#define RADEON_PARAM_DEVICE_ID 17 +#define RADEON_PARAM_DEVICE_ID 16 #endif #ifdef HAVE_LIBDRM_RADEON -- cgit v1.2.3 From 86556f8bdab2c59a33619ecfda011bce8f047acb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 7 Apr 2009 15:05:53 +1000 Subject: radeon/r200/r300: fix missing dma buffer validation this make gnome shell run --- src/mesa/drivers/dri/r200/r200_state.c | 3 +++ src/mesa/drivers/dri/r300/r300_texstate.c | 2 ++ src/mesa/drivers/dri/radeon/radeon_common.c | 4 ---- src/mesa/drivers/dri/radeon/radeon_state.c | 4 ++++ 4 files changed, 9 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index f040713980f..1b9724d6429 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -2308,6 +2308,9 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx) RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); } + if (rmesa->radeon.dma.current) + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.dma.current, RADEON_GEM_DOMAIN_GTT, 0); + return radeon_revalidate_bos(ctx); } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 5a87b5da43d..cf4cad73d29 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -313,6 +313,8 @@ GLboolean r300ValidateBuffers(GLcontext * ctx) radeon_validate_bo(&rmesa->radeon, t->mt->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); } + if (rmesa->radeon.dma.current) + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.dma.current, RADEON_GEM_DOMAIN_GTT, 0); return radeon_revalidate_bos(ctx); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index a5b8d3253f8..756c09fff3b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -789,14 +789,10 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) */ void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) { - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - radeon_firevertices(radeon); /* don't pipeline cliprect changes */ - radeon_draw_buffer(ctx, ctx->DrawBuffer); } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index dcca326c667..28eea444377 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2082,6 +2082,10 @@ static GLboolean r100ValidateBuffers(GLcontext *ctx) RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); } + if (rmesa->radeon.dma.current) + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.dma.current, + RADEON_GEM_DOMAIN_GTT, 0); + return radeon_revalidate_bos(ctx); } -- cgit v1.2.3 From e2ce1d80d10d700cf15b84d0ec1605875226629e Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Tue, 7 Apr 2009 21:08:40 +1000 Subject: r300: swtcl rewrite and cleanup - remove unused variables - silence compiler warnings - fix twosided lighting - fix point attenuation - unify indentation --- src/mesa/drivers/dri/r300/r300_context.h | 17 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 445 ++++++++++++++++--------------- src/mesa/drivers/dri/r300/r300_swtcl.h | 16 ++ 3 files changed, 250 insertions(+), 228 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 5ef59d258e8..86e68e35fc6 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -656,6 +656,16 @@ struct r300_swtcl_info { * Offset of the 3UB specular color data within a hardware (swtcl) vertex. */ GLuint specoffset; + + struct vertex_attribute{ + GLuint attr; + GLubyte format; + GLubyte dst_loc; + GLuint swizzle; + GLubyte write_mask; + } vert_attrs[VERT_ATTRIB_MAX]; + + GLubyte vertex_attr_count; }; @@ -678,17 +688,10 @@ struct r300_context { GLboolean disable_lowimpact_fallback; - DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ - struct r300_swtcl_info swtcl; GLboolean vap_flush_needed; }; -struct r300_buffer_object { - struct gl_buffer_object mesa_obj; - int id; -}; - #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx)) extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index f57516acf41..d8a68f7fc5e 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -28,38 +28,16 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* * Authors: * Dave Airlie + * Maciej Cencora */ -/* derived from r200 swtcl path */ - - - -#include "main/glheader.h" -#include "main/mtypes.h" -#include "main/colormac.h" -#include "main/enums.h" -#include "main/image.h" -#include "main/imports.h" -#include "main/light.h" -#include "main/macros.h" - -#include "swrast/s_context.h" -#include "swrast/s_fog.h" -#include "swrast_setup/swrast_setup.h" -#include "math/m_translate.h" #include "tnl/tnl.h" -#include "tnl/t_context.h" #include "tnl/t_pipeline.h" -#include "r300_context.h" #include "r300_swtcl.h" -#include "r300_state.h" -#include "r300_ioctl.h" #include "r300_emit.h" #include "r300_tex.h" -void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset); -void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr); #define EMIT_ATTR( ATTR, STYLE ) \ do { \ rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ @@ -75,27 +53,93 @@ do { \ rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) -static void r300SetVertexFormat( GLcontext *ctx ) +#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask) \ +do { \ + attrs[num_attrs].attr = (_attr); \ + attrs[num_attrs].format = (_format); \ + attrs[num_attrs].dst_loc = (_dst_loc); \ + attrs[num_attrs].swizzle = (_swizzle); \ + attrs[num_attrs].write_mask = (_write_mask); \ + ++num_attrs; \ +} while (0) + +static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - DECLARE_RENDERINPUTS(index_bitset); - GLuint InputsRead = 0, OutputsWritten = 0; - int vap_fmt_1 = 0; - int offset = 0; + struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; int vte = 0; - int fog_id; - GLint inputs[VERT_ATTRIB_MAX]; - GLint tab[VERT_ATTRIB_MAX]; - int swizzle[VERT_ATTRIB_MAX][4]; - GLuint i, nr; - GLuint sz; - - DECLARE_RENDERINPUTS(render_inputs_bitset); - RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset); - RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset ); - RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset); + int i, j, reg_count; + uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; + uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; + + for (i = 0; i < R300_VIR_CMDSIZE-1; ++i) + vir0[i] = vir1[i] = 0; + + for (i = 0, j = 0; i < rmesa->radeon.swtcl.vertex_attr_count; ++i) { + int tmp, data_format; + switch (attrs[i].format) { + case EMIT_1F: + data_format = R300_DATA_TYPE_FLOAT_1; + break; + case EMIT_2F: + data_format = R300_DATA_TYPE_FLOAT_2; + break; + case EMIT_3F: + data_format = R300_DATA_TYPE_FLOAT_3; + break; + case EMIT_4F: + data_format = R300_DATA_TYPE_FLOAT_4; + break; + case EMIT_4UB_4F_RGBA: + case EMIT_4UB_4F_ABGR: + data_format = R300_DATA_TYPE_BYTE | R300_NORMALIZE; + break; + default: + fprintf(stderr, "%s: Invalid data format type", __FUNCTION__); + _mesa_exit(-1); + break; + } + + tmp = data_format | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT); + if (i % 2 == 0) { + vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT; + vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT); + } else { + vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT; + vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; + ++j; + } + } + + reg_count = (rmesa->radeon.swtcl.vertex_attr_count + 1) >> 1; + if (rmesa->radeon.swtcl.vertex_attr_count % 2 != 0) { + vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; + } else { + vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; + } + + R300_STATECHANGE(rmesa, vir[0]); + R300_STATECHANGE(rmesa, vir[1]); + R300_STATECHANGE(rmesa, vof); + R300_STATECHANGE(rmesa, vte); + R300_STATECHANGE(rmesa, vic); + + if (rmesa->radeon.radeonScreen->kernel_mm) { + rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[0].cmd[0] |= (reg_count & 0x3FFF) << 16; + rmesa->hw.vir[1].cmd[0] |= (reg_count & 0x3FFF) << 16; + } else { + ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = reg_count; + ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count; + } + + rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); + rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); + rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); + rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); vte = rmesa->hw.vte.cmd[1]; vte &= ~(R300_VTX_XY_FMT | R300_VTX_Z_FMT | R300_VTX_W0_FMT); @@ -111,52 +155,74 @@ static void r300SetVertexFormat( GLcontext *ctx ) } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); + + rmesa->hw.vte.cmd[1] = vte; + rmesa->hw.vte.cmd[2] = rmesa->radeon.swtcl.vertex_size; +} + + +static void r300SetVertexFormat( GLcontext *ctx ) +{ + r300ContextPtr rmesa = R300_CONTEXT( ctx ); + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *VB = &tnl->vb; + int fog_id = -1; + GLuint InputsRead = 0; + GLuint OutputsWritten = 0; + int num_attrs = 0; + struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; + + rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0; rmesa->radeon.swtcl.vertex_attr_count = 0; - /* EMIT_ATTR's must be in order as they tell t_vertex.c how to - * build up a hardware vertex. - */ - if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POS)) { - sz = VB->AttribPtr[VERT_ATTRIB_POS]->size; + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS)) { InputsRead |= 1 << VERT_ATTRIB_POS; OutputsWritten |= 1 << VERT_RESULT_HPOS; - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_1F + sz - 1 ); - offset = sz; - } else { - offset = 4; - EMIT_PAD(4 * sizeof(float)); + EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); + ADD_ATTR(VERT_ATTRIB_POS, EMIT_4F, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW); + rmesa->swtcl.coloroffset = 4; } -/* - if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POINTSIZE )) { - EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F ); - offset += 1; - } -*/ - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR0)) { - sz = VB->AttribPtr[VERT_ATTRIB_COLOR0]->size; - rmesa->swtcl.coloroffset = offset; + + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR0)) { InputsRead |= 1 << VERT_ATTRIB_COLOR0; OutputsWritten |= 1 << VERT_RESULT_COL0; - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_1F + sz - 1 ); - offset += sz; +#if MESA_LITTLE_ENDIAN + EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA ); + ADD_ATTR(VERT_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW); +#else + EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR ); + ADD_ATTR(VERT_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW); +#endif } - rmesa->swtcl.specoffset = 0; - if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) { - sz = VB->AttribPtr[VERT_ATTRIB_COLOR1]->size; - rmesa->swtcl.specoffset = offset; - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_1F + sz - 1 ); + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 )) { + GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); InputsRead |= 1 << VERT_ATTRIB_COLOR1; OutputsWritten |= 1 << VERT_RESULT_COL1; +#if MESA_LITTLE_ENDIAN + EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA ); + ADD_ATTR(VERT_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR1, swiz, MASK_XYZW); +#else + EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR ); + ADD_ATTR(VERT_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR1, swiz, MASK_XYZW); +#endif + rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1; + } + + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) { + GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); + InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE; + OutputsWritten |= 1 << VERT_RESULT_PSIZ; + EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F ); + ADD_ATTR(VERT_ATTRIB_POINT_SIZE, EMIT_1F, SWTCL_OVM_POINT_SIZE, swiz, MASK_X); } - fog_id = -1; - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) { + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_FOG)) { /* find first free tex coord slot */ - if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { + if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { int i; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (!RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) { + if (!RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { fog_id = i; break; } @@ -170,37 +236,56 @@ static void r300SetVertexFormat( GLcontext *ctx ) _mesa_exit(-1); } - sz = VB->AttribPtr[VERT_ATTRIB_FOG]->size; - EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F + sz - 1); InputsRead |= 1 << VERT_ATTRIB_FOG; OutputsWritten |= 1 << VERT_RESULT_FOGC; - vap_fmt_1 |= sz << (3 * fog_id); + GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); + EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F ); + ADD_ATTR(VERT_ATTRIB_FOG, EMIT_1F, SWTCL_OVM_TEX(fog_id), swiz, MASK_X); } - if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { + if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { int i; - + GLuint swiz, mask, format; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) { - sz = VB->TexCoordPtr[i]->size; + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { + switch (VB->TexCoordPtr[i]->size) { + case 1: + case 2: + format = EMIT_2F; + swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO); + mask = MASK_X | MASK_Y; + break; + case 3: + format = EMIT_3F; + swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); + mask = MASK_X | MASK_Y | MASK_Z; + break; + case 4: + format = EMIT_4F; + swiz = SWIZZLE_XYZW; + mask = MASK_XYZW; + break; + default: + continue; + } InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); - EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_1F + sz - 1 ); - vap_fmt_1 |= sz << (3 * i); + EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); + ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, mask); } } } /* RS can't put fragment position on the pixel stack, so stuff it in texcoord if needed */ - if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POS) && (ctx->FragmentProgram._Current->Base.InputsRead & FRAG_BIT_WPOS)) { + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS) && (ctx->FragmentProgram._Current->Base.InputsRead & FRAG_BIT_WPOS)) { int first_free_tex = -1; if (fog_id >= 0) { first_free_tex = fog_id+1; } else { - if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { + if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { int i; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (!RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) { + if (!RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { first_free_tex = i; break; } @@ -215,83 +300,14 @@ static void r300SetVertexFormat( GLcontext *ctx ) _mesa_exit(-1); } - sz = VB->AttribPtr[VERT_ATTRIB_POS]->size; InputsRead |= 1 << (VERT_ATTRIB_TEX0 + first_free_tex); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + first_free_tex); - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_1F + sz - 1 ); - vap_fmt_1 |= sz << (3 * first_free_tex); - } - - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) { - inputs[i] = nr++; - } else { - inputs[i] = -1; - } - } - - /* Fixed, apply to vir0 only */ - if (InputsRead & (1 << VERT_ATTRIB_POS)) - inputs[VERT_ATTRIB_POS] = 0; - if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) - inputs[VERT_ATTRIB_COLOR0] = 2; - if (InputsRead & (1 << VERT_ATTRIB_COLOR1)) - inputs[VERT_ATTRIB_COLOR1] = 3; - if (InputsRead & (1 << VERT_ATTRIB_FOG)) - inputs[VERT_ATTRIB_FOG] = 6 + fog_id; - for (i = VERT_ATTRIB_TEX0; i <= VERT_ATTRIB_TEX7; i++) - if (InputsRead & (1 << i)) - inputs[i] = 6 + (i - VERT_ATTRIB_TEX0); - - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) { - tab[nr++] = i; - } - } - - for (i = 0; i < nr; i++) { - int ci; - - swizzle[i][0] = SWIZZLE_ZERO; - swizzle[i][1] = SWIZZLE_ZERO; - swizzle[i][2] = SWIZZLE_ZERO; - swizzle[i][3] = SWIZZLE_ONE; - - for (ci = 0; ci < VB->AttribPtr[tab[i]]->size; ci++) { - swizzle[i][ci] = ci; - } + EMIT_ATTR( _TNL_ATTRIB_TEX(first_free_tex), EMIT_4F ); + ADD_ATTR(VERT_ATTRIB_TEX0 + first_free_tex, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); } R300_NEWPRIM(rmesa); - if (rmesa->radeon.radeonScreen->kernel_mm) { - R300_STATECHANGE(rmesa, vir[0]); - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= - (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], - VB->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; - R300_STATECHANGE(rmesa, vir[1]); - rmesa->hw.vir[1].cmd[0] |= - (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, - nr) & 0x3FFF) << 16; - } else { - R300_STATECHANGE(rmesa, vir[0]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = - r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], - VB->AttribPtr, inputs, tab, nr); - R300_STATECHANGE(rmesa, vir[1]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = - r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, - nr); - } - - R300_STATECHANGE(rmesa, vic); - rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - - R300_STATECHANGE(rmesa, vof); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_fmt_1; + r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten); rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, @@ -301,30 +317,25 @@ static void r300SetVertexFormat( GLcontext *ctx ) rmesa->radeon.swtcl.vertex_size /= 4; - RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset ); - - - R300_STATECHANGE(rmesa, vte); - rmesa->hw.vte.cmd[1] = vte; - rmesa->hw.vte.cmd[2] = rmesa->radeon.swtcl.vertex_size; + RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, tnl->render_inputs_bitset); } + static GLuint reduced_prim[] = { - GL_POINTS, - GL_LINES, - GL_LINES, - GL_LINES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, + GL_POINTS, + GL_LINES, + GL_LINES, + GL_LINES, + GL_TRIANGLES, + GL_TRIANGLES, + GL_TRIANGLES, + GL_TRIANGLES, + GL_TRIANGLES, + GL_TRIANGLES, }; static void r300RasterPrimitive( GLcontext *ctx, GLuint prim ); static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); -//static void r300ResetLineStipple( GLcontext *ctx ); /*********************************************************************** * Emit primitives as inline vertices * @@ -353,8 +364,6 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); const char *r300verts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int))) #define VERTEX r300Vertex -#define DO_DEBUG_VERTS (1 && (RADEON_DEBUG & DEBUG_VERTS)) -#define PRINT_VERTEX(x) #undef TAG #define TAG(x) r300_##x #include "tnl_dd/t_dd_triemit.h" @@ -411,31 +420,37 @@ static struct { #define AREA_IS_CCW( a ) (a < 0) #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) -/* Only used to pull back colors into vertices (ie, we know color is - * floating point). - */ -#define R300_COLOR( dst, src ) \ -do { \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[0], (src)[2]); \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[1], (src)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[2], (src)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[3], (src)[3]); \ +#define VERT_SET_RGBA( v, c ) \ +do { \ + r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \ + UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ + UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ + UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ + UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \ } while (0) -#define VERT_SET_RGBA( v, c ) if (coloroffset) R300_COLOR( v->ub4[coloroffset], c ) -#define VERT_COPY_RGBA( v0, v1 ) if (coloroffset) v0->ui[coloroffset] = v1->ui[coloroffset] -#define VERT_SAVE_RGBA( idx ) if (coloroffset) color[idx] = v[idx]->ui[coloroffset] -#define VERT_RESTORE_RGBA( idx ) if (coloroffset) v[idx]->ui[coloroffset] = color[idx] +#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset] -#define R300_SPEC( dst, src ) \ -do { \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[0], (src)[2]); \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[1], (src)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE((dst)[2], (src)[0]); \ +#define VERT_SET_SPEC( v0, c ) \ +do { \ + if (specoffset) { \ + UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.red, (c)[0]); \ + UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.green, (c)[1]); \ + UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.blue, (c)[2]); \ + } \ } while (0) -#define VERT_SET_SPEC( v, c ) if (specoffset) R300_SPEC( v->ub4[specoffset], c ) -#define VERT_COPY_SPEC( v0, v1 ) if (specoffset) COPY_3V(v0->ub4[specoffset], v1->ub4[specoffset]) +#define VERT_COPY_SPEC( v0, v1 ) \ +do { \ + if (specoffset) { \ + v0->v.specular.red = v1->v.specular.red; \ + v0->v.specular.green = v1->v.specular.green; \ + v0->v.specular.blue = v1->v.specular.blue; \ + } \ +} while (0) + +#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset] +#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx] #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset] #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx] @@ -445,7 +460,7 @@ do { \ #define LOCAL_VARS(n) \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ + GLuint color[n] = { 0, }, spec[n] = { 0, }; \ GLuint coloroffset = rmesa->swtcl.coloroffset; \ GLuint specoffset = rmesa->swtcl.specoffset; \ (void) color; (void) spec; (void) coloroffset; (void) specoffset; @@ -569,8 +584,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) static void r300RenderStart(GLcontext *ctx) { - r300ContextPtr rmesa = R300_CONTEXT( ctx ); - // fprintf(stderr, "%s\n", __FUNCTION__); + r300ContextPtr rmesa = R300_CONTEXT( ctx ); r300ChooseRenderState(ctx); r300SetVertexFormat(ctx); @@ -586,7 +600,6 @@ static void r300RenderStart(GLcontext *ctx) if (rmesa->radeon.dma.flush != NULL) { rmesa->radeon.dma.flush(ctx); } - } static void r300RenderFinish(GLcontext *ctx) @@ -598,7 +611,7 @@ static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) r300ContextPtr rmesa = R300_CONTEXT(ctx); if (rmesa->radeon.swtcl.hw_primitive != hwprim) { - R300_NEWPRIM( rmesa ); + R300_NEWPRIM( rmesa ); rmesa->radeon.swtcl.hw_primitive = hwprim; } } @@ -610,17 +623,13 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) rmesa->radeon.swtcl.render_primitive = prim; if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED)) - return; + return; r300RasterPrimitive( ctx, reduced_prim[prim] ); - // fprintf(stderr, "%s\n", __FUNCTION__); - } static void r300ResetLineStipple(GLcontext *ctx) { - - } void r300InitSwtcl(GLcontext *ctx) @@ -653,22 +662,16 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); - RENDERINPUTS_ZERO( rmesa->tnl_index_bitset ); _tnl_need_projected_coords( ctx, GL_FALSE ); r300ChooseRenderState(ctx); - - _mesa_validate_all_lighting_tables( ctx ); - - tnl->Driver.NotifyMaterialChange = - _mesa_validate_all_lighting_tables; } void r300DestroySwtcl(GLcontext *ctx) { } -void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) +static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { BATCH_LOCALS(&rmesa->radeon); @@ -684,7 +687,7 @@ void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_b END_BATCH(); } -void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) +static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) { BATCH_LOCALS(&rmesa->radeon); int type, num_verts; @@ -700,20 +703,20 @@ void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r300ContextPtr rmesa = R300_CONTEXT(ctx); - rcommonEnsureCmdBufSpace(&rmesa->radeon, + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - radeonEmitState(&rmesa->radeon); - r300EmitVertexAOS(rmesa, - rmesa->radeon.swtcl.vertex_size, - rmesa->radeon.dma.current, - current_offset); - - r300EmitVbufPrim(rmesa, + radeonEmitState(&rmesa->radeon); + r300EmitVertexAOS(rmesa, + rmesa->radeon.swtcl.vertex_size, + rmesa->radeon.dma.current, + current_offset); + + r300EmitVbufPrim(rmesa, rmesa->radeon.swtcl.hw_primitive, rmesa->radeon.swtcl.numverts); - r300EmitCacheFlush(rmesa); - COMMIT_BATCH(); + r300EmitCacheFlush(rmesa); + COMMIT_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index 23b4ce34698..ebc99c9e8a7 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -39,6 +39,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r300_context.h" +#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) +#define MASK_X R300_WRITE_ENA_X +#define MASK_Y R300_WRITE_ENA_Y +#define MASK_Z R300_WRITE_ENA_Z +#define MASK_W R300_WRITE_ENA_W + +/* + * Here are definitions of OVM locations of vertex attributes for non TCL hw + */ +#define SWTCL_OVM_POS 0 +#define SWTCL_OVM_COLOR0 2 +#define SWTCL_OVM_COLOR1 3 +#define SWTCL_OVM_TEX(n) ((n) + 6) +#define SWTCL_OVM_POINT_SIZE 15 + + extern void r300InitSwtcl( GLcontext *ctx ); extern void r300DestroySwtcl( GLcontext *ctx ); -- cgit v1.2.3 From 90ffce497395d8c02fee2ea4ee4c025eede3d876 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 7 Apr 2009 12:37:10 -0400 Subject: radeon: fix compiler warning --- src/mesa/drivers/dri/radeon/radeon_state.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 28eea444377..80cfdaa2bff 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2142,6 +2142,8 @@ GLboolean radeonValidateState( GLcontext *ctx ) rmesa->radeon.NewGLState = 0; + + return GL_TRUE; } -- cgit v1.2.3 From 3b1d5440015c2bfa76d91bd8bb3954bde48f4815 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Tue, 7 Apr 2009 23:51:28 +0200 Subject: r300: fix regression from swtcl rewrite Fix wrong attribute emit and revert to previous behaviour of calculating VAP_OUT_VTX_FMT_1 register value. We can't use r300VAPOutputCntl1 function because it assumes that all texture coords have 4 components and that is the case for HW TCL path, but not for SW TCL. --- src/mesa/drivers/dri/r300/r300_swtcl.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index ca91cf750b5..fce34eac22a 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -63,7 +63,7 @@ do { \ ++num_attrs; \ } while (0) -static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) +static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten, GLuint vap_out_fmt_1) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); @@ -139,7 +139,12 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); + /** + * Can't use r300VAPOutputCntl1 function because it assumes + * that all texture coords have 4 components and that's the case + * for HW TCL path, but not for SW TCL. + */ + rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_out_fmt_1; vte = rmesa->hw.vte.cmd[1]; vte &= ~(R300_VTX_XY_FMT | R300_VTX_Z_FMT | R300_VTX_W0_FMT); @@ -166,7 +171,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) r300ContextPtr rmesa = R300_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - int fog_id = -1; + int fog_id = -1, vap_out_fmt_1 = 0; GLuint InputsRead = 0; GLuint OutputsWritten = 0; int num_attrs = 0; @@ -241,10 +246,11 @@ static void r300SetVertexFormat( GLcontext *ctx ) GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F ); ADD_ATTR(VERT_ATTRIB_FOG, EMIT_1F, SWTCL_OVM_TEX(fog_id), swiz, MASK_X); + vap_out_fmt_1 |= 1 << (fog_id * 3); } if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i; + int i, size; GLuint swiz, mask, format; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { @@ -254,16 +260,19 @@ static void r300SetVertexFormat( GLcontext *ctx ) format = EMIT_2F; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO); mask = MASK_X | MASK_Y; + size = 2; break; case 3: format = EMIT_3F; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); mask = MASK_X | MASK_Y | MASK_Z; + size = 3; break; case 4: format = EMIT_4F; swiz = SWIZZLE_XYZW; mask = MASK_XYZW; + size = 4; break; default: continue; @@ -272,6 +281,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, mask); + vap_out_fmt_1 |= size << (i * 3); } } } @@ -302,12 +312,13 @@ static void r300SetVertexFormat( GLcontext *ctx ) InputsRead |= 1 << (VERT_ATTRIB_TEX0 + first_free_tex); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + first_free_tex); - EMIT_ATTR( _TNL_ATTRIB_TEX(first_free_tex), EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_TEX0 + first_free_tex, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); + EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); + ADD_ATTR(VERT_ATTRIB_POS, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); + vap_out_fmt_1 |= 4 << (first_free_tex * 3); } R300_NEWPRIM(rmesa); - r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten); + r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten, vap_out_fmt_1); rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, -- cgit v1.2.3 From 1ec0efa7d3a7fb0f3f81b83677c415cf835a7efc Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 8 Apr 2009 00:47:16 +0200 Subject: r300: reorder fog coordinate and WPOS fp attributes HW TCL path currently assumed fog, WPOS order. The order was inverted for SW TCL path. This hopefully fixes rest of fog and WPOS related bugs. Additionally fix some indentation, don't route unnecessary components of fog coordinates for performance reasons and simplify vertex attribute emitting for SW TCL path. --- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_state.c | 32 ++++++++--------- src/mesa/drivers/dri/r300/r300_swtcl.c | 64 ++++++++++------------------------ 3 files changed, 35 insertions(+), 63 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index bcf88038759..4fd6ba9b91a 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -191,7 +191,7 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) fprintf(stderr, "\tout of free texcoords to write fog coord\n"); _mesa_exit(-1); } - ret |= 4 << (3 * first_free_texcoord); + ret |= 1 << (3 * first_free_texcoord); } return ret; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 6796d36d4cd..46c3df70991 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1510,9 +1510,9 @@ static void r300SetupRSUnit(GLcontext * ctx) /* with TCL we always seem to route 4 components */ if (hw_tcl_on) - count = 4; + count = 4; else - count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size; + count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size; switch(count) { case 4: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break; @@ -1530,12 +1530,22 @@ static void r300SetupRSUnit(GLcontext * ctx) ++fp_reg; } + if (InputsRead & FRAG_BIT_WPOS) { + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); + r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); + InputsRead &= ~FRAG_BIT_WPOS; + rs_tex_count += 4; + ++tex_ip; + ++fp_reg; + } + if (InputsRead & FRAG_BIT_FOGC) { if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(R300_RS_SEL_K0) | R300_RS_SEL_R(R300_RS_SEL_K0); + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_Q(R300_RS_SEL_K1) | R300_RS_TEX_PTR(rs_tex_count); r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_FOGC; - rs_tex_count += 4; + rs_tex_count += 1; ++tex_ip; ++fp_reg; } else { @@ -1543,16 +1553,6 @@ static void r300SetupRSUnit(GLcontext * ctx) } } - if (InputsRead & FRAG_BIT_WPOS) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_WPOS; - rs_tex_count += 4; - ++tex_ip; - ++fp_reg; - } - InputsRead &= ~FRAG_BIT_WPOS; - /* Setup default color if no color or tex was set */ if (rs_tex_count == 0 && col_ip == 0) { r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001); @@ -1560,10 +1560,10 @@ static void r300SetupRSUnit(GLcontext * ctx) } high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; + r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; r300->hw.rc.cmd[2] |= high_rr - 1; - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr); if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index fce34eac22a..03c1521de7e 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -171,7 +171,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) r300ContextPtr rmesa = R300_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - int fog_id = -1, vap_out_fmt_1 = 0; + int first_free_tex = 0, vap_out_fmt_1 = 0; GLuint InputsRead = 0; GLuint OutputsWritten = 0; int num_attrs = 0; @@ -222,33 +222,6 @@ static void r300SetVertexFormat( GLcontext *ctx ) ADD_ATTR(VERT_ATTRIB_POINT_SIZE, EMIT_1F, SWTCL_OVM_POINT_SIZE, swiz, MASK_X); } - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_FOG)) { - /* find first free tex coord slot */ - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (!RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { - fog_id = i; - break; - } - } - } else { - fog_id = 0; - } - - if (fog_id == -1) { - fprintf(stderr, "\tout of free texcoords to do fog\n"); - _mesa_exit(-1); - } - - InputsRead |= 1 << VERT_ATTRIB_FOG; - OutputsWritten |= 1 << VERT_RESULT_FOGC; - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); - EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F ); - ADD_ATTR(VERT_ATTRIB_FOG, EMIT_1F, SWTCL_OVM_TEX(fog_id), swiz, MASK_X); - vap_out_fmt_1 |= 1 << (fog_id * 3); - } - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { int i, size; GLuint swiz, mask, format; @@ -282,30 +255,14 @@ static void r300SetVertexFormat( GLcontext *ctx ) EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, mask); vap_out_fmt_1 |= size << (i * 3); + ++first_free_tex; } } } /* RS can't put fragment position on the pixel stack, so stuff it in texcoord if needed */ if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS) && (ctx->FragmentProgram._Current->Base.InputsRead & FRAG_BIT_WPOS)) { - int first_free_tex = -1; - if (fog_id >= 0) { - first_free_tex = fog_id+1; - } else { - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (!RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { - first_free_tex = i; - break; - } - } - } else { - first_free_tex = 0; - } - } - - if (first_free_tex == -1) { + if (first_free_tex >= ctx->Const.MaxTextureUnits) { fprintf(stderr, "\tout of free texcoords to write w pos\n"); _mesa_exit(-1); } @@ -315,6 +272,21 @@ static void r300SetVertexFormat( GLcontext *ctx ) EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); ADD_ATTR(VERT_ATTRIB_POS, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); vap_out_fmt_1 |= 4 << (first_free_tex * 3); + ++first_free_tex; + } + + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_FOG)) { + if (first_free_tex >= ctx->Const.MaxTextureUnits) { + fprintf(stderr, "\tout of free texcoords to write fog coordinate\n"); + _mesa_exit(-1); + } + + InputsRead |= 1 << VERT_ATTRIB_FOG; + OutputsWritten |= 1 << VERT_RESULT_FOGC; + GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); + EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F ); + ADD_ATTR(VERT_ATTRIB_FOG, EMIT_1F, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_X); + vap_out_fmt_1 |= 1 << (first_free_tex * 3); } R300_NEWPRIM(rmesa); -- cgit v1.2.3 From 5e361c47abf2ee20140628d327eda9b39351d415 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 9 Apr 2009 10:51:10 +1000 Subject: r300: fix color tiling --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 2dd2c6a4df1..c575c9ac496 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -214,6 +214,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) struct radeon_renderbuffer *rrb; uint32_t cbpitch; uint32_t offset = r300->radeon.state.color.draw_offset; + uint32_t dw = 6; rrb = radeon_get_colorbuffer(&r300->radeon); if (!rrb || !rrb->bo) { @@ -230,11 +231,16 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R300_COLOR_TILE_ENABLE; - BEGIN_BATCH_NO_AUTOSTATE(8); + if (r300->radeon.radeonScreen->kernel_mm) + dw += 2; + BEGIN_BATCH_NO_AUTOSTATE(dw); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); - OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); + if (!r300->radeon.radeonScreen->kernel_mm) + OUT_BATCH(cbpitch); + else + OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { -- cgit v1.2.3 From 8181f8fbf9c3d0f60191ee874248b8113b215e30 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 12 Apr 2009 13:11:06 +0200 Subject: radeon: emit scissor when using cs path --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 174a7e1862f..c00f59f7ad2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -448,6 +448,17 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) // } END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); + OUT_BATCH(0); + OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); + if (rrb) { + OUT_BATCH(((rrb->width - 1) << RADEON_RE_WIDTH_SHIFT) | + ((rrb->height - 1) << RADEON_RE_HEIGHT_SHIFT)); + } else { + OUT_BATCH(0); + } + END_BATCH(); } static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) -- cgit v1.2.3 From 02b130fd4b1c4c35ed256fc345eead010db09205 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 12 Apr 2009 14:25:36 +0200 Subject: r200: validate vertex buffer --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 3a11a448eca..e34ea9655e0 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -209,6 +209,11 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, rmesa->radeon.tcl.elt_dma_offset = 0; rmesa->tcl.elt_used = min_nr * 2; + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.tcl.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0); + if (radeon_revalidate_bos(rmesa->radeon.glCtx) == GL_FALSE) + fprintf(stderr,"failure to revalidate BOs - badness\n"); + radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; -- cgit v1.2.3 From 1fd76ae930d20a241d534a86c489d92df9b051d3 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 12 Apr 2009 15:51:31 +0200 Subject: r200: fix texture level for compiz case --- src/mesa/drivers/dri/r200/r200_texstate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 9797f77ec4f..15758d767cf 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1422,8 +1422,8 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d ) */ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) { - const struct gl_texture_image *firstImage = - t->base.Image[0][t->mt->firstLevel]; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + const struct gl_texture_image *firstImage = t->base.Image[0][firstlevel]; GLint log2Width, log2Height, log2Depth, texelBytes; if ( t->bo ) { -- cgit v1.2.3 From 143b416af6662995059cd5209a750dbace78081c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 16 Apr 2009 13:06:08 +1000 Subject: radeon: take a bo reference when adding to validate list --- src/mesa/drivers/dri/radeon/radeon_common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 756c09fff3b..2449795ea94 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -928,6 +928,7 @@ void radeon_validate_reset_bos(radeonContextPtr radeon) int i; for (i = 0; i < radeon->state.validated_bo_count; i++) { + radeon_bo_unref(radeon->state.bos[i].bo); radeon->state.bos[i].bo = NULL; radeon->state.bos[i].read_domains = 0; radeon->state.bos[i].write_domain = 0; @@ -938,6 +939,7 @@ void radeon_validate_reset_bos(radeonContextPtr radeon) void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) { + radeon_bo_ref(bo); radeon->state.bos[radeon->state.validated_bo_count].bo = bo; radeon->state.bos[radeon->state.validated_bo_count].read_domains = read_domains; radeon->state.bos[radeon->state.validated_bo_count].write_domain = write_domain; -- cgit v1.2.3 From 3264352c577ce1d6681e70abd76624ede906df71 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 16 Apr 2009 13:06:24 +1000 Subject: dri: attempt to actually refcount the __DRIDrawable valgrind was showing a race between the drawable getting destroyed by the X resource freeing code, and the context getting destroyed later and freeing the drawable. However I've no idea if some other combination of things could cause this code to leak. --- src/mesa/drivers/dri/common/dri_util.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index 38c2e7b00d1..0ec4adc2325 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -37,6 +37,9 @@ typedef GLboolean ( * PFNGLXGETMSCRATEOMLPROC) (__DRIdrawable *drawable, int32_t *numerator, int32_t *denominator); #endif +static void dri_get_drawable(__DRIdrawable *pdp); +static void dri_put_drawable(__DRIdrawable *pdp); + /** * This is just a token extension used to signal that the driver * supports setting a read drawable. @@ -127,7 +130,7 @@ static int driUnbindContext(__DRIcontext *pcp) return GL_FALSE; } - pdp->refcount--; + dri_put_drawable(pdp); if (prp != pdp) { if (prp->refcount == 0) { @@ -135,7 +138,7 @@ static int driUnbindContext(__DRIcontext *pcp) return GL_FALSE; } - prp->refcount--; + dri_put_drawable(prp); } @@ -170,10 +173,10 @@ static int driBindContext(__DRIcontext *pcp, pcp->driReadablePriv = prp; if (pdp) { pdp->driContextPriv = pcp; - pdp->refcount++; + dri_get_drawable(pdp); } if ( prp && pdp != prp ) { - prp->refcount++; + dri_get_drawable(prp); } } @@ -430,7 +433,7 @@ driCreateNewDrawable(__DRIscreen *psp, const __DRIconfig *config, pdp->loaderPrivate = data; pdp->hHWDrawable = hwDrawable; - pdp->refcount = 0; + pdp->refcount = 1; pdp->pStamp = NULL; pdp->lastStamp = 0; pdp->index = 0; @@ -483,12 +486,19 @@ dri2CreateNewDrawable(__DRIscreen *screen, return pdraw; } - -static void -driDestroyDrawable(__DRIdrawable *pdp) +static void dri_get_drawable(__DRIdrawable *pdp) +{ + pdp->refcount++; +} + +static void dri_put_drawable(__DRIdrawable *pdp) { __DRIscreenPrivate *psp; + pdp->refcount--; + if (pdp->refcount) + return; + if (pdp) { psp = pdp->driScreenPriv; (*psp->DriverAPI.DestroyBuffer)(pdp); @@ -504,6 +514,12 @@ driDestroyDrawable(__DRIdrawable *pdp) } } +static void +driDestroyDrawable(__DRIdrawable *pdp) +{ + dri_put_drawable(pdp); +} + /*@}*/ -- cgit v1.2.3 From a92bc56e2428e4219e0eaaa6f142c6cc60fee710 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 16 Apr 2009 12:38:39 +0200 Subject: r300: update r500 path for reordered WPOS and FOG fp attributes Report and regression testing by Fabio Pedretti. --- src/mesa/drivers/dri/r300/r300_state.c | 36 +++++++++++++++++----------------- 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 46c3df70991..f464335422f 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1701,16 +1701,29 @@ static void r500SetupRSUnit(GLcontext * ctx) ++fp_reg; } + if (InputsRead & FRAG_BIT_WPOS) { + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | + ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | + ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | + ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); + + r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); + InputsRead &= ~FRAG_BIT_WPOS; + rs_tex_count += 4; + ++tex_ip; + ++fp_reg; + } + if (InputsRead & FRAG_BIT_FOGC) { if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | - ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | - ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | - ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= (rs_tex_count << R500_RS_IP_TEX_PTR_S_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_FOGC; - rs_tex_count += 4; + rs_tex_count += 1; ++tex_ip; ++fp_reg; } else { @@ -1718,19 +1731,6 @@ static void r500SetupRSUnit(GLcontext * ctx) } } - if (InputsRead & FRAG_BIT_WPOS) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | - ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | - ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | - ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_WPOS; - rs_tex_count += 4; - ++tex_ip; - ++fp_reg; - } - /* Setup default color if no color or tex was set */ if (rs_tex_count == 0 && col_ip == 0) { r300->hw.rr.cmd[R300_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001); -- cgit v1.2.3 From d7d5c97a215e6845ffa9fc60cee52da6a2d3148a Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 16 Apr 2009 17:50:13 +0200 Subject: r300: cleanup frag prog setup a little Use proper fields for marking if fp is translated, and if is translated succesfully. Now if fp gets translated (even unsuccesfully) fp->translated is true. If the translation failed (i.e. because we exceeded limit of maximum texture indirections) the fp->error is set. With a little updated fallback function it prevents non native fragment programs from beeing translated with every frame (the translation would fail anyway so there's no point to try again). Also implement IsProgramNative function for GL_FRAGMENT_PROGRAM_ARB (it should give some performance boost in apps that checks if program is native and falls back to simpler shader to meet hw limits if necessary) and cleanup indentation (remove whitespaces on empty lines). --- src/mesa/drivers/dri/r300/r300_fragprog.c | 6 ++-- src/mesa/drivers/dri/r300/r300_render.c | 32 +++++++++---------- src/mesa/drivers/dri/r300/r300_shader.c | 21 ++++++++++++- src/mesa/drivers/dri/r300/r300_state.c | 52 +++++++++++++++---------------- src/mesa/drivers/dri/r300/r500_fragprog.c | 7 +++-- 5 files changed, 70 insertions(+), 48 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 32182bb6674..f2d7cec5d36 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -175,7 +175,7 @@ static GLboolean transform_TEX( inst.SrcReg[0].File = PROGRAM_TEMPORARY; inst.SrcReg[0].Index = tmpreg; } - + tgt = radeonAppendInstructions(t->Program, 1); _mesa_copy_instructions(tgt, &inst, 1); @@ -466,8 +466,8 @@ void r300TranslateFragmentShader(r300ContextPtr r300, _mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL); - if (!fp->error) - fp->translated = GL_TRUE; + fp->translated = GL_TRUE; + if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) r300FragmentProgramDump(fp, &fp->code); r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 924305dd128..d33396e150a 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -194,7 +194,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) ((vertex_count + 0) << 16) | type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - + if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | @@ -224,12 +224,12 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) uint32_t voffset; int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; - + if (RADEON_DEBUG & DEBUG_VERTS) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); - + if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(sz+2+(nr * 2)); OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); @@ -240,7 +240,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - + voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, @@ -256,7 +256,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) RADEON_GEM_DOMAIN_GTT, 0, 0); } - + if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); @@ -280,7 +280,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - + voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); @@ -288,7 +288,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } - + if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); @@ -427,7 +427,7 @@ static int r300Fallback(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); const unsigned back = ctx->Stencil._BackFace; - + FALLBACK_IF(r300->radeon.Fallback); /* Do we need to use new-style shaders? * Also is there a better way to do this? */ @@ -435,19 +435,19 @@ static int r300Fallback(GLcontext * ctx) struct r500_fragment_program *fp = (struct r500_fragment_program *) (char *)ctx->FragmentProgram._Current; if (fp) { - if (!fp->translated) { + if (!fp->translated) r500TranslateFragmentShader(r300, fp); - FALLBACK_IF(!fp->translated); - } + + FALLBACK_IF(fp->error); } } else { struct r300_fragment_program *fp = (struct r300_fragment_program *) (char *)ctx->FragmentProgram._Current; if (fp) { - if (!fp->translated) { + if (!fp->translated) r300TranslateFragmentShader(r300, fp); - FALLBACK_IF(!fp->translated); - } + + FALLBACK_IF(fp->error); } } @@ -492,7 +492,7 @@ static GLboolean r300RunNonTCLRender(GLcontext * ctx, if (!r300ValidateBuffers(ctx)) return GL_TRUE; - + return r300RunRender(ctx, stage); } @@ -517,7 +517,7 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, if (!r300ValidateBuffers(ctx)) return GL_TRUE; - + r300UpdateShaders(rmesa); vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_shader.c b/src/mesa/drivers/dri/r300/r300_shader.c index f30fd986e0f..d90658ba478 100644 --- a/src/mesa/drivers/dri/r300/r300_shader.c +++ b/src/mesa/drivers/dri/r300/r300_shader.c @@ -81,7 +81,26 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) static GLboolean r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) { - return GL_TRUE; + if (target == GL_FRAGMENT_PROGRAM_ARB) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); + + if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog; + + if (!r500_fp->translated) + r500TranslateFragmentShader(rmesa, r500_fp); + + return !r500_fp->error; + } else { + struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)prog; + + if (!r300_fp->translated) + r300TranslateFragmentShader(rmesa, r300_fp); + + return !r300_fp->error; + } + } else + return GL_TRUE; } void r300InitShaderFuncs(struct dd_function_table *functions) diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index f464335422f..64ec8709760 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2301,7 +2301,7 @@ static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, } -static void r300SetupPixelShader(r300ContextPtr rmesa) +static GLboolean r300SetupPixelShader(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; struct r300_fragment_program *fp = (struct r300_fragment_program *) @@ -2309,15 +2309,12 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) struct r300_fragment_program_code *code; int i, k; - if (!fp) /* should only happenen once, just after context is created */ - return; - r300TranslateFragmentShader(rmesa, fp); - if (!fp->translated) { - fprintf(stderr, "%s: No valid fragment shader, exiting\n", - __FUNCTION__); - return; - } + + /* Program is not native, fallback to software */ + if (fp->error) + return GL_FALSE; + code = &fp->code; r300SetupTextures(ctx); @@ -2369,6 +2366,8 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]); rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]); } + + return GL_TRUE; } #define bump_r500fp_count(ptr, new_count) do{\ @@ -2385,7 +2384,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ } while(0) -static void r500SetupPixelShader(r300ContextPtr rmesa) +static GLboolean r500SetupPixelShader(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; struct r500_fragment_program *fp = (struct r500_fragment_program *) @@ -2393,18 +2392,15 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) int i; struct r500_fragment_program_code *code; - if (!fp) /* should only happenen once, just after context is created */ - return; - ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0; ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0; r500TranslateFragmentShader(rmesa, fp); - if (!fp->translated) { - fprintf(stderr, "%s: No valid fragment shader, exiting\n", - __FUNCTION__); - return; - } + + /* Program is not native, fallback to software */ + if (fp->error) + return GL_FALSE; + code = &fp->code; r300SetupTextures(ctx); @@ -2445,6 +2441,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) } bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4); + return GL_TRUE; } void r300UpdateShaderStates(r300ContextPtr rmesa) @@ -2452,6 +2449,10 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) GLcontext *ctx; ctx = rmesa->radeon.glCtx; + /* should only happenen once, just after context is created */ + if (!ctx->FragmentProgram._Current) + return; + r300SetEarlyZState(ctx); /* w_fmt value is set to get best performance @@ -2475,19 +2476,18 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; } - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - r500SetupPixelShader(rmesa); - else - r300SetupPixelShader(rmesa); - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + if (!r500SetupPixelShader(rmesa)) + return; r500SetupRSUnit(ctx); - else + } else { + if (!r300SetupPixelShader(rmesa)) + return; r300SetupRSUnit(ctx); + } if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) r300SetupVertexProgram(rmesa); - } /** diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 07a2a7b17ce..1b8343ab215 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -493,7 +493,10 @@ void r500TranslateFragmentShader(r300ContextPtr r300, _mesa_print_program(compiler.program); } - fp->translated = r500FragmentProgramEmit(&compiler); + if (!r500FragmentProgramEmit(&compiler)) + fp->error = GL_TRUE; + + fp->translated = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ _mesa_free_parameter_list(fp->mesa_program.Base.Parameters); @@ -505,7 +508,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300, r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); if (RADEON_DEBUG & DEBUG_PIXEL) { - if (fp->translated) { + if (!fp->error) { _mesa_printf("Machine-readable code:\n"); dump_program(&fp->code); } -- cgit v1.2.3 From 9028335371af465a73c13282a3608f76168e4d63 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 16 Apr 2009 18:22:44 +0200 Subject: r300: we always want non NDC coords format for swtcl --- src/mesa/drivers/dri/r300/r300_swtcl.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 03c1521de7e..553bdb12dd2 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -66,10 +66,7 @@ do { \ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten, GLuint vap_out_fmt_1) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; - int vte = 0; int i, j, reg_count; uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; @@ -123,7 +120,6 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW R300_STATECHANGE(rmesa, vir[0]); R300_STATECHANGE(rmesa, vir[1]); R300_STATECHANGE(rmesa, vof); - R300_STATECHANGE(rmesa, vte); R300_STATECHANGE(rmesa, vic); if (rmesa->radeon.radeonScreen->kernel_mm) { @@ -145,24 +141,6 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW * for HW TCL path, but not for SW TCL. */ rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_out_fmt_1; - - vte = rmesa->hw.vte.cmd[1]; - vte &= ~(R300_VTX_XY_FMT | R300_VTX_Z_FMT | R300_VTX_W0_FMT); - /* Important: - */ - if ( VB->NdcPtr != NULL ) { - VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; - vte |= R300_VTX_XY_FMT | R300_VTX_Z_FMT; - } - else { - VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; - vte |= R300_VTX_W0_FMT; - } - - assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - - rmesa->hw.vte.cmd[1] = vte; - rmesa->hw.vte.cmd[2] = rmesa->radeon.swtcl.vertex_size; } @@ -180,6 +158,9 @@ static void r300SetVertexFormat( GLcontext *ctx ) rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0; rmesa->radeon.swtcl.vertex_attr_count = 0; + /* We always want non Ndc coords format */ + VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS)) { InputsRead |= 1 << VERT_ATTRIB_POS; OutputsWritten |= 1 << VERT_RESULT_HPOS; -- cgit v1.2.3 From 3230cb5f532c9df6a262b339d947bb71c71c510e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 19 Apr 2009 22:04:42 +1000 Subject: radeon: update clear state with latest intel code --- src/mesa/drivers/dri/radeon/radeon_common.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 2449795ea94..dc281ee269c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -1258,6 +1258,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) GL_CURRENT_BIT | GL_DEPTH_BUFFER_BIT | GL_ENABLE_BIT | + GL_POLYGON_BIT | GL_STENCIL_BUFFER_BIT | GL_TRANSFORM_BIT | GL_CURRENT_BIT); @@ -1279,6 +1280,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) _mesa_Disable(GL_CLIP_PLANE3); _mesa_Disable(GL_CLIP_PLANE4); _mesa_Disable(GL_CLIP_PLANE5); + _mesa_PolygonMode(GL_FRONT_AND_BACK, GL_FILL); if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { saved_fp_enable = GL_TRUE; _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); @@ -1311,6 +1313,11 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) } } +#if FEATURE_ARB_vertex_buffer_object + _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0); + _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0); +#endif + radeon_meta_set_passthrough_transform(rmesa); for (i = 0; i < 4; i++) { -- cgit v1.2.3 From 3fd0084154b377f4189bb8bc8eae21dbce735860 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 17 Apr 2009 23:42:37 +0200 Subject: r300: context creation cleanup - move constant values initialization to seperate function - remove obvious comments --- src/mesa/drivers/dri/r300/r300_context.c | 186 +++++++++++++------------------ 1 file changed, 76 insertions(+), 110 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5f279d6629e..f16e5486f67 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -191,17 +191,6 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { 0, }; -static void r300RunPipeline(GLcontext * ctx) -{ - _mesa_lock_context_textures(ctx); - - if (ctx->NewState) - _mesa_update_state_locked(ctx); - - _tnl_run_pipeline(ctx); - _mesa_unlock_context_textures(ctx); -} - static void r300_get_lock(radeonContextPtr rmesa) { drm_radeon_sarea_t *sarea = rmesa->sarea; @@ -211,7 +200,7 @@ static void r300_get_lock(radeonContextPtr rmesa) if (!rmesa->radeonScreen->kernel_mm) radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); } -} +} static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { @@ -246,9 +235,9 @@ static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) { r300ContextPtr r300 = (r300ContextPtr)radeon; BATCH_LOCALS(radeon); - + r300->vap_flush_needed = GL_TRUE; - + cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); BEGIN_BATCH_NO_AUTOSTATE(2); OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); @@ -275,6 +264,60 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.fallback = r300_fallback; } +static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + + ctx->Const.MaxTextureImageUnits = + driQueryOptioni(&r300->radeon.optionCache, "texture_image_units"); + ctx->Const.MaxTextureCoordUnits = + driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units"); + ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits, + ctx->Const.MaxTextureCoordUnits); + ctx->Const.MaxTextureMaxAnisotropy = 16.0; + ctx->Const.MaxTextureLodBias = 16.0; + + if (screen->chip_family >= CHIP_FAMILY_RV515) + ctx->Const.MaxTextureLevels = 13; + else + ctx->Const.MaxTextureLevels = 12; + + ctx->Const.MinPointSize = 1.0; + ctx->Const.MinPointSizeAA = 1.0; + ctx->Const.MaxPointSize = R300_POINTSIZE_MAX; + ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX; + + ctx->Const.MinLineWidth = 1.0; + ctx->Const.MinLineWidthAA = 1.0; + ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; + ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; + + ctx->Const.MaxDrawBuffers = 1; + + /* currently bogus data */ + if (screen->chip_flags & RADEON_CHIPSET_TCL) { + ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeInstructions = + VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ + ctx->Const.VertexProgram.MaxTemps = 32; + ctx->Const.VertexProgram.MaxNativeTemps = + /*VSF_MAX_FRAGMENT_TEMPS */ 32; + ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; + } + + ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; + ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ + ctx->Const.FragmentProgram.MaxNativeParameters = PFS_NUM_CONST_REGS; + ctx->Const.FragmentProgram.MaxNativeAluInstructions = PFS_MAX_ALU_INST; + ctx->Const.FragmentProgram.MaxNativeTexInstructions = PFS_MAX_TEX_INST; + ctx->Const.FragmentProgram.MaxNativeInstructions = + PFS_MAX_ALU_INST + PFS_MAX_TEX_INST; + ctx->Const.FragmentProgram.MaxNativeTexIndirections = + PFS_MAX_TEX_INDIRECT; + ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; +} /* Create the device specific rendering context. */ @@ -293,7 +336,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, assert(driContextPriv); assert(screen); - /* Allocate the R300 context */ r300 = (r300ContextPtr) CALLOC(sizeof(*r300)); if (!r300) return GL_FALSE; @@ -301,19 +343,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; - r300_init_vtbl(&r300->radeon); - /* Parse configuration files. - * Do this here so that initialMaxAnisotropy is set before we create - * the default textures. - */ driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r300"); - r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, - "def_max_anisotropy"); - /* Init default driver functions then plug in our R300-specific functions - * (the texture functions are especially important) - */ + r300_init_vtbl(&r300->radeon); + _mesa_init_driver_functions(&functions); r300InitIoctlFuncs(&functions); r300InitStateFuncs(&functions); @@ -327,46 +361,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, return GL_FALSE; } - /* Init r300 context data */ - /* Set the maximum texture size small enough that we can guarentee that - * all texture units can bind a maximal texture and have them both in - * texturable memory at once. - */ - ctx = r300->radeon.glCtx; - - ctx->Const.MaxTextureImageUnits = - driQueryOptioni(&r300->radeon.optionCache, "texture_image_units"); - ctx->Const.MaxTextureCoordUnits = - driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units"); - ctx->Const.MaxTextureUnits = - MIN2(ctx->Const.MaxTextureImageUnits, - ctx->Const.MaxTextureCoordUnits); - ctx->Const.MaxTextureMaxAnisotropy = 16.0; - ctx->Const.MaxTextureLodBias = 16.0; - - if (screen->chip_family >= CHIP_FAMILY_RV515) - ctx->Const.MaxTextureLevels = 13; - else - ctx->Const.MaxTextureLevels = 12; - - ctx->Const.MinPointSize = 1.0; - ctx->Const.MinPointSizeAA = 1.0; - ctx->Const.MaxPointSize = R300_POINTSIZE_MAX; - ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX; - - ctx->Const.MinLineWidth = 1.0; - ctx->Const.MinLineWidthAA = 1.0; - ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; - ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; - - /* Needs further modifications */ -#if 0 - ctx->Const.MaxArrayLockSize = - ( /*512 */ RADEON_BUFFER_SIZE * 16 * 1024) / (4 * 4); -#endif - - ctx->Const.MaxDrawBuffers = 1; + r300InitConstValues(ctx, screen); + ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; + ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; /* Initialize the software rasterizer and helper modules. */ @@ -381,10 +379,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, */ _tnl_destroy_pipeline(ctx); _tnl_install_pipeline(ctx, r300_pipeline); - - /* Try and keep materials and vertices separate: - */ -/* _tnl_isolate_materials(ctx, GL_TRUE); */ + TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline; /* Configure swrast and TNL to match hardware characteristics: */ @@ -393,61 +388,32 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, _tnl_allow_pixel_fog(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_TRUE); - /* currently bogus data */ - if (screen->chip_flags & RADEON_CHIPSET_TCL) { - ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeInstructions = - VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ - ctx->Const.VertexProgram.MaxTemps = 32; - ctx->Const.VertexProgram.MaxNativeTemps = - /*VSF_MAX_FRAGMENT_TEMPS */ 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; - } - - ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; - ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ - ctx->Const.FragmentProgram.MaxNativeParameters = PFS_NUM_CONST_REGS; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = PFS_MAX_ALU_INST; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeInstructions = - PFS_MAX_ALU_INST + PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = - PFS_MAX_TEX_INDIRECT; - ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */ - ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; - ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; + radeon_fbo_init(&r300->radeon); + radeonInitSpanFuncs( ctx ); + r300InitCmdBuf(r300); + r300InitState(r300); + if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) + r300InitSwtcl(ctx); driInitExtensions(ctx, card_extensions, GL_TRUE); if (r300->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); - if (driQueryOptionb - (&r300->radeon.optionCache, "disable_stencil_two_side")) + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, + "def_max_anisotropy"); + + if (driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side")) _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); - if (r300->radeon.glCtx->Mesa_DXTn - && !driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc")) { + if (ctx->Mesa_DXTn && !driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc")) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); _mesa_enable_extension(ctx, "GL_S3_s3tc"); - } else - if (driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable")) - { + } else if (driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable")) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); } r300->disable_lowimpact_fallback = - driQueryOptionb(&r300->radeon.optionCache, - "disable_lowimpact_fallback"); - radeon_fbo_init(&r300->radeon); - radeonInitSpanFuncs( ctx ); - r300InitCmdBuf(r300); - r300InitState(r300); - if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) - r300InitSwtcl(ctx); - - TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline; + driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode"); if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) { -- cgit v1.2.3 From b552446b95baeece6bbb41afe64cdb2f5623e400 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 17 Apr 2009 23:54:20 +0200 Subject: r300: remove unnecessary forward function declaration --- src/mesa/drivers/dri/r300/r300_state.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 64ec8709760..5ae999b73a8 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -65,7 +65,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" extern int future_hw_tcl_on; -extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx); static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4]) { -- cgit v1.2.3 From cb4bef7ae0b5fe8de82c380bc98f19067394d355 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 01:58:52 +0200 Subject: r300: general cleanup - remove unused fields - remove unused defines and macros - flatten one structure --- src/mesa/drivers/dri/r300/r300_context.h | 41 ++++-------------------- src/mesa/drivers/dri/r300/r300_emit.c | 9 ++---- src/mesa/drivers/dri/r300/r300_state.c | 16 ++++----- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 28 +++++++++++++--- 5 files changed, 41 insertions(+), 55 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 602f86ba669..c3d91187a7f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -37,24 +37,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __R300_CONTEXT_H__ #define __R300_CONTEXT_H__ -#include "tnl/t_vertex.h" #include "drm.h" #include "radeon_drm.h" #include "dri_util.h" -#include "texmem.h" #include "radeon_common.h" -#include "main/macros.h" #include "main/mtypes.h" -#include "main/colormac.h" struct r300_context; typedef struct r300_context r300ContextRec; typedef struct r300_context *r300ContextPtr; -#include "main/mm.h" - /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble with other compilers ... GLUE! @@ -81,9 +75,6 @@ typedef struct r300_context *r300ContextPtr; #define R300_BLIT_WIDTH_BYTES 1024 #define R300_MAX_TEXTURE_UNITS 8 -struct r300_texture_state { - int tc_count; /* number of incoming texture coordinates from VAP */ -}; #define R300_VPT_CMD_0 0 @@ -303,7 +294,7 @@ struct r300_texture_state { struct r300_hw_state { struct radeon_state_atom vpt; /* viewport (1D98) */ struct radeon_state_atom vap_cntl; - struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ + struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ struct radeon_state_atom vof; /* VAP output format register 0x2090 */ struct radeon_state_atom vte; /* (20B0) */ struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ @@ -425,12 +416,8 @@ extern int hw_tcl_on; #include "tnl_dd/t_dd_vertex.h" #undef TAG -//#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current) #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp) -/* Should but doesnt work */ -//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp) - /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday. * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly. */ @@ -623,20 +610,6 @@ struct r500_fragment_program { #define R300_MAX_AOS_ARRAYS 16 -#define REG_COORDS 0 -#define REG_COLOR0 1 -#define REG_TEX0 2 - -struct r300_state { - struct r300_texture_state texture; - int sw_tcl_inputs[VERT_ATTRIB_MAX]; - struct r300_vertex_shader_state vertex_shader; - - - DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. - They are the same as tnl->render_inputs for fixed pipeline */ - -}; #define R300_FALLBACK_NONE 0 #define R300_FALLBACK_TCL 1 @@ -664,6 +637,8 @@ struct r300_swtcl_info { } vert_attrs[VERT_ATTRIB_MAX]; GLubyte vertex_attr_count; + + int sw_tcl_inputs[VERT_ATTRIB_MAX]; }; @@ -675,8 +650,7 @@ struct r300_context { struct r300_hw_state hw; - struct r300_state state; - struct gl_vertex_program *curr_vp; + struct r300_vertex_shader_state vertex_shader; struct r300_vertex_program *selected_vp; /* Vertex buffers @@ -688,6 +662,8 @@ struct r300_context { struct r300_swtcl_info swtcl; GLboolean vap_flush_needed; + + DECLARE_RENDERINPUTS(render_inputs_bitset); }; #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx)) @@ -703,11 +679,6 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx, struct r300_vertex_program_cont *vp, float *dst); -#define RADEON_D_CAPTURE 0 -#define RADEON_D_PLAYBACK 1 -#define RADEON_D_PLAYBACK_RAW 2 -#define RADEON_D_T 3 - #define r300PackFloat32 radeonPackFloat32 #define r300PackFloat24 radeonPackFloat24 diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4fd6ba9b91a..a19b0f19605 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -127,7 +127,6 @@ GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead) GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); GLuint i, vic_1 = 0; if (InputsRead & (1 << VERT_ATTRIB_POS)) @@ -139,10 +138,8 @@ GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) vic_1 |= R300_INPUT_CNTL_COLOR; - rmesa->state.texture.tc_count = 0; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) { - rmesa->state.texture.tc_count++; vic_1 |= R300_INPUT_CNTL_TC0 << i; } @@ -222,7 +219,7 @@ int r300EmitArrays(GLcontext * ctx) InputsRead = prog->key.InputsRead; OutputsWritten = prog->key.OutputsWritten; } else { - inputs = rmesa->state.sw_tcl_inputs; + inputs = rmesa->swtcl.sw_tcl_inputs; DECLARE_RENDERINPUTS(render_inputs_bitset); RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset); @@ -275,7 +272,7 @@ int r300EmitArrays(GLcontext * ctx) if (InputsRead & (1 << i)) inputs[i] = 6 + (i - VERT_ATTRIB_TEX0); - RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset); + RENDERINPUTS_COPY(rmesa->render_inputs_bitset, render_inputs_bitset); } assert(InputsRead); @@ -330,7 +327,7 @@ int r300EmitArrays(GLcontext * ctx) r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, nr); } - + /* Setup INPUT_CNTL. */ R300_STATECHANGE(rmesa, vic); rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 5ae999b73a8..86b85d525ff 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1432,7 +1432,7 @@ static void r300SetupRSUnit(GLcontext * ctx) if (hw_tcl_on) OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset); + RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); if (ctx->FragmentProgram._Current) InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; @@ -1583,7 +1583,7 @@ static void r500SetupRSUnit(GLcontext * ctx) if (hw_tcl_on) OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset); + RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); if (ctx->FragmentProgram._Current) InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; @@ -1853,7 +1853,7 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa) { - struct r300_vertex_shader_state *prog = &(rmesa->state.vertex_shader); + struct r300_vertex_shader_state *prog = &(rmesa->vertex_shader); GLuint o_reg = 0; GLuint i_reg = 0; int i; @@ -1862,11 +1862,11 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa) int program_end = 0; for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) { - if (rmesa->state.sw_tcl_inputs[i] != -1) { + if (rmesa->swtcl.sw_tcl_inputs[i] != -1) { prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT); - prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); program_end += 4; i_reg++; } @@ -2522,8 +2522,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) */ void r300InitState(r300ContextPtr r300) { - memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); - r300ResetHwState(r300); } diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 553bdb12dd2..934e1e22431 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -281,7 +281,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) rmesa->radeon.swtcl.vertex_size /= 4; - RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, tnl->render_inputs_bitset); + RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset); } diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 34d62617068..f7c50e9949a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat) { int bytes = 0; switch(mesaFormat) { - + case MESA_FORMAT_RGB_FXT1: case MESA_FORMAT_RGBA_FXT1: case MESA_FORMAT_RGB_DXT1: case MESA_FORMAT_RGBA_DXT1: bytes = 2; break; - + case MESA_FORMAT_RGBA_DXT3: case MESA_FORMAT_RGBA_DXT5: bytes = 4; default: break; } - + return bytes; } @@ -97,18 +97,38 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, lvl->width, lvl->height, lvl->depth, mt->compressed); + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = lvl->rowstride * lvl->height; + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } else { lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; lvl->size = lvl->rowstride * lvl->height * lvl->depth; + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } assert(lvl->size > 0); @@ -230,7 +250,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj, tObj->Image[face][level]; assert(baseImage); - + /* These must be signed values. MinLod and MaxLod can be negative numbers, * and having firstLevel and lastLevel as signed prevents the need for * extra sign checks. -- cgit v1.2.3 From 27d4546f600cb444f07a4d510a328540ff37f761 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 02:42:35 +0200 Subject: r300: r300/r500 fp shader merge WIP --- src/mesa/drivers/dri/r300/r300_context.c | 1 + src/mesa/drivers/dri/r300/r300_context.h | 9 ++++++ src/mesa/drivers/dri/r300/r300_fragprog.c | 46 +++++++++++++-------------- src/mesa/drivers/dri/r300/r300_fragprog.h | 4 +-- src/mesa/drivers/dri/r300/r300_render.c | 10 +++--- src/mesa/drivers/dri/r300/r300_shader.c | 9 +++--- src/mesa/drivers/dri/r300/r300_state.c | 53 +++++++++++++++++-------------- src/mesa/drivers/dri/r300/r500_fragprog.c | 44 ++++++++++++------------- src/mesa/drivers/dri/r300/r500_fragprog.h | 3 +- 9 files changed, 94 insertions(+), 85 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index f16e5486f67..10836bb16ab 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -392,6 +392,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, radeonInitSpanFuncs( ctx ); r300InitCmdBuf(r300); r300InitState(r300); + r300InitShaderFunctions(r300); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) r300InitSwtcl(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index c3d91187a7f..8d0f95e31ee 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -641,6 +641,13 @@ struct r300_swtcl_info { int sw_tcl_inputs[VERT_ATTRIB_MAX]; }; +struct r300_vtable { + void (* SetupRSUnit)(GLcontext *ctx); + void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings); + void ( *TranslateFragmentShader)(GLcontext *ctx, struct gl_fragment_program *fp); + GLboolean (* SetupPixelShader)(GLcontext *ctx); +}; + /** * \brief R300 context structure. @@ -648,6 +655,8 @@ struct r300_swtcl_info { struct r300_context { struct radeon_context radeon; /* parent class, must be first */ + struct r300_vtable vtbl; + struct r300_hw_state hw; struct r300_vertex_shader_state vertex_shader; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index f2d7cec5d36..2c3abb216be 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -401,25 +401,26 @@ static void build_state( } -void r300TranslateFragmentShader(r300ContextPtr r300, - struct r300_fragment_program *fp) +void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) { + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; struct r300_fragment_program_external_state state; - build_state(r300, fp, &state); - if (_mesa_memcmp(&fp->state, &state, sizeof(state))) { + build_state(r300, r300_fp, &state); + if (_mesa_memcmp(&r300_fp->state, &state, sizeof(state))) { /* TODO: cache compiled programs */ - fp->translated = GL_FALSE; - _mesa_memcpy(&fp->state, &state, sizeof(state)); + r300_fp->translated = GL_FALSE; + _mesa_memcpy(&r300_fp->state, &state, sizeof(state)); } - if (!fp->translated) { + if (!r300_fp->translated) { struct r300_fragment_program_compiler compiler; compiler.r300 = r300; - compiler.fp = fp; - compiler.code = &fp->code; - compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base); + compiler.fp = r300_fp; + compiler.code = &r300_fp->code; + compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Fragment Program: Initial program:\n"); @@ -433,10 +434,7 @@ void r300TranslateFragmentShader(r300ContextPtr r300, { &radeonTransformALU, 0 }, { &radeonTransformTrigSimple, 0 } }; - radeonLocalTransform( - r300->radeon.glCtx, - compiler.program, - 3, transformations); + radeonLocalTransform(ctx, compiler.program, 3, transformations); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Fragment Program: After native rewrite:\n"); @@ -449,7 +447,7 @@ void r300TranslateFragmentShader(r300ContextPtr r300, .BuildSwizzle = &r300FPBuildSwizzle, .RewriteDepthOut = GL_TRUE }; - radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce); + radeonNqssaDce(ctx, compiler.program, &nqssadce); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: after NqSSA-DCE:\n"); @@ -457,23 +455,23 @@ void r300TranslateFragmentShader(r300ContextPtr r300, } if (!r300FragmentProgramEmit(&compiler)) - fp->error = GL_TRUE; + r300_fp->error = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ - _mesa_free_parameter_list(fp->mesa_program.Base.Parameters); - fp->mesa_program.Base.Parameters = compiler.program->Parameters; + _mesa_free_parameter_list(fp->Base.Parameters); + fp->Base.Parameters = compiler.program->Parameters; compiler.program->Parameters = 0; - _mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL); + _mesa_reference_program(ctx, &compiler.program, NULL); - fp->translated = GL_TRUE; + r300_fp->translated = GL_TRUE; - if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) - r300FragmentProgramDump(fp, &fp->code); - r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); + if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) + r300FragmentProgramDump(r300_fp, &r300_fp->code); + r300UpdateStateParameters(ctx, _NEW_PROGRAM); } - update_params(r300, fp); + update_params(r300, r300_fp); } /* just some random things... */ diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 94fb554fb37..e1976277de9 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -107,9 +107,7 @@ struct r300_fragment_program; -extern void r300TranslateFragmentShader(r300ContextPtr r300, - struct r300_fragment_program *fp); - +extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); /** * Used internally by the r300 fragment program code to store compile-time diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index d33396e150a..ce333b80995 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -432,20 +432,18 @@ static int r300Fallback(GLcontext * ctx) /* Do we need to use new-style shaders? * Also is there a better way to do this? */ if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - struct r500_fragment_program *fp = (struct r500_fragment_program *) - (char *)ctx->FragmentProgram._Current; + struct r500_fragment_program *fp = (struct r500_fragment_program *) ctx->FragmentProgram._Current; if (fp) { if (!fp->translated) - r500TranslateFragmentShader(r300, fp); + r300->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); FALLBACK_IF(fp->error); } } else { - struct r300_fragment_program *fp = (struct r300_fragment_program *) - (char *)ctx->FragmentProgram._Current; + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; if (fp) { if (!fp->translated) - r300TranslateFragmentShader(r300, fp); + r300->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); FALLBACK_IF(fp->error); } diff --git a/src/mesa/drivers/dri/r300/r300_shader.c b/src/mesa/drivers/dri/r300/r300_shader.c index d90658ba478..ef0b5d037f4 100644 --- a/src/mesa/drivers/dri/r300/r300_shader.c +++ b/src/mesa/drivers/dri/r300/r300_shader.c @@ -83,19 +83,20 @@ r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) { if (target == GL_FRAGMENT_PROGRAM_ARB) { r300ContextPtr rmesa = R300_CONTEXT(ctx); + struct gl_fragment_program * fp = (struct gl_fragment_program *) prog; if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog; + struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)fp; if (!r500_fp->translated) - r500TranslateFragmentShader(rmesa, r500_fp); + rmesa->vtbl.TranslateFragmentShader(ctx, fp); return !r500_fp->error; } else { - struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)prog; + struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; if (!r300_fp->translated) - r300TranslateFragmentShader(rmesa, r300_fp); + rmesa->vtbl.TranslateFragmentShader(ctx, fp); return !r300_fp->error; } diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 86b85d525ff..09f83f3d122 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1399,9 +1399,8 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1); } - r300SetupFragmentShaderTextures(ctx, tmu_mappings); - } else - r500SetupFragmentShaderTextures(ctx, tmu_mappings); + } + r300->vtbl.SetupFragmentShaderTextures(ctx, tmu_mappings); if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n", @@ -2300,16 +2299,13 @@ static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, } -static GLboolean r300SetupPixelShader(r300ContextPtr rmesa) +static GLboolean r300SetupPixelShader(GLcontext *ctx) { - GLcontext *ctx = rmesa->radeon.glCtx; - struct r300_fragment_program *fp = (struct r300_fragment_program *) - (char *)ctx->FragmentProgram._Current; + r300ContextPtr rmesa = R300_CONTEXT(ctx); + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; struct r300_fragment_program_code *code; int i, k; - r300TranslateFragmentShader(rmesa, fp); - /* Program is not native, fallback to software */ if (fp->error) return GL_FALSE; @@ -2383,19 +2379,16 @@ static GLboolean r300SetupPixelShader(r300ContextPtr rmesa) if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ } while(0) -static GLboolean r500SetupPixelShader(r300ContextPtr rmesa) +static GLboolean r500SetupPixelShader(GLcontext *ctx) { - GLcontext *ctx = rmesa->radeon.glCtx; - struct r500_fragment_program *fp = (struct r500_fragment_program *) - (char *)ctx->FragmentProgram._Current; + r300ContextPtr rmesa = R300_CONTEXT(ctx); + struct r500_fragment_program *fp = (struct r500_fragment_program *) ctx->FragmentProgram._Current; int i; struct r500_fragment_program_code *code; ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0; ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0; - r500TranslateFragmentShader(rmesa, fp); - /* Program is not native, fallback to software */ if (fp->error) return GL_FALSE; @@ -2475,15 +2468,12 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; } - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - if (!r500SetupPixelShader(rmesa)) - return; - r500SetupRSUnit(ctx); - } else { - if (!r300SetupPixelShader(rmesa)) - return; - r300SetupRSUnit(ctx); - } + rmesa->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); + + if (!rmesa->vtbl.SetupPixelShader(ctx)) + return; + + rmesa->vtbl.SetupRSUnit(ctx); if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) r300SetupVertexProgram(rmesa); @@ -2595,3 +2585,18 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->DrawBuffer = radeonDrawBuffer; functions->ReadBuffer = radeonReadBuffer; } + +void r300InitShaderFunctions(r300ContextPtr r300) +{ + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + r300->vtbl.SetupRSUnit = r500SetupRSUnit; + r300->vtbl.SetupPixelShader = r500SetupPixelShader; + r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures; + r300->vtbl.TranslateFragmentShader = r500TranslateFragmentShader; + } else { + r300->vtbl.SetupRSUnit = r300SetupRSUnit; + r300->vtbl.SetupPixelShader = r300SetupPixelShader; + r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures; + r300->vtbl.TranslateFragmentShader = r300TranslateFragmentShader; + } +} diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 1b8343ab215..df507b674ea 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -439,25 +439,26 @@ static void build_state( static void dump_program(struct r500_fragment_program_code *code); -void r500TranslateFragmentShader(r300ContextPtr r300, - struct r500_fragment_program *fp) +void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) { + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)fp; struct r500_fragment_program_external_state state; - build_state(r300, fp, &state); - if (_mesa_memcmp(&fp->state, &state, sizeof(state))) { + build_state(r300, r500_fp, &state); + if (_mesa_memcmp(&r500_fp->state, &state, sizeof(state))) { /* TODO: cache compiled programs */ - fp->translated = GL_FALSE; - _mesa_memcpy(&fp->state, &state, sizeof(state)); + r500_fp->translated = GL_FALSE; + _mesa_memcpy(&r500_fp->state, &state, sizeof(state)); } - if (!fp->translated) { + if (!r500_fp->translated) { struct r500_fragment_program_compiler compiler; compiler.r300 = r300; - compiler.fp = fp; - compiler.code = &fp->code; - compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base); + compiler.fp = r500_fp; + compiler.code = &r500_fp->code; + compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: Initial program:\n"); @@ -472,8 +473,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300, { &radeonTransformDeriv, 0 }, { &radeonTransformTrigScale, 0 } }; - radeonLocalTransform(r300->radeon.glCtx, compiler.program, - 4, transformations); + radeonLocalTransform(ctx, compiler.program, 4, transformations); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: after native rewrite:\n"); @@ -486,7 +486,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300, .BuildSwizzle = &nqssadce_build_swizzle, .RewriteDepthOut = GL_TRUE }; - radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce); + radeonNqssaDce(ctx, compiler.program, &nqssadce); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: after NqSSA-DCE:\n"); @@ -494,29 +494,29 @@ void r500TranslateFragmentShader(r300ContextPtr r300, } if (!r500FragmentProgramEmit(&compiler)) - fp->error = GL_TRUE; + r500_fp->error = GL_TRUE; - fp->translated = GL_TRUE; + r500_fp->translated = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ - _mesa_free_parameter_list(fp->mesa_program.Base.Parameters); - fp->mesa_program.Base.Parameters = compiler.program->Parameters; + _mesa_free_parameter_list(fp->Base.Parameters); + fp->Base.Parameters = compiler.program->Parameters; compiler.program->Parameters = 0; - _mesa_reference_program(r300->radeon.glCtx, &compiler.program, 0); + _mesa_reference_program(ctx, &compiler.program, 0); - r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); + r300UpdateStateParameters(ctx, _NEW_PROGRAM); if (RADEON_DEBUG & DEBUG_PIXEL) { - if (!fp->error) { + if (!r500_fp->error) { _mesa_printf("Machine-readable code:\n"); - dump_program(&fp->code); + dump_program(&r500_fp->code); } } } - update_params(r300, fp); + update_params(r300, r500_fp); } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 1e45538f807..1456f7f467c 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -47,8 +47,7 @@ struct r500_fragment_program; -extern void r500TranslateFragmentShader(r300ContextPtr r300, - struct r500_fragment_program *fp); +extern void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); struct r500_fragment_program_compiler { r300ContextPtr r300; -- cgit v1.2.3 From aa04e7d475f6d6028c06c42bedc3c7d37ee78a0e Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 03:16:16 +0200 Subject: r300: merge r300/r500 fragment program structures --- src/mesa/drivers/dri/r300/r300_context.h | 60 ++++++-------------------- src/mesa/drivers/dri/r300/r300_fragprog.c | 18 ++++---- src/mesa/drivers/dri/r300/r300_fragprog_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_render.c | 21 ++------- src/mesa/drivers/dri/r300/r300_shader.c | 55 +++++------------------ src/mesa/drivers/dri/r300/r300_state.c | 37 ++++++---------- src/mesa/drivers/dri/r300/r500_fragprog.c | 44 +++++++++---------- src/mesa/drivers/dri/r300/r500_fragprog.h | 2 +- 8 files changed, 70 insertions(+), 169 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 8d0f95e31ee..0c7221b1909 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -458,7 +458,7 @@ struct r300_vertex_program_cont { #define PFS_NUM_CONST_REGS 16 struct r300_pfs_compile_state; - +struct r500_pfs_compile_state; /** * Stores state that influences the compilation of a fragment program. @@ -528,47 +528,6 @@ struct r300_fragment_program_code { int max_temp_idx; }; -/** - * Store everything about a fragment program that is needed - * to render with that program. - */ -struct r300_fragment_program { - struct gl_fragment_program mesa_program; - - GLboolean translated; - GLboolean error; - - struct r300_fragment_program_external_state state; - struct r300_fragment_program_code code; - - GLboolean WritesDepth; - GLuint optimization; -}; - -struct r500_pfs_compile_state; - -struct r500_fragment_program_external_state { - struct { - /** - * If the sampler is used as a shadow sampler, - * this field is: - * 0 - GL_LUMINANCE - * 1 - GL_INTENSITY - * 2 - GL_ALPHA - * depending on the depth texture mode. - */ - GLuint depth_texture_mode : 2; - - /** - * If the sampler is used as a shadow sampler, - * this field is (texture_compare_func - GL_NEVER). - * [e.g. if compare function is GL_LEQUAL, this field is 3] - * - * Otherwise, this field is 0. - */ - GLuint texture_compare_func : 3; - } unit[16]; -}; struct r500_fragment_program_code { struct { @@ -593,18 +552,23 @@ struct r500_fragment_program_code { int max_temp_idx; }; -struct r500_fragment_program { - struct gl_fragment_program mesa_program; +/** +* Store everything about a fragment program that is needed +* to render with that program. +*/ +struct r300_fragment_program { + struct gl_fragment_program Base; - GLcontext *ctx; GLboolean translated; GLboolean error; - struct r500_fragment_program_external_state state; - struct r500_fragment_program_code code; + struct r300_fragment_program_external_state state; + union { + struct r300_fragment_program_code r300; + struct r500_fragment_program_code r500; + } code; GLboolean writes_depth; - GLuint optimization; }; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 2c3abb216be..30f1bac72e7 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -247,13 +247,11 @@ static GLboolean transform_TEX( } -static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp) +static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) { - struct gl_fragment_program *mp = &fp->mesa_program; - /* Ask Mesa nicely to fill in ParameterValues for us */ - if (mp->Base.Parameters) - _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters); + if (fp->Base.Parameters) + _mesa_load_state_parameters(ctx, fp->Base.Parameters); } @@ -270,7 +268,7 @@ static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp) */ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) { - GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead; + GLuint InputsRead = compiler->fp->Base.Base.InputsRead; if (!(InputsRead & FRAG_BIT_WPOS)) return; @@ -391,7 +389,7 @@ static void build_state( _mesa_bzero(state, sizeof(*state)); for(unit = 0; unit < 16; ++unit) { - if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) { + if (fp->Base.Base.ShadowSamplers & (1 << unit)) { struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); @@ -419,7 +417,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) compiler.r300 = r300; compiler.fp = r300_fp; - compiler.code = &r300_fp->code; + compiler.code = &r300_fp->code.r300; compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { @@ -467,11 +465,11 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) r300_fp->translated = GL_TRUE; if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) - r300FragmentProgramDump(r300_fp, &r300_fp->code); + r300FragmentProgramDump(r300_fp, &r300_fp->code.r300); r300UpdateStateParameters(ctx, _NEW_PROGRAM); } - update_params(r300, r300_fp); + update_params(ctx, fp); } /* just some random things... */ diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c index 9f0b7e35349..690734a1eb5 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c @@ -201,7 +201,7 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst) if (inst->Alpha.DepthWriteMask) { code->alu.inst[ip].inst3 |= R300_ALU_DSTA_DEPTH; code->node[code->cur_node].flags |= R300_W_OUT; - c->fp->WritesDepth = GL_TRUE; + c->fp->writes_depth = GL_TRUE; } return GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index ce333b80995..91f58ade599 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -429,24 +429,11 @@ static int r300Fallback(GLcontext * ctx) const unsigned back = ctx->Stencil._BackFace; FALLBACK_IF(r300->radeon.Fallback); - /* Do we need to use new-style shaders? - * Also is there a better way to do this? */ - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - struct r500_fragment_program *fp = (struct r500_fragment_program *) ctx->FragmentProgram._Current; - if (fp) { - if (!fp->translated) - r300->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); - - FALLBACK_IF(fp->error); - } - } else { - struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; - if (fp) { - if (!fp->translated) - r300->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); - FALLBACK_IF(fp->error); - } + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; + if (fp && !fp->translated) { + r300->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); + FALLBACK_IF(fp->error); } FALLBACK_IF(ctx->RenderMode != GL_RENDER); diff --git a/src/mesa/drivers/dri/r300/r300_shader.c b/src/mesa/drivers/dri/r300/r300_shader.c index ef0b5d037f4..68fd8cd21e2 100644 --- a/src/mesa/drivers/dri/r300/r300_shader.c +++ b/src/mesa/drivers/dri/r300/r300_shader.c @@ -9,10 +9,8 @@ static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target, GLuint id) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_vertex_program_cont *vp; - struct r300_fragment_program *r300_fp; - struct r500_fragment_program *r500_fp; + struct r300_fragment_program *fp; switch (target) { case GL_VERTEX_STATE_PROGRAM_NV: @@ -20,28 +18,12 @@ static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target, vp = CALLOC_STRUCT(r300_vertex_program_cont); return _mesa_init_vertex_program(ctx, &vp->mesa_program, target, id); - case GL_FRAGMENT_PROGRAM_ARB: - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r500_fp = CALLOC_STRUCT(r500_fragment_program); - r500_fp->ctx = ctx; - return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program, - target, id); - } else { - r300_fp = CALLOC_STRUCT(r300_fragment_program); - return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program, - target, id); - } case GL_FRAGMENT_PROGRAM_NV: - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r500_fp = CALLOC_STRUCT(r500_fragment_program); - return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program, - target, id); - } else { - r300_fp = CALLOC_STRUCT(r300_fragment_program); - return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program, - target, id); - } + case GL_FRAGMENT_PROGRAM_ARB: + fp = CALLOC_STRUCT(r300_fragment_program); + return _mesa_init_fragment_program(ctx, &fp->Base, target, id); + default: _mesa_problem(ctx, "Bad target in r300NewProgram"); } @@ -57,20 +39,15 @@ static void r300DeleteProgram(GLcontext * ctx, struct gl_program *prog) static void r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_vertex_program_cont *vp = (void *)prog; struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)prog; - struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog; switch (target) { case GL_VERTEX_PROGRAM_ARB: vp->progs = NULL; break; case GL_FRAGMENT_PROGRAM_ARB: - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - r500_fp->translated = GL_FALSE; - else - r300_fp->translated = GL_FALSE; + r300_fp->translated = GL_FALSE; break; } @@ -83,23 +60,11 @@ r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) { if (target == GL_FRAGMENT_PROGRAM_ARB) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_fragment_program * fp = (struct gl_fragment_program *) prog; - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)fp; - - if (!r500_fp->translated) - rmesa->vtbl.TranslateFragmentShader(ctx, fp); - - return !r500_fp->error; - } else { - struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; - - if (!r300_fp->translated) - rmesa->vtbl.TranslateFragmentShader(ctx, fp); + struct r300_fragment_program *fp = (struct r300_fragment_program *)prog; + if (!fp->translated) + rmesa->vtbl.TranslateFragmentShader(ctx, &fp->Base); - return !r300_fp->error; - } + return !fp->error; } else return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 09f83f3d122..9304ffb3428 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -449,18 +449,9 @@ static void r300SetPolygonOffsetState(GLcontext * ctx, GLboolean state) static GLboolean current_fragment_program_writes_depth(GLcontext* ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - struct r300_fragment_program *fp = (struct r300_fragment_program *) - (char *)ctx->FragmentProgram._Current; - return (fp && fp->WritesDepth); - } else { - struct r500_fragment_program* fp = - (struct r500_fragment_program*)(char*) - ctx->FragmentProgram._Current; - return (fp && fp->writes_depth); - } + return (fp && fp->writes_depth); } static void r300SetEarlyZState(GLcontext * ctx) @@ -1072,7 +1063,7 @@ void r300UpdateStateParameters(GLcontext * ctx, GLuint new_state) if (!fp) return; - paramList = fp->mesa_program.Base.Parameters; + paramList = fp->Base.Base.Parameters; if (!paramList) return; @@ -1191,9 +1182,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) { r300ContextPtr r300 = R300_CONTEXT(ctx); int i; - struct r300_fragment_program *fp = (struct r300_fragment_program *) - (char *)ctx->FragmentProgram._Current; - struct r300_fragment_program_code *code = &fp->code; + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; + struct r300_fragment_program_code *code = &fp->code.r300; R300_STATECHANGE(r300, fpt); @@ -1234,9 +1224,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) { int i; - struct r500_fragment_program *fp = (struct r500_fragment_program *) - (char *)ctx->FragmentProgram._Current; - struct r500_fragment_program_code *code = &fp->code; + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; + struct r500_fragment_program_code *code = &fp->code.r500; /* find all the texture instructions and relocate the texture units */ for (i = 0; i < code->inst_end + 1; i++) { @@ -1391,7 +1380,7 @@ static void r300SetupTextures(GLcontext * ctx) return; if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - if (fp->mesa_program.UsesKill && last_hw_tmu < 0) { + if (fp->Base.UsesKill && last_hw_tmu < 0) { // The KILL operation requires the first texture unit // to be enabled. r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1; @@ -2310,7 +2299,7 @@ static GLboolean r300SetupPixelShader(GLcontext *ctx) if (fp->error) return GL_FALSE; - code = &fp->code; + code = &fp->code.r300; r300SetupTextures(ctx); @@ -2355,7 +2344,7 @@ static GLboolean r300SetupPixelShader(GLcontext *ctx) rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, code->const_nr * 4); for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, - &fp->mesa_program.Base, code->constant[i]); + &fp->Base.Base, code->constant[i]); rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]); rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]); rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]); @@ -2382,7 +2371,7 @@ static GLboolean r300SetupPixelShader(GLcontext *ctx) static GLboolean r500SetupPixelShader(GLcontext *ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r500_fragment_program *fp = (struct r500_fragment_program *) ctx->FragmentProgram._Current; + struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; int i; struct r500_fragment_program_code *code; @@ -2393,7 +2382,7 @@ static GLboolean r500SetupPixelShader(GLcontext *ctx) if (fp->error) return GL_FALSE; - code = &fp->code; + code = &fp->code.r500; r300SetupTextures(ctx); @@ -2425,7 +2414,7 @@ static GLboolean r500SetupPixelShader(GLcontext *ctx) R300_STATECHANGE(rmesa, r500fp_const); for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, - &fp->mesa_program.Base, code->constant[i]); + &fp->Base.Base, code->constant[i]); rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]); rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]); rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index df507b674ea..f5804521ee3 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -189,13 +189,11 @@ static GLboolean transform_TEX( } -static void update_params(r300ContextPtr r300, struct r500_fragment_program *fp) +static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) { - struct gl_fragment_program *mp = &fp->mesa_program; - /* Ask Mesa nicely to fill in ParameterValues for us */ - if (mp->Base.Parameters) - _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters); + if (fp->Base.Parameters) + _mesa_load_state_parameters(ctx, fp->Base.Parameters); } @@ -212,7 +210,7 @@ static void update_params(r300ContextPtr r300, struct r500_fragment_program *fp) */ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) { - GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead; + GLuint InputsRead = compiler->fp->Base.Base.InputsRead; if (!(InputsRead & FRAG_BIT_WPOS)) return; @@ -420,15 +418,15 @@ static GLuint build_func(GLuint comparefunc) */ static void build_state( r300ContextPtr r300, - struct r500_fragment_program *fp, - struct r500_fragment_program_external_state *state) + struct r300_fragment_program *fp, + struct r300_fragment_program_external_state *state) { int unit; _mesa_bzero(state, sizeof(*state)); for(unit = 0; unit < 16; ++unit) { - if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) { + if (fp->Base.Base.ShadowSamplers & (1 << unit)) { struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); @@ -442,22 +440,22 @@ static void dump_program(struct r500_fragment_program_code *code); void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) { r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)fp; - struct r500_fragment_program_external_state state; + struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; + struct r300_fragment_program_external_state state; - build_state(r300, r500_fp, &state); - if (_mesa_memcmp(&r500_fp->state, &state, sizeof(state))) { + build_state(r300, r300_fp, &state); + if (_mesa_memcmp(&r300_fp->state, &state, sizeof(state))) { /* TODO: cache compiled programs */ - r500_fp->translated = GL_FALSE; - _mesa_memcpy(&r500_fp->state, &state, sizeof(state)); + r300_fp->translated = GL_FALSE; + _mesa_memcpy(&r300_fp->state, &state, sizeof(state)); } - if (!r500_fp->translated) { + if (!r300_fp->translated) { struct r500_fragment_program_compiler compiler; compiler.r300 = r300; - compiler.fp = r500_fp; - compiler.code = &r500_fp->code; + compiler.fp = r300_fp; + compiler.code = &r300_fp->code.r500; compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { @@ -494,9 +492,9 @@ void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) } if (!r500FragmentProgramEmit(&compiler)) - r500_fp->error = GL_TRUE; + r300_fp->error = GL_TRUE; - r500_fp->translated = GL_TRUE; + r300_fp->translated = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ _mesa_free_parameter_list(fp->Base.Parameters); @@ -508,15 +506,15 @@ void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) r300UpdateStateParameters(ctx, _NEW_PROGRAM); if (RADEON_DEBUG & DEBUG_PIXEL) { - if (!r500_fp->error) { + if (!r300_fp->error) { _mesa_printf("Machine-readable code:\n"); - dump_program(&r500_fp->code); + dump_program(&r300_fp->code.r500); } } } - update_params(r300, r500_fp); + update_params(ctx, fp); } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 1456f7f467c..567a43cf613 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -51,7 +51,7 @@ extern void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_progr struct r500_fragment_program_compiler { r300ContextPtr r300; - struct r500_fragment_program *fp; + struct r300_fragment_program *fp; struct r500_fragment_program_code *code; struct gl_program *program; }; -- cgit v1.2.3 From 33af54af0da94e686ff6679d240a9ec246df3c7a Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 03:34:21 +0200 Subject: r300: merge r300/r500 fragment program compiler structure --- src/mesa/drivers/dri/r300/r300_context.h | 12 +++++++++--- src/mesa/drivers/dri/r300/r300_fragprog.c | 2 +- src/mesa/drivers/dri/r300/r300_fragprog.h | 8 -------- src/mesa/drivers/dri/r300/r300_fragprog_emit.c | 6 +++--- src/mesa/drivers/dri/r300/r300_state.c | 1 + src/mesa/drivers/dri/r300/r300_swtcl.c | 1 + src/mesa/drivers/dri/r300/r500_fragprog.c | 10 +++++----- src/mesa/drivers/dri/r300/r500_fragprog.h | 11 +---------- src/mesa/drivers/dri/r300/r500_fragprog_emit.c | 8 ++++---- 9 files changed, 25 insertions(+), 34 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 0c7221b1909..ff59ae7ecf4 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_common.h" #include "main/mtypes.h" +#include "shader/prog_instruction.h" struct r300_context; typedef struct r300_context r300ContextRec; @@ -66,8 +67,6 @@ typedef struct r300_context *r300ContextPtr; } #include "r300_vertprog.h" -#include "r500_fragprog.h" - /* The blit width for texture uploads @@ -563,7 +562,7 @@ struct r300_fragment_program { GLboolean error; struct r300_fragment_program_external_state state; - union { + union rX00_fragment_program_code { struct r300_fragment_program_code r300; struct r500_fragment_program_code r500; } code; @@ -572,6 +571,13 @@ struct r300_fragment_program { GLuint optimization; }; +struct r300_fragment_program_compiler { + r300ContextPtr r300; + struct r300_fragment_program *fp; + union rX00_fragment_program_code *code; + struct gl_program *program; +}; + #define R300_MAX_AOS_ARRAYS 16 diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 30f1bac72e7..eae4c46f694 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -417,7 +417,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) compiler.r300 = r300; compiler.fp = r300_fp; - compiler.code = &r300_fp->code.r300; + compiler.code = &r300_fp->code; compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index e1976277de9..631e40913c6 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -105,20 +105,12 @@ #endif -struct r300_fragment_program; - extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); /** * Used internally by the r300 fragment program code to store compile-time * only data. */ -struct r300_fragment_program_compiler { - r300ContextPtr r300; - struct r300_fragment_program *fp; - struct r300_fragment_program_code *code; - struct gl_program *program; -}; extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c index 690734a1eb5..693d485de9e 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c @@ -47,7 +47,7 @@ #define PROG_CODE \ struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \ - struct r300_fragment_program_code *code = c->code + struct r300_fragment_program_code *code = &c->code->r300 #define error(fmt, args...) do { \ fprintf(stderr, "%s::%s(): " fmt "\n", \ @@ -213,7 +213,7 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst) */ static GLboolean finish_node(struct r300_fragment_program_compiler *c) { - struct r300_fragment_program_code *code = c->code; + struct r300_fragment_program_code *code = &c->code->r300; struct r300_fragment_program_node *node = &code->node[code->cur_node]; if (node->alu_end < 0) { @@ -327,7 +327,7 @@ static const struct radeon_pair_handler pair_handler = { */ GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler) { - struct r300_fragment_program_code *code = compiler->code; + struct r300_fragment_program_code *code = &compiler->code->r300; _mesa_bzero(code, sizeof(struct r300_fragment_program_code)); code->node[0].alu_end = -1; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 9304ffb3428..493c4be6a00 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -61,6 +61,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_emit.h" #include "r300_fragprog.h" #include "r300_tex.h" +#include "r500_fragprog.h" #include "drirenderbuffer.h" diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 934e1e22431..256a2bb5cb2 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -34,6 +34,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/tnl.h" #include "tnl/t_pipeline.h" +#include "r300_state.h" #include "r300_swtcl.h" #include "r300_emit.h" #include "r300_tex.h" diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index f5804521ee3..526a0ea928f 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -62,8 +62,8 @@ static GLboolean transform_TEX( struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data) { - struct r500_fragment_program_compiler *compiler = - (struct r500_fragment_program_compiler*)data; + struct r300_fragment_program_compiler *compiler = + (struct r300_fragment_program_compiler*)data; struct prog_instruction inst = *orig_inst; struct prog_instruction* tgt; GLboolean destredirect = GL_FALSE; @@ -208,7 +208,7 @@ static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) * \todo if/when r5xx supports the radeon_program architecture, this is a * likely candidate for code sharing. */ -static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) +static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) { GLuint InputsRead = compiler->fp->Base.Base.InputsRead; @@ -451,11 +451,11 @@ void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) } if (!r300_fp->translated) { - struct r500_fragment_program_compiler compiler; + struct r300_fragment_program_compiler compiler; compiler.r300 = r300; compiler.fp = r300_fp; - compiler.code = &r300_fp->code.r500; + compiler.code = &r300_fp->code; compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 567a43cf613..4e72ef7aac2 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -45,17 +45,8 @@ #include "r300_state.h" #include "radeon_program.h" -struct r500_fragment_program; - extern void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); -struct r500_fragment_program_compiler { - r300ContextPtr r300; - struct r300_fragment_program *fp; - struct r500_fragment_program_code *code; - struct gl_program *program; -}; - -extern GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler); +extern GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); #endif diff --git a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c index 4631235f0d3..d9f81004e8a 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c @@ -49,8 +49,8 @@ #define PROG_CODE \ - struct r500_fragment_program_compiler *c = (struct r500_fragment_program_compiler*)data; \ - struct r500_fragment_program_code *code = c->code + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \ + struct r500_fragment_program_code *code = &c->code->r500 #define error(fmt, args...) do { \ fprintf(stderr, "%s::%s(): " fmt "\n", \ @@ -299,9 +299,9 @@ static const struct radeon_pair_handler pair_handler = { .MaxHwTemps = 128 }; -GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler) +GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler) { - struct r500_fragment_program_code *code = compiler->code; + struct r500_fragment_program_code *code = &compiler->code->r500; _mesa_bzero(code, sizeof(*code)); code->max_temp_idx = 1; -- cgit v1.2.3 From 97104c255942ee781777818633ca6c17b4fea312 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 03:44:36 +0200 Subject: r300: further r300/r500 merge preparation --- src/mesa/drivers/dri/r300/r300_context.h | 3 ++- src/mesa/drivers/dri/r300/r300_fragprog.c | 2 +- src/mesa/drivers/dri/r300/r300_state.c | 2 ++ src/mesa/drivers/dri/r300/r500_fragprog.c | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index ff59ae7ecf4..41417f3122f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -614,7 +614,8 @@ struct r300_swtcl_info { struct r300_vtable { void (* SetupRSUnit)(GLcontext *ctx); void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings); - void ( *TranslateFragmentShader)(GLcontext *ctx, struct gl_fragment_program *fp); + void (* TranslateFragmentShader)(GLcontext *ctx, struct gl_fragment_program *fp); + GLboolean (* FragmentProgramEmit)(struct r300_fragment_program_compiler *compiler); GLboolean (* SetupPixelShader)(GLcontext *ctx); }; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index eae4c46f694..d58b0921224 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -452,7 +452,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) _mesa_print_program(compiler.program); } - if (!r300FragmentProgramEmit(&compiler)) + if (!r300->vtbl.FragmentProgramEmit(&compiler)) r300_fp->error = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 493c4be6a00..95380a2870e 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2583,10 +2583,12 @@ void r300InitShaderFunctions(r300ContextPtr r300) r300->vtbl.SetupPixelShader = r500SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures; r300->vtbl.TranslateFragmentShader = r500TranslateFragmentShader; + r300->vtbl.FragmentProgramEmit = r500FragmentProgramEmit; } else { r300->vtbl.SetupRSUnit = r300SetupRSUnit; r300->vtbl.SetupPixelShader = r300SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures; r300->vtbl.TranslateFragmentShader = r300TranslateFragmentShader; + r300->vtbl.FragmentProgramEmit = r300FragmentProgramEmit; } } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 526a0ea928f..3e21e0f4975 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -491,7 +491,7 @@ void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) _mesa_print_program(compiler.program); } - if (!r500FragmentProgramEmit(&compiler)) + if (!r300->vtbl.FragmentProgramEmit(&compiler)) r300_fp->error = GL_TRUE; r300_fp->translated = GL_TRUE; -- cgit v1.2.3 From 155cc1647fb7ec488fb1d93ba68bc2523ffee381 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 04:00:51 +0200 Subject: r300: more prepare for merge --- src/mesa/drivers/dri/r300/r300_context.h | 1 + src/mesa/drivers/dri/r300/r300_fragprog.c | 10 +++++----- src/mesa/drivers/dri/r300/r300_fragprog.h | 5 +---- src/mesa/drivers/dri/r300/r300_state.c | 2 ++ src/mesa/drivers/dri/r300/r500_fragprog.c | 21 +++++++-------------- src/mesa/drivers/dri/r300/r500_fragprog.h | 1 + 6 files changed, 17 insertions(+), 23 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 41417f3122f..904218fde21 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -616,6 +616,7 @@ struct r300_vtable { void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings); void (* TranslateFragmentShader)(GLcontext *ctx, struct gl_fragment_program *fp); GLboolean (* FragmentProgramEmit)(struct r300_fragment_program_compiler *compiler); + void (* FragmentProgramDump)(union rX00_fragment_program_code *code); GLboolean (* SetupPixelShader)(GLcontext *ctx); }; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index d58b0921224..a8b885a4c6d 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -464,19 +464,19 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) r300_fp->translated = GL_TRUE; - if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) - r300FragmentProgramDump(r300_fp, &r300_fp->code.r300); r300UpdateStateParameters(ctx, _NEW_PROGRAM); + + if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) + r300->vtbl.FragmentProgramDump(&r300_fp->code); } update_params(ctx, fp); } /* just some random things... */ -void r300FragmentProgramDump( - struct r300_fragment_program *fp, - struct r300_fragment_program_code *code) +void r300FragmentProgramDump(union rX00_fragment_program_code *c) { + struct r300_fragment_program_code *code = &c->r300; int n, i, j; static int pc = 0; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 631e40913c6..5c2cb312af2 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -114,9 +114,6 @@ extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_progr extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); - -extern void r300FragmentProgramDump( - struct r300_fragment_program *fp, - struct r300_fragment_program_code *code); +extern void r300FragmentProgramDump(union rX00_fragment_program_code *c); #endif diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 95380a2870e..64b462bc909 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2584,11 +2584,13 @@ void r300InitShaderFunctions(r300ContextPtr r300) r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures; r300->vtbl.TranslateFragmentShader = r500TranslateFragmentShader; r300->vtbl.FragmentProgramEmit = r500FragmentProgramEmit; + r300->vtbl.FragmentProgramDump = r500FragmentProgramDump; } else { r300->vtbl.SetupRSUnit = r300SetupRSUnit; r300->vtbl.SetupPixelShader = r300SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures; r300->vtbl.TranslateFragmentShader = r300TranslateFragmentShader; r300->vtbl.FragmentProgramEmit = r300FragmentProgramEmit; + r300->vtbl.FragmentProgramDump = r300FragmentProgramDump; } } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 3e21e0f4975..3b45eee5377 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -435,8 +435,6 @@ static void build_state( } } -static void dump_program(struct r500_fragment_program_code *code); - void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) { r300ContextPtr r300 = R300_CONTEXT(ctx); @@ -494,24 +492,19 @@ void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) if (!r300->vtbl.FragmentProgramEmit(&compiler)) r300_fp->error = GL_TRUE; - r300_fp->translated = GL_TRUE; - /* Subtle: Rescue any parameters that have been added during transformations */ _mesa_free_parameter_list(fp->Base.Parameters); fp->Base.Parameters = compiler.program->Parameters; compiler.program->Parameters = 0; - _mesa_reference_program(ctx, &compiler.program, 0); + _mesa_reference_program(ctx, &compiler.program, NULL); - r300UpdateStateParameters(ctx, _NEW_PROGRAM); + r300_fp->translated = GL_TRUE; - if (RADEON_DEBUG & DEBUG_PIXEL) { - if (!r300_fp->error) { - _mesa_printf("Machine-readable code:\n"); - dump_program(&r300_fp->code.r500); - } - } + r300UpdateStateParameters(ctx, _NEW_PROGRAM); + if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) + r300->vtbl.FragmentProgramDump(&r300_fp->code); } update_params(ctx, fp); @@ -615,9 +608,9 @@ static char *to_texop(int val) return NULL; } -static void dump_program(struct r500_fragment_program_code *code) +void r500FragmentProgramDump(union rX00_fragment_program_code *c) { - + struct r500_fragment_program_code *code = &c->r500; fprintf(stderr, "R500 Fragment Program:\n--------\n"); int n; diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 4e72ef7aac2..5bda0d1d0da 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -49,4 +49,5 @@ extern void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_progr extern GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); +extern void r500FragmentProgramDump(union rX00_fragment_program_code *c); #endif -- cgit v1.2.3 From 300661d12a1f0ab6c81b087a2ca8c4655abf7066 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 12:39:13 +0200 Subject: r300: more r300/r500 unification reuse insert_WPOS_trailer function --- src/mesa/drivers/dri/r300/r300_fragprog.c | 4 +- src/mesa/drivers/dri/r300/r300_fragprog.h | 7 +- src/mesa/drivers/dri/r300/r500_fragprog.c | 107 ++---------------------------- src/mesa/drivers/dri/r300/r500_fragprog.h | 5 ++ 4 files changed, 13 insertions(+), 110 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index a8b885a4c6d..13a1c300ddf 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -263,10 +263,8 @@ static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) * All other code pieces that reference that input will be rewritten * to read from a newly allocated temporary. * - * \todo if/when r5xx supports the radeon_program architecture, this is a - * likely candidate for code sharing. */ -static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) +void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) { GLuint InputsRead = compiler->fp->Base.Base.InputsRead; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 5c2cb312af2..08f65843834 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -105,12 +105,9 @@ #endif -extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); +extern void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler); -/** - * Used internally by the r300 fragment program code to store compile-time - * only data. - */ +extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 3b45eee5377..eb93648e2fb 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -29,6 +29,7 @@ #include "radeon_nqssadce.h" #include "radeon_program_alu.h" +#include "r300_fragprog.h" static void reset_srcreg(struct prog_src_register* reg) @@ -197,110 +198,13 @@ static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) } -/** - * Transform the program to support fragment.position. - * - * Introduce a small fragment at the start of the program that will be - * the only code that directly reads the FRAG_ATTRIB_WPOS input. - * All other code pieces that reference that input will be rewritten - * to read from a newly allocated temporary. - * - * \todo if/when r5xx supports the radeon_program architecture, this is a - * likely candidate for code sharing. - */ -static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) -{ - GLuint InputsRead = compiler->fp->Base.Base.InputsRead; - - if (!(InputsRead & FRAG_BIT_WPOS)) - return; - - static gl_state_index tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0 - }; - struct prog_instruction *fpi; - GLuint window_index; - int i = 0; - GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY); - - _mesa_insert_instructions(compiler->program, 0, 3); - fpi = compiler->program->Instructions; - - /* perspective divide */ - fpi[i].Opcode = OPCODE_RCP; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_W; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_INPUT; - fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; - fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW; - i++; - - fpi[i].Opcode = OPCODE_MUL; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_INPUT; - fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; - fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW; - - fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[1].Index = tempregi; - fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW; - i++; - - /* viewport transformation */ - window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens); - - fpi[i].Opcode = OPCODE_MAD; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[0].Index = tempregi; - fpi[i].SrcReg[0].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - - fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR; - fpi[i].SrcReg[1].Index = window_index; - fpi[i].SrcReg[1].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - - fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR; - fpi[i].SrcReg[2].Index = window_index; - fpi[i].SrcReg[2].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - i++; - - for (; i < compiler->program->NumInstructions; ++i) { - int reg; - for (reg = 0; reg < 3; reg++) { - if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT && - fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) { - fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[reg].Index = tempregi; - } - } - } -} - - static void nqssadce_init(struct nqssadce_state* s) { s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW; s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W; } -static GLboolean is_native_swizzle(GLuint opcode, struct prog_src_register reg) +GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) { GLuint relevant; int i; @@ -366,8 +270,7 @@ static GLboolean is_native_swizzle(GLuint opcode, struct prog_src_register reg) * The only thing we *cannot* do in an ALU instruction is per-component * negation. Therefore, we split the MOV into two instructions when necessary. */ -static void nqssadce_build_swizzle(struct nqssadce_state *s, - struct prog_dst_register dst, struct prog_src_register src) +void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src) { struct prog_instruction *inst; GLuint negatebase[2] = { 0, 0 }; @@ -478,8 +381,8 @@ void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) struct radeon_nqssadce_descr nqssadce = { .Init = &nqssadce_init, - .IsNativeSwizzle = &is_native_swizzle, - .BuildSwizzle = &nqssadce_build_swizzle, + .IsNativeSwizzle = &r500FPIsNativeSwizzle, + .BuildSwizzle = &r500FPBuildSwizzle, .RewriteDepthOut = GL_TRUE }; radeonNqssaDce(ctx, compiler.program, &nqssadce); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 5bda0d1d0da..2e14098f5db 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -44,10 +44,15 @@ #include "r300_context.h" #include "r300_state.h" #include "radeon_program.h" +#include "radeon_nqssadce.h" extern void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); extern GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); extern void r500FragmentProgramDump(union rX00_fragment_program_code *c); + +extern GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg); + +extern void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src); #endif -- cgit v1.2.3 From a2d49eeaebcb9d5869e6f6d57d0aa050a825d8b6 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 13:35:43 +0200 Subject: r300: move common fp functions to seperate file --- src/mesa/drivers/dri/r300/Makefile | 1 + src/mesa/drivers/dri/r300/r300_context.h | 1 - src/mesa/drivers/dri/r300/r300_fragprog.c | 244 +------------------- src/mesa/drivers/dri/r300/r300_fragprog.h | 6 +- src/mesa/drivers/dri/r300/r300_fragprog_common.c | 282 +++++++++++++++++++++++ src/mesa/drivers/dri/r300/r300_fragprog_common.h | 35 +++ src/mesa/drivers/dri/r300/r300_render.c | 5 +- src/mesa/drivers/dri/r300/r300_shader.c | 31 ++- src/mesa/drivers/dri/r300/r300_state.c | 7 +- src/mesa/drivers/dri/r300/r500_fragprog.c | 132 +---------- src/mesa/drivers/dri/r300/r500_fragprog.h | 4 +- 11 files changed, 358 insertions(+), 390 deletions(-) create mode 100644 src/mesa/drivers/dri/r300/r300_fragprog_common.c create mode 100644 src/mesa/drivers/dri/r300/r300_fragprog_common.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 0dff9a12731..62715e3b50d 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -48,6 +48,7 @@ DRIVER_SOURCES = \ radeon_program_pair.c \ radeon_nqssadce.c \ r300_vertprog.c \ + r300_fragprog_common.c \ r300_fragprog.c \ r300_fragprog_swizzle.c \ r300_fragprog_emit.c \ diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 904218fde21..949a3ca45ad 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -614,7 +614,6 @@ struct r300_swtcl_info { struct r300_vtable { void (* SetupRSUnit)(GLcontext *ctx); void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings); - void (* TranslateFragmentShader)(GLcontext *ctx, struct gl_fragment_program *fp); GLboolean (* FragmentProgramEmit)(struct r300_fragment_program_compiler *compiler); void (* FragmentProgramDump)(union rX00_fragment_program_code *code); GLboolean (* SetupPixelShader)(GLcontext *ctx); diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 13a1c300ddf..825246687fb 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -25,21 +25,6 @@ * */ -/** - * \file - * - * Fragment program compiler. Perform transformations on the intermediate - * representation until the program is in a form where we can translate - * it more or less directly into machine-readable form. - * - * \author Ben Skeggs - * \author Jerome Glisse - */ - -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" -#include "shader/prog_instruction.h" #include "shader/prog_parameter.h" #include "shader/prog_print.h" @@ -49,8 +34,6 @@ #include "r300_state.h" #include "radeon_nqssadce.h" -#include "radeon_program_alu.h" - static void reset_srcreg(struct prog_src_register* reg) { @@ -81,7 +64,7 @@ static struct prog_src_register shadow_ambient(struct gl_program *program, int t * \todo If/when r5xx uses the radeon_program architecture, this can probably * be reused. */ -static GLboolean transform_TEX( +GLboolean r300_transform_TEX( struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data) { @@ -246,231 +229,6 @@ static GLboolean transform_TEX( return GL_TRUE; } - -static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) -{ - /* Ask Mesa nicely to fill in ParameterValues for us */ - if (fp->Base.Parameters) - _mesa_load_state_parameters(ctx, fp->Base.Parameters); -} - - -/** - * Transform the program to support fragment.position. - * - * Introduce a small fragment at the start of the program that will be - * the only code that directly reads the FRAG_ATTRIB_WPOS input. - * All other code pieces that reference that input will be rewritten - * to read from a newly allocated temporary. - * - */ -void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) -{ - GLuint InputsRead = compiler->fp->Base.Base.InputsRead; - - if (!(InputsRead & FRAG_BIT_WPOS)) - return; - - static gl_state_index tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0 - }; - struct prog_instruction *fpi; - GLuint window_index; - int i = 0; - GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY); - - _mesa_insert_instructions(compiler->program, 0, 3); - fpi = compiler->program->Instructions; - - /* perspective divide */ - fpi[i].Opcode = OPCODE_RCP; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_W; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_INPUT; - fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; - fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW; - i++; - - fpi[i].Opcode = OPCODE_MUL; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_INPUT; - fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; - fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW; - - fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[1].Index = tempregi; - fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW; - i++; - - /* viewport transformation */ - window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens); - - fpi[i].Opcode = OPCODE_MAD; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[0].Index = tempregi; - fpi[i].SrcReg[0].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - - fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR; - fpi[i].SrcReg[1].Index = window_index; - fpi[i].SrcReg[1].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - - fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR; - fpi[i].SrcReg[2].Index = window_index; - fpi[i].SrcReg[2].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - i++; - - for (; i < compiler->program->NumInstructions; ++i) { - int reg; - for (reg = 0; reg < 3; reg++) { - if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT && - fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) { - fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[reg].Index = tempregi; - } - } - } -} - - -static void nqssadce_init(struct nqssadce_state* s) -{ - s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW; - s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W; -} - - -static GLuint build_dtm(GLuint depthmode) -{ - switch(depthmode) { - default: - case GL_LUMINANCE: return 0; - case GL_INTENSITY: return 1; - case GL_ALPHA: return 2; - } -} - -static GLuint build_func(GLuint comparefunc) -{ - return comparefunc - GL_NEVER; -} - - -/** - * Collect all external state that is relevant for compiling the given - * fragment program. - */ -static void build_state( - r300ContextPtr r300, - struct r300_fragment_program *fp, - struct r300_fragment_program_external_state *state) -{ - int unit; - - _mesa_bzero(state, sizeof(*state)); - - for(unit = 0; unit < 16; ++unit) { - if (fp->Base.Base.ShadowSamplers & (1 << unit)) { - struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; - - state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); - state->unit[unit].texture_compare_func = build_func(tex->CompareFunc); - } - } -} - - -void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; - struct r300_fragment_program_external_state state; - - build_state(r300, r300_fp, &state); - if (_mesa_memcmp(&r300_fp->state, &state, sizeof(state))) { - /* TODO: cache compiled programs */ - r300_fp->translated = GL_FALSE; - _mesa_memcpy(&r300_fp->state, &state, sizeof(state)); - } - - if (!r300_fp->translated) { - struct r300_fragment_program_compiler compiler; - - compiler.r300 = r300; - compiler.fp = r300_fp; - compiler.code = &r300_fp->code; - compiler.program = _mesa_clone_program(ctx, &fp->Base); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Fragment Program: Initial program:\n"); - _mesa_print_program(compiler.program); - } - - insert_WPOS_trailer(&compiler); - - struct radeon_program_transformation transformations[] = { - { &transform_TEX, &compiler }, - { &radeonTransformALU, 0 }, - { &radeonTransformTrigSimple, 0 } - }; - radeonLocalTransform(ctx, compiler.program, 3, transformations); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Fragment Program: After native rewrite:\n"); - _mesa_print_program(compiler.program); - } - - struct radeon_nqssadce_descr nqssadce = { - .Init = &nqssadce_init, - .IsNativeSwizzle = &r300FPIsNativeSwizzle, - .BuildSwizzle = &r300FPBuildSwizzle, - .RewriteDepthOut = GL_TRUE - }; - radeonNqssaDce(ctx, compiler.program, &nqssadce); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: after NqSSA-DCE:\n"); - _mesa_print_program(compiler.program); - } - - if (!r300->vtbl.FragmentProgramEmit(&compiler)) - r300_fp->error = GL_TRUE; - - /* Subtle: Rescue any parameters that have been added during transformations */ - _mesa_free_parameter_list(fp->Base.Parameters); - fp->Base.Parameters = compiler.program->Parameters; - compiler.program->Parameters = 0; - - _mesa_reference_program(ctx, &compiler.program, NULL); - - r300_fp->translated = GL_TRUE; - - r300UpdateStateParameters(ctx, _NEW_PROGRAM); - - if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) - r300->vtbl.FragmentProgramDump(&r300_fp->code); - } - - update_params(ctx, fp); -} - /* just some random things... */ void r300FragmentProgramDump(union rX00_fragment_program_code *c) { diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 08f65843834..0713810adeb 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -105,12 +105,10 @@ #endif -extern void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler); - -extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); - extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); extern void r300FragmentProgramDump(union rX00_fragment_program_code *c); +extern GLboolean r300_transform_TEX(struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data); + #endif diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c new file mode 100644 index 00000000000..953d920d1fd --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2009 Maciej Cencora + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/** + * \file + * + * Fragment program compiler. Perform transformations on the intermediate + * representation until the program is in a form where we can translate + * it more or less directly into machine-readable form. + * + * \author Ben Skeggs + * \author Jerome Glisse + */ + +#include "r300_fragprog_common.h" + +#include "r300_fragprog.h" +#include "r300_fragprog_swizzle.h" +#include "r500_fragprog.h" + +#include "radeon_program.h" +#include "radeon_program_alu.h" + +static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) +{ + /* Ask Mesa nicely to fill in ParameterValues for us */ + if (fp->Base.Parameters) + _mesa_load_state_parameters(ctx, fp->Base.Parameters); +} + +static void nqssadce_init(struct nqssadce_state* s) +{ + s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW; + s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W; +} + +/** + * Transform the program to support fragment.position. + * + * Introduce a small fragment at the start of the program that will be + * the only code that directly reads the FRAG_ATTRIB_WPOS input. + * All other code pieces that reference that input will be rewritten + * to read from a newly allocated temporary. + * + */ +static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) +{ + GLuint InputsRead = compiler->fp->Base.Base.InputsRead; + + if (!(InputsRead & FRAG_BIT_WPOS)) + return; + + static gl_state_index tokens[STATE_LENGTH] = { + STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0 + }; + struct prog_instruction *fpi; + GLuint window_index; + int i = 0; + GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY); + + _mesa_insert_instructions(compiler->program, 0, 3); + fpi = compiler->program->Instructions; + + /* perspective divide */ + fpi[i].Opcode = OPCODE_RCP; + + fpi[i].DstReg.File = PROGRAM_TEMPORARY; + fpi[i].DstReg.Index = tempregi; + fpi[i].DstReg.WriteMask = WRITEMASK_W; + fpi[i].DstReg.CondMask = COND_TR; + + fpi[i].SrcReg[0].File = PROGRAM_INPUT; + fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; + fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW; + i++; + + fpi[i].Opcode = OPCODE_MUL; + + fpi[i].DstReg.File = PROGRAM_TEMPORARY; + fpi[i].DstReg.Index = tempregi; + fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; + fpi[i].DstReg.CondMask = COND_TR; + + fpi[i].SrcReg[0].File = PROGRAM_INPUT; + fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; + fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW; + + fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY; + fpi[i].SrcReg[1].Index = tempregi; + fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW; + i++; + + /* viewport transformation */ + window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens); + + fpi[i].Opcode = OPCODE_MAD; + + fpi[i].DstReg.File = PROGRAM_TEMPORARY; + fpi[i].DstReg.Index = tempregi; + fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; + fpi[i].DstReg.CondMask = COND_TR; + + fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY; + fpi[i].SrcReg[0].Index = tempregi; + fpi[i].SrcReg[0].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); + + fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR; + fpi[i].SrcReg[1].Index = window_index; + fpi[i].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); + + fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR; + fpi[i].SrcReg[2].Index = window_index; + fpi[i].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); + i++; + + for (; i < compiler->program->NumInstructions; ++i) { + int reg; + for (reg = 0; reg < 3; reg++) { + if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT && + fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) { + fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY; + fpi[i].SrcReg[reg].Index = tempregi; + } + } + } +} + +static GLuint build_dtm(GLuint depthmode) +{ + switch(depthmode) { + default: + case GL_LUMINANCE: return 0; + case GL_INTENSITY: return 1; + case GL_ALPHA: return 2; + } +} + +static GLuint build_func(GLuint comparefunc) +{ + return comparefunc - GL_NEVER; +} + +/** + * Collect all external state that is relevant for compiling the given + * fragment program. + */ +static void build_state( + r300ContextPtr r300, + struct r300_fragment_program *fp, + struct r300_fragment_program_external_state *state) +{ + int unit; + + _mesa_bzero(state, sizeof(*state)); + + for(unit = 0; unit < 16; ++unit) { + if (fp->Base.Base.ShadowSamplers & (1 << unit)) { + struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; + + state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); + state->unit[unit].texture_compare_func = build_func(tex->CompareFunc); + } + } +} + +void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; + struct r300_fragment_program_external_state state; + + build_state(r300, r300_fp, &state); + if (_mesa_memcmp(&r300_fp->state, &state, sizeof(state))) { + /* TODO: cache compiled programs */ + r300_fp->translated = GL_FALSE; + _mesa_memcpy(&r300_fp->state, &state, sizeof(state)); + } + + if (!r300_fp->translated) { + struct r300_fragment_program_compiler compiler; + + compiler.r300 = r300; + compiler.fp = r300_fp; + compiler.code = &r300_fp->code; + compiler.program = _mesa_clone_program(ctx, &fp->Base); + + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Fragment Program: Initial program:\n"); + _mesa_print_program(compiler.program); + } + + insert_WPOS_trailer(&compiler); + + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + struct radeon_program_transformation transformations[] = { + { &r500_transform_TEX, &compiler }, + { &radeonTransformALU, 0 }, + { &radeonTransformDeriv, 0 }, + { &radeonTransformTrigScale, 0 } + }; + radeonLocalTransform(ctx, compiler.program, 4, transformations); + } else { + struct radeon_program_transformation transformations[] = { + { &r300_transform_TEX, &compiler }, + { &radeonTransformALU, 0 }, + { &radeonTransformTrigSimple, 0 } + }; + radeonLocalTransform(ctx, compiler.program, 3, transformations); + } + + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Fragment Program: After native rewrite:\n"); + _mesa_print_program(compiler.program); + } + + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + struct radeon_nqssadce_descr nqssadce = { + .Init = &nqssadce_init, + .IsNativeSwizzle = &r500FPIsNativeSwizzle, + .BuildSwizzle = &r500FPBuildSwizzle, + .RewriteDepthOut = GL_TRUE + }; + radeonNqssaDce(ctx, compiler.program, &nqssadce); + } else { + struct radeon_nqssadce_descr nqssadce = { + .Init = &nqssadce_init, + .IsNativeSwizzle = &r300FPIsNativeSwizzle, + .BuildSwizzle = &r300FPBuildSwizzle, + .RewriteDepthOut = GL_TRUE + }; + radeonNqssaDce(ctx, compiler.program, &nqssadce); + } + + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Compiler: after NqSSA-DCE:\n"); + _mesa_print_program(compiler.program); + } + + if (!r300->vtbl.FragmentProgramEmit(&compiler)) + r300_fp->error = GL_TRUE; + + /* Subtle: Rescue any parameters that have been added during transformations */ + _mesa_free_parameter_list(fp->Base.Parameters); + fp->Base.Parameters = compiler.program->Parameters; + compiler.program->Parameters = 0; + + _mesa_reference_program(ctx, &compiler.program, NULL); + + r300_fp->translated = GL_TRUE; + + r300UpdateStateParameters(ctx, _NEW_PROGRAM); + + if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) + r300->vtbl.FragmentProgramDump(&r300_fp->code); + } + + update_params(ctx, fp); +} diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.h b/src/mesa/drivers/dri/r300/r300_fragprog_common.h new file mode 100644 index 00000000000..85ea86fecb1 --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2009 Maciej Cencora + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __R300_FRAGPROG_COMMON_H_ +#define __R300_FRAGPROG_COMMON_H_ + +#include "main/mtypes.h" + +extern void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); + +#endif diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 91f58ade599..41b5e30be49 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -72,7 +72,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_reg.h" #include "r300_tex.h" #include "r300_emit.h" -#include "r300_fragprog.h" +#include "r300_fragprog_common.h" + extern int future_hw_tcl_on; /** @@ -432,7 +433,7 @@ static int r300Fallback(GLcontext * ctx) struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; if (fp && !fp->translated) { - r300->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); + r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); FALLBACK_IF(fp->error); } diff --git a/src/mesa/drivers/dri/r300/r300_shader.c b/src/mesa/drivers/dri/r300/r300_shader.c index 68fd8cd21e2..0133b837966 100644 --- a/src/mesa/drivers/dri/r300/r300_shader.c +++ b/src/mesa/drivers/dri/r300/r300_shader.c @@ -1,10 +1,36 @@ +/* + * Copyright 2009 Maciej Cencora + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ #include "main/glheader.h" #include "shader/program.h" #include "tnl/tnl.h" #include "r300_context.h" -#include "r300_fragprog.h" +#include "r300_fragprog_common.h" static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target, GLuint id) @@ -59,10 +85,9 @@ static GLboolean r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) { if (target == GL_FRAGMENT_PROGRAM_ARB) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_fragment_program *fp = (struct r300_fragment_program *)prog; if (!fp->translated) - rmesa->vtbl.TranslateFragmentShader(ctx, &fp->Base); + r300TranslateFragmentShader(ctx, &fp->Base); return !fp->error; } else diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 64b462bc909..4cbbfd49c91 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -59,8 +59,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_reg.h" #include "r300_emit.h" -#include "r300_fragprog.h" #include "r300_tex.h" +#include "r300_fragprog_common.h" +#include "r300_fragprog.h" #include "r500_fragprog.h" #include "drirenderbuffer.h" @@ -2458,7 +2459,7 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; } - rmesa->vtbl.TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); + r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); if (!rmesa->vtbl.SetupPixelShader(ctx)) return; @@ -2582,14 +2583,12 @@ void r300InitShaderFunctions(r300ContextPtr r300) r300->vtbl.SetupRSUnit = r500SetupRSUnit; r300->vtbl.SetupPixelShader = r500SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures; - r300->vtbl.TranslateFragmentShader = r500TranslateFragmentShader; r300->vtbl.FragmentProgramEmit = r500FragmentProgramEmit; r300->vtbl.FragmentProgramDump = r500FragmentProgramDump; } else { r300->vtbl.SetupRSUnit = r300SetupRSUnit; r300->vtbl.SetupPixelShader = r300SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures; - r300->vtbl.TranslateFragmentShader = r300TranslateFragmentShader; r300->vtbl.FragmentProgramEmit = r300FragmentProgramEmit; r300->vtbl.FragmentProgramDump = r300FragmentProgramDump; } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index eb93648e2fb..6de92effe66 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -31,7 +31,6 @@ #include "radeon_program_alu.h" #include "r300_fragprog.h" - static void reset_srcreg(struct prog_src_register* reg) { _mesa_bzero(reg, sizeof(*reg)); @@ -59,7 +58,7 @@ static struct prog_src_register shadow_ambient(struct gl_program *program, int t * - introduce a temporary register when write masks are needed * */ -static GLboolean transform_TEX( +GLboolean r500_transform_TEX( struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data) { @@ -189,21 +188,6 @@ static GLboolean transform_TEX( return GL_TRUE; } - -static void update_params(GLcontext *ctx, struct gl_fragment_program *fp) -{ - /* Ask Mesa nicely to fill in ParameterValues for us */ - if (fp->Base.Parameters) - _mesa_load_state_parameters(ctx, fp->Base.Parameters); -} - - -static void nqssadce_init(struct nqssadce_state* s) -{ - s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW; - s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W; -} - GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) { GLuint relevant; @@ -299,120 +283,6 @@ void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, } } -static GLuint build_dtm(GLuint depthmode) -{ - switch(depthmode) { - default: - case GL_LUMINANCE: return 0; - case GL_INTENSITY: return 1; - case GL_ALPHA: return 2; - } -} - -static GLuint build_func(GLuint comparefunc) -{ - return comparefunc - GL_NEVER; -} - - -/** - * Collect all external state that is relevant for compiling the given - * fragment program. - */ -static void build_state( - r300ContextPtr r300, - struct r300_fragment_program *fp, - struct r300_fragment_program_external_state *state) -{ - int unit; - - _mesa_bzero(state, sizeof(*state)); - - for(unit = 0; unit < 16; ++unit) { - if (fp->Base.Base.ShadowSamplers & (1 << unit)) { - struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; - - state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); - state->unit[unit].texture_compare_func = build_func(tex->CompareFunc); - } - } -} - -void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)fp; - struct r300_fragment_program_external_state state; - - build_state(r300, r300_fp, &state); - if (_mesa_memcmp(&r300_fp->state, &state, sizeof(state))) { - /* TODO: cache compiled programs */ - r300_fp->translated = GL_FALSE; - _mesa_memcpy(&r300_fp->state, &state, sizeof(state)); - } - - if (!r300_fp->translated) { - struct r300_fragment_program_compiler compiler; - - compiler.r300 = r300; - compiler.fp = r300_fp; - compiler.code = &r300_fp->code; - compiler.program = _mesa_clone_program(ctx, &fp->Base); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: Initial program:\n"); - _mesa_print_program(compiler.program); - } - - insert_WPOS_trailer(&compiler); - - struct radeon_program_transformation transformations[] = { - { &transform_TEX, &compiler }, - { &radeonTransformALU, 0 }, - { &radeonTransformDeriv, 0 }, - { &radeonTransformTrigScale, 0 } - }; - radeonLocalTransform(ctx, compiler.program, 4, transformations); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: after native rewrite:\n"); - _mesa_print_program(compiler.program); - } - - struct radeon_nqssadce_descr nqssadce = { - .Init = &nqssadce_init, - .IsNativeSwizzle = &r500FPIsNativeSwizzle, - .BuildSwizzle = &r500FPBuildSwizzle, - .RewriteDepthOut = GL_TRUE - }; - radeonNqssaDce(ctx, compiler.program, &nqssadce); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: after NqSSA-DCE:\n"); - _mesa_print_program(compiler.program); - } - - if (!r300->vtbl.FragmentProgramEmit(&compiler)) - r300_fp->error = GL_TRUE; - - /* Subtle: Rescue any parameters that have been added during transformations */ - _mesa_free_parameter_list(fp->Base.Parameters); - fp->Base.Parameters = compiler.program->Parameters; - compiler.program->Parameters = 0; - - _mesa_reference_program(ctx, &compiler.program, NULL); - - r300_fp->translated = GL_TRUE; - - r300UpdateStateParameters(ctx, _NEW_PROGRAM); - - if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) - r300->vtbl.FragmentProgramDump(&r300_fp->code); - } - - update_params(ctx, fp); - -} static char *toswiz(int swiz_val) { switch(swiz_val) { diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 2e14098f5db..c7e313774cf 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -46,8 +46,6 @@ #include "radeon_program.h" #include "radeon_nqssadce.h" -extern void r500TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp); - extern GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); extern void r500FragmentProgramDump(union rX00_fragment_program_code *c); @@ -55,4 +53,6 @@ extern void r500FragmentProgramDump(union rX00_fragment_program_code *c); extern GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg); extern void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src); + +extern GLboolean r500_transform_TEX(struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data); #endif -- cgit v1.2.3 From 78878a13fe9cc5dea36c6427c99c7fe17391dbfb Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 13:37:30 +0200 Subject: r300: cleanup includes --- src/mesa/drivers/dri/r300/r300_fragprog.c | 7 ++----- src/mesa/drivers/dri/r300/r300_fragprog.h | 3 --- src/mesa/drivers/dri/r300/r300_fragprog_common.c | 5 +++++ src/mesa/drivers/dri/r300/r500_fragprog.c | 4 ---- src/mesa/drivers/dri/r300/r500_fragprog.h | 8 +------- 5 files changed, 8 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 825246687fb..921ca33c750 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -25,15 +25,12 @@ * */ +#include "r300_fragprog.h" + #include "shader/prog_parameter.h" -#include "shader/prog_print.h" #include "r300_context.h" -#include "r300_fragprog.h" #include "r300_fragprog_swizzle.h" -#include "r300_state.h" - -#include "radeon_nqssadce.h" static void reset_srcreg(struct prog_src_register* reg) { diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 0713810adeb..affa022a5cf 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -33,9 +33,6 @@ #ifndef __R300_FRAGPROG_H_ #define __R300_FRAGPROG_H_ -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" #include "shader/program.h" #include "shader/prog_instruction.h" diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c index 953d920d1fd..3d4bd5db217 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c @@ -38,6 +38,11 @@ #include "r300_fragprog_common.h" +#include "shader/program.h" +#include "shader/prog_parameter.h" +#include "shader/prog_print.h" + +#include "r300_state.h" #include "r300_fragprog.h" #include "r300_fragprog_swizzle.h" #include "r500_fragprog.h" diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 6de92effe66..e9c0d89dd43 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -27,10 +27,6 @@ #include "r500_fragprog.h" -#include "radeon_nqssadce.h" -#include "radeon_program_alu.h" -#include "r300_fragprog.h" - static void reset_srcreg(struct prog_src_register* reg) { _mesa_bzero(reg, sizeof(*reg)); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index c7e313774cf..9ca2f9be510 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -33,17 +33,10 @@ #ifndef __R500_FRAGPROG_H_ #define __R500_FRAGPROG_H_ -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" #include "shader/prog_parameter.h" -#include "shader/prog_print.h" -#include "shader/program.h" #include "shader/prog_instruction.h" #include "r300_context.h" -#include "r300_state.h" -#include "radeon_program.h" #include "radeon_nqssadce.h" extern GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); @@ -55,4 +48,5 @@ extern GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register r extern void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src); extern GLboolean r500_transform_TEX(struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data); + #endif -- cgit v1.2.3 From bcef4b63eba3b6072df3a699d0c4d5128e2515b9 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 19 Apr 2009 15:26:51 +0200 Subject: r300: revert part of cb4bef7ae0b5fe8de82c380bc98f19067394d355 Some debugging code got there by accident --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 28 ++++-------------------- 1 file changed, 4 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index f7c50e9949a..34d62617068 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat) { int bytes = 0; switch(mesaFormat) { - + case MESA_FORMAT_RGB_FXT1: case MESA_FORMAT_RGBA_FXT1: case MESA_FORMAT_RGB_DXT1: case MESA_FORMAT_RGBA_DXT1: bytes = 2; break; - + case MESA_FORMAT_RGBA_DXT3: case MESA_FORMAT_RGBA_DXT5: bytes = 4; default: break; } - + return bytes; } @@ -97,38 +97,18 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, lvl->width, lvl->height, lvl->depth, mt->compressed); - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = lvl->rowstride * lvl->height; - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } else { lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; lvl->size = lvl->rowstride * lvl->height * lvl->depth; - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } assert(lvl->size > 0); @@ -250,7 +230,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj, tObj->Image[face][level]; assert(baseImage); - + /* These must be signed values. MinLod and MaxLod can be negative numbers, * and having firstLevel and lastLevel as signed prevents the need for * extra sign checks. -- cgit v1.2.3 From 65fe0c86ffcff99f9f09606d462bf3731ea0c308 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 19 Apr 2009 15:28:10 +0200 Subject: r300: fix missing function declaration --- src/mesa/drivers/dri/r300/r300_context.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 949a3ca45ad..1c7bfc819bd 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -659,6 +659,8 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx, struct r300_vertex_program_cont *vp, float *dst); +extern void r300InitShaderFunctions(r300ContextPtr r300); + #define r300PackFloat32 radeonPackFloat32 #define r300PackFloat24 radeonPackFloat24 -- cgit v1.2.3 From 5dec94696e67ca5a1d008530cbfea90f03aeff16 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 24 Apr 2009 15:03:23 +0200 Subject: r300: emit cliprect when in dri2 mode --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index c575c9ac496..850ba370226 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -215,6 +215,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) uint32_t cbpitch; uint32_t offset = r300->radeon.state.color.draw_offset; uint32_t dw = 6; + int i; rrb = radeon_get_colorbuffer(&r300->radeon); if (!rrb || !rrb->bo) { @@ -250,6 +251,17 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) | (rrb->height << R300_SCISSORS_Y_SHIFT)); END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(16); + for (i = 0; i < 4; i++) { + OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); + OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH((rrb->width << R300_CLIPRECT_X_SHIFT) | (rrb->height << R300_CLIPRECT_Y_SHIFT)); + } + OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); + OUT_BATCH(0xAAAA); + OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1); + OUT_BATCH(0xffffff); + END_BATCH(); } else { BEGIN_BATCH_NO_AUTOSTATE(3); OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); @@ -258,6 +270,17 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) | ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT)); END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(16); + for (i = 0; i < 4; i++) { + OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); + OUT_BATCH((1088 << R300_CLIPRECT_X_SHIFT) | (1088 << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH(((1088 + rrb->width) << R300_CLIPRECT_X_SHIFT) | ((1088 + rrb->height) << R300_CLIPRECT_Y_SHIFT)); + } + OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); + OUT_BATCH(0xAAAA); + OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1); + OUT_BATCH(0xffffff); + END_BATCH(); } } } -- cgit v1.2.3 From 32d185eb60ea7d0d1a67429055f7544129d52276 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 24 Apr 2009 19:54:01 +0200 Subject: r300: fix cliprect values --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 850ba370226..4c6108cc636 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -248,14 +248,14 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) BEGIN_BATCH_NO_AUTOSTATE(3); OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); OUT_BATCH(0); - OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) | - (rrb->height << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) | + ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT)); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(16); for (i = 0; i < 4; i++) { OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT)); - OUT_BATCH((rrb->width << R300_CLIPRECT_X_SHIFT) | (rrb->height << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT)); } OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); OUT_BATCH(0xAAAA); @@ -267,14 +267,15 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) | - ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) | + ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT)); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(16); for (i = 0; i < 4; i++) { OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); - OUT_BATCH((1088 << R300_CLIPRECT_X_SHIFT) | (1088 << R300_CLIPRECT_Y_SHIFT)); - OUT_BATCH(((1088 + rrb->width) << R300_CLIPRECT_X_SHIFT) | ((1088 + rrb->height) << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | + ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT)); } OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); OUT_BATCH(0xAAAA); -- cgit v1.2.3 From 931c89f6f6f1f8449ed9d7b41f84e6948774b368 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 19 Apr 2009 21:13:18 +0200 Subject: r300: remove unnecessary function calls r300SetEarlyZState is called during r300UpdateShaderStates which is called for every rendering operation. --- src/mesa/drivers/dri/r300/r300_state.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 4cbbfd49c91..c86c16bfa71 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -524,8 +524,6 @@ static void r300SetAlphaState(GLcontext * ctx) R300_STATECHANGE(r300, at); r300->hw.at.cmd[R300_AT_ALPHA_TEST] = pp_misc; r300->hw.at.cmd[R300_AT_UNKNOWN] = 0; - - r300SetEarlyZState(ctx); } static void r300AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) @@ -573,8 +571,6 @@ static void r300SetDepthState(GLcontext * ctx) r300->hw.zs.cmd[R300_ZS_CNTL_1] |= translate_func(ctx->Depth.Func) << R300_Z_FUNC_SHIFT; } - - r300SetEarlyZState(ctx); } static void r300SetStencilState(GLcontext * ctx, GLboolean state) -- cgit v1.2.3 From 607c6cf1885c8f5fad7ff4a7baf919aa1d24050c Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 19 Apr 2009 21:25:01 +0200 Subject: r300: rename state According to r300_reg.h from radeon drm module 0x4f30 is ZB_ZMASK_OFFSET. Also cleanup as trailing whitespaces. --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 12 ++++++------ src/mesa/drivers/dri/r300/r300_context.h | 2 +- src/mesa/drivers/dri/r300/r300_reg.h | 6 ++++++ src/mesa/drivers/dri/r300/r300_state.c | 4 ++-- 4 files changed, 15 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 4c6108cc636..afca0e24a68 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -83,7 +83,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) BATCH_LOCALS(&r300->radeon); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i; - + if (!r300->radeon.radeonScreen->kernel_mm) { uint32_t dwords; dwords = (*atom->check) (ctx, atom); @@ -92,7 +92,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) END_BATCH(); return; } - + cmd.u = atom->cmd[0]; addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; ndw = cmd.vpu.count * 4; @@ -175,7 +175,7 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) for(i = 0; i < numtmus; ++i) { radeonTexObj *t = r300->hw.textures[i]; - + if (!t) notexture = 1; } @@ -304,7 +304,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ zbpitch |= R300_DEPTHMICROTILE_TILED; } - + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); @@ -606,8 +606,8 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.zb.emit = emit_zb_offset; ALLOC_STATE(zb_depthclearvalue, always, 2, 0); r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1); - ALLOC_STATE(unk4F30, always, 3, 0); - r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2); + ALLOC_STATE(zb_zmask, always, 3, 0); + r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2); ALLOC_STATE(zb_hiz_offset, always, 2, 0); r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1); ALLOC_STATE(zb_hiz_pitch, always, 2, 0); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 1c7bfc819bd..f8d914e7ac4 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -351,7 +351,7 @@ struct r300_hw_state { struct radeon_state_atom zstencil_format; struct radeon_state_atom zb; /* z buffer (4F20) */ struct radeon_state_atom zb_depthclearvalue; /* (4F28) */ - struct radeon_state_atom unk4F30; /* (4F30) */ + struct radeon_state_atom zb_zmask; /* (4F30) */ struct radeon_state_atom zb_hiz_offset; /* (4F44) */ struct radeon_state_atom zb_hiz_pitch; /* (4F54) */ diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index ed552d09bbc..79dd1e1fa21 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -2432,6 +2432,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* Z Buffer Clear Value */ #define R300_ZB_DEPTHCLEARVALUE 0x4f28 +#define R300_ZB_ZMASK_OFFSET 0x4f30 +#define R300_ZB_ZMASK_PITCH 0x4f34 +#define R300_ZB_ZMASK_WRINDEX 0x4f38 +#define R300_ZB_ZMASK_DWORD 0x4f3c +#define R300_ZB_ZMASK_RDINDEX 0x4f40 + /* Hierarchical Z Memory Offset */ #define R300_ZB_HIZ_OFFSET 0x4f44 diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index c86c16bfa71..14749bf2c72 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2205,8 +2205,8 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.zstencil_format.cmd[4] = 0x00000000; r300SetEarlyZState(ctx); - r300->hw.unk4F30.cmd[1] = 0; - r300->hw.unk4F30.cmd[2] = 0; + r300->hw.zb_zmask.cmd[1] = 0; + r300->hw.zb_zmask.cmd[2] = 0; r300->hw.zb_hiz_offset.cmd[1] = 0; -- cgit v1.2.3 From 199710914ab15926d19c5a848453674715bce334 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 23 Apr 2009 15:35:29 +0200 Subject: r300: remove unnecessary function calls ae_create_context is called by vbo_CreateContext ae_invalidate_state is called by vbo_InvalidateState --- src/mesa/drivers/dri/r300/r300_context.c | 1 - src/mesa/drivers/dri/r300/r300_state.c | 1 - 2 files changed, 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 10836bb16ab..3bde9ca30a8 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -373,7 +373,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, _tnl_CreateContext(ctx); _swsetup_CreateContext(ctx); _swsetup_Wakeup(ctx); - _ae_create_context(ctx); /* Install the customized pipeline: */ diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 14749bf2c72..a1f78c5244e 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2477,7 +2477,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) _swsetup_InvalidateState(ctx, new_state); _vbo_InvalidateState(ctx, new_state); _tnl_InvalidateState(ctx, new_state); - _ae_invalidate_state(ctx, new_state); if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { _mesa_update_framebuffer(ctx); -- cgit v1.2.3 From 25dd867c58e5008029dbb5277a82acbcc961a05a Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 23 Apr 2009 15:41:08 +0200 Subject: r300: handle texcoords properly add 1D texture case and setup default Q value to 1.0 --- src/mesa/drivers/dri/r300/r300_swtcl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 256a2bb5cb2..55187d4bc80 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -211,15 +211,19 @@ static void r300SetVertexFormat( GLcontext *ctx ) if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { switch (VB->TexCoordPtr[i]->size) { case 1: + format = EMIT_1F; + swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); + mask = MASK_X; + break; case 2: format = EMIT_2F; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO); + swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE); mask = MASK_X | MASK_Y; size = 2; break; case 3: format = EMIT_3F; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); + swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); mask = MASK_X | MASK_Y | MASK_Z; size = 3; break; -- cgit v1.2.3 From 7ff2dcbbdc74bf5e9650d4a94a253a0cab3e8863 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 23 Apr 2009 16:08:48 +0200 Subject: r300: add atom print function for kernel mm path --- src/mesa/drivers/dri/radeon/radeon_common.c | 64 +++++++++++++++++++++++------ 1 file changed, 52 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index dc281ee269c..312c2a72e92 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -851,20 +851,57 @@ void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei he radeon_window_moved(radeon); radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer); ctx->Driver.Viewport = old_viewport; - - } -static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state ) -{ - int i; - int dwords = (*state->check)(radeon->glCtx, state); - fprintf(stderr, "emit %s %d/%d\n", state->name, state->cmd_size, dwords); - - if (RADEON_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < dwords; i++) - fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); +static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state) +{ + int i, j, reg; + int dwords = (*state->check) (radeon->glCtx, state); + drm_r300_cmd_header_t cmd; + + fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); + + if (RADEON_DEBUG & DEBUG_VERBOSE) { + for (i = 0; i < dwords;) { + cmd = *((drm_r300_cmd_header_t *) &state->cmd[i]); + reg = (cmd.packet0.reghi << 8) | cmd.packet0.reglo; + fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n", + state->name, i, reg, cmd.packet0.count); + ++i; + for (j = 0; j < cmd.packet0.count && i < dwords; j++) { + fprintf(stderr, " %s[%d]: 0x%04x = %08x\n", + state->name, i, reg, state->cmd[i]); + reg += 4; + ++i; + } + } + } +} +static void radeon_print_state_atom_kmm(radeonContextPtr radeon, struct radeon_state_atom *state) +{ + int i, j, reg, count; + int dwords = (*state->check) (radeon->glCtx, state); + uint32_t packet0; + + fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); + + if (RADEON_DEBUG & DEBUG_VERBOSE) { + for (i = 0; i < dwords;) { + packet0 = state->cmd[i]; + reg = (packet0 & 0x1FFF) << 2; + count = ((packet0 & 0x3FFF0000) >> 16) + 1; + fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n", + state->name, i, reg, count); + ++i; + for (j = 0; j < count && i < dwords; j++) { + fprintf(stderr, " %s[%d]: 0x%04x = %08x\n", + state->name, i, reg, state->cmd[i]); + reg += 4; + ++i; + } + } + } } static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) @@ -882,7 +919,10 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) dwords = (*atom->check) (radeon->glCtx, atom); if (dwords) { if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(radeon, atom); + if (radeon->radeonScreen->kernel_mm) + radeon_print_state_atom_kmm(radeon, atom); + else + radeon_print_state_atom(radeon, atom); } if (atom->emit) { (*atom->emit)(radeon->glCtx, atom); -- cgit v1.2.3 From 22c0652c381e6773ff48e4c70ef5439a949919ae Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 23 Apr 2009 16:12:09 +0200 Subject: r300: flush stdout to get consistent debugging info --- src/mesa/drivers/dri/r300/r300_fragprog_common.c | 4 ++++ src/mesa/drivers/dri/r300/radeon_program_pair.c | 1 + 2 files changed, 5 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c index 3d4bd5db217..6eaad765500 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c @@ -214,8 +214,10 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) compiler.program = _mesa_clone_program(ctx, &fp->Base); if (RADEON_DEBUG & DEBUG_PIXEL) { + fflush(stdout); _mesa_printf("Fragment Program: Initial program:\n"); _mesa_print_program(compiler.program); + fflush(stdout); } insert_WPOS_trailer(&compiler); @@ -240,6 +242,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Fragment Program: After native rewrite:\n"); _mesa_print_program(compiler.program); + fflush(stdout); } if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { @@ -263,6 +266,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: after NqSSA-DCE:\n"); _mesa_print_program(compiler.program); + fflush(stdout); } if (!r300->vtbl.FragmentProgramEmit(&compiler)) diff --git a/src/mesa/drivers/dri/r300/radeon_program_pair.c b/src/mesa/drivers/dri/r300/radeon_program_pair.c index 5c6594bc2e1..906d36e5226 100644 --- a/src/mesa/drivers/dri/r300/radeon_program_pair.c +++ b/src/mesa/drivers/dri/r300/radeon_program_pair.c @@ -609,6 +609,7 @@ static void emit_all_tex(struct pair_state *s) if (s->Debug) { _mesa_printf(" "); _mesa_print_instruction(inst); + fflush(stdout); } s->Error = s->Error || !s->Handler->EmitTex(s->UserData, inst); } -- cgit v1.2.3 From d014d7d1bb33592f89fb08e8b656c27d67f9a3d3 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 24 Apr 2009 16:15:19 +0200 Subject: r300: always route 4 texcoord components to RS Routing <4 components may lead to lock up. Thanks to Alex Deucher for suggestion. --- src/mesa/drivers/dri/r300/r300_state.c | 64 +++++----------------------------- src/mesa/drivers/dri/r300/r300_swtcl.c | 19 +++++----- 2 files changed, 17 insertions(+), 66 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index a1f78c5244e..9c8b8adbe3b 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1482,6 +1482,7 @@ static void r300SetupRSUnit(GLcontext * ctx) } } + /* We always route 4 texcoord components */ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) continue; @@ -1491,26 +1492,10 @@ static void r300SetupRSUnit(GLcontext * ctx) continue; } - int swiz; - - /* with TCL we always seem to route 4 components */ - if (hw_tcl_on) - count = 4; - else - count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size; - - switch(count) { - case 4: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break; - case 3: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(R300_RS_SEL_K1); break; - default: - case 1: - case 2: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1); break; - }; - - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz | R300_RS_TEX_PTR(rs_tex_count); + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~(FRAG_BIT_TEX0 << i); - rs_tex_count += count; + rs_tex_count += 4; ++tex_ip; ++fp_reg; } @@ -1633,7 +1618,7 @@ static void r500SetupRSUnit(GLcontext * ctx) } } - + /* We always route 4 texcoord components */ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) continue; @@ -1643,45 +1628,14 @@ static void r500SetupRSUnit(GLcontext * ctx) continue; } - int swiz = 0; - - /* with TCL we always seem to route 4 components */ - if (hw_tcl_on) - count = 4; - else - count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size; - - if (count == 4) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= (rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else if (count == 3) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else if (count == 2) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else if (count == 1) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else { - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } + r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | + ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | + ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | + ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz; r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~(FRAG_BIT_TEX0 << i); - rs_tex_count += count; + rs_tex_count += 4; ++tex_ip; ++fp_reg; } diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 55187d4bc80..fc849889b60 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -204,34 +204,31 @@ static void r300SetVertexFormat( GLcontext *ctx ) ADD_ATTR(VERT_ATTRIB_POINT_SIZE, EMIT_1F, SWTCL_OVM_POINT_SIZE, swiz, MASK_X); } + /** + * Sending only one texcoord component may lead to lock up, + * so for all textures always output 4 texcoord components to RS. + */ if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i, size; - GLuint swiz, mask, format; + int i; + GLuint swiz, format; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { switch (VB->TexCoordPtr[i]->size) { case 1: format = EMIT_1F; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); - mask = MASK_X; break; case 2: format = EMIT_2F; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE); - mask = MASK_X | MASK_Y; - size = 2; break; case 3: format = EMIT_3F; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); - mask = MASK_X | MASK_Y | MASK_Z; - size = 3; break; case 4: format = EMIT_4F; swiz = SWIZZLE_XYZW; - mask = MASK_XYZW; - size = 4; break; default: continue; @@ -239,8 +236,8 @@ static void r300SetVertexFormat( GLcontext *ctx ) InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); - ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, mask); - vap_out_fmt_1 |= size << (i * 3); + ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, MASK_XYZW); + vap_out_fmt_1 |= 4 << (i * 3); ++first_free_tex; } } -- cgit v1.2.3 From 7f6b13be86884486baad1e7750511ce4a2eedde6 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 24 Apr 2009 16:52:33 +0200 Subject: r300: add point attenuation stage for TCL fallbacks --- src/mesa/drivers/dri/r300/r300_context.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3bde9ca30a8..51198901573 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -172,6 +172,7 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { &_tnl_fog_coordinate_stage, &_tnl_texgen_stage, &_tnl_texture_transform_stage, + &_tnl_point_attenuation_stage, &_tnl_vertex_program_stage, /* Try again to go to tcl? -- cgit v1.2.3 From 033d1365e6fa6e57bc11b47831af0cb4b7ad2edf Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 24 Apr 2009 16:28:47 +0200 Subject: r300: fix performance regression This performance regression on non TCL hw was introduced by ed4c6cbe017b4e8bacb7e012d4baaf77a20a2c33. This patch depends on "r300: always route 4 texcoord components to RS" and "r300: add point attenuation stage for TCL fallbacks". --- src/mesa/drivers/dri/r300/r300_context.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 51198901573..c80dcd8420b 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -364,7 +364,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx = r300->radeon.glCtx; r300InitConstValues(ctx, screen); - ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; + + if (hw_tcl_on) + ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; + ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; /* Initialize the software rasterizer and helper modules. -- cgit v1.2.3 From 78c0e6aefcef442f035494b6fc9f6b599fe75e7e Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 25 Apr 2009 13:48:53 +0200 Subject: r300: fix point size clamping when point is not attenuated --- src/mesa/drivers/dri/r300/r300_state.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 9c8b8adbe3b..99441a22fd6 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -728,7 +728,12 @@ static void r300ColorMask(GLcontext * ctx, static void r300PointSize(GLcontext * ctx, GLfloat size) { r300ContextPtr r300 = R300_CONTEXT(ctx); - /* same size limits for AA, non-AA points */ + + /* We need to clamp to user defined range here, because + * the HW clamping happens only for per vertex point size. */ + size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize); + + /* same size limits for AA, non-AA points */ size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize); R300_STATECHANGE(r300, ps); -- cgit v1.2.3 From 3d83a709b94e72608a061449bc30edc8af7c9ecc Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 25 Apr 2009 13:50:49 +0200 Subject: r300: fix valgrind warnings --- src/mesa/drivers/dri/radeon/radeon_common.c | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 312c2a72e92..8b5b892f0df 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -1186,7 +1186,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa) radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); } else { - struct drm_radeon_gem_info mminfo; + struct drm_radeon_gem_info mminfo = { 0 }; if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e24be0c9bb7..15414120289 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -249,8 +249,8 @@ static int radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) { int ret; - drm_radeon_getparam_t gp; - struct drm_radeon_info info; + drm_radeon_getparam_t gp = { 0 }; + struct drm_radeon_info info = { 0 }; if (sPriv->drm_version.major >= 2) { info.value = (uint64_t)value; @@ -869,7 +869,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); return NULL; } - + if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { screen->gartTextures.handle = dri_priv->gartTexHandle; screen->gartTextures.size = dri_priv->gartTexMapSize; @@ -884,7 +884,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); return NULL; } - + screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; } } @@ -1064,7 +1064,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) radeonScreenPtr screen; int i; int ret; - uint32_t device_id; + uint32_t device_id = 0; uint32_t temp = 0; /* Allocate the private area */ -- cgit v1.2.3 From e33e28f52acca27a0cd594c6474fdea1b61fd615 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Mon, 27 Apr 2009 14:53:20 +0200 Subject: r300: do front/back color selection in HW for software TCL path --- src/mesa/drivers/dri/r300/r300_swtcl.c | 44 +++++++++++++++++++++------------- src/mesa/drivers/dri/r300/r300_swtcl.h | 2 ++ 2 files changed, 29 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index fc849889b60..a40d0378db1 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -196,6 +196,29 @@ static void r300SetVertexFormat( GLcontext *ctx ) rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1; } + if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) { + VB->AttribPtr[VERT_ATTRIB_GENERIC0] = VB->ColorPtr[1]; + OutputsWritten |= 1 << VERT_RESULT_BFC0; +#if MESA_LITTLE_ENDIAN + EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA ); + ADD_ATTR(VERT_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW); +#else + EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR ); + ADD_ATTR(VERT_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW); +#endif + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 )) { + GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); + OutputsWritten |= 1 << VERT_RESULT_BFC1; +#if MESA_LITTLE_ENDIAN + EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA ); + ADD_ATTR(VERT_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR3, swiz, MASK_XYZW); +#else + EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR ); + ADD_ATTR(VERT_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR3, swiz, MASK_XYZW); +#endif + } + } + if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) { GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE; @@ -349,9 +372,8 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); * Build render functions from dd templates * ***********************************************************************/ -#define R300_TWOSIDE_BIT 0x01 -#define R300_UNFILLED_BIT 0x02 -#define R300_MAX_TRIFUNC 0x04 +#define R300_UNFILLED_BIT 0x01 +#define R300_MAX_TRIFUNC 0x02 static struct { tnl_points_func points; @@ -362,9 +384,9 @@ static struct { #define DO_FALLBACK 0 #define DO_UNFILLED (IND & R300_UNFILLED_BIT) -#define DO_TWOSIDE (IND & R300_TWOSIDE_BIT) +#define DO_TWOSIDE 0 #define DO_FLAT 0 -#define DO_OFFSET 0 +#define DO_OFFSET 0 #define DO_TRI 1 #define DO_QUAD 1 #define DO_LINE 1 @@ -452,26 +474,15 @@ do { \ #define TAG(x) x #include "tnl_dd/t_dd_tritmp.h" -#define IND (R300_TWOSIDE_BIT) -#define TAG(x) x##_twoside -#include "tnl_dd/t_dd_tritmp.h" - #define IND (R300_UNFILLED_BIT) #define TAG(x) x##_unfilled #include "tnl_dd/t_dd_tritmp.h" -#define IND (R300_TWOSIDE_BIT|R300_UNFILLED_BIT) -#define TAG(x) x##_twoside_unfilled -#include "tnl_dd/t_dd_tritmp.h" - - static void init_rast_tab( void ) { init(); - init_twoside(); init_unfilled(); - init_twoside_unfilled(); } /**********************************************************************/ @@ -523,7 +534,6 @@ static void r300ChooseRenderState( GLcontext *ctx ) GLuint index = 0; GLuint flags = ctx->_TriangleCaps; - if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT; if (index != rmesa->radeon.swtcl.RenderIndex) { diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index ebc99c9e8a7..75c419380d3 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -51,6 +51,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SWTCL_OVM_POS 0 #define SWTCL_OVM_COLOR0 2 #define SWTCL_OVM_COLOR1 3 +#define SWTCL_OVM_COLOR2 4 +#define SWTCL_OVM_COLOR3 5 #define SWTCL_OVM_TEX(n) ((n) + 6) #define SWTCL_OVM_POINT_SIZE 15 -- cgit v1.2.3 From 3c6bffa7618494a465ecb6ab6103143c12abb0c4 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Mon, 27 Apr 2009 15:31:01 +0200 Subject: r300: fallback only if stencil test is enabled --- src/mesa/drivers/dri/r300/r300_render.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 41b5e30be49..f87fee4af65 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -439,14 +439,9 @@ static int r300Fallback(GLcontext * ctx) FALLBACK_IF(ctx->RenderMode != GL_RENDER); - /* If GL_EXT_stencil_two_side is disabled, this fallback check can - * be removed. - */ - FALLBACK_IF(ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back] - || ctx->Stencil.ValueMask[0] != - ctx->Stencil.ValueMask[back] - || ctx->Stencil.WriteMask[0] != - ctx->Stencil.WriteMask[back]); + FALLBACK_IF(ctx->Stencil.Enabled && (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back] + || ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back] + || ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])); if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite) FALLBACK_IF(ctx->Point.PointSprite); -- cgit v1.2.3 From ce0d10dd6cd688d16e004c33ea4418cd7254a7f7 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Mon, 27 Apr 2009 16:25:34 +0200 Subject: r300: fix fragment program limits --- src/mesa/drivers/dri/r300/r300_context.c | 29 +++++++++++++++++--------- src/mesa/drivers/dri/r300/r300_context.h | 24 ++++++++++++--------- src/mesa/drivers/dri/r300/r300_fragprog_emit.c | 8 +++---- src/mesa/drivers/dri/r300/r500_fragprog_emit.c | 2 +- 4 files changed, 38 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index c80dcd8420b..4d1f10ba4d2 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -308,16 +308,25 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen) ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; } - ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; - ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ - ctx->Const.FragmentProgram.MaxNativeParameters = PFS_NUM_CONST_REGS; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = PFS_MAX_ALU_INST; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeInstructions = - PFS_MAX_ALU_INST + PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = - PFS_MAX_TEX_INDIRECT; - ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; + if (screen->chip_family >= CHIP_FAMILY_RV515) { + ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS; + ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ + ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS; + ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST; + ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST; + ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST; + ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST; + ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; + } else { + ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS; + ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ + ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS; + ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST; + ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST; + ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST; + ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT; + ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; + } } /* Create the device specific rendering context. diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index f8d914e7ac4..379977b2c76 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -450,11 +450,15 @@ struct r300_vertex_program_cont { struct r300_vertex_program *progs; }; -#define PFS_MAX_ALU_INST 64 -#define PFS_MAX_TEX_INST 64 -#define PFS_MAX_TEX_INDIRECT 4 -#define PFS_NUM_TEMP_REGS 32 -#define PFS_NUM_CONST_REGS 16 +#define R300_PFS_MAX_ALU_INST 64 +#define R300_PFS_MAX_TEX_INST 32 +#define R300_PFS_MAX_TEX_INDIRECT 4 +#define R300_PFS_NUM_TEMP_REGS 32 +#define R300_PFS_NUM_CONST_REGS 32 + +#define R500_PFS_MAX_INST 512 +#define R500_PFS_NUM_TEMP_REGS 128 +#define R500_PFS_NUM_CONST_REGS 256 struct r300_pfs_compile_state; struct r500_pfs_compile_state; @@ -500,7 +504,7 @@ struct r300_fragment_program_node { struct r300_fragment_program_code { struct { int length; /**< total # of texture instructions used */ - GLuint inst[PFS_MAX_TEX_INST]; + GLuint inst[R300_PFS_MAX_TEX_INST]; } tex; struct { @@ -510,7 +514,7 @@ struct r300_fragment_program_code { GLuint inst1; GLuint inst2; GLuint inst3; - } inst[PFS_MAX_ALU_INST]; + } inst[R300_PFS_MAX_ALU_INST]; } alu; struct r300_fragment_program_node node[4]; @@ -521,7 +525,7 @@ struct r300_fragment_program_code { * Remember which program register a given hardware constant * belongs to. */ - struct prog_src_register constant[PFS_NUM_CONST_REGS]; + struct prog_src_register constant[R300_PFS_NUM_CONST_REGS]; int const_nr; int max_temp_idx; @@ -536,7 +540,7 @@ struct r500_fragment_program_code { GLuint inst3; GLuint inst4; GLuint inst5; - } inst[512]; + } inst[R500_PFS_MAX_INST]; int inst_offset; int inst_end; @@ -545,7 +549,7 @@ struct r500_fragment_program_code { * Remember which program register a given hardware constant * belongs to. */ - struct prog_src_register constant[PFS_NUM_CONST_REGS]; + struct prog_src_register constant[R500_PFS_NUM_CONST_REGS]; int const_nr; int max_temp_idx; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c index 693d485de9e..af8bb3887bc 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c @@ -66,7 +66,7 @@ static GLboolean emit_const(void* data, GLuint file, GLuint index, GLuint *hwind } if (*hwindex >= code->const_nr) { - if (*hwindex >= PFS_NUM_CONST_REGS) { + if (*hwindex >= R300_PFS_NUM_CONST_REGS) { error("Out of hw constants!\n"); return GL_FALSE; } @@ -138,7 +138,7 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst) { PROG_CODE; - if (code->alu.length >= PFS_MAX_ALU_INST) { + if (code->alu.length >= R300_PFS_MAX_ALU_INST) { error("Too many ALU instructions"); return GL_FALSE; } @@ -275,7 +275,7 @@ static GLboolean emit_tex(void* data, struct prog_instruction* inst) { PROG_CODE; - if (code->tex.length >= PFS_MAX_TEX_INST) { + if (code->tex.length >= R300_PFS_MAX_TEX_INST) { error("Too many TEX instructions"); return GL_FALSE; } @@ -318,7 +318,7 @@ static const struct radeon_pair_handler pair_handler = { .EmitPaired = &emit_alu, .EmitTex = &emit_tex, .BeginTexBlock = &begin_tex, - .MaxHwTemps = PFS_NUM_TEMP_REGS + .MaxHwTemps = R300_PFS_NUM_TEMP_REGS }; /** diff --git a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c index d9f81004e8a..277f801c385 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c @@ -72,7 +72,7 @@ static GLboolean emit_const(void *data, GLuint file, GLuint idx, GLuint *hwindex } if (*hwindex >= code->const_nr) { - if (*hwindex >= PFS_NUM_CONST_REGS) { + if (*hwindex >= R500_PFS_NUM_CONST_REGS) { error("Out of hw constants!\n"); return GL_FALSE; } -- cgit v1.2.3 From 4e7d603fae8cff2a80096936ad210cb26a3f5f0e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Apr 2009 15:26:24 +1000 Subject: radeon: remove kernel mm, dri2 path takes care of it --- src/mesa/drivers/dri/radeon/radeon_screen.c | 104 ++++++++++++---------------- 1 file changed, 44 insertions(+), 60 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 15414120289..ed542d71fcc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -787,19 +787,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) { int ret; -#ifdef RADEON_PARAM_KERNEL_MM - ret = radeonGetParam(sPriv, RADEON_PARAM_KERNEL_MM, &screen->kernel_mm); - - if (ret && ret != -EINVAL) { - FREE( screen ); - fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); - return NULL; - } - - if (ret == -EINVAL) - screen->kernel_mm = 0; -#endif - ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, &screen->gart_buffer_offset); @@ -833,63 +820,60 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); } - if (!screen->kernel_mm) { - screen->mmio.handle = dri_priv->registerHandle; - screen->mmio.size = dri_priv->registerSize; - if ( drmMap( sPriv->fd, - screen->mmio.handle, - screen->mmio.size, - &screen->mmio.map ) ) { - FREE( screen ); - __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); - return NULL; - } + screen->mmio.handle = dri_priv->registerHandle; + screen->mmio.size = dri_priv->registerSize; + if ( drmMap( sPriv->fd, + screen->mmio.handle, + screen->mmio.size, + &screen->mmio.map ) ) { + FREE( screen ); + __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); + return NULL; + } - RADEONMMIO = screen->mmio.map; + RADEONMMIO = screen->mmio.map; - screen->status.handle = dri_priv->statusHandle; - screen->status.size = dri_priv->statusSize; - if ( drmMap( sPriv->fd, - screen->status.handle, - screen->status.size, - &screen->status.map ) ) { - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); - return NULL; - } - screen->scratch = (__volatile__ uint32_t *) - ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); + screen->status.handle = dri_priv->statusHandle; + screen->status.size = dri_priv->statusSize; + if ( drmMap( sPriv->fd, + screen->status.handle, + screen->status.size, + &screen->status.map ) ) { + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); + return NULL; + } + screen->scratch = (__volatile__ uint32_t *) + ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); + + screen->buffers = drmMapBufs( sPriv->fd ); + if ( !screen->buffers ) { + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); + return NULL; + } - screen->buffers = drmMapBufs( sPriv->fd ); - if ( !screen->buffers ) { + if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { + screen->gartTextures.handle = dri_priv->gartTexHandle; + screen->gartTextures.size = dri_priv->gartTexMapSize; + if ( drmMap( sPriv->fd, + screen->gartTextures.handle, + screen->gartTextures.size, + (drmAddressPtr)&screen->gartTextures.map ) ) { + drmUnmapBufs( screen->buffers ); drmUnmap( screen->status.map, screen->status.size ); drmUnmap( screen->mmio.map, screen->mmio.size ); FREE( screen ); - __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); + __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); return NULL; - } - - if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { - screen->gartTextures.handle = dri_priv->gartTexHandle; - screen->gartTextures.size = dri_priv->gartTexMapSize; - if ( drmMap( sPriv->fd, - screen->gartTextures.handle, - screen->gartTextures.size, - (drmAddressPtr)&screen->gartTextures.map ) ) { - drmUnmapBufs( screen->buffers ); - drmUnmap( screen->status.map, screen->status.size ); - drmUnmap( screen->mmio.map, screen->mmio.size ); - FREE( screen ); - __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); - return NULL; - } + } - screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; - } + screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; } - ret = radeon_set_screen_flags(screen, dri_priv->deviceID); if (ret == -1) return NULL; -- cgit v1.2.3 From 7731d931650d721550bc558ad84b6e3060fa94b9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Apr 2009 15:27:31 +1000 Subject: r300: remove unused debugging in set tex buffer paths --- src/mesa/drivers/dri/r200/r200_texstate.c | 1 - src/mesa/drivers/dri/r300/r300_texstate.c | 1 - 2 files changed, 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 15758d767cf..eee54cd73ba 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -833,7 +833,6 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo radeon_miptree_unreference(rImage->mt); rImage->mt = NULL; } - fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index cf4cad73d29..2d7ad555217 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -431,7 +431,6 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo radeon_miptree_unreference(rImage->mt); rImage->mt = NULL; } - fprintf(stderr,"settexbuf %dx%d@%d %d targ %x format %x\n", rb->width, rb->height, rb->cpp, rb->pitch, target, format); _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->width, rb->height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; -- cgit v1.2.3 From a9d64873d771a0ac8a319f036d97d827fea934df Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Apr 2009 15:35:52 +1000 Subject: radeon: further cleanup dri1 screen init --- src/mesa/drivers/dri/radeon/radeon_screen.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ed542d71fcc..544ab74997d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -904,7 +904,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { - if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) + if (screen->chip_family < CHIP_FAMILY_RS600) screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; else { FREE( screen ); @@ -1005,9 +1005,8 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->extensions[i++] = &driMediaStreamCounterExtension.base; } - if (!screen->kernel_mm) { #if !RADEON_COMMON - screen->extensions[i++] = &radeonTexOffsetExtension.base; + screen->extensions[i++] = &radeonTexOffsetExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) @@ -1030,10 +1029,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + screen->sarea_priv_offset); - if (screen->kernel_mm) - screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); - else - screen->bom = radeon_bo_manager_legacy_ctor(screen); + screen->bom = radeon_bo_manager_legacy_ctor(screen); if (screen->bom == NULL) { free(screen); return NULL; -- cgit v1.2.3 From 5ca4f3c5dad94f8e07aa7d93c076d4bc0acee1f6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Apr 2009 15:44:10 +1000 Subject: radeno: cleanup the startup path further --- src/mesa/drivers/dri/radeon/radeon_screen.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 544ab74997d..9ce950af179 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1010,16 +1010,15 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) - if (IS_R200_CLASS(screen)) - screen->extensions[i++] = &r200AllocateExtension.base; + if (IS_R200_CLASS(screen)) + screen->extensions[i++] = &r200AllocateExtension.base; - screen->extensions[i++] = &r200texOffsetExtension.base; + screen->extensions[i++] = &r200texOffsetExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - screen->extensions[i++] = &r300texOffsetExtension.base; + screen->extensions[i++] = &r300texOffsetExtension.base; #endif - } screen->extensions[i++] = NULL; sPriv->extensions = screen->extensions; -- cgit v1.2.3 From 55db6ce537f1fd9acf205400202abfcc3908d6c3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 28 Apr 2009 12:50:38 -0400 Subject: R300: add quadpipe overrides RV410 SE chips only have 1 quadpipe. Also, handle other R300 chip with quadpipe override. --- src/mesa/drivers/dri/radeon/radeon_screen.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 9ce950af179..70ae5d26e2e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -476,11 +476,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) screen->chip_family = CHIP_FAMILY_RS300; break; - /* 9500 with 1 pipe verified by: Reid Linnemann */ case PCI_CHIP_R300_AD: - screen->chip_family = CHIP_FAMILY_RV350; - screen->chip_flags = RADEON_CHIPSET_TCL; - break; case PCI_CHIP_R300_AE: case PCI_CHIP_R300_AF: case PCI_CHIP_R300_AG: @@ -942,6 +938,17 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) } else { screen->num_gb_pipes = temp; } + + /* pipe overrides */ + switch (dri_priv->deviceID) { + case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann */ + case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ + case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ + screen->num_gb_pipes = 1; + break; + default: + break; + } } if ( sPriv->drm_version.minor >= 10 ) { @@ -1106,6 +1113,18 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) } else { screen->num_gb_pipes = temp; } + + /* pipe overrides */ + switch (device_id) { + case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann */ + case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ + case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ + screen->num_gb_pipes = 1; + break; + default: + break; + } + } if (screen->chip_family <= CHIP_FAMILY_RS200) -- cgit v1.2.3 From 0b22615c2c860968a027c04519e25864ae69f6cd Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 2 May 2009 17:27:03 +0200 Subject: r300: set proper texture row alignment for IGP chips Looks like r400 based IGP chips require 64 byte alignment --- src/mesa/drivers/dri/r300/r300_context.c | 5 +++++ src/mesa/drivers/dri/radeon/radeon_common_context.c | 2 ++ src/mesa/drivers/dri/radeon/radeon_common_context.h | 1 + src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 11 ++++++----- 4 files changed, 14 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 4d1f10ba4d2..70c7730be9f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (r300->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); + if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 || + screen->chip_family == CHIP_FAMILY_RS740) { + r300->radeon.texture_row_align = 64; + } + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index ba74c97f2cb..3e713628ecb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon, radeon->texture_depth = ( glVisual->rgbBits > 16 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; + radeon->texture_row_align = 32; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index d32e5af5441..181688cbe46 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -421,6 +421,7 @@ struct radeon_context { */ int texture_depth; float initialMaxAnisotropy; + uint32_t texture_row_align; struct radeon_dma dma; struct radeon_hw_state hw; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 34d62617068..51538e37fad 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat) * \param curOffset points to the offset at which the image is to be stored * and is updated by this function according to the size of the image. */ -static void compute_tex_image_offset(radeon_mipmap_tree *mt, +static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, GLuint face, GLuint level, GLuint* curOffset) { radeon_mipmap_level *lvl = &mt->levels[level]; + uint32_t row_align = rmesa->texture_row_align - 1; /* Find image size in bytes */ if (mt->compressed) { @@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; } else { - lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; + lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; lvl->size = lvl->rowstride * lvl->height * lvl->depth; } assert(lvl->size > 0); @@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels) return size; } -static void calculate_miptree_layout(radeon_mipmap_tree *mt) +static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { GLuint curOffset; GLuint numLevels; @@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt) mt->levels[i].depth = minify(mt->depth0, i); for(face = 0; face < mt->faces; face++) - compute_tex_image_offset(mt, face, i, &curOffset); + compute_tex_image_offset(rmesa, mt, face, i, &curOffset); } /* Note the required size in memory */ @@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj * mt->tilebits = tilebits; mt->compressed = compressed; - calculate_miptree_layout(mt); + calculate_miptree_layout(rmesa, mt); mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, mt->totalsize, 1024, -- cgit v1.2.3 From f616995e5ed56745c4470b2ca5aeeb8d89a8c9db Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 5 May 2009 10:51:44 +1000 Subject: radeon/r200: enable all the optional drm support bits --- src/mesa/drivers/dri/radeon/radeon_screen.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 70ae5d26e2e..56dbe746881 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1073,6 +1073,15 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) screen->kernel_mm = 1; screen->chip_flags = 0; + /* if we have kms we can support all of these */ + screen->drmSupportsCubeMapsR200 = 1; + screen->drmSupportsBlendColor = 1; + screen->drmSupportsTriPerf = 1; + screen->drmSupportsFragShader = 1; + screen->drmSupportsPointSprites = 1; + screen->drmSupportsCubeMapsR100 = 1; + screen->drmSupportsVertexProgram = 1; + ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq); ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); -- cgit v1.2.3 From b2577937b61c2f182d905010ace960ef95c1a026 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Tue, 5 May 2009 17:45:50 +0200 Subject: r200: fix CS section size mismatch (bug 21565) --- src/mesa/drivers/dri/r200/r200_state_init.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 75262e46bd8..535d34f1152 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -505,6 +505,8 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) dwords += 6; if (rrb) dwords += 6; + if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) + dwords += 4; /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords); -- cgit v1.2.3 From 3503af07c4b7624252890e229cb6efd0ede2b7d6 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Tue, 5 May 2009 20:17:37 +0200 Subject: r200: fix another section size mismatch --- src/mesa/drivers/dri/r200/r200_state_init.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 535d34f1152..9eb95d60ab5 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -595,7 +595,6 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) hastexture = 0; } - dwords += 2; if (hastexture) dwords += 2; else -- cgit v1.2.3 From 5f8381724e81b594d6f11bb2d59964fbdbf22e90 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Tue, 5 May 2009 21:01:36 +0200 Subject: r200: fix some cube map issues remove the r100-ism of swapping cube faces which doesn't apply to r200, and also use precalculated offsets. Note that cube textures will still not work on r100 and r200 since mipmap layout is level-first order (for r300) whereas r100/r200 require face-first (and possibly also 2k alignment for face at least with tiling). --- src/mesa/drivers/dri/r200/r200_state_init.c | 36 ++++++++++------------------- 1 file changed, 12 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 9eb95d60ab5..4db7fa1210b 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -557,17 +557,12 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) if (t && t->mt && !t->image_override) dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); + /* is this ok even with drm older than 1.18? */ OUT_BATCH_TABLE(atom->cmd, 10); if (t && t->mt && !t->image_override) { - if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { - lvl = &t->mt->levels[0]; - OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); @@ -607,14 +602,8 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) if (hastexture) { OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); if (t->mt && !t->image_override) { - if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { - lvl = &t->mt->levels[0]; - OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { if (t->bo) OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, @@ -630,20 +619,19 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->cmd_size; - int i = atom->idx; + int i = atom->idx, j; radeonTexObj *t = r200->state.texture.unit[i].texobj; - GLuint size; + radeon_mipmap_level *lvl; BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5)); OUT_BATCH_TABLE(atom->cmd, 3); if (t && !t->image_override) { - size = t->mt->totalsize / 6; - OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0); - OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0); - OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0); - OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0); - OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0); + lvl = &t->mt->levels[0]; + for (j = 1; j <= 5; j++) { + OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } } END_BATCH(); } -- cgit v1.2.3 From acf086ebfa95b77bb221c15acf6776439063c0b7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 6 May 2009 13:34:34 +1000 Subject: r200: fix cubic emission. Still doesn't fix cubemaps, I really missed the whole drmsupports thing when testing this all originally --- src/mesa/drivers/dri/r200/r200_state_init.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 4db7fa1210b..be57ac31638 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -618,17 +618,18 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->cmd_size; + uint32_t dwords = 2; int i = atom->idx, j; radeonTexObj *t = r200->state.texture.unit[i].texobj; radeon_mipmap_level *lvl; - BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5)); - OUT_BATCH_TABLE(atom->cmd, 3); + BEGIN_BATCH_NO_AUTOSTATE(dwords + (4 * 5)); + OUT_BATCH_TABLE(atom->cmd, 2); if (t && !t->image_override) { lvl = &t->mt->levels[0]; for (j = 1; j <= 5; j++) { + OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0)); OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, RADEON_GEM_DOMAIN_VRAM, 0, 0); } -- cgit v1.2.3 From d7f62e54055c7b8afaf0683944a4ba907b96d6ec Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 6 May 2009 14:06:13 +1000 Subject: r100/r200: try and allocate miptree correct for hw. This doesn't make things worse but according to sroland it is how the GPU hw expects things on the r100/r200 --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 34 +++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 51538e37fad..8d1ba1cdbab 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -132,7 +132,33 @@ static GLuint minify(GLuint size, GLuint levels) return size; } -static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) + +static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt) +{ + GLuint curOffset; + GLuint numLevels; + GLuint i; + GLuint face; + + numLevels = mt->lastLevel - mt->firstLevel + 1; + assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + + curOffset = 0; + for(face = 0; face < mt->faces; face++) { + + for(i = 0; i < numLevels; i++) { + mt->levels[i].width = minify(mt->width0, i); + mt->levels[i].height = minify(mt->height0, i); + mt->levels[i].depth = minify(mt->depth0, i); + compute_tex_image_offset(rmesa, mt, face, i, &curOffset); + } + } + + /* Note the required size in memory */ + mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; +} + +static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { GLuint curOffset; GLuint numLevels; @@ -157,7 +183,6 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; } - /** * Create a new mipmap tree, calculate its layout and allocate memory. */ @@ -182,7 +207,10 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj * mt->tilebits = tilebits; mt->compressed = compressed; - calculate_miptree_layout(rmesa, mt); + if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300) + calculate_miptree_layout_r300(rmesa, mt); + else + calculate_miptree_layout_r100(rmesa, mt); mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, mt->totalsize, 1024, -- cgit v1.2.3 From 7f65fea95e56fe0dee91ba726358896c9899780a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 6 May 2009 14:43:07 +1000 Subject: radeon: hopefully fixup radeon cube state emission for kms --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index c00f59f7ad2..f5d4189d669 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -465,10 +465,11 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); - uint32_t dwords = atom->cmd_size; + uint32_t dwords = 2; int i = atom->idx, j; radeonTexObj *t = r100->state.texture.unit[i].texobj; radeon_mipmap_level *lvl; + uint32_t base_reg; if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) return; @@ -479,10 +480,17 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) if (!t->mt) return; - BEGIN_BATCH_NO_AUTOSTATE(dwords + 10); - OUT_BATCH_TABLE(atom->cmd, 3); + switch(i) { + case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; + case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; + default: + case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; + }; + BEGIN_BATCH_NO_AUTOSTATE(dwords + (5 * 4)); + OUT_BATCH_TABLE(atom->cmd, 2); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { + OUT_BATCH(CP_PACKET0(base_reg + (4 * (j-1)), 0)); OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, RADEON_GEM_DOMAIN_VRAM, 0, 0); } -- cgit v1.2.3 From cfc3ac8d6e3024d1284cfc3f50f695b6b8008c5f Mon Sep 17 00:00:00 2001 From: "Owen W. Taylor" Date: Wed, 6 May 2009 14:44:16 -0400 Subject: When clearing the stencil buffer, don't use a two-sided stencil In radeon_clear_tris(), when clearing the stencil buffer, pass GL_FRONT_AND_BACK to _mesa_StencilFuncSeparate(), to avoid triggering a software fallback on r300 and below. https://bugs.freedesktop.org/show_bug.cgi?id=21601 --- src/mesa/drivers/dri/radeon/radeon_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 8b5b892f0df..ee3ee9ca504 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -1429,7 +1429,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) if (this_mask & BUFFER_BIT_STENCIL) { _mesa_Enable(GL_STENCIL_TEST); _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); - _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, + _mesa_StencilFuncSeparate(GL_FRONT_AND_BACK, GL_ALWAYS, ctx->Stencil.Clear, ctx->Stencil.WriteMask[0]); } else { _mesa_Disable(GL_STENCIL_TEST); -- cgit v1.2.3 From 14365aa0ef278ac6e04a8c6e6d37e6625b0a309a Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 2 May 2009 17:37:20 +0200 Subject: r300: fix compiler warnings --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 2 ++ src/mesa/drivers/dri/radeon/radeon_common.c | 1 + src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 8 -------- src/mesa/drivers/dri/radeon/radeon_texture.c | 1 + 4 files changed, 4 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 6f1a0b45358..2d6b49257d5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -1,3 +1,5 @@ +#include + #ifndef RADEON_CS_WRAPPER_H #define RADEON_CS_WRAPPER_H diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index ee3ee9ca504..daf03a98566 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -62,6 +62,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/bufferobj.h" #include "main/buffers.h" #include "main/depth.h" +#include "main/polygon.h" #include "main/shaders.h" #include "main/texstate.h" #include "main/varray.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index b47b095cf20..e4ee2b99151 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -261,14 +261,6 @@ static int cs_set_age(struct radeon_cs *cs) return 0; } -static void dump_cmdbuf(struct radeon_cs *cs) -{ - int i; - for (i = 0; i < cs->cdw; i++){ - fprintf(stderr,"%x: %08x\n", i, cs->packets[i]); - } - -} static int cs_emit(struct radeon_cs *cs) { struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm; diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 35ed5424311..0f1d9c21584 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -38,6 +38,7 @@ #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" +#include "main/texgetimage.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ -- cgit v1.2.3 From dc8c7177592fc804f00409d53049af8e6b55f331 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 2 May 2009 19:34:57 +0200 Subject: r300: moar cleanup - remove unused r300UpdateClipPlanes function - move reg definition to r300_reg.h - remove incorrect forward definition of tnl_UpdateFixedFunctionProgram and add proper #include - remove unreachable code --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 6 +----- src/mesa/drivers/dri/r300/r300_reg.h | 3 +++ src/mesa/drivers/dri/r300/r300_state.c | 19 +------------------ src/mesa/drivers/dri/r300/r300_state.h | 4 ---- 4 files changed, 5 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index afca0e24a68..6ae724bff9d 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -55,9 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "radeon_reg.h" -#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 -# define RADEON_ONE_REG_WR (1 << 15) - /** # of dwords reserved for additional instructions that may need to be written * during flushing. */ @@ -71,7 +68,6 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; return t->packet0.count; } - return 0; } #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) @@ -111,7 +107,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) } else { BEGIN_BATCH_NO_AUTOSTATE(5 + ndw); } - OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr); + OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr); OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); for (i = 0; i < ndw; i++) { OUT_BATCH(atom->cmd[i+1]); diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index 79dd1e1fa21..c22616b95f6 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -3178,6 +3178,9 @@ enum { # define R300_W_SRC_RAS (1 << 2) +/* Packet0 field ordering to write all values to the same reg */ +#define RADEON_ONE_REG_WR (1 << 15) + /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. * Two parameter dwords: * 0. VAP_VTX_FMT: The first parameter is not written to hardware diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 99441a22fd6..330f1dab493 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -53,6 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "shader/prog_statevars.h" #include "vbo/vbo.h" #include "tnl/tnl.h" +#include "tnl/t_vp_build.h" #include "r300_context.h" #include "r300_ioctl.h" @@ -2467,24 +2468,6 @@ static void r300RenderMode(GLcontext * ctx, GLenum mode) (void)mode; } -void r300UpdateClipPlanes( GLcontext *ctx ) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLuint p; - - for (p = 0; p < ctx->Const.MaxClipPlanes; p++) { - if (ctx->Transform.ClipPlanesEnabled & (1 << p)) { - GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - - R300_STATECHANGE( rmesa, vpucp[p] ); - rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3]; - } - } -} - /** * Initialize driver's state callback functions */ diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index 247a20ee516..3921efa8e3a 100644 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ b/src/mesa/drivers/dri/r300/r300_state.h @@ -50,16 +50,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. r300->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -// r300_state.c -extern int future_hw_tcl_on; -void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx); void r300UpdateViewportOffset (GLcontext * ctx); void r300UpdateDrawBuffer (GLcontext * ctx); void r300UpdateStateParameters (GLcontext * ctx, GLuint new_state); void r300UpdateShaders (r300ContextPtr rmesa); void r300UpdateShaderStates (r300ContextPtr rmesa); void r300InitState (r300ContextPtr r300); -void r300UpdateClipPlanes (GLcontext * ctx); void r300InitStateFuncs (struct dd_function_table *functions); #endif /* __R300_STATE_H__ */ -- cgit v1.2.3 From a7bb95bf142ac9727a4223639742a8524f9c724b Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Tue, 5 May 2009 14:45:51 +0200 Subject: r300: add missing texture format Fixes piglit/texdepth --- src/mesa/drivers/dri/r300/r300_texstate.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 2d7ad555217..443fafe5e22 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -117,6 +117,7 @@ static const struct tx_table { _ASSIGN(INTENSITY_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, X, FL_I16)), _ASSIGN(Z16, R300_EASY_TX_FORMAT(X, X, X, X, X16)), _ASSIGN(Z24_S8, R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8)), + _ASSIGN(S8_Z24, R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8)), _ASSIGN(Z32, R300_EASY_TX_FORMAT(X, X, X, X, X32)), /* *INDENT-ON* */ }; -- cgit v1.2.3 From a67c29a268bdfecb910b929e05c0ea02c720caa6 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 8 May 2009 16:40:21 +0200 Subject: radeon: IRQ always enabled in DRI2 path no need to query kernel for it --- src/mesa/drivers/dri/radeon/radeon_screen.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 56dbe746881..5aeb968d41c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1081,8 +1081,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) screen->drmSupportsPointSprites = 1; screen->drmSupportsCubeMapsR100 = 1; screen->drmSupportsVertexProgram = 1; - - ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq); + screen->irq = 1; ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); if (ret) { -- cgit v1.2.3 From 13e0ff0df1bb75993bded7b248dd37f58fbfd22c Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sat, 9 May 2009 12:56:27 +0200 Subject: radeon: don't include cs uncondionaly --- src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h index 2d6b49257d5..6f1a0b45358 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h @@ -1,5 +1,3 @@ -#include - #ifndef RADEON_CS_WRAPPER_H #define RADEON_CS_WRAPPER_H -- cgit v1.2.3 From 98bb5c610dc68d8e9a185216ce9d2dc6d278c114 Mon Sep 17 00:00:00 2001 From: Joel Bosveld Date: Sun, 10 May 2009 18:26:40 +0200 Subject: radeon: add support for new dri2 interfaces & fix single buffer rendering --- src/mesa/drivers/dri/radeon/radeon_common.c | 39 +++++++ .../drivers/dri/radeon/radeon_common_context.c | 115 ++++++++++++++++++--- .../drivers/dri/radeon/radeon_common_context.h | 16 +++ 3 files changed, 154 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index daf03a98566..decea4518e6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -678,6 +678,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer); radeon->front_cliprects = GL_TRUE; + radeon->front_buffer_dirty = GL_TRUE; } else { rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer); radeon->front_cliprects = GL_FALSE; @@ -793,6 +794,24 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); + + if (ctx->DrawBuffer->Name == 0) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + + const GLboolean was_front_buffer_rendering = + radeon->is_front_buffer_rendering; + + radeon->is_front_buffer_rendering = (mode == GL_FRONT_LEFT) || + (mode == GL_FRONT); + + /* If we weren't front-buffer rendering before but we are now, make sure + * that the front-buffer has actually been allocated. + */ + if (!was_front_buffer_rendering && radeon->is_front_buffer_rendering) { + radeon_update_renderbuffers(radeon->dri.context, + radeon->dri.context->driDrawablePriv); + } + } radeon_draw_buffer(ctx, ctx->DrawBuffer); } @@ -1046,6 +1065,26 @@ void radeonFlush(GLcontext *ctx) if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); + + if ((ctx->DrawBuffer->Name == 0) && radeon->front_buffer_dirty) { + __DRIscreen *const screen = radeon->radeonScreen->driScreen; + + if (screen->dri2.loader && (screen->dri2.loader->base.version >= 2) + && (screen->dri2.loader->flushFrontBuffer != NULL)) { + (*screen->dri2.loader->flushFrontBuffer)(radeon->dri.drawable, + radeon->dri.drawable->loaderPrivate); + + /* Only clear the dirty bit if front-buffer rendering is no longer + * enabled. This is done so that the dirty bit can only be set in + * glDrawBuffer. Otherwise the dirty bit would have to be set at + * each of N places that do rendering. This has worse performances, + * but it is much easier to get correct. + */ + if (radeon->is_front_buffer_rendering) { + radeon->front_buffer_dirty = GL_FALSE; + } + } + } } /* Make sure all commands have been sent to the hardware and have diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 3e713628ecb..124b587bab1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -406,6 +406,23 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, } } +static unsigned +radeon_bits_per_pixel(const struct radeon_renderbuffer *rb) +{ + switch (rb->base._ActualFormat) { + case GL_RGB5: + case GL_DEPTH_COMPONENT16: + return 16; + case GL_RGB8: + case GL_RGBA8: + case GL_DEPTH_COMPONENT24: + case GL_DEPTH24_STENCIL8_EXT: + case GL_STENCIL_INDEX8_EXT: + return 32; + default: + return 0; + } +} void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) @@ -426,22 +443,63 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) draw = drawable->driverPrivate; screen = context->driScreenPriv; radeon = (radeonContextPtr) context->driverPrivate; - i = 0; - if (draw->color_rb[0]) - attachments[i++] = __DRI_BUFFER_FRONT_LEFT; - if (draw->color_rb[1]) - attachments[i++] = __DRI_BUFFER_BACK_LEFT; - if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH)) - attachments[i++] = __DRI_BUFFER_DEPTH; - if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL)) - attachments[i++] = __DRI_BUFFER_STENCIL; + + if ((screen->dri2.loader->base.version > 2) + && (screen->dri2.loader->getBuffersWithFormat != NULL)) { + struct radeon_renderbuffer *depth_rb; + struct radeon_renderbuffer *stencil_rb; + + i = 0; + if ((radeon->is_front_buffer_rendering || !draw->color_rb[1]) + && draw->color_rb[0]) { + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]); + } + + if (draw->color_rb[1]) { + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]); + } + + depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); + stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL); + + if ((depth_rb != NULL) && (stencil_rb != NULL)) { + attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL; + attachments[i++] = radeon_bits_per_pixel(depth_rb); + } else if (depth_rb != NULL) { + attachments[i++] = __DRI_BUFFER_DEPTH; + attachments[i++] = radeon_bits_per_pixel(depth_rb); + } else if (stencil_rb != NULL) { + attachments[i++] = __DRI_BUFFER_STENCIL; + attachments[i++] = radeon_bits_per_pixel(stencil_rb); + } + + buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable, + &drawable->w, + &drawable->h, + attachments, i / 2, + &count, + drawable->loaderPrivate); + } else { + i = 0; + if (draw->color_rb[0]) + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + if (draw->color_rb[1]) + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH)) + attachments[i++] = __DRI_BUFFER_DEPTH; + if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL)) + attachments[i++] = __DRI_BUFFER_STENCIL; - buffers = (*screen->dri2.loader->getBuffers)(drawable, - &drawable->w, - &drawable->h, - attachments, i, - &count, - drawable->loaderPrivate); + buffers = (*screen->dri2.loader->getBuffers)(drawable, + &drawable->w, + &drawable->h, + attachments, i, + &count, + drawable->loaderPrivate); + } + if (buffers == NULL) return; @@ -466,6 +524,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) rb = draw->color_rb[0]; regname = "dri2 front buffer"; break; + case __DRI_BUFFER_FAKE_FRONT_LEFT: + rb = draw->color_rb[0]; + regname = "dri2 fake front buffer"; + break; case __DRI_BUFFER_BACK_LEFT: rb = draw->color_rb[1]; regname = "dri2 back buffer"; @@ -474,6 +536,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); regname = "dri2 depth buffer"; break; + case __DRI_BUFFER_DEPTH_STENCIL: + rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); + regname = "dri2 depth / stencil buffer"; + break; case __DRI_BUFFER_STENCIL: rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL); regname = "dri2 stencil buffer"; @@ -535,7 +601,24 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) radeon_renderbuffer_set_bo(rb, bo); radeon_bo_unref(bo); - + + if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) { + rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL); + if (rb != NULL) { + struct radeon_bo *stencil_bo = NULL; + + if (rb->bo) { + uint32_t name = radeon_gem_name_bo(rb->bo); + if (name == buffers[i].name) + continue; + } + + stencil_bo = bo; + radeon_bo_ref(stencil_bo); + radeon_renderbuffer_set_bo(rb, stencil_bo); + radeon_bo_unref(stencil_bo); + } + } } driUpdateFramebufferSize(radeon->glCtx, drawable); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 181688cbe46..446c2f6269b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -463,6 +463,22 @@ struct radeon_context { GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ GLboolean front_cliprects; + /** + * Set if rendering has occured to the drawable's front buffer. + * + * This is used in the DRI2 case to detect that glFlush should also copy + * the contents of the fake front buffer to the real front buffer. + */ + GLboolean front_buffer_dirty; + + /** + * Track whether front-buffer rendering is currently enabled + * + * A separate flag is used to track this in order to support MRT more + * easily. + */ + GLboolean is_front_buffer_rendering; + struct { struct gl_fragment_program *bitmap_fp; struct gl_vertex_program *passthrough_vp; -- cgit v1.2.3 From 0bfa8dfaaf49703eb5c3237b5cae6201b8755e4d Mon Sep 17 00:00:00 2001 From: Tormod Volden Date: Tue, 12 May 2009 09:32:11 +0200 Subject: radeon: avoid segfault in radeon_update_renderbuffers() if using DRI1 Basically the same as 43d9020ff1e975e7f4f9480d9ef24f0b9fb2141f for intel. Bug 21688. Signed-off-by: Tormod Volden --- src/mesa/drivers/dri/radeon/radeon_common_context.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 124b587bab1..6fb6f92cb94 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -428,7 +428,7 @@ void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) { unsigned int attachments[10]; - __DRIbuffer *buffers; + __DRIbuffer *buffers = NULL; __DRIscreen *screen; struct radeon_renderbuffer *rb; int i, count; @@ -444,7 +444,8 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) screen = context->driScreenPriv; radeon = (radeonContextPtr) context->driverPrivate; - if ((screen->dri2.loader->base.version > 2) + if (screen->dri2.loader + && (screen->dri2.loader->base.version > 2) && (screen->dri2.loader->getBuffersWithFormat != NULL)) { struct radeon_renderbuffer *depth_rb; struct radeon_renderbuffer *stencil_rb; @@ -481,7 +482,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) attachments, i / 2, &count, drawable->loaderPrivate); - } else { + } else if (screen->dri2.loader) { i = 0; if (draw->color_rb[0]) attachments[i++] = __DRI_BUFFER_FRONT_LEFT; -- cgit v1.2.3 From 05c19ec7f0717549c010afc0b6cdc81962d32675 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Tue, 12 May 2009 13:04:32 +0200 Subject: r300/r500: make sure we detect constant buffer changes This was broken with last merge see f48473e42511f8d37a239a07f791bc0a87209e5b for explanations. --- src/mesa/drivers/dri/r300/r300_fragprog_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c index 6eaad765500..2a880e6d144 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c @@ -281,7 +281,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) r300_fp->translated = GL_TRUE; - r300UpdateStateParameters(ctx, _NEW_PROGRAM); + r300UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); if (r300_fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) r300->vtbl.FragmentProgramDump(&r300_fp->code); -- cgit v1.2.3 From c514c1f99493147bbba7a1dbe157c0492f4cf2eb Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Tue, 12 May 2009 13:05:57 +0200 Subject: radeon: glReadBuffer set _NEW_BUFFERS, not _NEW_PIXEL This was broken with last merge see 62043b27575c378c027251316421e4699f461108 for explanations --- src/mesa/drivers/dri/r200/r200_state.c | 2 +- src/mesa/drivers/dri/r300/r300_state.c | 4 ++-- src/mesa/drivers/dri/radeon/radeon_state.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index a06ea17e799..6802e190a76 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -2319,7 +2319,7 @@ GLboolean r200ValidateState( GLcontext *ctx ) r200ContextPtr rmesa = R200_CONTEXT(ctx); GLuint new_state = rmesa->radeon.NewGLState; - if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { + if (new_state & _NEW_BUFFERS) { _mesa_update_framebuffer(ctx); /* this updates the DrawBuffer's Width/Height if it's a FBO */ _mesa_update_draw_buffer_bounds(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 217a16818e3..301ede3aedb 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2221,7 +2221,7 @@ void r300UpdateShaders(r300ContextPtr rmesa) r300ResetHwState(rmesa); r300UpdateStateParameters(ctx, _NEW_PROGRAM | - _NEW_PROGRAM_CONSTANTS); + _NEW_PROGRAM_CONSTANTS); return; } } @@ -2441,7 +2441,7 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) _vbo_InvalidateState(ctx, new_state); _tnl_InvalidateState(ctx, new_state); - if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { + if (new_state & _NEW_BUFFERS) { _mesa_update_framebuffer(ctx); /* this updates the DrawBuffer's Width/Height if it's a FBO */ _mesa_update_draw_buffer_bounds(ctx); diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index d9a7ef60612..34c8cb42fa4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2094,7 +2094,7 @@ GLboolean radeonValidateState( GLcontext *ctx ) r100ContextPtr rmesa = R100_CONTEXT(ctx); GLuint new_state = rmesa->radeon.NewGLState; - if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { + if (new_state & _NEW_BUFFERS) { _mesa_update_framebuffer(ctx); /* this updates the DrawBuffer's Width/Height if it's a FBO */ _mesa_update_draw_buffer_bounds(ctx); -- cgit v1.2.3 From 038f0bf5916df5bae1145d234589e5fd528bb7fa Mon Sep 17 00:00:00 2001 From: "Owen W. Taylor" Date: Fri, 8 May 2009 18:58:41 -0400 Subject: Remove subpixel offset from viewport Remove an eigth-pixel offset of the viewport inherited from R100 code. This seems not to be necessary and causes blurring when sampling textures 1:1. https://bugs.freedesktop.org/show_bug.cgi?id=20340 --- src/mesa/drivers/dri/r300/r300_state.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 301ede3aedb..b82399574a3 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -923,12 +923,6 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, * Window position and viewport transformation */ -/* - * To correctly position primitives: - */ -#define SUBPIXEL_X 0.125 -#define SUBPIXEL_Y 0.125 - static void r300UpdateWindow(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); @@ -949,9 +943,9 @@ static void r300UpdateWindow(GLcontext * ctx) } GLfloat sx = v[MAT_SX]; - GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; + GLfloat tx = v[MAT_TX] + xoffset; GLfloat sy = v[MAT_SY] * y_scale; - GLfloat ty = (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y; + GLfloat ty = (v[MAT_TY] * y_scale) + y_bias; GLfloat sz = v[MAT_SZ] * depthScale; GLfloat tz = v[MAT_TZ] * depthScale; @@ -990,8 +984,8 @@ void r300UpdateViewportOffset(GLcontext * ctx) GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; - GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; - GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; + GLfloat tx = v[MAT_TX] + xoffset; + GLfloat ty = (-v[MAT_TY]) + yoffset; if (rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] != r300PackFloat32(tx) || rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] != r300PackFloat32(ty)) { -- cgit v1.2.3 From 34eab5dd9c837769f1259e1f900b4528586d23b2 Mon Sep 17 00:00:00 2001 From: "Owen W. Taylor" Date: Wed, 6 May 2009 22:45:33 -0400 Subject: Call _mesa_update_stencil() before accessing ctx->Stencil._Enabled ctx->Stencil._Enabled is derived state and not immediately updated when the stencil parameters are changed; we need to make sure that it is up-to-date before accessing it. https://bugs.freedesktop.org/show_bug.cgi?id=21608 --- src/mesa/drivers/dri/radeon/radeon_common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index decea4518e6..2f55dadcb98 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -744,6 +744,8 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) if (ctx->Driver.Enable) { ctx->Driver.Enable(ctx, GL_DEPTH_TEST, (ctx->Depth.Test && fb->Visual.depthBits > 0)); + /* Need to update the derived ctx->Stencil._Enabled first */ + _mesa_update_stencil(ctx); ctx->Driver.Enable(ctx, GL_STENCIL_TEST, (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0)); } else { -- cgit v1.2.3 From ea6a74abbe4053b958d640425e061f0ceec92291 Mon Sep 17 00:00:00 2001 From: "Owen W. Taylor" Date: Wed, 6 May 2009 22:42:50 -0400 Subject: Don't use an alpha texture format for GLX_TEXTURE_FORMAT_RGB_EXT In r300SetTexBuffer2(), if the passed in text glx_texture_format is GLX_TEXTURE_FORMAT_RGB_EXT, then we should use an RGB-only texture format, even if the DRI buffer has four channels. https://bugs.freedesktop.org/show_bug.cgi?id=21609 --- src/mesa/drivers/dri/r300/r300_texstate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 443fafe5e22..6d6a90aa88a 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -449,7 +449,10 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo pitch_val = rb->pitch; switch (rb->cpp) { case 4: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + else + t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); t->pp_txfilter |= tx_table[2].filter; pitch_val /= 4; break; -- cgit v1.2.3 From ca792be42b238bd1c8f8a99ad72ea8558cbbfc32 Mon Sep 17 00:00:00 2001 From: "Owen W. Taylor" Date: Sat, 9 May 2009 15:23:34 -0400 Subject: radeon: Don't crash generating mipmaps when pixels=NULL When a NULL value of pixels is passed to TexImage2D and SGIS_generate_mipmap is enabled, don't try to generate the mipmap tree: we don't have data yet for the texture and will crash. https://bugs.freedesktop.org/show_bug.cgi?id=21648 --- src/mesa/drivers/dri/radeon/radeon_texture.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 0f1d9c21584..564da19f58e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -612,11 +612,10 @@ static void radeon_teximage( _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); } - } - - /* SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - radeon_generate_mipmap(ctx, texObj->Target, texObj); + /* SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + radeon_generate_mipmap(ctx, texObj->Target, texObj); + } } _mesa_unmap_teximage_pbo(ctx, packing); @@ -741,12 +740,12 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); } + /* GL_SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + radeon_generate_mipmap(ctx, texObj->Target, texObj); + } } - /* GL_SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - radeon_generate_mipmap(ctx, texObj->Target, texObj); - } radeon_teximage_unmap(image); _mesa_unmap_teximage_pbo(ctx, packing); -- cgit v1.2.3 From 7cd57e35b6427068b87c2fdb6c2aadef57f53520 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 13 May 2009 19:43:04 -0400 Subject: R1xx/r2xx: Don't use an alpha texture format for GLX_TEXTURE_FORMAT_RGB_EXT In r*00SetTexBuffer2(), if the passed in text glx_texture_format is GLX_TEXTURE_FORMAT_RGB_EXT, then we should use an RGB-only texture format, even if the DRI buffer has four channels. https://bugs.freedesktop.org/show_bug.cgi?id=21609 --- src/mesa/drivers/dri/r200/r200_texstate.c | 5 ++++- src/mesa/drivers/dri/radeon/radeon_texstate.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index eee54cd73ba..ed1995e147c 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -850,7 +850,10 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo pitch_val = rb->pitch; switch (rb->cpp) { case 4: - t->pp_txformat = tx_table_le[MESA_FORMAT_ARGB8888].format; + if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) + t->pp_txformat = tx_table_le[MESA_FORMAT_RGB888].format; + else + t->pp_txformat = tx_table_le[MESA_FORMAT_ARGB8888].format; t->pp_txfilter |= tx_table_le[MESA_FORMAT_ARGB8888].filter; break; case 3: diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index e4df33766eb..279bcd4df6a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -722,7 +722,10 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ pitch_val = rb->pitch; switch (rb->cpp) { case 4: - t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; + if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) + t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; + else + t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; break; case 3: -- cgit v1.2.3 From 76a64958a4ca38ec27b63a909979c493c507b952 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 14 May 2009 17:24:19 +0200 Subject: r300: don't send now forbidden register to kernel when with memory manager --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 51 ++++++++++++++++++++++++++++---- src/mesa/drivers/dri/r300/r300_context.h | 10 +++++-- src/mesa/drivers/dri/r300/r300_state.c | 22 +++++++++----- 3 files changed, 67 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 6ae724bff9d..a0d99ddfb67 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -308,6 +308,34 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) END_BATCH(); } +static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + + if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH(atom->cmd[0]); + OUT_BATCH(atom->cmd[1]); + OUT_BATCH(atom->cmd[2]); + OUT_BATCH(atom->cmd[3]); + END_BATCH(); + } +} + +static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + + if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(atom->cmd[0]); + OUT_BATCH(atom->cmd[1]); + END_BATCH(); + } +} + static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); @@ -464,7 +492,10 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(gb_enable, always, 2, 0); r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1); ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0); - r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5); + r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3); + r300->hw.gb_misc.emit = emit_gb_misc; + ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0); + r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2); ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0); r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1); ALLOC_STATE(ga_point_s0, always, 5, 0); @@ -479,8 +510,11 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1); ALLOC_STATE(ga_line_stipple, always, 4, 0); r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3); - ALLOC_STATE(shade, always, 5, 0); - r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4); + ALLOC_STATE(shade, always, 2, 0); + r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1); + r300->hw.shade.emit = emit_shade_misc; + ALLOC_STATE(shade2, always, 4, 0); + r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3); ALLOC_STATE(polygon_mode, always, 4, 0); r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3); ALLOC_STATE(fogp, always, 3, 0); @@ -587,8 +621,15 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9); ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1); - ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + if (is_r500) { + ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + } else { + ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = (2 << 30); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = (2 << 30); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = (2 << 30); + } ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); r300->hw.zs.cmd[R300_ZS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 379977b2c76..d45e4beec0b 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -116,9 +116,11 @@ typedef struct r300_context *r300ContextPtr; #define R300_GB_MISC_MSPOS_0 1 #define R300_GB_MISC_MSPOS_1 2 #define R300_GB_MISC_TILE_CONFIG 3 -#define R300_GB_MISC_SELECT 4 -#define R300_GB_MISC_AA_CONFIG 5 -#define R300_GB_MISC_CMDSIZE 6 +#define R300_GB_MISC_CMDSIZE 4 +#define R300_GB_MISC2_CMD_0 0 +#define R300_GB_MISC2_SELECT 1 +#define R300_GB_MISC2_AA_CONFIG 2 +#define R300_GB_MISC2_CMDSIZE 3 #define R300_TXE_CMD_0 0 #define R300_TXE_ENABLE 1 @@ -307,6 +309,7 @@ struct r300_hw_state { struct radeon_state_atom pvs; /* pvs_cntl (22D0) */ struct radeon_state_atom gb_enable; /* (4008) */ struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ + struct radeon_state_atom gb_misc2; /* Multisampling position shifts ? (4010) */ struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ struct radeon_state_atom ga_triangle_stipple; /* (4214) */ struct radeon_state_atom ps; /* pointsize (421C) */ @@ -314,6 +317,7 @@ struct r300_hw_state { struct radeon_state_atom lcntl; /* line control */ struct radeon_state_atom ga_line_stipple; /* (4260) */ struct radeon_state_atom shade; + struct radeon_state_atom shade2; struct radeon_state_atom polygon_mode; struct radeon_state_atom fogp; /* fog parameters (4294) */ struct radeon_state_atom ga_soft_reset; /* (429C) */ diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index b82399574a3..7a025aa56f5 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -829,18 +829,19 @@ static void r300ShadeModel(GLcontext * ctx, GLenum mode) R300_STATECHANGE(rmesa, shade); rmesa->hw.shade.cmd[1] = 0x00000002; + R300_STATECHANGE(rmesa, shade2); switch (mode) { case GL_FLAT: - rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_FLAT; + rmesa->hw.shade2.cmd[1] = R300_RE_SHADE_MODEL_FLAT; break; case GL_SMOOTH: - rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_SMOOTH; + rmesa->hw.shade2.cmd[1] = R300_RE_SHADE_MODEL_SMOOTH; break; default: return; } - rmesa->hw.shade.cmd[3] = 0x00000000; - rmesa->hw.shade.cmd[4] = 0x00000000; + rmesa->hw.shade2.cmd[2] = 0x00000000; + rmesa->hw.shade2.cmd[3] = 0x00000000; } static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face, @@ -2079,8 +2080,8 @@ static void r300ResetHwState(r300ContextPtr r300) } /* XXX: Enable anti-aliasing? */ - r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE; - r300->hw.gb_misc.cmd[R300_GB_MISC_SELECT] = 0; + r300->hw.gb_misc2.cmd[R300_GB_MISC2_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE; + r300->hw.gb_misc2.cmd[R300_GB_MISC2_SELECT] = 0; r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0); r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0); @@ -2151,8 +2152,13 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0; - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; + } else { + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = (2 << 30); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = (2 << 30); + } r300->hw.zb_depthclearvalue.cmd[1] = 0; -- cgit v1.2.3 From 42f16aa4e0d9f1c5f016919ed04c55430507234e Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 13 May 2009 22:24:57 +0200 Subject: r300: further cleanup - move extensions init into seperate function - move options handling into seperate function - create new structure to hold options values - use context->options.hw_tcl_enabled field instead of global hw_tcl_on and future_hw_tcl_on variables --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 5 +- src/mesa/drivers/dri/r300/r300_context.c | 104 +++++++++++++++---------------- src/mesa/drivers/dri/r300/r300_context.h | 10 ++- src/mesa/drivers/dri/r300/r300_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_ioctl.c | 5 +- src/mesa/drivers/dri/r300/r300_render.c | 14 ++--- src/mesa/drivers/dri/r300/r300_state.c | 27 ++++---- 7 files changed, 82 insertions(+), 85 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index a0d99ddfb67..253378767b7 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -420,12 +420,11 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) void r300InitCmdBuf(r300ContextPtr r300) { int mtu; - int has_tcl = 1; + int has_tcl; int is_r500 = 0; int i; - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; + has_tcl = r300->options.hw_tcl_enabled; if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 70c7730be9f..3c16e80d2bb 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -72,10 +72,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ -/* hw_tcl_on derives from future_hw_tcl_on when its safe to change it. */ -int future_hw_tcl_on = 1; -int hw_tcl_on = 1; - #define need_GL_VERSION_2_0 #define need_GL_ARB_point_parameters #define need_GL_ARB_vertex_program @@ -296,7 +292,7 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen) ctx->Const.MaxDrawBuffers = 1; /* currently bogus data */ - if (screen->chip_flags & RADEON_CHIPSET_TCL) { + if (r300->options.hw_tcl_enabled) { ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; @@ -329,6 +325,47 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen) } } +static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen) +{ + struct r300_options options = { 0 }; + + driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, + screen->driScreen->myNum, "r300"); + + r300->disable_lowimpact_fallback = driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); + + options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side"); + options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable"); + options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc"); + + if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW) + options.hw_tcl_enabled = 0; + else + options.hw_tcl_enabled = 1; + + r300->options = options; +} + +static void r300InitGLExtensions(GLcontext *ctx) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + + driInitExtensions(ctx, card_extensions, GL_TRUE); + if (r300->radeon.radeonScreen->kernel_mm) + driInitExtensions(ctx, mm_extensions, GL_FALSE); + + if (r300->options.stencil_two_side_disabled) + _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); + + if (ctx->Mesa_DXTn && !r300->options.s3tc_force_enabled) { + _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); + _mesa_enable_extension(ctx, "GL_S3_s3tc"); + } else if (r300->options.s3tc_force_disabled) { + _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc"); + } +} + /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, @@ -340,7 +377,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, struct dd_function_table functions; r300ContextPtr r300; GLcontext *ctx; - int tcl_mode; assert(glVisual); assert(driContextPriv); @@ -350,11 +386,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (!r300) return GL_FALSE; - if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) - hw_tcl_on = future_hw_tcl_on = 0; - - driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, - screen->driScreen->myNum, "r300"); + r300ParseOptions(r300, screen); r300_init_vtbl(&r300->radeon); @@ -372,13 +404,14 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, } ctx = r300->radeon.glCtx; - r300InitConstValues(ctx, screen); - if (hw_tcl_on) + if (r300->options.hw_tcl_enabled) ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; + r300InitConstValues(ctx, screen); + /* Initialize the software rasterizer and helper modules. */ _swrast_CreateContext(ctx); @@ -400,56 +433,21 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, _tnl_allow_pixel_fog(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_TRUE); + if (!r300->options.hw_tcl_enabled) + r300InitSwtcl(ctx); + radeon_fbo_init(&r300->radeon); - radeonInitSpanFuncs( ctx ); + radeonInitSpanFuncs( ctx ); r300InitCmdBuf(r300); r300InitState(r300); r300InitShaderFunctions(r300); - if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) - r300InitSwtcl(ctx); - - driInitExtensions(ctx, card_extensions, GL_TRUE); - if (r300->radeon.radeonScreen->kernel_mm) - driInitExtensions(ctx, mm_extensions, GL_FALSE); if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 || screen->chip_family == CHIP_FAMILY_RS740) { r300->radeon.texture_row_align = 64; } - r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, - "def_max_anisotropy"); - - if (driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side")) - _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); - - if (ctx->Mesa_DXTn && !driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc")) { - _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); - _mesa_enable_extension(ctx, "GL_S3_s3tc"); - } else if (driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable")) { - _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); - } - - r300->disable_lowimpact_fallback = - driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); - - tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode"); - if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) { - fprintf(stderr, "disabling 3D acceleration\n"); -#if R200_MERGED - FALLBACK(&r300->radeon, RADEON_FALLBACK_DISABLE, 1); -#endif - } - if (tcl_mode == DRI_CONF_TCL_SW || - !(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { - if (r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - r300->radeon.radeonScreen->chip_flags &= - ~RADEON_CHIPSET_TCL; - fprintf(stderr, "Disabling HW TCL support\n"); - } - TCL_FALLBACK(r300->radeon.glCtx, - RADEON_TCL_FALLBACK_TCL_DISABLE, 1); - } + r300InitGLExtensions(ctx); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index d45e4beec0b..ad8b5a2ae45 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -412,8 +412,6 @@ struct r300_vertex_shader_state { struct r300_vertex_shader_fragment program; }; -extern int hw_tcl_on; - #define COLOR_IS_RGBA #define TAG(x) r300##x #include "tnl_dd/t_dd_vertex.h" @@ -648,6 +646,14 @@ struct r300_context { GLboolean disable_lowimpact_fallback; + struct r300_options { + uint32_t conformance_mode:1; + uint32_t hw_tcl_enabled:1; + uint32_t s3tc_force_enabled:1; + uint32_t s3tc_force_disabled:1; + uint32_t stencil_two_side_disabled:1; + } options; + struct r300_swtcl_info swtcl; GLboolean vap_flush_needed; diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index a19b0f19605..20b77bc9aea 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -214,7 +214,7 @@ int r300EmitArrays(GLcontext * ctx) struct r300_vertex_program *prog = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); - if (hw_tcl_on) { + if (rmesa->options.hw_tcl_enabled) { inputs = prog->inputs; InputsRead = prog->key.InputsRead; OutputsWritten = prog->key.OutputsWritten; diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index a7f5121da74..6766eb3eaee 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -215,12 +215,11 @@ static void r300EmitClearState(GLcontext * ctx) BATCH_LOCALS(&r300->radeon); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; int i; - int has_tcl = 1; + int has_tcl; int is_r500 = 0; GLuint vap_cntl; - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; + has_tcl = r300->options.hw_tcl_enabled; if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index f87fee4af65..93fdc575885 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -74,8 +74,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_emit.h" #include "r300_fragprog_common.h" -extern int future_hw_tcl_on; - /** * \brief Convert a OpenGL primitive type into a R300 primitive type. */ @@ -468,8 +466,8 @@ static GLboolean r300RunNonTCLRender(GLcontext * ctx, if (r300Fallback(ctx) >= R300_FALLBACK_RAST) return GL_TRUE; - if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - return GL_TRUE; + if (rmesa->options.hw_tcl_enabled == GL_FALSE) + return GL_TRUE; if (!r300ValidateBuffers(ctx)) return GL_TRUE; @@ -483,16 +481,14 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_vertex_program *vp; - hw_tcl_on = future_hw_tcl_on; - if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); - if (hw_tcl_on == GL_FALSE) + if (rmesa->options.hw_tcl_enabled == GL_FALSE) return GL_TRUE; if (r300Fallback(ctx) >= R300_FALLBACK_TCL) { - hw_tcl_on = GL_FALSE; + rmesa->options.hw_tcl_enabled = GL_FALSE; return GL_TRUE; } @@ -503,7 +499,7 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); if (vp->native == GL_FALSE) { - hw_tcl_on = GL_FALSE; + rmesa->options.hw_tcl_enabled = GL_FALSE; return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 7a025aa56f5..873ac4aaec6 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -67,8 +67,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" -extern int future_hw_tcl_on; - static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4]) { r300ContextPtr rmesa = R300_CONTEXT(ctx); @@ -367,7 +365,7 @@ static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) GLint *ip; /* no VAP UCP on non-TCL chipsets */ - if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (!rmesa->options.hw_tcl_enabled) return; p = (GLint) plane - (GLint) GL_CLIP_PLANE0; @@ -386,7 +384,7 @@ static void r300SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) GLuint p; /* no VAP UCP on non-TCL chipsets */ - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (!r300->options.hw_tcl_enabled) return; p = cap - GL_CLIP_PLANE0; @@ -1416,8 +1414,9 @@ static void r300SetupRSUnit(GLcontext * ctx) int fp_reg, high_rr; int col_ip, tex_ip; int rs_tex_count = 0; - int i, count, col_fmt; + int i, count, col_fmt, hw_tcl_on; + hw_tcl_on = r300->options.hw_tcl_enabled; if (hw_tcl_on) OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else @@ -1552,8 +1551,9 @@ static void r500SetupRSUnit(GLcontext * ctx) int fp_reg, high_rr; int col_ip, tex_ip; int rs_tex_count = 0; - int i, count, col_fmt; + int i, count, col_fmt, hw_tcl_on; + hw_tcl_on = r300->options.hw_tcl_enabled; if (hw_tcl_on) OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else @@ -1764,7 +1764,7 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, pvs_num_cntrls = MIN2(6, vtx_mem_size/temp_count); R300_STATECHANGE(rmesa, vap_cntl); - if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + if (rmesa->options.hw_tcl_enabled) { rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = (pvs_num_slots << R300_PVS_NUM_SLOTS_SHIFT) | (pvs_num_cntrls << R300_PVS_NUM_CNTLRS_SHIFT) | @@ -1894,7 +1894,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) 0x400 area might have something to do with pixel shaders as it appears right after pfs programming. 0x406 is set to { 0.0, 0.0, 1.0, 0.0 } most of the time but should change with smooth points and in other rare cases. */ //setup_vertex_shader_fragment(rmesa, 0x406, &unk4); - if (hw_tcl_on && ((struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) { + if (rmesa->options.hw_tcl_enabled && ((struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) { r300SetupRealVertexProgram(rmesa); } else { /* FIXME: This needs to be replaced by vertex shader generation code. */ @@ -1972,10 +1972,9 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) static void r300ResetHwState(r300ContextPtr r300) { GLcontext *ctx = r300->radeon.glCtx; - int has_tcl = 1; + int has_tcl; - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; + has_tcl = r300->options.hw_tcl_enabled; if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); @@ -2193,7 +2192,7 @@ void r300UpdateShaders(r300ContextPtr rmesa) ctx = rmesa->radeon.glCtx; - if (rmesa->radeon.NewGLState && hw_tcl_on) { + if (rmesa->radeon.NewGLState && rmesa->options.hw_tcl_enabled) { rmesa->radeon.NewGLState = 0; for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { @@ -2217,7 +2216,7 @@ void r300UpdateShaders(r300ContextPtr rmesa) r300TranslateVertexShader(vp); */ if (vp->translated == GL_FALSE) { fprintf(stderr, "Failing back to sw-tcl\n"); - hw_tcl_on = future_hw_tcl_on = 0; + rmesa->options.hw_tcl_enabled = 0; r300ResetHwState(rmesa); r300UpdateStateParameters(ctx, _NEW_PROGRAM | @@ -2425,7 +2424,7 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->vtbl.SetupRSUnit(ctx); - if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (rmesa->options.hw_tcl_enabled) r300SetupVertexProgram(rmesa); } -- cgit v1.2.3 From d6da805c4e6f060a4a531aba89d4a7db885767f4 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 13 May 2009 22:28:39 +0200 Subject: r300: remove unnecessary switch cases --- src/mesa/drivers/dri/r300/r300_state.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 873ac4aaec6..c0e3dbe9949 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1917,14 +1917,6 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) state ? "GL_TRUE" : "GL_FALSE"); switch (cap) { - case GL_TEXTURE_1D: - case GL_TEXTURE_2D: - case GL_TEXTURE_3D: - /* empty */ - break; - case GL_FOG: - /* empty */ - break; case GL_ALPHA_TEST: r300SetAlphaState(ctx); break; -- cgit v1.2.3 From 621f65ab86f94f7a228e5f96061a8e3451f15db0 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 13 May 2009 22:33:27 +0200 Subject: r300: r300EmitArrays should never fail --- src/mesa/drivers/dri/r300/r300_emit.c | 9 ++------- src/mesa/drivers/dri/r300/r300_emit.h | 2 +- src/mesa/drivers/dri/r300/r300_render.c | 3 +-- 3 files changed, 4 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 20b77bc9aea..45e7074002e 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -196,9 +196,8 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) /* Emit vertex data to GART memory * Route inputs to the vertex processor - * This function should never return R300_FALLBACK_TCL when using software tcl. */ -int r300EmitArrays(GLcontext * ctx) +void r300EmitArrays(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); @@ -284,9 +283,7 @@ int r300EmitArrays(GLcontext * ctx) } } - if (nr > R300_MAX_AOS_ARRAYS) { - return R300_FALLBACK_TCL; - } + assert(nr <= R300_MAX_AOS_ARRAYS); for (i = 0; i < nr; i++) { int ci; @@ -341,8 +338,6 @@ int r300EmitArrays(GLcontext * ctx) r300VAPOutputCntl1(ctx, OutputsWritten); rmesa->radeon.tcl.aos_count = nr; - - return R300_FALLBACK_NONE; } void r300EmitCacheFlush(r300ContextPtr rmesa) diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 80c22d5e9ab..e6485e9bd75 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -216,7 +216,7 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) } } -extern int r300EmitArrays(GLcontext * ctx); +extern void r300EmitArrays(GLcontext * ctx); extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 93fdc575885..4d2d9e761d4 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -390,8 +390,7 @@ static GLboolean r300RunRender(GLcontext * ctx, fprintf(stderr, "%s\n", __FUNCTION__); r300UpdateShaders(rmesa); - if (r300EmitArrays(ctx)) - return GL_TRUE; + r300EmitArrays(ctx); r300UpdateShaderStates(rmesa); -- cgit v1.2.3 From 2240c0d33365189f975b84b06792e2a5ecb8b13a Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 14 May 2009 02:07:49 +0200 Subject: r300: software fallbacking handling rewrite Until now falling back to software rasterizer worked only for TCL enabled cards. For non TCL cards we used to plug our rendering functions in r300InitSwtcl, and we had never restored original functions for software rasterizer. --- src/mesa/drivers/dri/r300/r300_context.c | 4 +- src/mesa/drivers/dri/r300/r300_context.h | 8 +- src/mesa/drivers/dri/r300/r300_render.c | 137 ++++++++++++++++++------------- src/mesa/drivers/dri/r300/r300_render.h | 49 +++++++++++ src/mesa/drivers/dri/r300/r300_state.c | 93 ++++++++++++++------- src/mesa/drivers/dri/r300/r300_swtcl.c | 10 +-- src/mesa/drivers/dri/r300/r300_swtcl.h | 6 ++ 7 files changed, 208 insertions(+), 99 deletions(-) create mode 100644 src/mesa/drivers/dri/r300/r300_render.h (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3c16e80d2bb..5b22a11bca2 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -332,7 +332,6 @@ static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen) driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r300"); - r300->disable_lowimpact_fallback = driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side"); @@ -344,6 +343,8 @@ static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen) else options.hw_tcl_enabled = 1; + options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); + r300->options = options; } @@ -405,6 +406,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx = r300->radeon.glCtx; + r300->fallback = 0; if (r300->options.hw_tcl_enabled) ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index ad8b5a2ae45..d9e1944d716 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -587,10 +587,6 @@ struct r300_fragment_program_compiler { #define R300_MAX_AOS_ARRAYS 16 -#define R300_FALLBACK_NONE 0 -#define R300_FALLBACK_TCL 1 -#define R300_FALLBACK_RAST 2 - /* r300_swtcl.c */ struct r300_swtcl_info { @@ -644,8 +640,6 @@ struct r300_context { GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - GLboolean disable_lowimpact_fallback; - struct r300_options { uint32_t conformance_mode:1; uint32_t hw_tcl_enabled:1; @@ -657,6 +651,8 @@ struct r300_context { struct r300_swtcl_info swtcl; GLboolean vap_flush_needed; + uint32_t fallback; + DECLARE_RENDERINPUTS(render_inputs_bitset); }; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 4d2d9e761d4..7edeaed6d82 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -50,6 +50,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * no bugs... */ +#include "r300_render.h" + #include "main/glheader.h" #include "main/state.h" #include "main/imports.h" @@ -73,6 +75,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_tex.h" #include "r300_emit.h" #include "r300_fragprog_common.h" +#include "r300_swtcl.h" /** * \brief Convert a OpenGL primitive type into a R300 primitive type. @@ -378,7 +381,7 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, COMMIT_BATCH(); } -static GLboolean r300RunRender(GLcontext * ctx, +static void r300RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { r300ContextPtr rmesa = R300_CONTEXT(ctx); @@ -407,51 +410,77 @@ static GLboolean r300RunRender(GLcontext * ctx, r300EmitCacheFlush(rmesa); radeonReleaseArrays(ctx, ~0); - - return GL_FALSE; } -#define FALLBACK_IF(expr) \ - do { \ - if (expr) { \ - if (1 || RADEON_DEBUG & DEBUG_FALLBACKS) \ - WARN_ONCE("Software fallback:%s\n", \ - #expr); \ - return R300_FALLBACK_RAST; \ - } \ - } while(0) - -static int r300Fallback(GLcontext * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - const unsigned back = ctx->Stencil._BackFace; - FALLBACK_IF(r300->radeon.Fallback); - - struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; - if (fp && !fp->translated) { - r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); - FALLBACK_IF(fp->error); +static const char *getFallbackString(uint32_t bit) +{ + switch (bit) { + case R300_FALLBACK_VERTEX_PROGRAM : + return "vertex program"; + case R300_FALLBACK_LINE_SMOOTH: + return "smooth lines"; + case R300_FALLBACK_POINT_SMOOTH: + return "smooth points"; + case R300_FALLBACK_POLYGON_SMOOTH: + return "smooth polygons"; + case R300_FALLBACK_LINE_STIPPLE: + return "line stipple"; + case R300_FALLBACK_POLYGON_STIPPLE: + return "polygon stipple"; + case R300_FALLBACK_STENCIL_TWOSIDE: + return "two-sided stencil"; + case R300_FALLBACK_RENDER_MODE: + return "render mode != GL_RENDER"; + case R300_FALLBACK_FRAGMENT_PROGRAM: + return "fragment program"; + case R300_FALLBACK_INVALID_BUFFERS: + return "invalid buffers"; + default: + return "unknown"; } +} - FALLBACK_IF(ctx->RenderMode != GL_RENDER); - - FALLBACK_IF(ctx->Stencil.Enabled && (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back] - || ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back] - || ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])); - - if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite) - FALLBACK_IF(ctx->Point.PointSprite); - - if (!r300->disable_lowimpact_fallback) { - FALLBACK_IF(ctx->Polygon.StippleFlag); - FALLBACK_IF(ctx->Multisample._Enabled); - FALLBACK_IF(ctx->Line.StippleFlag); - FALLBACK_IF(ctx->Line.SmoothFlag); - FALLBACK_IF(ctx->Point.SmoothFlag); +void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode) +{ + TNLcontext *tnl = TNL_CONTEXT(ctx); + r300ContextPtr rmesa = R300_CONTEXT(ctx); + uint32_t old_fallback = rmesa->fallback; + static uint32_t fallback_warn = 0; + + if (mode) { + if ((fallback_warn & bit) == 0) { + _mesa_fprintf(stderr, "WARNING! Falling back to software for %s\n", getFallbackString(bit)); + fallback_warn |= bit; + } + rmesa->fallback |= bit; + /* update only if we change from no raster fallbacks to some raster fallbacks */ + if (((old_fallback & R300_RASTER_FALLBACK_MASK) == 0) && + ((bit & R300_RASTER_FALLBACK_MASK) > 0)) { + + radeon_firevertices(&rmesa->radeon); + rmesa->radeon.swtcl.RenderIndex = ~0; + _swsetup_Wakeup( ctx ); + } + } else { + rmesa->fallback &= ~bit; + /* update only if we have disabled all raster fallbacks */ + if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) { + _swrast_flush( ctx ); + + tnl->Driver.Render.Start = r300RenderStart; + tnl->Driver.Render.Finish = r300RenderFinish; + tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive; + tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple; + tnl->Driver.Render.BuildVertices = _tnl_build_vertices; + tnl->Driver.Render.CopyPV = _tnl_copy_pv; + tnl->Driver.Render.Interp = _tnl_interp; + + _tnl_invalidate_vertex_state( ctx, ~0 ); + _tnl_invalidate_vertices( ctx, ~0 ); + } } - - return R300_FALLBACK_NONE; + } static GLboolean r300RunNonTCLRender(GLcontext * ctx, @@ -462,23 +491,21 @@ static GLboolean r300RunNonTCLRender(GLcontext * ctx, if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); - if (r300Fallback(ctx) >= R300_FALLBACK_RAST) + if (rmesa->fallback & R300_RASTER_FALLBACK_MASK) return GL_TRUE; if (rmesa->options.hw_tcl_enabled == GL_FALSE) return GL_TRUE; - if (!r300ValidateBuffers(ctx)) - return GL_TRUE; + r300RunRender(ctx, stage); - return r300RunRender(ctx, stage); + return GL_FALSE; } static GLboolean r300RunTCLRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_vertex_program *vp; if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); @@ -486,23 +513,17 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, if (rmesa->options.hw_tcl_enabled == GL_FALSE) return GL_TRUE; - if (r300Fallback(ctx) >= R300_FALLBACK_TCL) { - rmesa->options.hw_tcl_enabled = GL_FALSE; - return GL_TRUE; - } - - if (!r300ValidateBuffers(ctx)) - return GL_TRUE; - + /* Call it here so we can fallback early */ r300UpdateShaders(rmesa); - vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); - if (vp->native == GL_FALSE) { - rmesa->options.hw_tcl_enabled = GL_FALSE; + r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, !r300ValidateBuffers(ctx)); + + if (rmesa->fallback) return GL_TRUE; - } - return r300RunRender(ctx, stage); + r300RunRender(ctx, stage); + + return GL_FALSE; } const struct tnl_pipeline_stage _r300_render_stage = { diff --git a/src/mesa/drivers/dri/r300/r300_render.h b/src/mesa/drivers/dri/r300/r300_render.h new file mode 100644 index 00000000000..fbc9581e06a --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_render.h @@ -0,0 +1,49 @@ +/* + * Copyright 2009 Maciej Cencora + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __R300_RENDER_H__ +#define __R300_RENDER_H__ + +#include "main/mtypes.h" + +#define R300_FALLBACK_VERTEX_PROGRAM (1 << 0) +#define R300_TCL_FALLBACK_MASK 0x0000ffff + +#define R300_FALLBACK_LINE_SMOOTH (1 << 16) +#define R300_FALLBACK_POINT_SMOOTH (1 << 17) +#define R300_FALLBACK_POLYGON_SMOOTH (1 << 18) +#define R300_FALLBACK_LINE_STIPPLE (1 << 19) +#define R300_FALLBACK_POLYGON_STIPPLE (1 << 20) +#define R300_FALLBACK_STENCIL_TWOSIDE (1 << 21) +#define R300_FALLBACK_RENDER_MODE (1 << 22) +#define R300_FALLBACK_FRAGMENT_PROGRAM (1 << 23) +#define R300_FALLBACK_INVALID_BUFFERS (1 << 31) +#define R300_RASTER_FALLBACK_MASK 0xffff0000 + +extern void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode); + +#endif diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index c0e3dbe9949..397a26c3dfe 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_fragprog_common.h" #include "r300_fragprog.h" #include "r500_fragprog.h" +#include "r300_render.h" #include "drirenderbuffer.h" @@ -574,10 +575,26 @@ static void r300SetDepthState(GLcontext * ctx) } } +static void r300CatchStencilFallback(GLcontext *ctx) +{ + const unsigned back = ctx->Stencil._BackFace; + + if (ctx->Stencil._Enabled && (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back] + || ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back] + || ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])) { + r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_TRUE); + } else { + r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE); + } +} + static void r300SetStencilState(GLcontext * ctx, GLboolean state) { r300ContextPtr r300 = R300_CONTEXT(ctx); GLboolean hw_stencil = GL_FALSE; + + r300CatchStencilFallback(ctx); + if (ctx->DrawBuffer) { struct radeon_renderbuffer *rrbStencil = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); @@ -593,10 +610,6 @@ static void r300SetStencilState(GLcontext * ctx, GLboolean state) r300->hw.zs.cmd[R300_ZS_CNTL_0] &= ~R300_STENCIL_ENABLE; } - } else { -#if R200_MERGED - FALLBACK(&r300->radeon, RADEON_FALLBACK_STENCIL, state); -#endif } } @@ -846,11 +859,14 @@ static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face, GLenum func, GLint ref, GLuint mask) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLuint refmask = - ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT) - | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT); - const unsigned back = ctx->Stencil._BackFace; + GLuint refmask; GLuint flag; + const unsigned back = ctx->Stencil._BackFace; + + r300CatchStencilFallback(ctx); + + refmask = ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT) + | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT); R300_STATECHANGE(rmesa, zs); rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK; @@ -878,6 +894,8 @@ static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) { r300ContextPtr rmesa = R300_CONTEXT(ctx); + r300CatchStencilFallback(ctx); + R300_STATECHANGE(rmesa, zs); rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &= ~(R300_STENCILREF_MASK << @@ -894,6 +912,8 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, r300ContextPtr rmesa = R300_CONTEXT(ctx); const unsigned back = ctx->Stencil._BackFace; + r300CatchStencilFallback(ctx); + R300_STATECHANGE(rmesa, zs); /* It is easier to mask what's left.. */ rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= @@ -1934,14 +1954,31 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_CLIP_PLANE5: r300SetClipPlaneState(ctx, cap, state); break; + case GL_CULL_FACE: + r300UpdateCulling(ctx); + break; case GL_DEPTH_TEST: r300SetDepthState(ctx); break; - case GL_STENCIL_TEST: - r300SetStencilState(ctx, state); + case GL_LINE_SMOOTH: + if (rmesa->options.conformance_mode) + r300SwitchFallback(ctx, R300_FALLBACK_LINE_SMOOTH, ctx->Line.SmoothFlag); break; - case GL_CULL_FACE: - r300UpdateCulling(ctx); + case GL_LINE_STIPPLE: + if (rmesa->options.conformance_mode) + r300SwitchFallback(ctx, R300_FALLBACK_LINE_STIPPLE, ctx->Line.StippleFlag); + break; + case GL_POINT_SMOOTH: + if (rmesa->options.conformance_mode) + r300SwitchFallback(ctx, R300_FALLBACK_POINT_SMOOTH, ctx->Point.SmoothFlag); + break; + case GL_POLYGON_SMOOTH: + if (rmesa->options.conformance_mode) + r300SwitchFallback(ctx, R300_FALLBACK_POLYGON_SMOOTH, ctx->Polygon.SmoothFlag); + break; + case GL_POLYGON_STIPPLE: + if (rmesa->options.conformance_mode) + r300SwitchFallback(ctx, R300_FALLBACK_POLYGON_STIPPLE, ctx->Polygon.StippleFlag); break; case GL_POLYGON_OFFSET_POINT: case GL_POLYGON_OFFSET_LINE: @@ -1953,6 +1990,9 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) rmesa->radeon.state.scissor.enabled = state; radeonUpdateScissor( ctx ); break; + case GL_STENCIL_TEST: + r300SetStencilState(ctx, state); + break; default: break; } @@ -2180,9 +2220,11 @@ void r300UpdateShaders(r300ContextPtr rmesa) { GLcontext *ctx; struct r300_vertex_program *vp; + struct r300_fragment_program *fp; int i; ctx = rmesa->radeon.glCtx; + fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; if (rmesa->radeon.NewGLState && rmesa->options.hw_tcl_enabled) { rmesa->radeon.NewGLState = 0; @@ -2202,20 +2244,17 @@ void r300UpdateShaders(r300ContextPtr rmesa) } r300SelectVertexShader(rmesa); - vp = (struct r300_vertex_program *) - CURRENT_VERTEX_SHADER(ctx); - /*if (vp->translated == GL_FALSE) - r300TranslateVertexShader(vp); */ - if (vp->translated == GL_FALSE) { - fprintf(stderr, "Failing back to sw-tcl\n"); - rmesa->options.hw_tcl_enabled = 0; - r300ResetHwState(rmesa); - - r300UpdateStateParameters(ctx, _NEW_PROGRAM | - _NEW_PROGRAM_CONSTANTS); - return; - } + vp = (struct r300_vertex_program *) CURRENT_VERTEX_SHADER(ctx); + r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, !vp->native); + } + + if (fp) { + if (!fp->translated) + r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); + + r300SwitchFallback(ctx, R300_FALLBACK_FRAGMENT_PROGRAM, fp->error); } + r300UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); } @@ -2457,9 +2496,7 @@ void r300InitState(r300ContextPtr r300) static void r300RenderMode(GLcontext * ctx, GLenum mode) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - (void)rmesa; - (void)mode; + r300SwitchFallback(ctx, R300_FALLBACK_RENDER_MODE, ctx->RenderMode != GL_RENDER); } /** diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index a40d0378db1..78fa031479c 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -324,7 +324,6 @@ static GLuint reduced_prim[] = { }; static void r300RasterPrimitive( GLcontext *ctx, GLuint prim ); -static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); /*********************************************************************** * Emit primitives as inline vertices * @@ -558,7 +557,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) } -static void r300RenderStart(GLcontext *ctx) +void r300RenderStart(GLcontext *ctx) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); @@ -578,7 +577,7 @@ static void r300RenderStart(GLcontext *ctx) } } -static void r300RenderFinish(GLcontext *ctx) +void r300RenderFinish(GLcontext *ctx) { } @@ -592,7 +591,7 @@ static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) } } -static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) +void r300RenderPrimitive(GLcontext *ctx, GLenum prim) { r300ContextPtr rmesa = R300_CONTEXT(ctx); @@ -604,7 +603,7 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) r300RasterPrimitive( ctx, reduced_prim[prim] ); } -static void r300ResetLineStipple(GLcontext *ctx) +void r300ResetLineStipple(GLcontext *ctx) { } @@ -640,7 +639,6 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_invalidate_vertices( ctx, ~0 ); _tnl_need_projected_coords( ctx, GL_FALSE ); - r300ChooseRenderState(ctx); } void r300DestroySwtcl(GLcontext *ctx) diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index 75c419380d3..14826f08171 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -60,5 +60,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r300InitSwtcl( GLcontext *ctx ); extern void r300DestroySwtcl( GLcontext *ctx ); +extern void r300RenderStart(GLcontext *ctx); +extern void r300RenderFinish(GLcontext *ctx); +extern void r300RenderPrimitive(GLcontext *ctx, GLenum prim); +extern void r300ResetLineStipple(GLcontext *ctx); + extern void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset); + #endif -- cgit v1.2.3 From 6f1a86ca1eb4a44a738d0ad99861d948c9749de6 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 13 May 2009 23:09:39 +0200 Subject: r300: move forward declarations to where they belong --- src/mesa/drivers/dri/r300/r300_context.c | 5 +---- src/mesa/drivers/dri/r300/r300_render.h | 4 ++++ 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5b22a11bca2..be8d480c1cb 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "r300_tex.h" #include "r300_emit.h" +#include "r300_render.h" #include "r300_swtcl.h" #include "radeon_bocs_wrapper.h" @@ -150,10 +151,6 @@ const struct dri_extension gl_20_extension[] = { {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, }; - -extern struct tnl_pipeline_stage _r300_render_stage; -extern const struct tnl_pipeline_stage _r300_tcl_stage; - static const struct tnl_pipeline_stage *r300_pipeline[] = { /* Try and go straight to t&l diff --git a/src/mesa/drivers/dri/r300/r300_render.h b/src/mesa/drivers/dri/r300/r300_render.h index fbc9581e06a..940d2566e2c 100644 --- a/src/mesa/drivers/dri/r300/r300_render.h +++ b/src/mesa/drivers/dri/r300/r300_render.h @@ -44,6 +44,10 @@ #define R300_FALLBACK_INVALID_BUFFERS (1 << 31) #define R300_RASTER_FALLBACK_MASK 0xffff0000 +extern const struct tnl_pipeline_stage _r300_render_stage; + +extern const struct tnl_pipeline_stage _r300_tcl_stage; + extern void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode); #endif -- cgit v1.2.3 From 12ed56f1ddfbd40df16d4ab47b546ee25218118f Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 13 May 2009 23:49:04 +0200 Subject: r300: rename functions Be consistent with function naming: use Setup/Emit names for functions that modify hardware state --- src/mesa/drivers/dri/r300/r300_context.h | 2 +- src/mesa/drivers/dri/r300/r300_fragprog.h | 2 +- src/mesa/drivers/dri/r300/r300_fragprog_common.c | 2 +- src/mesa/drivers/dri/r300/r300_fragprog_emit.c | 2 +- src/mesa/drivers/dri/r300/r300_state.c | 4 ++-- src/mesa/drivers/dri/r300/r500_fragprog.h | 2 +- src/mesa/drivers/dri/r300/r500_fragprog_emit.c | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index d9e1944d716..cd25b1da017 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -616,7 +616,7 @@ struct r300_swtcl_info { struct r300_vtable { void (* SetupRSUnit)(GLcontext *ctx); void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings); - GLboolean (* FragmentProgramEmit)(struct r300_fragment_program_compiler *compiler); + GLboolean (* BuildFragmentProgramHwCode)(struct r300_fragment_program_compiler *compiler); void (* FragmentProgramDump)(union rX00_fragment_program_code *code); GLboolean (* SetupPixelShader)(GLcontext *ctx); }; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index affa022a5cf..5ce6f33cee7 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -102,7 +102,7 @@ #endif -extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); +extern GLboolean r300BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler); extern void r300FragmentProgramDump(union rX00_fragment_program_code *c); diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c index 2a880e6d144..abc8757ba1f 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c @@ -269,7 +269,7 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct gl_fragment_program *fp) fflush(stdout); } - if (!r300->vtbl.FragmentProgramEmit(&compiler)) + if (!r300->vtbl.BuildFragmentProgramHwCode(&compiler)) r300_fp->error = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c index af8bb3887bc..b75656e7ee1 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c @@ -325,7 +325,7 @@ static const struct radeon_pair_handler pair_handler = { * Final compilation step: Turn the intermediate radeon_program into * machine-readable instructions. */ -GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler) +GLboolean r300BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler) { struct r300_fragment_program_code *code = &compiler->code->r300; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 397a26c3dfe..7b523e532f4 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2551,13 +2551,13 @@ void r300InitShaderFunctions(r300ContextPtr r300) r300->vtbl.SetupRSUnit = r500SetupRSUnit; r300->vtbl.SetupPixelShader = r500SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures; - r300->vtbl.FragmentProgramEmit = r500FragmentProgramEmit; + r300->vtbl.BuildFragmentProgramHwCode = r500BuildFragmentProgramHwCode; r300->vtbl.FragmentProgramDump = r500FragmentProgramDump; } else { r300->vtbl.SetupRSUnit = r300SetupRSUnit; r300->vtbl.SetupPixelShader = r300SetupPixelShader; r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures; - r300->vtbl.FragmentProgramEmit = r300FragmentProgramEmit; + r300->vtbl.BuildFragmentProgramHwCode = r300BuildFragmentProgramHwCode; r300->vtbl.FragmentProgramDump = r300FragmentProgramDump; } } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index 9ca2f9be510..1179bf66073 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -39,7 +39,7 @@ #include "r300_context.h" #include "radeon_nqssadce.h" -extern GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); +extern GLboolean r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler); extern void r500FragmentProgramDump(union rX00_fragment_program_code *c); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c index 277f801c385..30f4514897e 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c @@ -299,7 +299,7 @@ static const struct radeon_pair_handler pair_handler = { .MaxHwTemps = 128 }; -GLboolean r500FragmentProgramEmit(struct r300_fragment_program_compiler *compiler) +GLboolean r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler) { struct r500_fragment_program_code *code = &compiler->code->r500; -- cgit v1.2.3 From 1961caeda849faeb9265d6df5724f2454f4c1055 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 13 May 2009 23:58:21 +0200 Subject: r300: move some code to common path --- src/mesa/drivers/dri/r300/r300_context.h | 2 +- src/mesa/drivers/dri/r300/r300_state.c | 31 +++++++++++-------------------- 2 files changed, 12 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index cd25b1da017..4111fa2d81a 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -618,7 +618,7 @@ struct r300_vtable { void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings); GLboolean (* BuildFragmentProgramHwCode)(struct r300_fragment_program_compiler *compiler); void (* FragmentProgramDump)(union rX00_fragment_program_code *code); - GLboolean (* SetupPixelShader)(GLcontext *ctx); + void (* SetupPixelShader)(GLcontext *ctx); }; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 7b523e532f4..5821395f661 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2279,21 +2279,15 @@ static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, } -static GLboolean r300SetupPixelShader(GLcontext *ctx) +static void r300SetupPixelShader(GLcontext *ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; struct r300_fragment_program_code *code; int i, k; - /* Program is not native, fallback to software */ - if (fp->error) - return GL_FALSE; - code = &fp->code.r300; - r300SetupTextures(ctx); - R300_STATECHANGE(rmesa, fpi[0]); R300_STATECHANGE(rmesa, fpi[1]); R300_STATECHANGE(rmesa, fpi[2]); @@ -2341,8 +2335,6 @@ static GLboolean r300SetupPixelShader(GLcontext *ctx) rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]); rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]); } - - return GL_TRUE; } #define bump_r500fp_count(ptr, new_count) do{\ @@ -2359,7 +2351,7 @@ static GLboolean r300SetupPixelShader(GLcontext *ctx) if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ } while(0) -static GLboolean r500SetupPixelShader(GLcontext *ctx) +static void r500SetupPixelShader(GLcontext *ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_fragment_program *fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; @@ -2369,14 +2361,8 @@ static GLboolean r500SetupPixelShader(GLcontext *ctx) ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0; ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0; - /* Program is not native, fallback to software */ - if (fp->error) - return GL_FALSE; - code = &fp->code.r500; - r300SetupTextures(ctx); - R300_STATECHANGE(rmesa, fp); rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx; @@ -2412,17 +2398,18 @@ static GLboolean r500SetupPixelShader(GLcontext *ctx) rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]); } bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4); - - return GL_TRUE; } void r300UpdateShaderStates(r300ContextPtr rmesa) { GLcontext *ctx; ctx = rmesa->radeon.glCtx; + struct r300_fragment_program *r300_fp; + + r300_fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; /* should only happenen once, just after context is created */ - if (!ctx->FragmentProgram._Current) + if (!r300_fp) return; r300SetEarlyZState(ctx); @@ -2450,9 +2437,13 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); - if (!rmesa->vtbl.SetupPixelShader(ctx)) + if (r300_fp->error) return; + r300SetupTextures(ctx); + + rmesa->vtbl.SetupPixelShader(ctx); + rmesa->vtbl.SetupRSUnit(ctx); if (rmesa->options.hw_tcl_enabled) -- cgit v1.2.3 From f8c30793d161618fa1cdc788ad7984566b236d5e Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 14 May 2009 00:10:52 +0200 Subject: r300: more cleanup - remove unnecessary r300TranslateFragmentShader call from r300UpdateShaderStates (it is already called in r300UpdateShaders) - remove unnecessary null ptr checks --- src/mesa/drivers/dri/r300/r300_state.c | 40 +++++++++++----------------------- 1 file changed, 13 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 5821395f661..502bdd2f6d4 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1395,9 +1395,6 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1); - if (!fp) /* should only happenen once, just after context is created */ - return; - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { if (fp->Base.UsesKill && last_hw_tmu < 0) { // The KILL operation requires the first texture unit @@ -1442,12 +1439,7 @@ static void r300SetupRSUnit(GLcontext * ctx) else RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); - if (ctx->FragmentProgram._Current) - InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; - else { - fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); - return; /* This should only ever happen once.. */ - } + InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; R300_STATECHANGE(r300, ri); R300_STATECHANGE(r300, rc); @@ -1579,12 +1571,7 @@ static void r500SetupRSUnit(GLcontext * ctx) else RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); - if (ctx->FragmentProgram._Current) - InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; - else { - fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); - return; /* This should only ever happen once.. */ - } + InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; R300_STATECHANGE(r300, ri); R300_STATECHANGE(r300, rc); @@ -2226,9 +2213,14 @@ void r300UpdateShaders(r300ContextPtr rmesa) ctx = rmesa->radeon.glCtx; fp = (struct r300_fragment_program *) ctx->FragmentProgram._Current; - if (rmesa->radeon.NewGLState && rmesa->options.hw_tcl_enabled) { - rmesa->radeon.NewGLState = 0; + /* should only happenen once, just after context is created */ + /* TODO: shouldn't we fallback to sw here? */ + if (!fp) { + _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); + return; + } + if (rmesa->radeon.NewGLState && rmesa->options.hw_tcl_enabled) { for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { rmesa->temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i]; @@ -2248,14 +2240,13 @@ void r300UpdateShaders(r300ContextPtr rmesa) r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, !vp->native); } - if (fp) { - if (!fp->translated) - r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); + if (!fp->translated || rmesa->radeon.NewGLState) + r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); - r300SwitchFallback(ctx, R300_FALLBACK_FRAGMENT_PROGRAM, fp->error); - } + r300SwitchFallback(ctx, R300_FALLBACK_FRAGMENT_PROGRAM, fp->error); r300UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); + rmesa->radeon.NewGLState = 0; } static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, @@ -2435,11 +2426,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; } - r300TranslateFragmentShader(ctx, ctx->FragmentProgram._Current); - - if (r300_fp->error) - return; - r300SetupTextures(ctx); rmesa->vtbl.SetupPixelShader(ctx); -- cgit v1.2.3 From 1b49f1ca7f9ffda8b4a75ef2ad0be4c2c0eb820a Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 14 May 2009 00:22:21 +0200 Subject: r300: minor code movement --- src/mesa/drivers/dri/r300/r300_state.c | 42 +++++++++++++++++----------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 502bdd2f6d4..af9e553eb59 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -460,6 +460,7 @@ static void r300SetEarlyZState(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); GLuint topZ = R300_ZTOP_ENABLE; + GLuint w_fmt, fgdepthsrc; if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS) topZ = R300_ZTOP_DISABLE; @@ -476,6 +477,26 @@ static void r300SetEarlyZState(GLcontext * ctx) R300_STATECHANGE(r300, zstencil_format); r300->hw.zstencil_format.cmd[2] = topZ; } + + /* w_fmt value is set to get best performance + * see p.130 R5xx 3D acceleration guide v1.3 */ + if (current_fragment_program_writes_depth(ctx)) { + fgdepthsrc = R300_FG_DEPTH_SRC_SHADER; + w_fmt = R300_W_FMT_W24 | R300_W_SRC_US; + } else { + fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; + w_fmt = R300_W_FMT_W0 | R300_W_SRC_US; + } + + if (w_fmt != r300->hw.us_out_fmt.cmd[5]) { + R300_STATECHANGE(r300, us_out_fmt); + r300->hw.us_out_fmt.cmd[5] = w_fmt; + } + + if (fgdepthsrc != r300->hw.fg_depth_src.cmd[1]) { + R300_STATECHANGE(r300, fg_depth_src); + r300->hw.fg_depth_src.cmd[1] = fgdepthsrc; + } } static void r300SetAlphaState(GLcontext * ctx) @@ -2405,27 +2426,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) r300SetEarlyZState(ctx); - /* w_fmt value is set to get best performance - * see p.130 R5xx 3D acceleration guide v1.3 */ - GLuint w_fmt, fgdepthsrc; - if (current_fragment_program_writes_depth(ctx)) { - fgdepthsrc = R300_FG_DEPTH_SRC_SHADER; - w_fmt = R300_W_FMT_W24 | R300_W_SRC_US; - } else { - fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; - w_fmt = R300_W_FMT_W0 | R300_W_SRC_US; - } - - if (w_fmt != rmesa->hw.us_out_fmt.cmd[5]) { - R300_STATECHANGE(rmesa, us_out_fmt); - rmesa->hw.us_out_fmt.cmd[5] = w_fmt; - } - - if (fgdepthsrc != rmesa->hw.fg_depth_src.cmd[1]) { - R300_STATECHANGE(rmesa, fg_depth_src); - rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; - } - r300SetupTextures(ctx); rmesa->vtbl.SetupPixelShader(ctx); -- cgit v1.2.3 From 73d2a4a04750b18463b51750651d3925d63ae074 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 14 May 2009 02:21:09 +0200 Subject: r300: cleanup vertex program related functions - move vertex program related functions to r300_vertprog.c - use _mesa_bitcount instead of self-made bit_count function - remove duplicated field in r300_vertex_shader_fragment.body union - rename r300_vertex_shader_fragment to r300_vertex_shader_hw_code - rename r300_vertex_program field native to error - remove unnecessary r300_vertex_shader_state structure - remove unused r300_vertex_program and r300_vertex_program_cont fields - remove disabled code --- src/mesa/drivers/dri/r300/r300_context.h | 49 +++----- src/mesa/drivers/dri/r300/r300_emit.c | 3 +- src/mesa/drivers/dri/r300/r300_state.c | 179 +++--------------------------- src/mesa/drivers/dri/r300/r300_state.h | 1 + src/mesa/drivers/dri/r300/r300_vertprog.c | 145 +++++++++++++++++++++--- src/mesa/drivers/dri/r300/r300_vertprog.h | 3 + 6 files changed, 164 insertions(+), 216 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 4111fa2d81a..2ea064ed452 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -399,56 +399,40 @@ struct r300_hw_state { #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0) #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1) -struct r300_vertex_shader_fragment { - int length; - union { - GLuint d[VSF_MAX_FRAGMENT_LENGTH]; - float f[VSF_MAX_FRAGMENT_LENGTH]; - GLuint i[VSF_MAX_FRAGMENT_LENGTH]; - } body; -}; - -struct r300_vertex_shader_state { - struct r300_vertex_shader_fragment program; -}; - #define COLOR_IS_RGBA #define TAG(x) r300##x #include "tnl_dd/t_dd_vertex.h" #undef TAG -#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp) - -/* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday. - * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly. - */ - -struct r300_vertex_program_key { - GLuint InputsRead; - GLuint OutputsWritten; - GLuint OutputsAdded; -}; - struct r300_vertex_program { struct r300_vertex_program *next; - struct r300_vertex_program_key key; - int translated; - struct r300_vertex_shader_fragment program; + struct r300_vertex_program_key { + GLuint InputsRead; + GLuint OutputsWritten; + GLuint OutputsAdded; + } key; + + struct r300_vertex_shader_hw_code { + int length; + union { + GLuint d[VSF_MAX_FRAGMENT_LENGTH]; + float f[VSF_MAX_FRAGMENT_LENGTH]; + } body; + } hw_code; + + GLboolean translated; + GLboolean error; int pos_end; int num_temporaries; /* Number of temp vars used by program */ int wpos_idx; int inputs[VERT_ATTRIB_MAX]; int outputs[VERT_RESULT_MAX]; - int native; - int ref_count; - int use_ref_count; }; struct r300_vertex_program_cont { struct gl_vertex_program mesa_program; /* Must be first */ - struct r300_vertex_shader_fragment params; struct r300_vertex_program *progs; }; @@ -632,7 +616,6 @@ struct r300_context { struct r300_hw_state hw; - struct r300_vertex_shader_state vertex_shader; struct r300_vertex_program *selected_vp; /* Vertex buffers diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 45e7074002e..1e79a76b47f 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -210,8 +210,7 @@ void r300EmitArrays(GLcontext * ctx) int vir_inputs[VERT_ATTRIB_MAX]; GLint tab[VERT_ATTRIB_MAX]; int swizzle[VERT_ATTRIB_MAX][4]; - struct r300_vertex_program *prog = - (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); + struct r300_vertex_program *prog = rmesa->selected_vp; if (rmesa->options.hw_tcl_enabled) { inputs = prog->inputs; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index af9e553eb59..91f9acd5bfb 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -65,6 +65,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_fragprog.h" #include "r500_fragprog.h" #include "r300_render.h" +#include "r300_vertprog.h" #include "drirenderbuffer.h" @@ -1455,8 +1456,9 @@ static void r300SetupRSUnit(GLcontext * ctx) int i, count, col_fmt, hw_tcl_on; hw_tcl_on = r300->options.hw_tcl_enabled; + if (hw_tcl_on) - OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; + OutputsWritten.vp_outputs = r300->selected_vp->key.OutputsWritten; else RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); @@ -1587,8 +1589,9 @@ static void r500SetupRSUnit(GLcontext * ctx) int i, count, col_fmt, hw_tcl_on; hw_tcl_on = r300->options.hw_tcl_enabled; + if (hw_tcl_on) - OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; + OutputsWritten.vp_outputs = r300->selected_vp->key.OutputsWritten; else RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); @@ -1717,58 +1720,9 @@ static void r500SetupRSUnit(GLcontext * ctx) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); } - - - -#define bump_vpu_count(ptr, new_count) do{\ - drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ - int _nc=(new_count)/4; \ - assert(_nc < 256); \ - if(_nc>_p->vpu.count)_p->vpu.count=_nc;\ - }while(0) - -static INLINE void r300SetupVertexProgramFragment(r300ContextPtr r300, int dest, struct r300_vertex_shader_fragment *vsf) -{ - int i; - - if (vsf->length == 0) - return; - - if (vsf->length & 0x3) { - fprintf(stderr, "VERTEX_SHADER_FRAGMENT must have length divisible by 4\n"); - _mesa_exit(-1); - } - - switch ((dest >> 8) & 0xf) { - case 0: - R300_STATECHANGE(r300, vpi); - for (i = 0; i < vsf->length; i++) - r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); - bump_vpu_count(r300->hw.vpi.cmd, vsf->length + 4 * (dest & 0xff)); - break; - - case 2: - R300_STATECHANGE(r300, vpp); - for (i = 0; i < vsf->length; i++) - r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); - bump_vpu_count(r300->hw.vpp.cmd, vsf->length + 4 * (dest & 0xff)); - break; - case 4: - R300_STATECHANGE(r300, vps); - for (i = 0; i < vsf->length; i++) - r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); - bump_vpu_count(r300->hw.vps.cmd, vsf->length + 4 * (dest & 0xff)); - break; - default: - fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest); - _mesa_exit(-1); - } -} - #define MIN3(a, b, c) ((a) < (b) ? MIN2(a, c) : MIN2(b, c)) - -static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, +void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count) { int vtx_mem_size; @@ -1822,115 +1776,6 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, } -static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa) -{ - struct r300_vertex_shader_state *prog = &(rmesa->vertex_shader); - GLuint o_reg = 0; - GLuint i_reg = 0; - int i; - int inst_count = 0; - int param_count = 0; - int program_end = 0; - - for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) { - if (rmesa->swtcl.sw_tcl_inputs[i] != -1) { - prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT); - prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - program_end += 4; - i_reg++; - } - } - - prog->program.length = program_end; - - r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, - &(prog->program)); - inst_count = (prog->program.length / 4) - 1; - - r300VapCntl(rmesa, i_reg, o_reg, 0); - - R300_STATECHANGE(rmesa, pvs); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = - (0 << R300_PVS_FIRST_INST_SHIFT) | - (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | - (inst_count << R300_PVS_LAST_INST_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = - (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = - (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); -} - -static int bit_count (int x) -{ - x = ((x & 0xaaaaaaaaU) >> 1) + (x & 0x55555555U); - x = ((x & 0xccccccccU) >> 2) + (x & 0x33333333U); - x = (x >> 16) + (x & 0xffff); - x = ((x & 0xf0f0) >> 4) + (x & 0x0f0f); - return (x >> 8) + (x & 0x00ff); -} - -static void r300SetupRealVertexProgram(r300ContextPtr rmesa) -{ - GLcontext *ctx = rmesa->radeon.glCtx; - struct r300_vertex_program *prog = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); - int inst_count = 0; - int param_count = 0; - - /* FIXME: r300SetupVertexProgramFragment */ - R300_STATECHANGE(rmesa, vpp); - param_count = - r300VertexProgUpdateParams(ctx, - (struct r300_vertex_program_cont *) - ctx->VertexProgram._Current, - (float *)&rmesa->hw.vpp. - cmd[R300_VPP_PARAM_0]); - bump_vpu_count(rmesa->hw.vpp.cmd, param_count); - param_count /= 4; - - r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, &(prog->program)); - inst_count = (prog->program.length / 4) - 1; - - r300VapCntl(rmesa, bit_count(prog->key.InputsRead), - bit_count(prog->key.OutputsWritten), prog->num_temporaries); - - R300_STATECHANGE(rmesa, pvs); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = - (0 << R300_PVS_FIRST_INST_SHIFT) | - (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | - (inst_count << R300_PVS_LAST_INST_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = - (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = - (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); -} - - -static void r300SetupVertexProgram(r300ContextPtr rmesa) -{ - GLcontext *ctx = rmesa->radeon.glCtx; - - /* Reset state, in case we don't use something */ - ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0; - - /* Not sure why this doesnt work... - 0x400 area might have something to do with pixel shaders as it appears right after pfs programming. - 0x406 is set to { 0.0, 0.0, 1.0, 0.0 } most of the time but should change with smooth points and in other rare cases. */ - //setup_vertex_shader_fragment(rmesa, 0x406, &unk4); - if (rmesa->options.hw_tcl_enabled && ((struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) { - r300SetupRealVertexProgram(rmesa); - } else { - /* FIXME: This needs to be replaced by vertex shader generation code. */ - r300SetupDefaultVertexProgram(rmesa); - } - -} - /** * Enable/Disable states. * @@ -2227,7 +2072,6 @@ static void r300ResetHwState(r300ContextPtr r300) void r300UpdateShaders(r300ContextPtr rmesa) { GLcontext *ctx; - struct r300_vertex_program *vp; struct r300_fragment_program *fp; int i; @@ -2257,8 +2101,7 @@ void r300UpdateShaders(r300ContextPtr rmesa) } r300SelectVertexShader(rmesa); - vp = (struct r300_vertex_program *) CURRENT_VERTEX_SHADER(ctx); - r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, !vp->native); + r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, rmesa->selected_vp->error); } if (!fp->translated || rmesa->radeon.NewGLState) @@ -2432,8 +2275,12 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->vtbl.SetupRSUnit(ctx); - if (rmesa->options.hw_tcl_enabled) - r300SetupVertexProgram(rmesa); + if (rmesa->options.hw_tcl_enabled) { + if (rmesa->fallback & R300_FALLBACK_VERTEX_PROGRAM) + r300SetupSwtclVertexProgram(rmesa); + else + r300SetupVertexProgram(rmesa); + } } /** diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index 3921efa8e3a..cac639d7c66 100644 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ b/src/mesa/drivers/dri/r300/r300_state.h @@ -57,5 +57,6 @@ void r300UpdateShaders (r300ContextPtr rmesa); void r300UpdateShaderStates (r300ContextPtr rmesa); void r300InitState (r300ContextPtr r300); void r300InitStateFuncs (struct dd_function_table *functions); +void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count); #endif /* __R300_STATE_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 146daa367cd..949c0b499c4 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -38,6 +38,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/tnl.h" #include "r300_context.h" +#include "r300_state.h" /* TODO: Get rid of t_src_class call */ #define CMP_SRCS(a, b) ((a.RelAddr != b.RelAddr) || (a.Index != b.Index && \ @@ -64,7 +65,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. int u_temp_used = (VSF_MAX_FRAGMENT_TEMPS - 1) - u_temp_i; \ if((vp->num_temporaries + u_temp_used) > VSF_MAX_FRAGMENT_TEMPS) { \ WARN_ONCE("Ran out of temps, num temps %d, us %d\n", vp->num_temporaries, u_temp_used); \ - vp->native = GL_FALSE; \ + vp->error = GL_TRUE; \ } \ u_temp_i=VSF_MAX_FRAGMENT_TEMPS-1; \ } while (0) @@ -1007,14 +1008,13 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp, struct prog_src_register src[3]; vp->pos_end = 0; /* Not supported yet */ - vp->program.length = 0; - /*vp->num_temporaries=mesa_vp->Base.NumTemporaries; */ + vp->hw_code.length = 0; vp->translated = GL_TRUE; - vp->native = GL_TRUE; + vp->error = GL_FALSE; t_inputs_outputs(vp); - for (inst = vp->program.body.i; vpi->Opcode != OPCODE_END; + for (inst = vp->hw_code.body.d; vpi->Opcode != OPCODE_END; vpi++, inst += 4) { FREE_TEMPS(); @@ -1176,7 +1176,7 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp, &u_temp_i); break; default: - assert(0); + vp->error = GL_TRUE; break; } } @@ -1198,16 +1198,10 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp, } } - vp->program.length = (inst - vp->program.body.i); - if (vp->program.length >= VSF_MAX_FRAGMENT_LENGTH) { - vp->program.length = 0; - vp->native = GL_FALSE; + vp->hw_code.length = (inst - vp->hw_code.body.d); + if (vp->hw_code.length >= VSF_MAX_FRAGMENT_LENGTH) { + vp->error = GL_TRUE; } -#if 0 - fprintf(stderr, "hw program:\n"); - for (i = 0; i < vp->program.length; i++) - fprintf(stderr, "%08x\n", vp->program.body.d[i]); -#endif } /* DP4 version seems to trigger some hw peculiarity */ @@ -1466,3 +1460,124 @@ void r300SelectVertexShader(r300ContextPtr r300) vpc->progs = vp; r300->selected_vp = vp; } + +#define bump_vpu_count(ptr, new_count) do { \ + drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr)); \ + int _nc=(new_count)/4; \ + assert(_nc < 256); \ + if(_nc>_p->vpu.count)_p->vpu.count=_nc; \ + } while(0) + +static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_vertex_shader_hw_code *code) +{ + int i; + + assert((code->length > 0) && (code->length % 4 == 0)); + + switch ((dest >> 8) & 0xf) { + case 0: + R300_STATECHANGE(r300, vpi); + for (i = 0; i < code->length; i++) + r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]); + bump_vpu_count(r300->hw.vpi.cmd, code->length + 4 * (dest & 0xff)); + break; + case 2: + R300_STATECHANGE(r300, vpp); + for (i = 0; i < code->length; i++) + r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]); + bump_vpu_count(r300->hw.vpp.cmd, code->length + 4 * (dest & 0xff)); + break; + case 4: + R300_STATECHANGE(r300, vps); + for (i = 0; i < code->length; i++) + r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (code->body.d[i]); + bump_vpu_count(r300->hw.vps.cmd, code->length + 4 * (dest & 0xff)); + break; + default: + fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest); + _mesa_exit(-1); + } +} + +void r300SetupSwtclVertexProgram(r300ContextPtr rmesa) +{ + struct r300_vertex_shader_hw_code *hw_code; + GLuint o_reg = 0; + GLuint i_reg = 0; + int i; + int inst_count = 0; + int param_count = 0; + int program_end = 0; + + /* Reset state, in case we don't use something */ + ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0; + ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0; + ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0; + + hw_code = _mesa_malloc(sizeof(struct r300_vertex_shader_hw_code)); + + for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) { + if (rmesa->swtcl.sw_tcl_inputs[i] != -1) { + hw_code->body.d[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT); + hw_code->body.d[program_end + 1] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_X, + PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + hw_code->body.d[program_end + 2] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, + PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + hw_code->body.d[program_end + 3] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, + PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); + program_end += 4; + i_reg++; + } + } + + hw_code->length = program_end; + + r300EmitVertexProgram(rmesa, R300_PVS_CODE_START, hw_code); + inst_count = (hw_code->length / 4) - 1; + + r300VapCntl(rmesa, i_reg, o_reg, 0); + + R300_STATECHANGE(rmesa, pvs); + rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = (0 << R300_PVS_FIRST_INST_SHIFT) | (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | + (inst_count << R300_PVS_LAST_INST_SHIFT); + + rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); + rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); + + _mesa_free(hw_code); +} + +void r300SetupVertexProgram(r300ContextPtr rmesa) +{ + GLcontext *ctx = rmesa->radeon.glCtx; + struct r300_vertex_program *prog = rmesa->selected_vp; + int inst_count = 0; + int param_count = 0; + + /* Reset state, in case we don't use something */ + ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0; + ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0; + ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0; + + R300_STATECHANGE(rmesa, vpp); + param_count = r300VertexProgUpdateParams(ctx, + (struct r300_vertex_program_cont *) + ctx->VertexProgram._Current, + (float *)&rmesa->hw.vpp. + cmd[R300_VPP_PARAM_0]); + bump_vpu_count(rmesa->hw.vpp.cmd, param_count); + param_count /= 4; + + r300EmitVertexProgram(rmesa, R300_PVS_CODE_START, &(prog->hw_code)); + inst_count = (prog->hw_code.length / 4) - 1; + + r300VapCntl(rmesa, _mesa_bitcount(prog->key.InputsRead), + _mesa_bitcount(prog->key.OutputsWritten), prog->num_temporaries); + + R300_STATECHANGE(rmesa, pvs); + rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = (0 << R300_PVS_FIRST_INST_SHIFT) | (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | + (inst_count << R300_PVS_LAST_INST_SHIFT); + + rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); + rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); +} diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.h b/src/mesa/drivers/dri/r300/r300_vertprog.h index 2f35f02bc84..44b5f981a9a 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.h +++ b/src/mesa/drivers/dri/r300/r300_vertprog.h @@ -32,4 +32,7 @@ #endif +void r300SetupVertexProgram(r300ContextPtr rmesa); +void r300SetupSwtclVertexProgram(r300ContextPtr rmesa); + #endif -- cgit v1.2.3 From d039cf4574893e480d33f286e3526c6805d919fd Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 18 May 2009 10:13:05 +0200 Subject: radeon: fix DRI1 cmd stream --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 26 ++++++++++++++++---------- src/mesa/drivers/dri/r300/r300_state.c | 9 ++------- 2 files changed, 18 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 253378767b7..60ad8ea14b3 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -312,7 +312,6 @@ static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(&r300->radeon); - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH(atom->cmd[0]); @@ -323,6 +322,19 @@ static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom) } } +static void emit_threshold_misc(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH(atom->cmd[0]); + OUT_BATCH(atom->cmd[1]); + OUT_BATCH(atom->cmd[2]); + END_BATCH(); + } +} + static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); @@ -620,15 +632,9 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9); ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1); - if (is_r500) { - ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); - } else { - ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = (2 << 30); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = (2 << 30); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = (2 << 30); - } + ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + r300->hw.rb3d_discard_src_pixel_lte_threshold.emit = emit_threshold_misc; ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); r300->hw.zs.cmd[R300_ZS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 91f9acd5bfb..efbe5cacabc 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2036,13 +2036,8 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0; - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - } else { - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = (2 << 30); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = (2 << 30); - } + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; r300->hw.zb_depthclearvalue.cmd[1] = 0; -- cgit v1.2.3 From 8308bf9ee155b405ad42e6621daf33a108330418 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 20 May 2009 13:21:24 +0200 Subject: r200: fix indexed draw color order and cs missmatch --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 3 ++- src/mesa/drivers/dri/r200/r200_state_init.c | 6 ++++-- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index e34ea9655e0..0487c3fcf59 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -137,6 +137,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) BEGIN_BATCH(8+2); OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | + R200_VF_COLOR_ORDER_RGBA | ((vertex_count + 0) << 16) | type); @@ -243,7 +244,7 @@ void r200EmitVertexAOS( r200ContextPtr rmesa, __FUNCTION__, vertex_size, offset); - BEGIN_BATCH(5); + BEGIN_BATCH(7); OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index be57ac31638..a7167790967 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -295,12 +295,16 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9 h.i = hdr; \ _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ _sz = h.veclinear.count * 4; \ + if (r200->radeon.radeonScreen->kernel_mm && _sz) { \ + BEGIN_BATCH_NO_AUTOSTATE(dwords); \ OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ OUT_BATCH(0); \ OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \ OUT_BATCH_TABLE((data), _sz); \ + END_BATCH(); \ + } \ } while(0) #define OUT_SCL(hdr, data) do { \ @@ -367,9 +371,7 @@ static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) uint32_t dwords = atom->cmd_size; dwords += 4; - BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); - END_BATCH(); } static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) -- cgit v1.2.3 From c696dd0f62c195d71cf7ecbdd04d9b156dd0da0b Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 20 May 2009 16:34:06 +0200 Subject: radeon: set max texture size This still need some work to actually report somethings reasonable if no memory manager is available. --- src/mesa/drivers/dri/r200/r200_context.c | 4 ++++ src/mesa/drivers/dri/r300/r300_context.c | 4 ++++ src/mesa/drivers/dri/radeon/radeon_context.c | 5 +++++ 3 files changed, 13 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index f80f0d8ac73..8924849d082 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -354,6 +354,10 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); + /* FIXME: When no memory manager is available we should set this + * to some reasonable value based on texture memory pool size */ + ctx->Const.MaxTextureLevels = 12; + ctx->Const.MaxTextureMaxAnisotropy = 16.0; /* No wide AA points. diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index be8d480c1cb..dbd5ce589e3 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -268,6 +268,10 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen) driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units"); ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits, ctx->Const.MaxTextureCoordUnits); + /* FIXME: When no memory manager is available we should set this + * to some reasonable value based on texture memory pool size */ + /* FIXME: r5xx limit is 4096 */ + ctx->Const.MaxTextureLevels = 12; ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 2600c78df39..8f780c443c9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -283,6 +283,11 @@ r100CreateContext( const __GLcontextModes *glVisual, i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); + /* FIXME: When no memory manager is available we should set this + * to some reasonable value based on texture memory pool size */ + /* FIXME: does r100 support 2048x2048 texture ? */ + ctx->Const.MaxTextureLevels = 12; + ctx->Const.MaxTextureMaxAnisotropy = 16.0; /* No wide points. -- cgit v1.2.3 From 01daeadf8cd8c56820585c3da88cc626dcdc33d0 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Wed, 20 May 2009 16:39:33 +0200 Subject: radeon: Increase reference count of current renderbuffers. Fixes glxinfo: main/renderbuffer.c:2159: _mesa_reference_renderbuffer: Assertion `oldRb->Magic == 0xaabbccdd' failed. --- src/mesa/drivers/dri/radeon/radeon_common.c | 4 ++-- src/mesa/drivers/dri/radeon/radeon_common.h | 4 ++-- src/mesa/drivers/dri/radeon/radeon_common_context.c | 9 +++++---- src/mesa/drivers/dri/radeon/radeon_common_context.h | 4 ++-- 4 files changed, 11 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 2f55dadcb98..76e884d705b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -752,8 +752,8 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL); } - radeon->state.depth.rrb = rrbDepth; - radeon->state.color.rrb = rrbColor; + _mesa_reference_renderbuffer(&radeon->state.depth.rb, &rrbDepth->base); + _mesa_reference_renderbuffer(&radeon->state.color.rb, &rrbColor->base); radeon->state.color.draw_offset = offset; #if 0 diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index c2fbb0950d5..b60792df0be 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -77,7 +77,7 @@ static inline struct radeon_renderbuffer *radeon_get_renderbuffer(struct gl_fram static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) { struct radeon_renderbuffer *rrb; - rrb = rmesa->state.depth.rrb; + rrb = radeon_renderbuffer(rmesa->state.depth.rb); if (!rrb) return NULL; @@ -88,7 +88,7 @@ static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPt { struct radeon_renderbuffer *rrb; - rrb = rmesa->state.color.rrb; + rrb = radeon_renderbuffer(rmesa->state.color.rb); if (!rrb) return NULL; return rrb; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 6fb6f92cb94..622bb98f3ec 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -39,6 +39,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" #include "main/context.h" #include "main/framebuffer.h" +#include "main/renderbuffer.h" #include "main/state.h" #include "main/simple_list.h" #include "swrast/swrast.h" @@ -651,10 +652,10 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, radeon_update_renderbuffers(driContextPriv, driDrawPriv); if (driDrawPriv != driReadPriv) radeon_update_renderbuffers(driContextPriv, driReadPriv); - radeon->state.color.rrb = - radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT); - radeon->state.depth.rrb = - radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH); + _mesa_reference_renderbuffer(&radeon->state.color.rb, + &(radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT)->base)); + _mesa_reference_renderbuffer(&radeon->state.depth.rb, + &(radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH)->base)); } else { radeon_make_renderbuffer_current(radeon, drfb); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 446c2f6269b..af05f4ae32e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -121,13 +121,13 @@ struct radeon_framebuffer struct radeon_colorbuffer_state { GLuint clear; int roundEnable; - struct radeon_renderbuffer *rrb; + struct gl_renderbuffer *rb; uint32_t draw_offset; /* offset into color renderbuffer - FBOs */ }; struct radeon_depthbuffer_state { GLuint clear; - struct radeon_renderbuffer *rrb; + struct gl_renderbuffer *rb; }; struct radeon_scissor_state { -- cgit v1.2.3 From a13e96359baaa0331561f86ef6487feba6540464 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 20 May 2009 22:18:31 +0200 Subject: r200: fix vbo array rendering --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 6 ++---- src/mesa/drivers/dri/radeon/radeon_dma.c | 3 +++ 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 0487c3fcf59..55ea81a57cf 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -148,12 +148,12 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) rmesa->radeon.tcl.elt_dma_bo, rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(vertex_count/2); + OUT_BATCH((vertex_count + 1)/2); } else { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); - OUT_BATCH(vertex_count/2); + OUT_BATCH((vertex_count + 1)/2); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -173,8 +173,6 @@ void r200FlushElts(GLcontext *ctx) assert( rmesa->radeon.dma.flush == r200FlushElts ); rmesa->radeon.dma.flush = NULL; - elt_used = (elt_used + 2) & ~2; - nr = elt_used / 2; radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 5ffee86e5a3..574e47ed302 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -319,6 +319,9 @@ void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) radeonContextPtr radeon = RADEON_CONTEXT( ctx ); int i; + if (radeon->dma.flush) { + radeon->dma.flush(radeon->glCtx); + } if (radeon->tcl.elt_dma_bo) { radeon_bo_unref(radeon->tcl.elt_dma_bo); radeon->tcl.elt_dma_bo = NULL; -- cgit v1.2.3 From d7cc0eb47930d6c8ebfd18fefbe48fe8eec696a0 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 21 May 2009 13:49:15 +0200 Subject: radeon: maxbuffer size is in bytes --- src/mesa/drivers/dri/radeon/radeon_dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 574e47ed302..a357afe6798 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -164,7 +164,7 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) { - size = MAX2(size, MAX_DMA_BUF_SZ * 16); + size = MAX2(size, MAX_DMA_BUF_SZ); if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) fprintf(stderr, "%s\n", __FUNCTION__); @@ -202,7 +202,7 @@ again_alloc: if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE) fprintf(stderr,"failure to revalidate BOs - badness\n"); - + radeon_bo_map(rmesa->dma.current, 1); } -- cgit v1.2.3 From 434f9200422a9e937277ca592ef14a63781dec16 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 22 May 2009 23:44:44 +0200 Subject: radeon: reading back to scratch reg through status map doesn't work For some unknown reasons the scratch reg value doesn't endup in the status map at the scratch reg offset, this is a temporary work around until we figure out why it doesn't work. --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 03a6299ed8a..6a8da402b1b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -48,6 +48,7 @@ #include "radeon_drm.h" #include "radeon_common.h" #include "radeon_bocs_wrapper.h" +#include "radeon_macros.h" /* no seriously texmem.c is this screwed up */ struct bo_legacy_texture_object { @@ -164,6 +165,7 @@ static int legacy_free_handle(struct bo_manager_legacy *bom, uint32_t handle) static void legacy_get_current_age(struct bo_manager_legacy *boml) { drm_radeon_getparam_t gp; + unsigned char *RADEONMMIO = NULL; int r; if (IS_R300_CLASS(boml->screen)) { @@ -175,8 +177,11 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml) fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); exit(1); } - } else - boml->current_age = boml->screen->scratch[3]; + } else { + RADEONMMIO = boml->screen->mmio.map; + boml->current_age = boml->screen->scratch[3]; + boml->current_age = INREG(RADEON_GUI_SCRATCH_REG3); + } } static int legacy_is_pending(struct radeon_bo *bo) -- cgit v1.2.3 From 7dd184dc4da37233471875df6f40cce0560cb7bc Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Sun, 24 May 2009 14:55:51 +0200 Subject: radeon: Remove drawable & readable from radeon_dri_mirror MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The duplication of state data caused a crash due to double-free on destruction of context, because a variable wasn't correctly null'ed out. Signed-off-by: Nicolai Hähnle --- src/mesa/drivers/dri/r200/r200_ioctl.c | 30 ++-- src/mesa/drivers/dri/r200/r200_pixel.c | 30 ++-- src/mesa/drivers/dri/r200/r200_state.c | 152 ++++++++++----------- src/mesa/drivers/dri/r200/r200_swtcl.c | 36 ++--- src/mesa/drivers/dri/r300/r300_ioctl.c | 16 +-- src/mesa/drivers/dri/r300/r300_state.c | 18 +-- src/mesa/drivers/dri/radeon/radeon_common.c | 63 +++++---- .../drivers/dri/radeon/radeon_common_context.c | 66 ++++----- .../drivers/dri/radeon/radeon_common_context.h | 27 ++-- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 54 ++++---- src/mesa/drivers/dri/radeon/radeon_lock.c | 8 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + src/mesa/drivers/dri/radeon/radeon_state.c | 128 ++++++++--------- 13 files changed, 310 insertions(+), 319 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 0262aea880e..0b3398a730e 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -31,7 +31,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Authors: * Keith Whitwell */ - + #include #include @@ -66,7 +66,7 @@ static void r200UserClear(GLcontext *ctx, GLuint mask) static void r200KernelClear(GLcontext *ctx, GLuint flags) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLint cx, cy, cw, ch, ret; GLuint i; @@ -94,7 +94,7 @@ static void r200KernelClear(GLcontext *ctx, GLuint flags) if ( rmesa->radeon.sarea->last_clear - clear <= 25 ) { break; } - + if (rmesa->radeon.do_usleeps) { UNLOCK_HARDWARE( &rmesa->radeon ); DO_USLEEP( 1 ); @@ -190,7 +190,7 @@ static void r200KernelClear(GLcontext *ctx, GLuint flags) static void r200Clear( GLcontext *ctx, GLbitfield mask ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLuint flags = 0; GLuint color_mask = 0; GLuint orig_mask = mask; @@ -202,7 +202,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) { LOCK_HARDWARE( &rmesa->radeon ); UNLOCK_HARDWARE( &rmesa->radeon ); - if ( dPriv->numClipRects == 0 ) + if ( dPriv->numClipRects == 0 ) return; } @@ -236,7 +236,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) _swrast_Clear( ctx, mask ); } - if ( !flags ) + if ( !flags ) return; if (rmesa->using_hyperz) { @@ -267,7 +267,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) * device fd. */ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, - GLfloat readfreq, GLfloat writefreq, + GLfloat readfreq, GLfloat writefreq, GLfloat priority) { GET_CURRENT_CONTEXT(ctx); @@ -277,7 +277,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, int ret; if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, + fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, writefreq, priority); if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeon.radeonScreen->gartTextures.map) @@ -294,12 +294,12 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, ret = drmCommandWriteRead( rmesa->radeon.radeonScreen->driScreen->fd, DRM_RADEON_ALLOC, &alloc, sizeof(alloc)); - + if (ret) { fprintf(stderr, "%s: DRM_RADEON_ALLOC ret %d\n", __FUNCTION__, ret); return NULL; } - + { char *region_start = (char *)rmesa->radeon.radeonScreen->gartTextures.map; return (void *)(region_start + region_offset); @@ -326,7 +326,7 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) region_offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map; - if (region_offset < 0 || + if (region_offset < 0 || region_offset > rmesa->radeon.radeonScreen->gartTextures.size) { fprintf(stderr, "offset %d outside range 0..%d\n", region_offset, rmesa->radeon.radeonScreen->gartTextures.size); @@ -335,12 +335,12 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) memfree.region = RADEON_MEM_REGION_GART; memfree.region_offset = region_offset; - + ret = drmCommandWrite( rmesa->radeon.radeonScreen->driScreen->fd, DRM_RADEON_FREE, &memfree, sizeof(memfree)); - - if (ret) + + if (ret) fprintf(stderr, "%s: DRM_RADEON_FREE ret %d\n", __FUNCTION__, ret); } @@ -374,7 +374,7 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid ); - + return valid; } diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 354daef07f6..654f2c6ae98 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -65,8 +65,8 @@ check_color( const GLcontext *ctx, GLenum type, GLenum format, return GL_FALSE; } - if ( type == GL_UNSIGNED_INT_8_8_8_8_REV && - cpp == 4 && + if ( type == GL_UNSIGNED_INT_8_8_8_8_REV && + cpp == 4 && format == GL_BGRA ) { if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: passed 2\n", __FUNCTION__); @@ -83,7 +83,7 @@ static GLboolean check_color_per_fragment_ops( const GLcontext *ctx ) { int result; - result = (!( ctx->Color.AlphaEnabled || + result = (!( ctx->Color.AlphaEnabled || ctx->Depth.Test || ctx->Fog.Enabled || ctx->Scissor.Enabled || @@ -96,7 +96,7 @@ check_color_per_fragment_ops( const GLcontext *ctx ) ctx->Texture._EnabledUnits ) && ctx->Current.RasterPosValid); - + return result; } @@ -163,7 +163,7 @@ r200TryReadPixels( GLcontext *ctx, /* Only accelerate reading to GART buffers. */ - if ( !r200IsGartMemory(rmesa, pixels, + if ( !r200IsGartMemory(rmesa, pixels, pitch * height * rmesa->radeon.radeonScreen->cpp ) ) { if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: dest not GART\n", __FUNCTION__); @@ -224,7 +224,7 @@ r200TryReadPixels( GLcontext *ctx, drm_clip_rect_t *box = dPriv->pClipRects; int i; - r200EmitWait( rmesa, RADEON_WAIT_3D ); + r200EmitWait( rmesa, RADEON_WAIT_3D ); y = dPriv->h - y - height; x += dPriv->x; @@ -241,7 +241,7 @@ r200TryReadPixels( GLcontext *ctx, GLint by = box[i].y1; GLint bw = box[i].x2 - bx; GLint bh = box[i].y2 - by; - + if (bx < x) bw -= x - bx, bx = x; if (by < y) bh -= y - by, by = y; if (bx + bw > x + width) bw = x + width - bx; @@ -277,9 +277,9 @@ r200ReadPixels( GLcontext *ctx, if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); - if (!r200TryReadPixels( ctx, x, y, width, height, format, type, pack, + if (!r200TryReadPixels( ctx, x, y, width, height, format, type, pack, pixels)) - _swrast_ReadPixels( ctx, x, y, width, height, format, type, pack, + _swrast_ReadPixels( ctx, x, y, width, height, format, type, pack, pixels); } @@ -293,7 +293,7 @@ static void do_draw_pix( GLcontext *ctx, GLuint planemask) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); drm_clip_rect_t *box = dPriv->pClipRects; struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorDrawBuffers[0]; driRenderbuffer *drb = (driRenderbuffer *) rb; @@ -325,7 +325,7 @@ static void do_draw_pix( GLcontext *ctx, rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); y -= height; /* cope with pixel zoom */ - + if (!clip_pixelrect(ctx, ctx->DrawBuffer, &x, &y, &width, &height, &size)) { @@ -409,7 +409,7 @@ r200TryDrawPixels( GLcontext *ctx, if (planemask != ~0) return GL_FALSE; /* fix me -- should be possible */ - /* Can't do conversions on GART reads/draws. + /* Can't do conversions on GART reads/draws. */ if ( !r200IsGartMemory( rmesa, pixels, size ) ) { if (R200_DEBUG & DEBUG_PIXEL) @@ -484,9 +484,9 @@ r200Bitmap( GLcontext *ctx, GLint px, GLint py, void r200InitPixelFuncs( GLcontext *ctx ) { if (!getenv("R200_NO_BLITS")) { - ctx->Driver.ReadPixels = r200ReadPixels; - ctx->Driver.DrawPixels = r200DrawPixels; - if (getenv("R200_HW_BITMAP")) + ctx->Driver.ReadPixels = r200ReadPixels; + ctx->Driver.DrawPixels = r200DrawPixels; + if (getenv("R200_HW_BITMAP")) ctx->Driver.Bitmap = r200Bitmap; } } diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 6802e190a76..f8ebe0df57e 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -79,7 +79,7 @@ static void r200AlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref ) switch ( func ) { case GL_NEVER: - pp_misc |= R200_ALPHA_TEST_FAIL; + pp_misc |= R200_ALPHA_TEST_FAIL; break; case GL_LESS: pp_misc |= R200_ALPHA_TEST_LESS; @@ -479,7 +479,7 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) } } break; - case GL_FOG_COLOR: + case GL_FOG_COLOR: R200_STATECHANGE( rmesa, ctx ); UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color ); i = radeonPackColor( 4, col[0], col[1], col[2], 0 ); @@ -507,7 +507,7 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) if (out_0 != rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0]) { R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = out_0; + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = out_0; } break; @@ -696,7 +696,7 @@ static void r200LineStipple( GLcontext *ctx, GLint factor, GLushort pattern ) r200ContextPtr rmesa = R200_CONTEXT(ctx); R200_STATECHANGE( rmesa, lin ); - rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = + rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern)); } @@ -720,10 +720,10 @@ static void r200ColorMask( GLcontext *ctx, if (!(r && g && b && a)) flag |= R200_PLANE_MASK_ENABLE; - if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) { - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag; - } + if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) { + R200_STATECHANGE( rmesa, ctx ); + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag; + } if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) { R200_STATECHANGE( rmesa, msk ); @@ -774,7 +774,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* FIXME: Use window x,y offsets into stipple RAM. */ stipple.mask = rmesa->state.stipple.mask; - drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, + drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, &stipple, sizeof(stipple) ); UNLOCK_HARDWARE( &rmesa->radeon ); } @@ -785,7 +785,7 @@ static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0; /* Can't generally do unfilled via tcl, but some good special - * cases work. + * cases work. */ TCL_FALLBACK( ctx, R200_TCL_FALLBACK_UNFILLED, flag); if (rmesa->radeon.TclFallback) { @@ -827,34 +827,34 @@ static void r200UpdateSpecular( GLcontext *ctx ) if (ctx->Light.Enabled && ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT) | - (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); + (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0; rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1; rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE; p |= R200_SPECULAR_ENABLE; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= + rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_DIFFUSE_SPECULAR_COMBINE; } else if (ctx->Light.Enabled) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= + ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0; rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE; } else if (ctx->Fog.ColorSumEnabled ) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT) | - (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); + (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); p |= R200_SPECULAR_ENABLE; } else { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= + ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)); } if (ctx->Fog.Enabled) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= + ((R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1; } @@ -865,7 +865,7 @@ static void r200UpdateSpecular( GLcontext *ctx ) /* Update vertex/render formats */ - if (rmesa->radeon.TclFallback) { + if (rmesa->radeon.TclFallback) { r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } @@ -877,7 +877,7 @@ static void r200UpdateSpecular( GLcontext *ctx ) */ -/* Update on colormaterial, material emmissive/ambient, +/* Update on colormaterial, material emmissive/ambient, * lightmodel.globalambient */ static void update_global_ambient( GLcontext *ctx ) @@ -891,23 +891,23 @@ static void update_global_ambient( GLcontext *ctx ) */ if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] & ((3 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | - (3 << R200_FRONT_AMBIENT_SOURCE_SHIFT))) == 0) + (3 << R200_FRONT_AMBIENT_SOURCE_SHIFT))) == 0) { - COPY_3V( &fcmd[GLT_RED], + COPY_3V( &fcmd[GLT_RED], ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]); ACC_SCALE_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient, ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]); - } + } else { COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient ); } - + R200_DB_STATECHANGE(rmesa, &rmesa->hw.glt); } -/* Update on change to +/* Update on change to * - light[p].colors * - light[p].enabled */ @@ -921,10 +921,10 @@ static void update_light_colors( GLcontext *ctx, GLuint p ) r200ContextPtr rmesa = R200_CONTEXT(ctx); float *fcmd = (float *)R200_DB_STATE( lit[p] ); - COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient ); + COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient ); COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse ); COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular ); - + R200_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] ); } } @@ -944,7 +944,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) if (ctx->Light.ColorMaterialEnabled) { GLuint mask = ctx->Light.ColorMaterialBitmask; - + if (mask & MAT_BIT_FRONT_EMISSION) { light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT); @@ -960,7 +960,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) else light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT); - + if (mask & MAT_BIT_FRONT_DIFFUSE) { light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT); @@ -968,7 +968,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) else light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT); - + if (mask & MAT_BIT_FRONT_SPECULAR) { light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT); @@ -977,7 +977,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT); } - + if (mask & MAT_BIT_BACK_EMISSION) { light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << R200_BACK_EMISSIVE_SOURCE_SHIFT); @@ -1027,8 +1027,8 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) R200_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = light_model_ctl1; } - - + + } void r200UpdateMaterial( GLcontext *ctx ) @@ -1038,7 +1038,7 @@ void r200UpdateMaterial( GLcontext *ctx ) GLfloat *fcmd = (GLfloat *)R200_DB_STATE( mtl[0] ); GLfloat *fcmd2 = (GLfloat *)R200_DB_STATE( mtl[1] ); GLuint mask = ~0; - + /* Might be possible and faster to update everything unconditionally? */ if (ctx->Light.ColorMaterialEnabled) mask &= ~ctx->Light.ColorMaterialBitmask; @@ -1124,7 +1124,7 @@ void r200UpdateMaterial( GLcontext *ctx ) * * which are calculated in light.c and are correct for the current * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW - * and _MESA_NEW_NEED_EYE_COORDS. + * and _MESA_NEW_NEED_EYE_COORDS. */ static void update_light( GLcontext *ctx ) { @@ -1141,8 +1141,8 @@ static void update_light( GLcontext *ctx ) tmp &= ~R200_LIGHT_IN_MODELSPACE; else tmp |= R200_LIGHT_IN_MODELSPACE; - - if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]) + + if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]) { R200_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = tmp; @@ -1166,10 +1166,10 @@ static void update_light( GLcontext *ctx ) if (ctx->Light.Light[p].Enabled) { struct gl_light *l = &ctx->Light.Light[p]; GLfloat *fcmd = (GLfloat *)R200_DB_STATE( lit[p] ); - + if (l->EyePosition[3] == 0.0) { - COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); - COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); + COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); + COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); fcmd[LIT_POSITION_W] = 0; fcmd[LIT_DIRECTION_W] = 0; } else { @@ -1193,21 +1193,21 @@ static void r200Lightfv( GLcontext *ctx, GLenum light, GLint p = light - GL_LIGHT0; struct gl_light *l = &ctx->Light.Light[p]; GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd; - + switch (pname) { - case GL_AMBIENT: + case GL_AMBIENT: case GL_DIFFUSE: case GL_SPECULAR: update_light_colors( ctx, p ); break; - case GL_SPOT_DIRECTION: - /* picked up in update_light */ + case GL_SPOT_DIRECTION: + /* picked up in update_light */ break; case GL_POSITION: { - /* positions picked up in update_light, but can do flag here */ + /* positions picked up in update_light, but can do flag here */ GLuint flag = (p&1)? R200_LIGHT_1_IS_LOCAL : R200_LIGHT_0_IS_LOCAL; GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2; @@ -1323,7 +1323,7 @@ static void r200LightModelfv( GLcontext *ctx, GLenum pname, r200ContextPtr rmesa = R200_CONTEXT(ctx); switch (pname) { - case GL_LIGHT_MODEL_AMBIENT: + case GL_LIGHT_MODEL_AMBIENT: update_global_ambient( ctx ); break; @@ -1582,7 +1582,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - rmesa->radeon.state.stencil.clear = + rmesa->radeon.state.stencil.clear = ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << R200_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT)); @@ -1607,7 +1607,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1663,7 +1663,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, void r200UpdateViewportOffset( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1693,8 +1693,8 @@ void r200UpdateViewportOffset( GLcontext *ctx ) R200_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ - stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & R200_STIPPLE_COORD_MASK); - sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1) + stx = 31 - ((dPriv->x - 1) & R200_STIPPLE_COORD_MASK); + sty = 31 - ((dPriv->y + dPriv->h - 1) & R200_STIPPLE_COORD_MASK); m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) | @@ -1808,7 +1808,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_CLIP_PLANE2: case GL_CLIP_PLANE3: case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: + case GL_CLIP_PLANE5: p = cap-GL_CLIP_PLANE0; R200_STATECHANGE( rmesa, tcl ); if (state) { @@ -1860,7 +1860,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; } r200UpdateSpecular( ctx ); /* for PK_SPEC */ - if (rmesa->radeon.TclFallback) + if (rmesa->radeon.TclFallback) r200ChooseVertexState( ctx ); _mesa_allow_light_in_model( ctx, !state ); break; @@ -1875,13 +1875,13 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_LIGHT7: R200_STATECHANGE(rmesa, tcl); p = cap - GL_LIGHT0; - if (p&1) + if (p&1) flag = (R200_LIGHT_1_ENABLE | - R200_LIGHT_1_ENABLE_AMBIENT | + R200_LIGHT_1_ENABLE_AMBIENT | R200_LIGHT_1_ENABLE_SPECULAR); else flag = (R200_LIGHT_0_ENABLE | - R200_LIGHT_0_ENABLE_AMBIENT | + R200_LIGHT_0_ENABLE_AMBIENT | R200_LIGHT_0_ENABLE_SPECULAR); if (state) @@ -1889,7 +1889,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) else rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag; - /* + /* */ update_light_colors( ctx, p ); break; @@ -2043,7 +2043,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_TEXTURE_GEN_T: /* Picked up in r200UpdateTextureState. */ - rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; + rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; break; case GL_COLOR_SUM_EXT: @@ -2160,7 +2160,7 @@ void r200LightingSpaceChange( GLcontext *ctx ) r200ContextPtr rmesa = R200_CONTEXT(ctx); GLboolean tmp; - if (R200_DEBUG & DEBUG_STATE) + if (R200_DEBUG & DEBUG_STATE) fprintf(stderr, "%s %d BEFORE %x\n", __FUNCTION__, ctx->_NeedEyeCoords, rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]); @@ -2176,7 +2176,7 @@ void r200LightingSpaceChange( GLcontext *ctx ) rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_RESCALE_NORMALS; } - if (R200_DEBUG & DEBUG_STATE) + if (R200_DEBUG & DEBUG_STATE) fprintf(stderr, "%s %d AFTER %x\n", __FUNCTION__, ctx->_NeedEyeCoords, rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]); } @@ -2219,7 +2219,7 @@ static void update_texturematrix( GLcontext *ctx ) GLuint compsel = rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]; int unit; - if (R200_DEBUG & DEBUG_STATE) + if (R200_DEBUG & DEBUG_STATE) fprintf(stderr, "%s before COMPSEL: %x\n", __FUNCTION__, rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]); @@ -2227,7 +2227,7 @@ static void update_texturematrix( GLcontext *ctx ) rmesa->TexMatCompSel = 0; for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { - if (!ctx->Texture.Unit[unit]._ReallyEnabled) + if (!ctx->Texture.Unit[unit]._ReallyEnabled) continue; if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) { @@ -2237,21 +2237,21 @@ static void update_texturematrix( GLcontext *ctx ) rmesa->TexMatCompSel |= R200_OUTPUT_TEX_0 << unit; if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) { - /* Need to preconcatenate any active texgen + /* Need to preconcatenate any active texgen * obj/eyeplane matrices: */ _math_matrix_mul_matrix( &rmesa->tmpmat, - ctx->TextureMatrixStack[unit].Top, + ctx->TextureMatrixStack[unit].Top, &rmesa->TexGenMatrix[unit] ); upload_matrix( rmesa, rmesa->tmpmat.m, R200_MTX_TEX0+unit ); - } + } else { - upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m, + upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m, R200_MTX_TEX0+unit ); } } else if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) { - upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m, + upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m, R200_MTX_TEX0+unit ); } } @@ -2277,7 +2277,7 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx) int i; radeon_validate_reset_bos(&rmesa->radeon); - + rrb = radeon_get_colorbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { @@ -2295,7 +2295,7 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx) for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { radeonTexObj *t; - + if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; @@ -2323,7 +2323,7 @@ GLboolean r200ValidateState( GLcontext *ctx ) _mesa_update_framebuffer(ctx); /* this updates the DrawBuffer's Width/Height if it's a FBO */ _mesa_update_draw_buffer_bounds(ctx); - + R200_STATECHANGE(rmesa, ctx); } @@ -2341,7 +2341,7 @@ GLboolean r200ValidateState( GLcontext *ctx ) /* Need an event driven matrix update? */ - if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) + if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, R200_MTX_MVP ); /* Need these for lighting (shouldn't upload otherwise) @@ -2365,7 +2365,7 @@ GLboolean r200ValidateState( GLcontext *ctx ) /* emit all active clip planes if projection matrix changes. */ if (new_state & (_NEW_PROJECTION)) { - if (ctx->Transform.ClipPlanesEnabled) + if (ctx->Transform.ClipPlanesEnabled) r200UpdateClipPlanes( ctx ); } @@ -2437,7 +2437,7 @@ static void r200WrapRunPipeline( GLcontext *ctx ) } /* Run the pipeline. - */ + */ _tnl_run_pipeline( ctx ); if (has_material) { diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 712da980775..83e70b586d7 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -56,7 +56,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /*********************************************************************** - * Initialization + * Initialization ***********************************************************************/ #define EMIT_ATTR( ATTR, STYLE, F0 ) \ @@ -118,7 +118,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) } rmesa->swtcl.coloroffset = offset; -#if MESA_LITTLE_ENDIAN +#if MESA_LITTLE_ENDIAN EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT) ); #else EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT) ); @@ -129,7 +129,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) || RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) { -#if MESA_LITTLE_ENDIAN +#if MESA_LITTLE_ENDIAN if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) { rmesa->swtcl.specoffset = offset; EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, (R200_VTX_PK_RGBA << R200_VTX_COLOR_1_SHIFT) ); @@ -192,7 +192,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attrs, rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); rmesa->radeon.swtcl.vertex_size /= 4; @@ -278,7 +278,7 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset) rmesa->radeon.dma.current, current_offset); - + r200EmitVbufPrim( rmesa, rmesa->radeon.swtcl.hw_primitive, rmesa->radeon.swtcl.numverts); @@ -338,7 +338,7 @@ static void r200ResetLineStipple( GLcontext *ctx ); r200ContextPtr rmesa = R200_CONTEXT(ctx); \ const char *r200verts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int))) -#define VERTEX radeonVertex +#define VERTEX radeonVertex #define DO_DEBUG_VERTS (1 && (R200_DEBUG & DEBUG_VERTS)) #undef TAG @@ -539,7 +539,7 @@ void r200ChooseRenderState( GLcontext *ctx ) GLuint index = 0; GLuint flags = ctx->_TriangleCaps; - if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) + if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) return; if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R200_TWOSIDE_BIT; @@ -597,7 +597,7 @@ static void r200RenderPrimitive( GLcontext *ctx, GLenum prim ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); rmesa->radeon.swtcl.render_primitive = prim; - if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) + if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) r200RasterPrimitive( ctx, reduced_hw_prim(ctx, prim) ); } @@ -695,7 +695,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) /** * Cope with depth operations by drawing individual pixels as points. - * + * * \todo * The way the vertex state is set in this routine is hokey. It seems to * work, but it's very hackish. This whole routine is pretty hackish. If @@ -710,14 +710,14 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, const GLubyte *bitmap ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - const GLfloat *rc = ctx->Current.RasterColor; + const GLfloat *rc = ctx->Current.RasterColor; GLint row, col; radeonVertex vert; GLuint orig_vte; GLuint h; - /* Turn off tcl. + /* Turn off tcl. */ TCL_FALLBACK( ctx, R200_TCL_FALLBACK_BITMAP, 1 ); @@ -768,7 +768,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, R200_VPORT_Z_SCALE_ENA | R200_VPORT_X_OFFSET_ENA | R200_VPORT_Y_OFFSET_ENA | - R200_VPORT_Z_OFFSET_ENA); + R200_VPORT_Z_OFFSET_ENA); /* Turn off other stuff: Stipple?, texture?, blending?, etc. */ @@ -813,14 +813,14 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, */ LOCK_HARDWARE( &rmesa->radeon ); UNLOCK_HARDWARE( &rmesa->radeon ); - h = rmesa->radeon.dri.drawable->h + rmesa->radeon.dri.drawable->y; - px += rmesa->radeon.dri.drawable->x; + h = radeon_get_drawable(&rmesa->radeon)->h + radeon_get_drawable(&rmesa->radeon)->y; + px += radeon_get_drawable(&rmesa->radeon)->x; /* Clipping handled by existing mechansims in r200_ioctl.c? */ for (row=0; rowLsbFirst) { @@ -899,9 +899,9 @@ void r200InitSwtcl( GLcontext *ctx ) tnl->Driver.Render.Interp = _tnl_interp; /* FIXME: what are these numbers? */ - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, + _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 36 * sizeof(GLfloat) ); - + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 6766eb3eaee..104079b4dbe 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -79,7 +79,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, { BATCH_LOCALS(&r300->radeon); GLcontext *ctx = r300->radeon.glCtx; - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon); GLuint cbpitch = 0; r300ContextPtr rmesa = r300; @@ -200,7 +200,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]); OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); } - + r300EmitCacheFlush(rmesa); cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); @@ -213,7 +213,7 @@ static void r300EmitClearState(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(&r300->radeon); - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon); int i; int has_tcl; int is_r500 = 0; @@ -447,7 +447,7 @@ static void r300EmitClearState(GLcontext * ctx) R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | R500_ALU_RGBA_A_SWIZ_0; - + r500fp.cmd[7] = 0; emit_r500fp(ctx, &r500fp); } @@ -541,9 +541,9 @@ static void r300EmitClearState(GLcontext * ctx) } static void r300KernelClear(GLcontext *ctx, GLuint flags) -{ +{ r300ContextPtr r300 = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon); struct radeon_framebuffer *rfb = dPriv->driverPrivate; struct radeon_renderbuffer *rrb; struct radeon_renderbuffer *rrbd; @@ -565,7 +565,7 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags) r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); bits = 0; } - + if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT); r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); @@ -590,7 +590,7 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags) static void r300Clear(GLcontext * ctx, GLbitfield mask) { r300ContextPtr r300 = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon); const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask); GLbitfield swrast_mask = 0, tri_mask = 0; int i; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index efbe5cacabc..582e8c27e31 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -967,7 +967,7 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, static void r300UpdateWindow(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1020,7 +1020,7 @@ static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) void r300UpdateViewportOffset(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = ((radeonContextPtr) rmesa)->dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = (GLfloat) dPriv->x; GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1052,12 +1052,14 @@ r300FetchStateParameter(GLcontext * ctx, switch (state[0]) { case STATE_INTERNAL: switch (state[1]) { - case STATE_R300_WINDOW_DIMENSION: - value[0] = r300->radeon.dri.drawable->w * 0.5f; /* width*0.5 */ - value[1] = r300->radeon.dri.drawable->h * 0.5f; /* height*0.5 */ - value[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */ - value[3] = 1.0F; /* not used */ - break; + case STATE_R300_WINDOW_DIMENSION: { + __DRIdrawablePrivate * drawable = radeon_get_drawable(&r300->radeon); + value[0] = drawable->w * 0.5f; /* width*0.5 */ + value[1] = drawable->h * 0.5f; /* height*0.5 */ + value[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */ + value[3] = 1.0F; /* not used */ + break; + } case STATE_R300_TEXRECT_FACTOR:{ struct gl_texture_object *t = diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 76e884d705b..e2e0ba07a3b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -153,7 +153,7 @@ void radeon_get_cliprects(radeonContextPtr radeon, unsigned int *num_cliprects, int *x_off, int *y_off) { - __DRIdrawablePrivate *dPriv = radeon->dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(radeon); struct radeon_framebuffer *rfb = dPriv->driverPrivate; if (radeon->constant_cliprect) { @@ -185,15 +185,15 @@ void radeon_get_cliprects(radeonContextPtr radeon, */ void radeonSetCliprects(radeonContextPtr radeon) { - __DRIdrawablePrivate *const drawable = radeon->dri.drawable; - __DRIdrawablePrivate *const readable = radeon->dri.readable; + __DRIdrawablePrivate *const drawable = radeon_get_drawable(radeon); + __DRIdrawablePrivate *const readable = radeon_get_readable(radeon); struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate; struct radeon_framebuffer *const read_rfb = readable->driverPrivate; int x_off, y_off; radeon_get_cliprects(radeon, &radeon->pClipRects, &radeon->numClipRects, &x_off, &y_off); - + if ((draw_rfb->base.Width != drawable->w) || (draw_rfb->base.Height != drawable->h)) { _mesa_resize_framebuffer(radeon->glCtx, &draw_rfb->base, @@ -221,9 +221,9 @@ void radeonUpdateScissor( GLcontext *ctx ) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - if ( rmesa->dri.drawable ) { - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; - + if ( radeon_get_drawable(rmesa) ) { + __DRIdrawablePrivate *dPriv = radeon_get_drawable(rmesa); + int x = ctx->Scissor.X; int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height; int w = ctx->Scissor.X + ctx->Scissor.Width - 1; @@ -425,11 +425,11 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, radeonContextPtr rmesa; struct radeon_framebuffer *rfb; GLint nbox, i, ret; - + assert(dPriv); assert(dPriv->driContextPriv); assert(dPriv->driContextPriv->driverPrivate); - + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; LOCK_HARDWARE(rmesa); @@ -506,7 +506,7 @@ static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_tar UNLOCK_HARDWARE(rmesa); driWaitForVBlank(dPriv, missed_target); - + return 0; } @@ -540,7 +540,7 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) radeon->sarea->nbox = 1; ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP ); - + UNLOCK_HARDWARE(radeon); if ( ret ) { @@ -638,7 +638,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL, *rrbColor = NULL; uint32_t offset = 0; - + if (!fb) { /* this can happen during the initial context initialization */ @@ -650,7 +650,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); return; } - + /* Do this here, note core Mesa, since this function is called from * many places within the driver. */ @@ -737,7 +737,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); else ctx->NewState |= _NEW_POLYGON; - + /* * Update depth test state */ @@ -751,7 +751,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) } else { ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL); } - + _mesa_reference_renderbuffer(&radeon->state.depth.rb, &rrbDepth->base); _mesa_reference_renderbuffer(&radeon->state.color.rb, &rrbColor->base); radeon->state.color.draw_offset = offset; @@ -762,7 +762,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, ctx->Viewport.Width, ctx->Viewport.Height); } else { - + } #endif ctx->NewState |= _NEW_VIEWPORT; @@ -814,7 +814,7 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) radeon->dri.context->driDrawablePriv); } } - + radeon_draw_buffer(ctx, ctx->DrawBuffer); } @@ -836,7 +836,7 @@ void radeonReadBuffer( GLcontext *ctx, GLenum mode ) */ void radeonUpdatePageFlipping(radeonContextPtr radeon) { - struct radeon_framebuffer *rfb = radeon->dri.drawable->driverPrivate; + struct radeon_framebuffer *rfb = radeon_get_drawable(radeon)->driverPrivate; rfb->pf_active = radeon->sarea->pfState; rfb->pf_current_page = radeon->sarea->pfCurrentPage; @@ -869,7 +869,6 @@ void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei he old_viewport = ctx->Driver.Viewport; ctx->Driver.Viewport = NULL; - radeon->dri.drawable = driContext->driDrawablePriv; radeon_window_moved(radeon); radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer); ctx->Driver.Viewport = old_viewport; @@ -962,7 +961,7 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) } } } - + COMMIT_BATCH(); } @@ -1032,7 +1031,7 @@ void radeonEmitState(radeonContextPtr radeon) if (!radeon->cmdbuf.cs->cdw) { if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "Begin reemit state\n"); - + radeonEmitAtoms(radeon, GL_FALSE); } @@ -1064,7 +1063,7 @@ void radeonFlush(GLcontext *ctx) radeon->dma.flush( ctx ); radeonEmitState(radeon); - + if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); @@ -1073,8 +1072,8 @@ void radeonFlush(GLcontext *ctx) if (screen->dri2.loader && (screen->dri2.loader->base.version >= 2) && (screen->dri2.loader->flushFrontBuffer != NULL)) { - (*screen->dri2.loader->flushFrontBuffer)(radeon->dri.drawable, - radeon->dri.drawable->loaderPrivate); + __DRIdrawablePrivate * drawable = radeon_get_drawable(radeon); + (*screen->dri2.loader->flushFrontBuffer)(drawable, drawable->loaderPrivate); /* Only clear the dirty bit if front-buffer rendering is no longer * enabled. This is done so that the dirty bit can only be set in @@ -1161,7 +1160,7 @@ int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller) int ret; radeonReleaseDmaRegion(rmesa); - + LOCK_HARDWARE(rmesa); ret = rcommonFlushCmdBufLocked(rmesa, caller); UNLOCK_HARDWARE(rmesa); @@ -1223,7 +1222,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa) rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); assert(rmesa->cmdbuf.cs != NULL); rmesa->cmdbuf.size = size; - + if (!rmesa->radeonScreen->kernel_mm) { radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); @@ -1334,7 +1333,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) unsigned int saved_active_texture; assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH | - BUFFER_BIT_STENCIL)) == 0); + BUFFER_BIT_STENCIL)) == 0); _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | GL_CURRENT_BIT | @@ -1346,7 +1345,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) GL_CURRENT_BIT); _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); saved_active_texture = ctx->Texture.CurrentUnit; - + /* Disable existing GL state we don't want to apply to a clear. */ _mesa_Disable(GL_ALPHA_TEST); _mesa_Disable(GL_BLEND); @@ -1375,10 +1374,10 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) saved_shader_program = ctx->Shader.CurrentProgram->Name; _mesa_UseProgramObjectARB(0); } - + if (ctx->Texture._EnabledUnits != 0) { int i; - + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { _mesa_ActiveTextureARB(GL_TEXTURE0 + i); _mesa_Disable(GL_TEXTURE_1D); @@ -1394,14 +1393,14 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) } } } - + #if FEATURE_ARB_vertex_buffer_object _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0); _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0); #endif radeon_meta_set_passthrough_transform(rmesa); - + for (i = 0; i < 4; i++) { color[i][0] = ctx->Color.ClearColor[0]; color[i][1] = ctx->Color.ClearColor[1]; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 622bb98f3ec..e9967986a3f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -147,8 +147,6 @@ GLboolean radeonInitContext(radeonContextPtr radeon, /* DRI fields */ radeon->dri.context = driContextPriv; radeon->dri.screen = sPriv; - radeon->dri.drawable = NULL; - radeon->dri.readable = NULL; radeon->dri.hwContext = driContextPriv->hHWContext; radeon->dri.hwLock = &sPriv->pSAREA->lock; radeon->dri.fd = sPriv->fd; @@ -171,7 +169,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon, "IRQ's not enabled, falling back to %s: %d %d\n", radeon->do_usleeps ? "usleeps" : "busy waits", fthrottle_mode, radeon->radeonScreen->irq); - + radeon->texture_depth = driQueryOptioni (&radeon->optionCache, "texture_depth"); if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) @@ -217,7 +215,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) radeon_firevertices(radeon); _mesa_make_current(NULL, NULL, NULL); } - + assert(radeon); if (radeon) { @@ -233,14 +231,11 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) _tnl_DestroyContext( radeon->glCtx ); _vbo_DestroyContext( radeon->glCtx ); _swrast_DestroyContext( radeon->glCtx ); - - radeonDestroyBuffer(radeon->dri.drawable); - radeonDestroyBuffer(radeon->dri.readable); /* free atom list */ /* free the Mesa context */ _mesa_destroy_context(radeon->glCtx); - + /* _mesa_destroy_context() might result in calls to functions that * depend on the DriverCtx, so don't set it to NULL before. * @@ -248,7 +243,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) */ /* free the option cache */ driDestroyOptionCache(&radeon->optionCache); - + rcommonDestroyCmdBuf(radeon); radeon_destroy_atom_list(radeon); @@ -346,12 +341,12 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, int size = 4096*4096*4; /* if radeon->fake */ struct radeon_renderbuffer *rb; - + if (radeon->radeonScreen->kernel_mm) { radeon_make_kernel_renderbuffer_current(radeon, draw); return; } - + if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { if (!rb->bo) { @@ -440,7 +435,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); - + draw = drawable->driverPrivate; screen = context->driScreenPriv; radeon = (radeonContextPtr) context->driverPrivate; @@ -493,7 +488,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) attachments[i++] = __DRI_BUFFER_DEPTH; if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL)) attachments[i++] = __DRI_BUFFER_STENCIL; - + buffers = (*screen->dri2.loader->getBuffers)(drawable, &drawable->w, &drawable->h, @@ -591,7 +586,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) fprintf(stderr, "failed to attach %s %d\n", regname, buffers[i].name); - + } } @@ -648,7 +643,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, drfb = driDrawPriv->driverPrivate; readfb = driReadPriv->driverPrivate; - if (driContextPriv->driScreenPriv->dri2.enabled) { + if (driContextPriv->driScreenPriv->dri2.enabled) { radeon_update_renderbuffers(driContextPriv, driDrawPriv); if (driDrawPriv != driReadPriv) radeon_update_renderbuffers(driContextPriv, driReadPriv); @@ -664,9 +659,6 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, if (RADEON_DEBUG & DEBUG_DRI) fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb); - if (radeon->dri.readable != driReadPriv) - radeon->dri.readable = driReadPriv; - driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); if (driReadPriv != driDrawPriv) driUpdateFramebufferSize(radeon->glCtx, driReadPriv); @@ -676,29 +668,25 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, _mesa_update_state(radeon->glCtx); if (radeon->glCtx->DrawBuffer == &drfb->base) { - - if (radeon->dri.drawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - int i; - driDrawPriv->vblFlags = - (radeon->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&radeon-> - optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank(driDrawPriv); - drfb->vbl_waited = driDrawPriv->vblSeq; - - for (i = 0; i < 2; i++) { - if (drfb->color_rb[i]) - drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq; - } - + if (driDrawPriv->swap_interval == (unsigned)-1) { + int i; + driDrawPriv->vblFlags = + (radeon->radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; + + driDrawableInitVBlank(driDrawPriv); + drfb->vbl_waited = driDrawPriv->vblSeq; + + for (i = 0; i < 2; i++) { + if (drfb->color_rb[i]) + drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq; } - radeon->dri.drawable = driDrawPriv; - - radeon_window_moved(radeon); + } + + radeon_window_moved(radeon); radeon_draw_buffer(radeon->glCtx, &drfb->base); } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index af05f4ae32e..e995062657f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -117,7 +117,7 @@ struct radeon_framebuffer }; - + struct radeon_colorbuffer_state { GLuint clear; int roundEnable; @@ -346,16 +346,6 @@ struct radeon_dri_mirror { __DRIcontextPrivate *context; /* DRI context */ __DRIscreenPrivate *screen; /* DRI screen */ - /** - * DRI drawable bound to this context for drawing. - */ - __DRIdrawablePrivate *drawable; - - /** - * DRI drawable bound to this context for reading. - */ - __DRIdrawablePrivate *readable; - drm_context_t hwContext; drm_hw_lock_t *hwLock; int fd; @@ -416,7 +406,7 @@ struct radeon_cmdbuf { struct radeon_context { GLcontext *glCtx; radeonScreenPtr radeonScreen; /* Screen private DRI data */ - + /* Texture object bookkeeping */ int texture_depth; @@ -458,7 +448,7 @@ struct radeon_context { driOptionCache optionCache; struct radeon_cmdbuf cmdbuf; - + drm_clip_rect_t fboRect; GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ GLboolean front_cliprects; @@ -507,6 +497,17 @@ struct radeon_context { #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) +static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon) +{ + return radeon->dri.context->driDrawablePriv; +} + +static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon) +{ + return radeon->dri.context->driReadablePriv; +} + + /** * This function takes a float and packs it into a uint32_t */ diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index b5fde6d3de5..caa0c4a896d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -35,7 +35,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include -#include +#include #include "main/attrib.h" #include "main/enable.h" @@ -114,7 +114,7 @@ void radeonSetUpAtomList( r100ContextPtr rmesa ) } /* Fire a section of the retained (indexed_verts) buffer as a regular - * primtive. + * primtive. */ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, GLuint vertex_format, @@ -124,7 +124,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - + radeonEmitState(&rmesa->radeon); #if RADEON_OLD_PACKETS @@ -135,7 +135,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, } else { OUT_BATCH(rmesa->ioctl.vertex_offset); } - + OUT_BATCH(vertex_nr); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | @@ -149,10 +149,10 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, RADEON_GEM_DOMAIN_GTT, 0, 0); } - + END_BATCH(); - -#else + +#else BEGIN_BATCH(4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 1); OUT_BATCH(vertex_format); @@ -173,7 +173,7 @@ void radeonFlushElts( GLcontext *ctx ) int nr; uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start); int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw); - + if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -230,9 +230,9 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - + radeonEmitState(&rmesa->radeon); - + rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; /* round up min_nr to align the state */ @@ -248,7 +248,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, } OUT_BATCH(0xffff); OUT_BATCH(vertex_format); - OUT_BATCH(primitive | + OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_IND | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); @@ -257,7 +257,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); OUT_BATCH(vertex_format); - OUT_BATCH(primitive | + OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_IND | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_MAOS_ENABLE | @@ -269,7 +269,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, rmesa->tcl.elt_used = min_nr; retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); - + if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s: header prim %x \n", __FUNCTION__, primitive); @@ -305,7 +305,7 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa, #endif } - + void radeonEmitAOS( r100ContextPtr rmesa, GLuint nr, @@ -314,7 +314,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, #if RADEON_OLD_PACKETS assert( nr == 1 ); rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; - rmesa->ioctl.vertex_offset = + rmesa->ioctl.vertex_offset = (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); #else BATCH_LOCALS(&rmesa->radeon); @@ -336,7 +336,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - + voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, @@ -352,7 +352,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, RADEON_GEM_DOMAIN_GTT, 0, 0); } - + if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); @@ -370,7 +370,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - + voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); @@ -378,7 +378,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } - + if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); @@ -427,7 +427,7 @@ static void radeonUserClear(GLcontext *ctx, GLuint mask) static void radeonKernelClear(GLcontext *ctx, GLuint flags) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; uint32_t clear; GLint ret, i; @@ -529,7 +529,7 @@ static void radeonKernelClear(GLcontext *ctx, GLuint flags) depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1; depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2; depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2; - depth_boxes[n].f[CLEAR_DEPTH] = + depth_boxes[n].f[CLEAR_DEPTH] = (float)rmesa->radeon.state.depth.clear; } @@ -548,7 +548,7 @@ static void radeonKernelClear(GLcontext *ctx, GLuint flags) static void radeonClear( GLcontext *ctx, GLbitfield mask ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLuint flags = 0; GLuint color_mask = 0; GLuint orig_mask = mask; @@ -560,11 +560,11 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) { LOCK_HARDWARE( &rmesa->radeon ); UNLOCK_HARDWARE( &rmesa->radeon ); - if ( dPriv->numClipRects == 0 ) + if ( dPriv->numClipRects == 0 ) return; } - - radeon_firevertices(&rmesa->radeon); + + radeon_firevertices(&rmesa->radeon); if ( mask & BUFFER_BIT_FRONT_LEFT ) { flags |= RADEON_FRONT; @@ -594,12 +594,12 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) _swrast_Clear( ctx, mask ); } - if ( !flags ) + if ( !flags ) return; if (rmesa->using_hyperz) { flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) +/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) flags |= RADEON_USE_HIERZ; */ if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index fe19218d7ae..5774f7ebcf7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -58,8 +58,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) { - __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; - __DRIdrawablePrivate *const readable = rmesa->dri.readable; + __DRIdrawablePrivate *const drawable = radeon_get_drawable(rmesa); + __DRIdrawablePrivate *const readable = radeon_get_readable(rmesa); __DRIscreenPrivate *sPriv = rmesa->dri.screen; assert(drawable != NULL); @@ -95,8 +95,8 @@ void radeon_lock_hardware(radeonContextPtr radeon) struct radeon_framebuffer *rfb = NULL; struct radeon_renderbuffer *rrb = NULL; - if (radeon->dri.drawable) { - rfb = radeon->dri.drawable->driverPrivate; + if (radeon_get_drawable(radeon)) { + rfb = radeon_get_drawable(radeon)->driverPrivate; if (rfb) rrb = radeon_get_renderbuffer(&rfb->base, diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 5aeb968d41c..3ba11e848e3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1374,6 +1374,7 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, #endif #if !RADEON_COMMON + (void)screen; return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); #endif return GL_FALSE; diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 34c8cb42fa4..06b8c299368 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -149,7 +149,7 @@ static void radeonBlendFuncSeparate( GLcontext *ctx, GLenum sfactorA, GLenum dfactorA ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & + GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK); GLboolean fallback = GL_FALSE; @@ -392,7 +392,7 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) rmesa->hw.fog.cmd[FOG_D] = d.i; } break; - case GL_FOG_COLOR: + case GL_FOG_COLOR: RADEON_STATECHANGE( rmesa, ctx ); UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color ); rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~RADEON_FOG_COLOR_MASK; @@ -495,7 +495,7 @@ static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern ) r100ContextPtr rmesa = R100_CONTEXT(ctx); RADEON_STATECHANGE( rmesa, lin ); - rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = + rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern)); } @@ -558,7 +558,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* FIXME: Use window x,y offsets into stipple RAM. */ stipple.mask = rmesa->state.stipple.mask; - drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, + drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, &stipple, sizeof(drm_radeon_stipple_t) ); UNLOCK_HARDWARE( &rmesa->radeon ); } @@ -569,7 +569,7 @@ static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0; /* Can't generally do unfilled via tcl, but some good special - * cases work. + * cases work. */ TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, flag); if (rmesa->radeon.TclFallback) { @@ -617,7 +617,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE; rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE; p |= RADEON_SPECULAR_ENABLE; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= + rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_DIFFUSE_SPECULAR_COMBINE; } else if (ctx->Light.Enabled) { @@ -647,7 +647,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) RADEON_TCL_COMPUTE_SPECULAR) != 0; } } - + TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_FOGCOORDSPEC, flag); if (NEED_SECONDARY_COLOR(ctx)) { @@ -663,7 +663,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) /* Update vertex/render formats */ - if (rmesa->radeon.TclFallback) { + if (rmesa->radeon.TclFallback) { radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } @@ -675,7 +675,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) */ -/* Update on colormaterial, material emmissive/ambient, +/* Update on colormaterial, material emmissive/ambient, * lightmodel.globalambient */ static void update_global_ambient( GLcontext *ctx ) @@ -688,23 +688,23 @@ static void update_global_ambient( GLcontext *ctx ) */ if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] & ((3 << RADEON_EMISSIVE_SOURCE_SHIFT) | - (3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0) + (3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0) { - COPY_3V( &fcmd[GLT_RED], + COPY_3V( &fcmd[GLT_RED], ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]); ACC_SCALE_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient, ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]); - } + } else { COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient ); } - + RADEON_DB_STATECHANGE(rmesa, &rmesa->hw.glt); } -/* Update on change to +/* Update on change to * - light[p].colors * - light[p].enabled */ @@ -718,10 +718,10 @@ static void update_light_colors( GLcontext *ctx, GLuint p ) r100ContextPtr rmesa = R100_CONTEXT(ctx); float *fcmd = (float *)RADEON_DB_STATE( lit[p] ); - COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient ); + COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient ); COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse ); COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular ); - + RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] ); } } @@ -735,7 +735,7 @@ static void check_twoside_fallback( GLcontext *ctx ) if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) { if (ctx->Light.ColorMaterialEnabled && - (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) != + (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) != ((ctx->Light.ColorMaterialBitmask & FRONT_MATERIAL_BITS)<<1)) fallback = GL_TRUE; else { @@ -743,7 +743,7 @@ static void check_twoside_fallback( GLcontext *ctx ) if (memcmp( ctx->Light.Material.Attrib[i], ctx->Light.Material.Attrib[i+1], sizeof(GLfloat)*4) != 0) { - fallback = GL_TRUE; + fallback = GL_TRUE; break; } } @@ -761,8 +761,8 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) | (3 << RADEON_AMBIENT_SOURCE_SHIFT) | (3 << RADEON_DIFFUSE_SOURCE_SHIFT) | - (3 << RADEON_SPECULAR_SOURCE_SHIFT)); - + (3 << RADEON_SPECULAR_SOURCE_SHIFT)); + if (ctx->Light.ColorMaterialEnabled) { GLuint mask = ctx->Light.ColorMaterialBitmask; @@ -783,7 +783,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT); } - + if (mask & MAT_BIT_FRONT_DIFFUSE) { light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE << RADEON_DIFFUSE_SOURCE_SHIFT); @@ -792,7 +792,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT); } - + if (mask & MAT_BIT_FRONT_SPECULAR) { light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE << RADEON_SPECULAR_SOURCE_SHIFT); @@ -810,10 +810,10 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT); } - + if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) { RADEON_STATECHANGE( rmesa, tcl ); - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1; + rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1; } } @@ -823,14 +823,14 @@ void radeonUpdateMaterial( GLcontext *ctx ) GLfloat (*mat)[4] = ctx->Light.Material.Attrib; GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl ); GLuint mask = ~0; - + if (ctx->Light.ColorMaterialEnabled) mask &= ~ctx->Light.ColorMaterialBitmask; if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); - + if (mask & MAT_BIT_FRONT_EMISSION) { fcmd[MTL_EMMISSIVE_RED] = mat[MAT_ATTRIB_FRONT_EMISSION][0]; fcmd[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_FRONT_EMISSION][1]; @@ -880,7 +880,7 @@ void radeonUpdateMaterial( GLcontext *ctx ) * * which are calculated in light.c and are correct for the current * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW - * and _MESA_NEW_NEED_EYE_COORDS. + * and _MESA_NEW_NEED_EYE_COORDS. */ static void update_light( GLcontext *ctx ) { @@ -897,12 +897,12 @@ static void update_light( GLcontext *ctx ) tmp &= ~RADEON_LIGHT_IN_MODELSPACE; else tmp |= RADEON_LIGHT_IN_MODELSPACE; - + /* Leave this test disabled: (unexplained q3 lockup) (even with new packets) */ - if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) + if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) { RADEON_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = tmp; @@ -926,10 +926,10 @@ static void update_light( GLcontext *ctx ) if (ctx->Light.Light[p].Enabled) { struct gl_light *l = &ctx->Light.Light[p]; GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( lit[p] ); - + if (l->EyePosition[3] == 0.0) { - COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); - COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); + COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); + COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); fcmd[LIT_POSITION_W] = 0; fcmd[LIT_DIRECTION_W] = 0; } else { @@ -953,26 +953,26 @@ static void radeonLightfv( GLcontext *ctx, GLenum light, GLint p = light - GL_LIGHT0; struct gl_light *l = &ctx->Light.Light[p]; GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd; - + switch (pname) { - case GL_AMBIENT: + case GL_AMBIENT: case GL_DIFFUSE: case GL_SPECULAR: update_light_colors( ctx, p ); break; - case GL_SPOT_DIRECTION: - /* picked up in update_light */ + case GL_SPOT_DIRECTION: + /* picked up in update_light */ break; case GL_POSITION: { - /* positions picked up in update_light, but can do flag here */ + /* positions picked up in update_light, but can do flag here */ GLuint flag; GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2; /* FIXME: Set RANGE_ATTEN only when needed */ - if (p&1) + if (p&1) flag = RADEON_LIGHT_1_IS_LOCAL; else flag = RADEON_LIGHT_0_IS_LOCAL; @@ -1064,7 +1064,7 @@ static void radeonLightfv( GLcontext *ctx, GLenum light, } } - + static void radeonLightModelfv( GLcontext *ctx, GLenum pname, @@ -1073,7 +1073,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, r100ContextPtr rmesa = R100_CONTEXT(ctx); switch (pname) { - case GL_LIGHT_MODEL_AMBIENT: + case GL_LIGHT_MODEL_AMBIENT: update_global_ambient( ctx ); break; @@ -1247,14 +1247,14 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP, and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC, but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */ - + GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP; GLuint tempRADEON_STENCIL_FAIL_INC_WRAP; GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP; GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP; GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP; GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP; - + if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) { tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC; tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC; @@ -1271,7 +1271,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP; tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP; } - + RADEON_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK | RADEON_STENCIL_ZFAIL_MASK | @@ -1363,7 +1363,7 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - rmesa->radeon.state.stencil.clear = + rmesa->radeon.state.stencil.clear = ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << RADEON_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT)); @@ -1388,7 +1388,7 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) void radeonUpdateWindow( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1443,7 +1443,7 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, void radeonUpdateViewportOffset( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1473,8 +1473,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) RADEON_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ - stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK); - sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1) + stx = 31 - ((dPriv->x - 1) & RADEON_STIPPLE_COORD_MASK); + sty = 31 - ((dPriv->y + dPriv->h - 1) & RADEON_STIPPLE_COORD_MASK); m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) | @@ -1613,7 +1613,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_CLIP_PLANE2: case GL_CLIP_PLANE3: case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: + case GL_CLIP_PLANE5: p = cap-GL_CLIP_PLANE0; RADEON_STATECHANGE( rmesa, tcl ); if (state) { @@ -1678,13 +1678,13 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_LIGHT7: RADEON_STATECHANGE(rmesa, tcl); p = cap - GL_LIGHT0; - if (p&1) + if (p&1) flag = (RADEON_LIGHT_1_ENABLE | - RADEON_LIGHT_1_ENABLE_AMBIENT | + RADEON_LIGHT_1_ENABLE_AMBIENT | RADEON_LIGHT_1_ENABLE_SPECULAR); else flag = (RADEON_LIGHT_0_ENABLE | - RADEON_LIGHT_0_ENABLE_AMBIENT | + RADEON_LIGHT_0_ENABLE_AMBIENT | RADEON_LIGHT_0_ENABLE_SPECULAR); if (state) @@ -1692,7 +1692,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) else rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag; - /* + /* */ update_light_colors( ctx, p ); break; @@ -1730,7 +1730,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE; } break; - + case GL_NORMALIZE: RADEON_STATECHANGE( rmesa, tcl ); if ( state ) { @@ -1830,7 +1830,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_TEXTURE_GEN_T: /* Picked up in radeonUpdateTextureState. */ - rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; + rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; break; case GL_COLOR_SUM_EXT: @@ -1864,7 +1864,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx ) rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS; } - if (RADEON_DEBUG & DEBUG_STATE) + if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s %d AFTER %x\n", __FUNCTION__, ctx->_NeedEyeCoords, rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]); } @@ -2051,7 +2051,7 @@ static GLboolean r100ValidateBuffers(GLcontext *ctx) int i; radeon_validate_reset_bos(&rmesa->radeon); - + rrb = radeon_get_colorbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { @@ -2069,7 +2069,7 @@ static GLboolean r100ValidateBuffers(GLcontext *ctx) for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { radeonTexObj *t; - + if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; @@ -2112,7 +2112,7 @@ GLboolean radeonValidateState( GLcontext *ctx ) /* Need an event driven matrix update? */ - if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) + if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, MODEL_PROJ ); /* Need these for lighting (shouldn't upload otherwise) @@ -2136,7 +2136,7 @@ GLboolean radeonValidateState( GLcontext *ctx ) /* emit all active clip planes if projection matrix changes. */ if (new_state & (_NEW_PROJECTION)) { - if (ctx->Transform.ClipPlanesEnabled) + if (ctx->Transform.ClipPlanesEnabled) radeonUpdateClipPlanes( ctx ); } @@ -2165,8 +2165,8 @@ static GLboolean check_material( GLcontext *ctx ) TNLcontext *tnl = TNL_CONTEXT(ctx); GLint i; - for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT; - i < _TNL_ATTRIB_MAT_BACK_INDEXES; + for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT; + i < _TNL_ATTRIB_MAT_BACK_INDEXES; i++) if (tnl->vb.AttribPtr[i] && tnl->vb.AttribPtr[i]->stride) @@ -2174,7 +2174,7 @@ static GLboolean check_material( GLcontext *ctx ) return GL_FALSE; } - + static void radeonWrapRunPipeline( GLcontext *ctx ) { @@ -2197,7 +2197,7 @@ static void radeonWrapRunPipeline( GLcontext *ctx ) } /* Run the pipeline. - */ + */ _tnl_run_pipeline( ctx ); if (has_material) { -- cgit v1.2.3 From 9b1efcb87c794ded9306f01336d48a80aaad3261 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sat, 23 May 2009 21:57:25 +0200 Subject: radeon: realloc dma if needed after revalidate Revalidate can trigger flushing and dma buffer deallocation, so retry allocation on such case. --- src/mesa/drivers/dri/radeon/radeon_dma.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index a357afe6798..48b0d638183 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -203,6 +203,12 @@ again_alloc: if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE) fprintf(stderr,"failure to revalidate BOs - badness\n"); + if (!rmesa->dma.current) { + /* Cmd buff have been flushed in radeon_revalidate_bos */ + rmesa->dma.nr_released_bufs = 0; + goto again_alloc; + } + radeon_bo_map(rmesa->dma.current, 1); } -- cgit v1.2.3 From 80f1ac87f2cb42ae8370174a75d1271950e59657 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 25 May 2009 11:29:32 +0200 Subject: r200: emit cliprect with indexed primitive --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 55ea81a57cf..8b2335d149c 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -135,7 +135,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) if (vertex_count > 0) { BEGIN_BATCH(8+2); - OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0); + OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | R200_VF_COLOR_ORDER_RGBA | ((vertex_count + 0) << 16) | -- cgit v1.2.3 From 39ef33708c1a048863a1956cd99782013791ca92 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 25 May 2009 13:17:22 +0200 Subject: r200: fix multitexturing in dri2 path --- src/mesa/drivers/dri/r200/r200_state_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index a7167790967..83920093378 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -598,7 +598,7 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) dwords -= 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7)); + OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7)); OUT_BATCH_TABLE((atom->cmd + 1), 8); if (hastexture) { -- cgit v1.2.3 From 714f5e689fb1a69142995260e3c8908c12407b47 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 25 May 2009 15:47:39 +0200 Subject: r200: emit scissor when dri2 is enabled In DRI1 kernel emit scissor but in dri2 cs path we have to explicitly program them. --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 8b2335d149c..df9dd83344c 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -105,6 +105,35 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] ); } +void r200EmitScissor(r200ContextPtr rmesa) +{ + BATCH_LOCALS(&rmesa->radeon); + if (!rmesa->radeon.radeonScreen->kernel_mm) { + return; + } + if (rmesa->radeon.state.scissor.enabled) { + BEGIN_BATCH(8); + OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0)); + OUT_BATCH(R200_SCISSOR_ENABLE | rmesa->hw.set.cmd[SET_RE_CNTL]); + OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0)); + OUT_BATCH(R200_SCISSOR_ENABLE_0); + OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_TL_0, 0)); + OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | + rmesa->radeon.state.scissor.rect.x1); + OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_BR_0, 0)); + OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) | + (rmesa->radeon.state.scissor.rect.x2 - 1)); + END_BATCH(); + } else { + BEGIN_BATCH(4); + OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0)); + OUT_BATCH(rmesa->hw.set.cmd[SET_RE_CNTL] & ~R200_SCISSOR_ENABLE); + OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0)); + OUT_BATCH(0); + END_BATCH(); + } +} + /* Fire a section of the retained (indexed_verts) buffer as a regular * primtive. */ @@ -121,6 +150,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, rmesa->store.cmd_used/4, primitive, vertex_nr); + r200EmitScissor(rmesa); BEGIN_BATCH(3); OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); @@ -134,6 +164,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) BATCH_LOCALS(&rmesa->radeon); if (vertex_count > 0) { + r200EmitScissor(rmesa); BEGIN_BATCH(8+2); OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | -- cgit v1.2.3 From 9dee2f20a204f375eb4321092cf5dea6476c1c24 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 25 May 2009 16:05:45 +0200 Subject: radeon: on update drawable don't firevertices as it might be call from GetLock To avoid locking bug we shouldn't not call firevertices from this path as it's call from radeon get lock. --- src/mesa/drivers/dri/radeon/radeon_common.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index e2e0ba07a3b..466eda784ef 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -769,9 +769,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) /* Set state we know depends on drawable parameters: */ - if (ctx->Driver.Scissor) - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); + radeonUpdateScissor(ctx); radeon->NewGLState |= _NEW_SCISSOR; if (ctx->Driver.DepthRange) -- cgit v1.2.3 From 6141c9ba71df68c44fb4f8c9409f23b557009ca0 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 27 May 2009 09:36:07 +0200 Subject: radeon: emit scissor when using cs submission style. --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index caa0c4a896d..8f8878ee104 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -113,6 +113,31 @@ void radeonSetUpAtomList( r100ContextPtr rmesa ) insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt); } +void radeonEmitScissor(r100ContextPtr rmesa) +{ + BATCH_LOCALS(&rmesa->radeon); + if (!rmesa->radeon.radeonScreen->kernel_mm) { + return; + } + if (rmesa->radeon.state.scissor.enabled) { + BEGIN_BATCH(6); + OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); + OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); + OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); + OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | + rmesa->radeon.state.scissor.rect.x1); + OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); + OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) | + (rmesa->radeon.state.scissor.rect.x2 - 1)); + END_BATCH(); + } else { + BEGIN_BATCH(2); + OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); + OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); + END_BATCH(); + } +} + /* Fire a section of the retained (indexed_verts) buffer as a regular * primtive. */ @@ -126,6 +151,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); radeonEmitState(&rmesa->radeon); + radeonEmitScissor(rmesa); #if RADEON_OLD_PACKETS BEGIN_BATCH(8); @@ -180,6 +206,8 @@ void radeonFlushElts( GLcontext *ctx ) assert( rmesa->radeon.dma.flush == radeonFlushElts ); rmesa->radeon.dma.flush = NULL; + radeonEmitScissor(rmesa); + nr = rmesa->tcl.elt_used; #if RADEON_OLD_PACKETS -- cgit v1.2.3 From 3a6dd3ebb33a35779b0d5be2c8cab581a56f245a Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 27 May 2009 21:50:03 +0200 Subject: radeon: emit scissor before emiting vertices --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 8f8878ee104..01c45df2dfa 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -206,8 +206,6 @@ void radeonFlushElts( GLcontext *ctx ) assert( rmesa->radeon.dma.flush == radeonFlushElts ); rmesa->radeon.dma.flush = NULL; - radeonEmitScissor(rmesa); - nr = rmesa->tcl.elt_used; #if RADEON_OLD_PACKETS @@ -260,6 +258,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); radeonEmitState(&rmesa->radeon); + radeonEmitScissor(rmesa); rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; @@ -280,7 +279,6 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, RADEON_CP_VC_CNTL_PRIM_WALK_IND | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); - #else BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); -- cgit v1.2.3 From 2f9189d538ac56bd241ccc8f8f82bc4fdd779aa6 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 28 May 2009 11:40:58 +0200 Subject: r300: rework texture offset emission. --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 60ad8ea14b3..e605076a519 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -179,27 +179,33 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) if (r300->radeon.radeonScreen->kernel_mm && notexture) { return; } - BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus); for(i = 0; i < numtmus; ++i) { radeonTexObj *t = r300->hw.textures[i]; - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); if (t && !t->image_override) { + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + END_BATCH(); } else if (!t) { - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + /* Texture unit hasn't a texture bound nothings to do */ } else { /* override cases */ if (t->bo) { + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + END_BATCH(); } else if (!r300->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); OUT_BATCH(t->override_offset); - } - else - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + END_BATCH(); + } else { + /* Texture unit hasn't a texture bound nothings to do */ + } } } - END_BATCH(); } } -- cgit v1.2.3 From 5dcbcbfca4f3c00de1fdab28d1cc8d691f67edce Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 28 May 2009 13:48:38 +0200 Subject: r300: when using cs path emit scissor in the cmdbuffer --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 39 +++++++++++++++++++++++++++++++++ src/mesa/drivers/dri/r300/r300_cmdbuf.h | 1 + src/mesa/drivers/dri/r300/r300_render.c | 2 ++ src/mesa/drivers/dri/r300/r300_swtcl.c | 1 + 4 files changed, 43 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index e605076a519..b949c3b5b21 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -209,6 +209,45 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) } } +void r300_emit_scissor(GLcontext *ctx) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + unsigned x1, y1, x2, y2; + struct radeon_renderbuffer *rrb; + + if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { + return; + } + rrb = radeon_get_colorbuffer(&r300->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + if (r300->radeon.state.scissor.enabled) { + x1 = r300->radeon.state.scissor.rect.x1; + y1 = r300->radeon.state.scissor.rect.y1; + x2 = r300->radeon.state.scissor.rect.x2 - 1; + y2 = r300->radeon.state.scissor.rect.y2 - 1; + } else { + x1 = 0; + y1 = 0; + x2 = rrb->width - 1; + y2 = rrb->height - 1; + } + if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { + x1 += R300_SCISSORS_OFFSET; + y1 += R300_SCISSORS_OFFSET; + x2 += R300_SCISSORS_OFFSET; + y2 += R300_SCISSORS_OFFSET; + } + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); + OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT)); + END_BATCH(); +} + static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { r300ContextPtr r300 = R300_CONTEXT(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index 3786813de36..53bcc0eeb49 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -39,6 +39,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" extern void r300InitCmdBuf(r300ContextPtr r300); +void r300_emit_scissor(GLcontext *ctx); void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 7edeaed6d82..92310a02647 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -189,6 +189,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) { BATCH_LOCALS(&rmesa->radeon); + r300_emit_scissor(rmesa->radeon.glCtx); if (vertex_count > 0) { BEGIN_BATCH(10); OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); @@ -329,6 +330,7 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) { BATCH_LOCALS(&rmesa->radeon); + r300_emit_scissor(rmesa->radeon.glCtx); BEGIN_BATCH(3); OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 78fa031479c..68e24dec8fa 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -683,6 +683,7 @@ void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); radeonEmitState(&rmesa->radeon); + r300_emit_scissor(ctx); r300EmitVertexAOS(rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, -- cgit v1.2.3 From c1ccc7d5394c23a371540e1b2c3d35b0da3b30d6 Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Sun, 31 May 2009 16:32:58 +0200 Subject: radeon: Provide a more detailled GL_RENDERER string. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Display the chip family and PCI ID. This can be parsed easily, and essentially all information that the driver has about the chip can be deduced from it. Signed-off-by: Nicolai Hähnle --- .../drivers/dri/radeon/radeon_common_context.c | 50 +++++++++++++++++++--- src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + src/mesa/drivers/dri/radeon/radeon_screen.h | 1 + 3 files changed, 47 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index e9967986a3f..eb0e5b35e5e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -52,6 +52,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. int RADEON_DEBUG = (0); #endif + +static const char* get_chip_family_name(int chip_family) +{ + switch(chip_family) { + case CHIP_FAMILY_R100: return "R100"; + case CHIP_FAMILY_RV100: return "RV100"; + case CHIP_FAMILY_RS100: return "RS100"; + case CHIP_FAMILY_RV200: return "RV200"; + case CHIP_FAMILY_RS200: return "RS200"; + case CHIP_FAMILY_R200: return "R200"; + case CHIP_FAMILY_RV250: return "RV250"; + case CHIP_FAMILY_RS300: return "RS300"; + case CHIP_FAMILY_RV280: return "RV280"; + case CHIP_FAMILY_R300: return "R300"; + case CHIP_FAMILY_R350: return "R350"; + case CHIP_FAMILY_RV350: return "RV350"; + case CHIP_FAMILY_RV380: return "RV380"; + case CHIP_FAMILY_R420: return "R420"; + case CHIP_FAMILY_RV410: return "RV410"; + case CHIP_FAMILY_RS400: return "RS400"; + case CHIP_FAMILY_RS600: return "RS600"; + case CHIP_FAMILY_RS690: return "RS690"; + case CHIP_FAMILY_RS740: return "RS740"; + case CHIP_FAMILY_RV515: return "RV515"; + case CHIP_FAMILY_R520: return "R520"; + case CHIP_FAMILY_RV530: return "RV530"; + case CHIP_FAMILY_R580: return "R580"; + case CHIP_FAMILY_RV560: return "RV560"; + case CHIP_FAMILY_RV570: return "RV570"; + default: return "unknown"; + } +} + + /* Return various strings for glGetString(). */ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) @@ -71,16 +105,22 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) unsigned offset; GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : radeon->radeonScreen->AGPMode; - const char* chipname; + const char* chipclass; + char hardwarename[32]; if (IS_R300_CLASS(radeon->radeonScreen)) - chipname = "R300"; + chipclass = "R300"; else if (IS_R200_CLASS(radeon->radeonScreen)) - chipname = "R200"; + chipclass = "R200"; else - chipname = "R100"; + chipclass = "R100"; + + sprintf(hardwarename, "%s (%s %04X)", + chipclass, + get_chip_family_name(radeon->radeonScreen->chip_family), + radeon->radeonScreen->device_id); - offset = driGetRendererString(buffer, chipname, DRIVER_DATE, + offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE, agp_mode); if (IS_R300_CLASS(radeon->radeonScreen)) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 3ba11e848e3..12ae4ada5db 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -400,6 +400,7 @@ static const __DRItexBufferExtension r300TexBufferExtension = { static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) { + screen->device_id = device_id; screen->chip_flags = 0; switch ( device_id ) { case PCI_CHIP_RADEON_LY: diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 8605eb4f075..fe5c7d875a0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -59,6 +59,7 @@ typedef struct radeon_screen { int chip_flags; int cpp; int card_type; + int device_id; /* PCI ID */ int AGPMode; unsigned int irq; /* IRQ number (0 means none) */ -- cgit v1.2.3 From ab60a44331462b659f491dfb11e125daeb556973 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 27 May 2009 22:12:56 +0200 Subject: r300: always pass 4 color components to RS unit Even if we don't pass all 4 color components to vertex shader unit, the vertex program can generate the missing components. --- src/mesa/drivers/dri/r300/r300_state.c | 48 +++++----------------------------- 1 file changed, 6 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 582e8c27e31..bbe993429bf 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1448,14 +1448,12 @@ union r300_outputs_written { static void r300SetupRSUnit(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; union r300_outputs_written OutputsWritten; GLuint InputsRead; int fp_reg, high_rr; int col_ip, tex_ip; int rs_tex_count = 0; - int i, count, col_fmt, hw_tcl_on; + int i, col_fmt, hw_tcl_on; hw_tcl_on = r300->options.hw_tcl_enabled; @@ -1483,15 +1481,7 @@ static void r300SetupRSUnit(GLcontext * ctx) if (InputsRead & FRAG_BIT_COL0) { if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { - count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size; - if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; - else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; - else - col_fmt = R300_RS_COL_FMT_0001; - - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt); + r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA); r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL0; ++col_ip; @@ -1503,15 +1493,7 @@ static void r300SetupRSUnit(GLcontext * ctx) if (InputsRead & FRAG_BIT_COL1) { if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { - count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size; - if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; - else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; - else - col_fmt = R300_RS_COL_FMT_0001; - - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt); + r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA); r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL1; ++col_ip; @@ -1581,14 +1563,12 @@ static void r300SetupRSUnit(GLcontext * ctx) static void r500SetupRSUnit(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; union r300_outputs_written OutputsWritten; GLuint InputsRead; int fp_reg, high_rr; int col_ip, tex_ip; int rs_tex_count = 0; - int i, count, col_fmt, hw_tcl_on; + int i, col_fmt, hw_tcl_on; hw_tcl_on = r300->options.hw_tcl_enabled; @@ -1616,15 +1596,7 @@ static void r500SetupRSUnit(GLcontext * ctx) if (InputsRead & FRAG_BIT_COL0) { if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { - count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size; - if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; - else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; - else - col_fmt = R300_RS_COL_FMT_0001; - - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); + r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA); r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL0; ++col_ip; @@ -1636,15 +1608,7 @@ static void r500SetupRSUnit(GLcontext * ctx) if (InputsRead & FRAG_BIT_COL1) { if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { - count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size; - if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; - else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; - else - col_fmt = R300_RS_COL_FMT_0001; - - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); + r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA); r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL1; ++col_ip; -- cgit v1.2.3 From a27b689d08d88f99ebccf58bbba64d3cfc668866 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 27 May 2009 22:17:31 +0200 Subject: r300: fixup vertex attributes ordering Always allocate the vertex program input registers in the same order as the vertex attributes are passed in vertex arrays. --- src/mesa/drivers/dri/r300/r300_vertprog.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 949c0b499c4..35e5ec0f8e7 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -215,21 +215,8 @@ static void vp_dump_inputs(struct r300_vertex_program *vp, char *caller) static unsigned long t_src_index(struct r300_vertex_program *vp, struct prog_src_register *src) { - int i; - int max_reg = -1; - if (src->File == PROGRAM_INPUT) { - if (vp->inputs[src->Index] != -1) - return vp->inputs[src->Index]; - - for (i = 0; i < VERT_ATTRIB_MAX; i++) - if (vp->inputs[i] > max_reg) - max_reg = vp->inputs[i]; - - vp->inputs[src->Index] = max_reg + 1; - - //vp_dump_inputs(vp, __FUNCTION__); - + assert(vp->inputs[src->Index] != -1); return vp->inputs[src->Index]; } else { if (src->Index < 0) { @@ -944,11 +931,17 @@ static GLuint *r300TranslateOpcodeXPD(struct r300_vertex_program *vp, static void t_inputs_outputs(struct r300_vertex_program *vp) { int i; - int cur_reg = 0; + int cur_reg; - for (i = 0; i < VERT_ATTRIB_MAX; i++) - vp->inputs[i] = -1; + cur_reg = -1; + for (i = 0; i < VERT_ATTRIB_MAX; i++) { + if (vp->key.InputsRead & (1 << i)) + vp->inputs[i] = ++cur_reg; + else + vp->inputs[i] = -1; + } + cur_reg = 0; for (i = 0; i < VERT_RESULT_MAX; i++) vp->outputs[i] = -1; -- cgit v1.2.3 From e98082997c8cfe3bf9c1c1cdc40c23ee897d1007 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 30 May 2009 13:28:47 +0200 Subject: r300: prepare for different vertex data type support --- src/mesa/drivers/dri/r300/r300_context.h | 32 +++++--- src/mesa/drivers/dri/r300/r300_render.h | 6 ++ src/mesa/drivers/dri/r300/r300_state.c | 58 ++++++++++++++ src/mesa/drivers/dri/r300/r300_state.h | 1 + src/mesa/drivers/dri/r300/r300_swtcl.c | 133 +++++++------------------------ src/mesa/drivers/dri/r300/r300_swtcl.h | 6 -- 6 files changed, 116 insertions(+), 120 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 2ea064ed452..7694fe4862f 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -584,16 +584,6 @@ struct r300_swtcl_info { */ GLuint specoffset; - struct vertex_attribute{ - GLuint attr; - GLubyte format; - GLubyte dst_loc; - GLuint swizzle; - GLubyte write_mask; - } vert_attrs[VERT_ATTRIB_MAX]; - - GLubyte vertex_attr_count; - int sw_tcl_inputs[VERT_ATTRIB_MAX]; }; @@ -605,6 +595,27 @@ struct r300_vtable { void (* SetupPixelShader)(GLcontext *ctx); }; +struct r300_vertex_buffer { + struct vertex_attribute { + /* generic */ + GLubyte element; + GLvoid *data; + GLboolean free_needed; + GLuint stride; + GLuint dwords; + GLubyte size; /* number of components */ + + /* hw specific */ + uint32_t data_type:4; + uint32_t dst_loc:5; + uint32_t _signed:1; + uint32_t normalize:1; + uint32_t swizzle:12; + uint32_t write_mask:4; + } attribs[VERT_ATTRIB_MAX]; + + GLubyte num_attribs; +}; /** * \brief R300 context structure. @@ -632,6 +643,7 @@ struct r300_context { } options; struct r300_swtcl_info swtcl; + struct r300_vertex_buffer vbuf; GLboolean vap_flush_needed; uint32_t fallback; diff --git a/src/mesa/drivers/dri/r300/r300_render.h b/src/mesa/drivers/dri/r300/r300_render.h index 940d2566e2c..002cd613dc9 100644 --- a/src/mesa/drivers/dri/r300/r300_render.h +++ b/src/mesa/drivers/dri/r300/r300_render.h @@ -44,6 +44,12 @@ #define R300_FALLBACK_INVALID_BUFFERS (1 << 31) #define R300_RASTER_FALLBACK_MASK 0xffff0000 +#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) +#define MASK_X R300_WRITE_ENA_X +#define MASK_Y R300_WRITE_ENA_Y +#define MASK_Z R300_WRITE_ENA_Z +#define MASK_W R300_WRITE_ENA_W + extern const struct tnl_pipeline_stage _r300_render_stage; extern const struct tnl_pipeline_stage _r300_tcl_stage; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index bbe993429bf..a04326fca97 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2216,6 +2216,64 @@ static void r500SetupPixelShader(GLcontext *ctx) bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4); } +void r300SetupVAP(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) +{ + r300ContextPtr rmesa = R300_CONTEXT( ctx ); + struct vertex_attribute *attrs = rmesa->vbuf.attribs; + int i, j, reg_count; + uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; + uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; + + for (i = 0; i < R300_VIR_CMDSIZE-1; ++i) + vir0[i] = vir1[i] = 0; + + for (i = 0, j = 0; i < rmesa->vbuf.num_attribs; ++i) { + int tmp; + + tmp = attrs[i].data_type | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT); + if (attrs[i]._signed) + tmp |= R300_SIGNED; + if (attrs[i].normalize) + tmp |= R300_NORMALIZE; + + if (i % 2 == 0) { + vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT; + vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT); + } else { + vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT; + vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; + ++j; + } + } + + reg_count = (rmesa->vbuf.num_attribs + 1) >> 1; + if (rmesa->vbuf.num_attribs % 2 != 0) { + vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; + } else { + vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; + } + + R300_STATECHANGE(rmesa, vir[0]); + R300_STATECHANGE(rmesa, vir[1]); + R300_STATECHANGE(rmesa, vof); + R300_STATECHANGE(rmesa, vic); + + if (rmesa->radeon.radeonScreen->kernel_mm) { + rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; + rmesa->hw.vir[0].cmd[0] |= (reg_count & 0x3FFF) << 16; + rmesa->hw.vir[1].cmd[0] |= (reg_count & 0x3FFF) << 16; + } else { + ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = reg_count; + ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count; + } + + rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); + rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); + rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); + rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); +} + void r300UpdateShaderStates(r300ContextPtr rmesa) { GLcontext *ctx; diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index cac639d7c66..23282894202 100644 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ b/src/mesa/drivers/dri/r300/r300_state.h @@ -58,5 +58,6 @@ void r300UpdateShaderStates (r300ContextPtr rmesa); void r300InitState (r300ContextPtr r300); void r300InitStateFuncs (struct dd_function_table *functions); void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count); +void r300SetupVAP(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten); #endif /* __R300_STATE_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 68e24dec8fa..fd6312ae261 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -38,6 +38,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_swtcl.h" #include "r300_emit.h" #include "r300_tex.h" +#include "r300_render.h" #define EMIT_ATTR( ATTR, STYLE ) \ do { \ @@ -54,107 +55,28 @@ do { \ rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) -#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask) \ +#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask, _normalize) \ do { \ - attrs[num_attrs].attr = (_attr); \ - attrs[num_attrs].format = (_format); \ + attrs[num_attrs].element = (_attr); \ + attrs[num_attrs].data_type = (_format); \ attrs[num_attrs].dst_loc = (_dst_loc); \ attrs[num_attrs].swizzle = (_swizzle); \ attrs[num_attrs].write_mask = (_write_mask); \ + attrs[num_attrs]._signed = 0; \ + attrs[num_attrs].normalize = (_normalize); \ ++num_attrs; \ } while (0) -static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten, GLuint vap_out_fmt_1) -{ - r300ContextPtr rmesa = R300_CONTEXT( ctx ); - struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; - int i, j, reg_count; - uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; - uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; - - for (i = 0; i < R300_VIR_CMDSIZE-1; ++i) - vir0[i] = vir1[i] = 0; - - for (i = 0, j = 0; i < rmesa->radeon.swtcl.vertex_attr_count; ++i) { - int tmp, data_format; - switch (attrs[i].format) { - case EMIT_1F: - data_format = R300_DATA_TYPE_FLOAT_1; - break; - case EMIT_2F: - data_format = R300_DATA_TYPE_FLOAT_2; - break; - case EMIT_3F: - data_format = R300_DATA_TYPE_FLOAT_3; - break; - case EMIT_4F: - data_format = R300_DATA_TYPE_FLOAT_4; - break; - case EMIT_4UB_4F_RGBA: - case EMIT_4UB_4F_ABGR: - data_format = R300_DATA_TYPE_BYTE | R300_NORMALIZE; - break; - default: - fprintf(stderr, "%s: Invalid data format type", __FUNCTION__); - _mesa_exit(-1); - break; - } - - tmp = data_format | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT); - if (i % 2 == 0) { - vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT; - vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT); - } else { - vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT; - vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; - ++j; - } - } - - reg_count = (rmesa->radeon.swtcl.vertex_attr_count + 1) >> 1; - if (rmesa->radeon.swtcl.vertex_attr_count % 2 != 0) { - vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; - } else { - vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; - } - - R300_STATECHANGE(rmesa, vir[0]); - R300_STATECHANGE(rmesa, vir[1]); - R300_STATECHANGE(rmesa, vof); - R300_STATECHANGE(rmesa, vic); - - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= (reg_count & 0x3FFF) << 16; - rmesa->hw.vir[1].cmd[0] |= (reg_count & 0x3FFF) << 16; - } else { - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = reg_count; - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count; - } - - rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); - /** - * Can't use r300VAPOutputCntl1 function because it assumes - * that all texture coords have 4 components and that's the case - * for HW TCL path, but not for SW TCL. - */ - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_out_fmt_1; -} - - static void r300SetVertexFormat( GLcontext *ctx ) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - int first_free_tex = 0, vap_out_fmt_1 = 0; + int first_free_tex = 0; GLuint InputsRead = 0; GLuint OutputsWritten = 0; int num_attrs = 0; - struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; + struct vertex_attribute *attrs = rmesa->vbuf.attribs; rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0; rmesa->radeon.swtcl.vertex_attr_count = 0; @@ -166,7 +88,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) InputsRead |= 1 << VERT_ATTRIB_POS; OutputsWritten |= 1 << VERT_RESULT_HPOS; EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_POS, EMIT_4F, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0); rmesa->swtcl.coloroffset = 4; } @@ -175,10 +97,10 @@ static void r300SetVertexFormat( GLcontext *ctx ) OutputsWritten |= 1 << VERT_RESULT_COL0; #if MESA_LITTLE_ENDIAN EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1); #else EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1); #endif } @@ -188,10 +110,10 @@ static void r300SetVertexFormat( GLcontext *ctx ) OutputsWritten |= 1 << VERT_RESULT_COL1; #if MESA_LITTLE_ENDIAN EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR1, swiz, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1); #else EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR1, swiz, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1); #endif rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1; } @@ -201,20 +123,21 @@ static void r300SetVertexFormat( GLcontext *ctx ) OutputsWritten |= 1 << VERT_RESULT_BFC0; #if MESA_LITTLE_ENDIAN EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1); #else EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1); #endif if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 )) { + VB->AttribPtr[VERT_ATTRIB_GENERIC1] = VB->SecondaryColorPtr[1]; GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); OutputsWritten |= 1 << VERT_RESULT_BFC1; #if MESA_LITTLE_ENDIAN EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR3, swiz, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1); #else EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR3, swiz, MASK_XYZW); + ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1); #endif } } @@ -224,7 +147,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE; OutputsWritten |= 1 << VERT_RESULT_PSIZ; EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F ); - ADD_ATTR(VERT_ATTRIB_POINT_SIZE, EMIT_1F, SWTCL_OVM_POINT_SIZE, swiz, MASK_X); + ADD_ATTR(VERT_ATTRIB_POINT_SIZE, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_POINT_SIZE, swiz, MASK_X, 0); } /** @@ -233,24 +156,28 @@ static void r300SetVertexFormat( GLcontext *ctx ) */ if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { int i; - GLuint swiz, format; + GLuint swiz, format, hw_format; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { switch (VB->TexCoordPtr[i]->size) { case 1: format = EMIT_1F; + hw_format = R300_DATA_TYPE_FLOAT_1; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); break; case 2: format = EMIT_2F; + hw_format = R300_DATA_TYPE_FLOAT_2; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE); break; case 3: format = EMIT_3F; + hw_format = R300_DATA_TYPE_FLOAT_3; swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); break; case 4: format = EMIT_4F; + hw_format = R300_DATA_TYPE_FLOAT_4; swiz = SWIZZLE_XYZW; break; default: @@ -259,8 +186,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); - ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, MASK_XYZW); - vap_out_fmt_1 |= 4 << (i * 3); + ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(i), swiz, MASK_XYZW, 0); ++first_free_tex; } } @@ -276,8 +202,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) InputsRead |= 1 << (VERT_ATTRIB_TEX0 + first_free_tex); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + first_free_tex); EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_POS, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); - vap_out_fmt_1 |= 4 << (first_free_tex * 3); + ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW, 0); ++first_free_tex; } @@ -291,12 +216,12 @@ static void r300SetVertexFormat( GLcontext *ctx ) OutputsWritten |= 1 << VERT_RESULT_FOGC; GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F ); - ADD_ATTR(VERT_ATTRIB_FOG, EMIT_1F, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_X); - vap_out_fmt_1 |= 1 << (first_free_tex * 3); + ADD_ATTR(VERT_ATTRIB_FOG, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0); } R300_NEWPRIM(rmesa); - r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten, vap_out_fmt_1); + rmesa->vbuf.num_attribs = num_attrs; + r300SetupVAP(ctx, InputsRead, OutputsWritten); rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index 14826f08171..cebc895c47a 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -39,12 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r300_context.h" -#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -#define MASK_X R300_WRITE_ENA_X -#define MASK_Y R300_WRITE_ENA_Y -#define MASK_Z R300_WRITE_ENA_Z -#define MASK_W R300_WRITE_ENA_W - /* * Here are definitions of OVM locations of vertex attributes for non TCL hw */ -- cgit v1.2.3 From fd80128e15c6393fa85088577ab2ca320c6cb8ae Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 30 May 2009 20:38:29 +0200 Subject: r300: add hw accelerated support for different vertex data formats --- src/mesa/drivers/dri/r300/Makefile | 1 + src/mesa/drivers/dri/r300/r300_context.c | 9 +- src/mesa/drivers/dri/r300/r300_context.h | 10 + src/mesa/drivers/dri/r300/r300_draw.c | 435 +++++++++++++++++++++++++++++++ src/mesa/drivers/dri/r300/r300_emit.c | 5 + src/mesa/drivers/dri/r300/r300_render.c | 77 ++---- src/mesa/drivers/dri/r300/r300_render.h | 5 +- 7 files changed, 485 insertions(+), 57 deletions(-) create mode 100644 src/mesa/drivers/dri/r300/r300_draw.c (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 62715e3b50d..bdb09624be4 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -37,6 +37,7 @@ RADEON_COMMON_SOURCES = \ DRIVER_SOURCES = \ radeon_screen.c \ r300_context.c \ + r300_draw.c \ r300_ioctl.c \ r300_cmdbuf.c \ r300_state.c \ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index dbd5ce589e3..b7911f23cce 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -153,10 +153,6 @@ const struct dri_extension gl_20_extension[] = { static const struct tnl_pipeline_stage *r300_pipeline[] = { - /* Try and go straight to t&l - */ - &_r300_tcl_stage, - /* Catch any t&l fallbacks */ &_tnl_vertex_transform_stage, @@ -436,8 +432,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, _tnl_allow_pixel_fog(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_TRUE); - if (!r300->options.hw_tcl_enabled) + if (r300->options.hw_tcl_enabled) { + r300InitDraw(ctx); + } else { r300InitSwtcl(ctx); + } radeon_fbo_init(&r300->radeon); radeonInitSpanFuncs( ctx ); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 7694fe4862f..11cfb55a9b5 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -617,6 +617,13 @@ struct r300_vertex_buffer { GLubyte num_attribs; }; +struct r300_index_buffer { + GLvoid *ptr; + GLboolean is_32bit; + GLboolean free_needed; + GLuint count; +}; + /** * \brief R300 context structure. */ @@ -644,6 +651,7 @@ struct r300_context { struct r300_swtcl_info swtcl; struct r300_vertex_buffer vbuf; + struct r300_index_buffer ind_buf; GLboolean vap_flush_needed; uint32_t fallback; @@ -666,6 +674,8 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx, extern void r300InitShaderFunctions(r300ContextPtr r300); +extern void r300InitDraw(GLcontext *ctx); + #define r300PackFloat32 radeonPackFloat32 #define r300PackFloat24 radeonPackFloat24 diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c new file mode 100644 index 00000000000..ba748787214 --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_draw.c @@ -0,0 +1,435 @@ +/************************************************************************** + * + * Copyright 2009 Maciej Cencora + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#include + +#include "main/glheader.h" +#include "main/context.h" +#include "main/state.h" +#include "main/api_validate.h" +#include "main/enums.h" + +#include "r300_reg.h" +#include "r300_context.h" +#include "r300_emit.h" +#include "r300_render.h" +#include "r300_state.h" +#include "r300_tex.h" + +#include "tnl/tnl.h" +#include "tnl/t_vp_build.h" +#include "vbo/vbo_context.h" +#include "swrast/swrast.h" +#include "swrast_setup/swrast_setup.h" + +static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf, struct gl_buffer_object **bo, GLuint *nr_bo) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_index_buffer *ind_buf = &r300->ind_buf; + GLvoid *src_ptr; + + if (!mesa_ind_buf) { + ind_buf->ptr = NULL; + return; + } + + ind_buf->count = mesa_ind_buf->count; + if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) { + bo[*nr_bo] = mesa_ind_buf->obj; + (*nr_bo)++; + ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj); + assert(mesa_ind_buf->obj->Pointer != NULL); + } + src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr); + + if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) { + GLubyte *in = (GLubyte *)src_ptr; + GLuint *out = _mesa_malloc(sizeof(GLuint) * mesa_ind_buf->count); + int i; + + for (i = 0; i < mesa_ind_buf->count; ++i) { + out[i] = (GLuint) in[i]; + } + + ind_buf->ptr = out; + ind_buf->free_needed = GL_TRUE; + ind_buf->is_32bit = GL_TRUE; + } else if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) { + ind_buf->ptr = src_ptr; + ind_buf->free_needed = GL_FALSE; + ind_buf->is_32bit = GL_FALSE; + } else { + ind_buf->ptr = src_ptr; + ind_buf->free_needed = GL_FALSE; + ind_buf->is_32bit = GL_TRUE; + } +} + +static int getTypeSize(GLenum type) +{ + switch (type) { + case GL_DOUBLE: + return sizeof(GLdouble); + case GL_FLOAT: + return sizeof(GLfloat); + case GL_INT: + return sizeof(GLint); + case GL_UNSIGNED_INT: + return sizeof(GLuint); + case GL_SHORT: + return sizeof(GLshort); + case GL_UNSIGNED_SHORT: + return sizeof(GLushort); + case GL_BYTE: + return sizeof(GLbyte); + case GL_UNSIGNED_BYTE: + return sizeof(GLubyte); + default: + assert(0); + return 0; + } +} + +#define CONVERT( TYPE, MACRO ) do { \ + GLuint i, j, sz; \ + sz = input->Size; \ + if (input->Normalized) { \ + for (i = 0; i < count; i++) { \ + const TYPE *in = (TYPE *)src_ptr; \ + for (j = 0; j < sz; j++) { \ + *dst_ptr++ = MACRO(*in); \ + in++; \ + } \ + src_ptr += input->StrideB; \ + } \ + } else { \ + for (i = 0; i < count; i++) { \ + const TYPE *in = (TYPE *)src_ptr; \ + for (j = 0; j < sz; j++) { \ + *dst_ptr++ = (GLfloat)(*in); \ + in++; \ + } \ + src_ptr += input->StrideB; \ + } \ + } \ +} while (0) + +static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const struct gl_client_array *input, struct gl_buffer_object **bo, GLuint *nr_bo) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_vertex_buffer *vbuf = &r300->vbuf; + struct vertex_attribute r300_attr; + const void *src_ptr; + GLenum type; + + if (input->BufferObj->Name) { + if (!input->BufferObj->Pointer) { + bo[*nr_bo] = input->BufferObj; + (*nr_bo)++; + ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj); + assert(input->BufferObj->Pointer != NULL); + } + + src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr); + } else + src_ptr = input->Ptr; + + if (input->Type == GL_DOUBLE || ((getTypeSize(input->Type) * input->Size) % 4 > 0)) { + if (RADEON_DEBUG & DEBUG_FALLBACKS) { + fprintf(stderr, "%s: Converting vertex attributes, attribute data format %x,", __FUNCTION__, input->Type); + fprintf(stderr, "stride %d, components %d\n", input->StrideB, input->Size); + } + + GLfloat *dst_ptr, *tmp; + tmp = dst_ptr = _mesa_malloc(sizeof(GLfloat) * input->Size * count); + + switch (input->Type) { + case GL_DOUBLE: + CONVERT(GLdouble, (GLfloat)); + break; + case GL_UNSIGNED_INT: + CONVERT(GLuint, UINT_TO_FLOAT); + break; + case GL_INT: + CONVERT(GLint, INT_TO_FLOAT); + break; + case GL_UNSIGNED_SHORT: + CONVERT(GLushort, USHORT_TO_FLOAT); + break; + case GL_SHORT: + CONVERT(GLshort, SHORT_TO_FLOAT); + break; + case GL_UNSIGNED_BYTE: + assert(input->Format != GL_BGRA); + CONVERT(GLubyte, UBYTE_TO_FLOAT); + break; + case GL_BYTE: + CONVERT(GLbyte, BYTE_TO_FLOAT); + break; + } + + type = GL_FLOAT; + r300_attr.free_needed = GL_TRUE; + r300_attr.data = tmp; + r300_attr.stride = sizeof(GLfloat) * input->Size; + r300_attr.dwords = input->Size; + } else { + type = input->Type; + r300_attr.free_needed = GL_FALSE; + r300_attr.data = (GLvoid *)src_ptr; + r300_attr.stride = input->StrideB; + r300_attr.dwords = getTypeSize(type) * input->Size / 4; + } + + r300_attr.size = input->Size; + r300_attr.element = attr; + r300_attr.dst_loc = vbuf->num_attribs; + + switch (type) { + case GL_FLOAT: + switch (input->Size) { + case 1: r300_attr.data_type = R300_DATA_TYPE_FLOAT_1; break; + case 2: r300_attr.data_type = R300_DATA_TYPE_FLOAT_2; break; + case 3: r300_attr.data_type = R300_DATA_TYPE_FLOAT_3; break; + case 4: r300_attr.data_type = R300_DATA_TYPE_FLOAT_4; break; + } + r300_attr._signed = 0; + r300_attr.normalize = 0; + break; + case GL_SHORT: + r300_attr._signed = 1; + r300_attr.normalize = input->Normalized; + if (input->Size == 2) + r300_attr.data_type = R300_DATA_TYPE_SHORT_2; + else if (input->Size == 4) + r300_attr.data_type = R300_DATA_TYPE_SHORT_4; + else + assert(0); + break; + case GL_BYTE: + assert(input->Size == 4); + r300_attr._signed = 1; + r300_attr.normalize = input->Normalized; + r300_attr.data_type = R300_DATA_TYPE_BYTE; + break; + case GL_UNSIGNED_SHORT: + r300_attr._signed = 0; + r300_attr.normalize = input->Normalized; + if (input->Size == 2) + r300_attr.data_type = R300_DATA_TYPE_SHORT_2; + else if (input->Size == 4) + r300_attr.data_type = R300_DATA_TYPE_SHORT_4; + else + assert(0); + break; + case GL_UNSIGNED_BYTE: + assert(input->Size == 4); + r300_attr._signed = 0; + r300_attr.normalize = input->Normalized; + if (input->Format == GL_BGRA) + r300_attr.data_type = R300_DATA_TYPE_D3DCOLOR; + else + r300_attr.data_type = R300_DATA_TYPE_BYTE; + break; + + default: + case GL_DOUBLE: + case GL_INT: + case GL_UNSIGNED_INT: + assert(0); + break; + } + + switch (input->Size) { + case 4: + r300_attr.swizzle = SWIZZLE_XYZW; + break; + case 3: + r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); + break; + case 2: + r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE); + break; + case 1: + r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); + break; + } + + r300_attr.write_mask = MASK_XYZW; + + vbuf->attribs[vbuf->num_attribs] = r300_attr; + ++vbuf->num_attribs; +} + +static void r300SetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], int count, struct gl_buffer_object **bo, GLuint *nr_bo) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_vertex_buffer *vbuf = &r300->vbuf; + + { + int i, tmp; + + tmp = r300->selected_vp->key.InputsRead; + i = 0; + vbuf->num_attribs = 0; + while (tmp) { + /* find first enabled bit */ + while (!(tmp & 1)) { + tmp >>= 1; + ++i; + } + + r300TranslateAttrib(ctx, i, count, arrays[i], bo, nr_bo); + + tmp >>= 1; + ++i; + } + } + + r300SwitchFallback(ctx, R300_FALLBACK_AOS_LIMIT, vbuf->num_attribs > R300_MAX_AOS_ARRAYS); + if (r300->fallback) + return; + + { + int i; + + for (i = 0; i < vbuf->num_attribs; i++) { + rcommon_emit_vector(ctx, &r300->radeon.tcl.aos[i], + vbuf->attribs[i].data, vbuf->attribs[i].dwords, + vbuf->attribs[i].stride, count); + } + + r300->radeon.tcl.aos_count = vbuf->num_attribs; + } +} + +static void r300FreeData(GLcontext *ctx, struct gl_buffer_object **bo, GLuint nr_bo) +{ + { + struct r300_vertex_buffer *vbuf = &R300_CONTEXT(ctx)->vbuf; + int i; + + for (i = 0; i < vbuf->num_attribs; i++) { + if (vbuf->attribs[i].free_needed) + _mesa_free(vbuf->attribs[i].data); + } + } + + { + struct r300_index_buffer *ind_buf = &R300_CONTEXT(ctx)->ind_buf; + if (ind_buf->free_needed) + _mesa_free(ind_buf->ptr); + } + + { + int i; + + for (i = 0; i < nr_bo; ++i) { + ctx->Driver.UnmapBuffer(ctx, 0, bo[i]); + } + } +} + +static GLboolean r300TryDrawPrims(GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLuint min_index, + GLuint max_index ) +{ + struct r300_context *r300 = R300_CONTEXT(ctx); + struct gl_buffer_object *bo[VERT_ATTRIB_MAX+1]; + GLuint i, nr_bo = 0; + + if (ctx->NewState) + _mesa_update_state( ctx ); + + if (r300->options.hw_tcl_enabled) + _tnl_UpdateFixedFunctionProgram(ctx); + + r300UpdateShaders(r300); + + r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, !r300ValidateBuffers(ctx)); + + r300FixupIndexBuffer(ctx, ib, bo, &nr_bo); + + r300SetVertexFormat(ctx, arrays, max_index + 1, bo, &nr_bo); + + if (r300->fallback) + return GL_FALSE; + + r300SetupVAP(ctx, r300->selected_vp->key.InputsRead, r300->selected_vp->key.OutputsWritten); + + r300UpdateShaderStates(r300); + + r300EmitCacheFlush(r300); + radeonEmitState(&r300->radeon); + + for (i = 0; i < nr_prims; ++i) { + r300RunRenderPrimitive(ctx, prim[i].start, prim[i].start + prim[i].count, prim[i].mode); + } + + r300EmitCacheFlush(r300); + + radeonReleaseArrays(ctx, ~0); + + r300FreeData(ctx, bo, nr_bo); + + return GL_TRUE; +} + +/* TODO: rebase if number of indices in any of primitives is > 8192 for 32bit indices or 16384 for 16bit indices */ + +static void r300DrawPrims(GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLuint min_index, + GLuint max_index) +{ + GLboolean retval; + + if (min_index) { + vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r300DrawPrims ); + return; + } + + /* Make an attempt at drawing */ + retval = r300TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); + + /* If failed run tnl pipeline - it should take care of fallbacks */ + if (!retval) + _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); +} + +void r300InitDraw(GLcontext *ctx) +{ + struct vbo_context *vbo = vbo_context(ctx); + + vbo->draw_prims = r300DrawPrims; +} diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 1e79a76b47f..d6c29ea3887 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -337,6 +337,11 @@ void r300EmitArrays(GLcontext * ctx) r300VAPOutputCntl1(ctx, OutputsWritten); rmesa->radeon.tcl.aos_count = nr; + + /* Fill index buffer info */ + rmesa->ind_buf.ptr = vb->Elts; + rmesa->ind_buf.is_32bit = GL_TRUE; + rmesa->ind_buf.free_needed = GL_FALSE; } void r300EmitCacheFlush(r300ContextPtr rmesa) diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 92310a02647..4982bc63b94 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -172,16 +172,19 @@ int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim) return num_verts - verts_off; } -static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) +static void r300EmitElts(GLcontext * ctx, unsigned long n_elts) { r300ContextPtr rmesa = R300_CONTEXT(ctx); void *out; + GLbyte el_size; + + el_size = rmesa->ind_buf.is_32bit ? 4 : 2; radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, - &rmesa->radeon.tcl.elt_dma_offset, n_elts * 4, 4); + &rmesa->radeon.tcl.elt_dma_offset, n_elts * el_size, 4); radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; - memcpy(out, elts, n_elts * 4); + memcpy(out, rmesa->ind_buf.ptr, n_elts * el_size); radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); } @@ -191,12 +194,20 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) r300_emit_scissor(rmesa->radeon.glCtx); if (vertex_count > 0) { + int size; + BEGIN_BATCH(10); OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - ((vertex_count + 0) << 16) | - type | + if (rmesa->ind_buf.is_32bit) { + size = vertex_count; + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | + ((vertex_count + 0) << 16) | type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit); + } else { + size = (vertex_count + 1) >> 1; + OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | + ((vertex_count + 0) << 16) | type); + } if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); @@ -206,13 +217,13 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) rmesa->radeon.tcl.elt_dma_bo, rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(vertex_count); + OUT_BATCH(size); } else { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | (R300_VAP_PORT_IDX0 >> 2)); OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); - OUT_BATCH(vertex_count); + OUT_BATCH(size); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -337,12 +348,10 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) END_BATCH(); } -static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, - int start, int end, int prim) +void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); int type, num_verts; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; type = r300PrimitiveType(rmesa, prim); num_verts = r300NumVerts(rmesa, end - start, prim); @@ -356,7 +365,7 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, */ rcommonEnsureCmdBufSpace(&rmesa->radeon, 64, __FUNCTION__); - if (vb->Elts) { + if (rmesa->ind_buf.ptr) { if (num_verts > 65535) { /* not implemented yet */ WARN_ONCE("Too many elts\n"); @@ -373,7 +382,7 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, * allocating the index array might actually evict the vertex * arrays. *sigh* */ - r300EmitElts(ctx, vb->Elts, num_verts); + r300EmitElts(ctx, num_verts); r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); r300FireEB(rmesa, num_verts, type); } else { @@ -383,8 +392,7 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, COMMIT_BATCH(); } -static void r300RunRender(GLcontext * ctx, - struct tnl_pipeline_stage *stage) +static void r300RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { r300ContextPtr rmesa = R300_CONTEXT(ctx); int i; @@ -406,7 +414,7 @@ static void r300RunRender(GLcontext * ctx, GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); GLuint start = vb->Primitive[i].start; GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; - r300RunRenderPrimitive(rmesa, ctx, start, end, prim); + r300RunRenderPrimitive(ctx, start, end, prim); } r300EmitCacheFlush(rmesa); @@ -436,6 +444,8 @@ static const char *getFallbackString(uint32_t bit) return "render mode != GL_RENDER"; case R300_FALLBACK_FRAGMENT_PROGRAM: return "fragment program"; + case R300_FALLBACK_AOS_LIMIT: + return "aos limit"; case R300_FALLBACK_INVALID_BUFFERS: return "invalid buffers"; default: @@ -504,30 +514,6 @@ static GLboolean r300RunNonTCLRender(GLcontext * ctx, return GL_FALSE; } -static GLboolean r300RunTCLRender(GLcontext * ctx, - struct tnl_pipeline_stage *stage) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->options.hw_tcl_enabled == GL_FALSE) - return GL_TRUE; - - /* Call it here so we can fallback early */ - r300UpdateShaders(rmesa); - - r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, !r300ValidateBuffers(ctx)); - - if (rmesa->fallback) - return GL_TRUE; - - r300RunRender(ctx, stage); - - return GL_FALSE; -} - const struct tnl_pipeline_stage _r300_render_stage = { "r300 Hardware Rasterization", NULL, @@ -536,12 +522,3 @@ const struct tnl_pipeline_stage _r300_render_stage = { NULL, r300RunNonTCLRender }; - -const struct tnl_pipeline_stage _r300_tcl_stage = { - "r300 Hardware Transform, Clipping and Lighting", - NULL, - NULL, - NULL, - NULL, - r300RunTCLRender -}; diff --git a/src/mesa/drivers/dri/r300/r300_render.h b/src/mesa/drivers/dri/r300/r300_render.h index 002cd613dc9..192d738f5ff 100644 --- a/src/mesa/drivers/dri/r300/r300_render.h +++ b/src/mesa/drivers/dri/r300/r300_render.h @@ -41,6 +41,7 @@ #define R300_FALLBACK_STENCIL_TWOSIDE (1 << 21) #define R300_FALLBACK_RENDER_MODE (1 << 22) #define R300_FALLBACK_FRAGMENT_PROGRAM (1 << 23) +#define R300_FALLBACK_AOS_LIMIT (1 << 30) #define R300_FALLBACK_INVALID_BUFFERS (1 << 31) #define R300_RASTER_FALLBACK_MASK 0xffff0000 @@ -52,8 +53,8 @@ extern const struct tnl_pipeline_stage _r300_render_stage; -extern const struct tnl_pipeline_stage _r300_tcl_stage; - extern void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode); +extern void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim); + #endif -- cgit v1.2.3 From 365799caea2fce684ac9c10ff14211b5d13cc46f Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 30 May 2009 13:19:07 +0200 Subject: r300: enable EXT_vertex_array_bgra extensions --- src/mesa/drivers/dri/r300/r300_context.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index b7911f23cce..9004a3ffab5 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -124,6 +124,7 @@ const struct dri_extension card_extensions[] = { {"GL_EXT_texture_lod_bias", NULL}, {"GL_EXT_texture_mirror_clamp", NULL}, {"GL_EXT_texture_rectangle", NULL}, + {"GL_EXT_vertex_array_bgra", NULL}, {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions}, {"GL_ATI_texture_env_combine3", NULL}, {"GL_ATI_texture_mirror_once", NULL}, -- cgit v1.2.3 From 6cd0628f9f35cc4529b94310e5356d15080a9d04 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 30 May 2009 15:09:19 +0200 Subject: r300: prepare for some code duplication removal --- src/mesa/drivers/dri/r300/r300_swtcl.c | 19 ++++++++++++++----- src/mesa/drivers/dri/r300/r300_swtcl.h | 1 + 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index fd6312ae261..ecc837745d3 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -67,7 +67,7 @@ do { \ ++num_attrs; \ } while (0) -static void r300SetVertexFormat( GLcontext *ctx ) +void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_OutputsWritten) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); @@ -219,8 +219,19 @@ static void r300SetVertexFormat( GLcontext *ctx ) ADD_ATTR(VERT_ATTRIB_FOG, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0); } - R300_NEWPRIM(rmesa); rmesa->vbuf.num_attribs = num_attrs; + *_InputsRead = InputsRead; + *_OutputsWritten = OutputsWritten; + + RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset); +} + +static void r300PrepareVertices(GLcontext *ctx) +{ + r300ContextPtr rmesa = R300_CONTEXT(ctx); + GLuint InputsRead, OutputsWritten; + + r300ChooseSwtclVertexFormat(ctx, &InputsRead, &OutputsWritten); r300SetupVAP(ctx, InputsRead, OutputsWritten); rmesa->radeon.swtcl.vertex_size = @@ -230,8 +241,6 @@ static void r300SetVertexFormat( GLcontext *ctx ) NULL, 0 ); rmesa->radeon.swtcl.vertex_size /= 4; - - RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset); } @@ -487,7 +496,7 @@ void r300RenderStart(GLcontext *ctx) r300ContextPtr rmesa = R300_CONTEXT( ctx ); r300ChooseRenderState(ctx); - r300SetVertexFormat(ctx); + r300PrepareVertices(ctx); r300ValidateBuffers(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index cebc895c47a..c271d265468 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -50,6 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SWTCL_OVM_TEX(n) ((n) + 6) #define SWTCL_OVM_POINT_SIZE 15 +extern void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *InputsRead, GLuint *OutputsWritten); extern void r300InitSwtcl( GLcontext *ctx ); extern void r300DestroySwtcl( GLcontext *ctx ); -- cgit v1.2.3 From 72c78b99926aab6af38248b5aa6b0fb1f9d42005 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 30 May 2009 13:50:50 +0200 Subject: r300: rewrite vertex setup for software T&L path using functions from software TCL path --- src/mesa/drivers/dri/r300/r300_emit.c | 230 ++++---------------------------- src/mesa/drivers/dri/r300/r300_emit.h | 5 +- src/mesa/drivers/dri/r300/r300_render.c | 19 +++ src/mesa/drivers/dri/r300/r300_render.h | 9 ++ 4 files changed, 54 insertions(+), 209 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index d6c29ea3887..cf31596d9b8 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -31,6 +31,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * \file * * \author Keith Whitwell + * \author Maciej Cencora */ #include "main/glheader.h" @@ -49,74 +50,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_state.h" #include "r300_emit.h" #include "r300_ioctl.h" - - -#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \ - SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \ - SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \ - SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \ - SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \ - SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE -#error Cannot change these! -#endif - -#define DEBUG_ALL DEBUG_VERTS - -#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \ - (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT) - -GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, - int *inputs, GLint * tab, GLuint nr) -{ - GLuint i, dw; - - /* type, inputs, stop bit, size */ - for (i = 0; i < nr; i += 2) { - /* make sure input is valid, would lockup the gpu */ - assert(inputs[tab[i]] != -1); - dw = (R300_SIGNED | DW_SIZE(i)); - if (i + 1 == nr) { - dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; - } else { - assert(inputs[tab[i + 1]] != -1); - dw |= (R300_SIGNED | - DW_SIZE(i + 1)) << R300_DATA_TYPE_1_SHIFT; - if (i + 2 == nr) { - dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; - } - } - dst[i >> 1] = dw; - } - - return (nr + 1) >> 1; -} - -static GLuint r300VAPInputRoute1Swizzle(int swizzle[4]) -{ - return (swizzle[0] << R300_SWIZZLE_SELECT_X_SHIFT) | - (swizzle[1] << R300_SWIZZLE_SELECT_Y_SHIFT) | - (swizzle[2] << R300_SWIZZLE_SELECT_Z_SHIFT) | - (swizzle[3] << R300_SWIZZLE_SELECT_W_SHIFT); -} - -GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr) -{ - GLuint i, dw; - - for (i = 0; i < nr; i += 2) { - dw = (r300VAPInputRoute1Swizzle(swizzle[i]) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | - R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT; - if (i + 1 < nr) { - dw |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | - R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; - } - dst[i >> 1] = dw; - } - - return (nr + 1) >> 1; -} +#include "r300_render.h" +#include "r300_swtcl.h" GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead) { @@ -194,154 +129,39 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) return ret; } -/* Emit vertex data to GART memory - * Route inputs to the vertex processor - */ -void r300EmitArrays(GLcontext * ctx) +GLboolean r300EmitArrays(GLcontext * ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - GLuint nr; - GLuint count = vb->Count; - GLuint i; - GLuint InputsRead = 0, OutputsWritten = 0; - int *inputs = NULL; - int vir_inputs[VERT_ATTRIB_MAX]; - GLint tab[VERT_ATTRIB_MAX]; - int swizzle[VERT_ATTRIB_MAX][4]; - struct r300_vertex_program *prog = rmesa->selected_vp; - - if (rmesa->options.hw_tcl_enabled) { - inputs = prog->inputs; - InputsRead = prog->key.InputsRead; - OutputsWritten = prog->key.OutputsWritten; - } else { - inputs = rmesa->swtcl.sw_tcl_inputs; - - DECLARE_RENDERINPUTS(render_inputs_bitset); - RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset); - - vb->AttribPtr[VERT_ATTRIB_POS] = vb->ClipPtr; - - assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)); - assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_NORMAL) == 0); - - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)) { - InputsRead |= 1 << VERT_ATTRIB_POS; - OutputsWritten |= 1 << VERT_RESULT_HPOS; - } + r300ContextPtr r300 = R300_CONTEXT(ctx); + struct r300_vertex_buffer *vbuf = &r300->vbuf; + GLuint InputsRead, OutputsWritten; - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR0)) { - InputsRead |= 1 << VERT_ATTRIB_COLOR0; - OutputsWritten |= 1 << VERT_RESULT_COL0; - } - - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR1)) { - InputsRead |= 1 << VERT_ATTRIB_COLOR1; - OutputsWritten |= 1 << VERT_RESULT_COL1; - } - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_TEX(i))) { - InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); - OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); - } - } - - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) { - inputs[i] = nr++; - } else { - inputs[i] = -1; - } - } + r300ChooseSwtclVertexFormat(ctx, &InputsRead, &OutputsWritten); - /* Fixed, apply to vir0 only */ - memcpy(vir_inputs, inputs, VERT_ATTRIB_MAX * sizeof(int)); - inputs = vir_inputs; - if (InputsRead & VERT_ATTRIB_POS) - inputs[VERT_ATTRIB_POS] = 0; - if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) - inputs[VERT_ATTRIB_COLOR0] = 2; - if (InputsRead & (1 << VERT_ATTRIB_COLOR1)) - inputs[VERT_ATTRIB_COLOR1] = 3; - for (i = VERT_ATTRIB_TEX0; i <= VERT_ATTRIB_TEX7; i++) - if (InputsRead & (1 << i)) - inputs[i] = 6 + (i - VERT_ATTRIB_TEX0); - - RENDERINPUTS_COPY(rmesa->render_inputs_bitset, render_inputs_bitset); - } + r300SwitchFallback(ctx, R300_FALLBACK_AOS_LIMIT, vbuf->num_attribs > R300_MAX_AOS_ARRAYS); + if (r300->fallback & R300_RASTER_FALLBACK_MASK) + return GL_FALSE; - assert(InputsRead); - assert(OutputsWritten); + { + struct vertex_buffer *mesa_vb = &TNL_CONTEXT(ctx)->vb; + GLuint attr, i; - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) { - tab[nr++] = i; + for (i = 0; i < vbuf->num_attribs; i++) { + attr = vbuf->attribs[i].element; + rcommon_emit_vector(ctx, &r300->radeon.tcl.aos[i], mesa_vb->AttribPtr[attr]->data, + mesa_vb->AttribPtr[attr]->size, mesa_vb->AttribPtr[attr]->stride, mesa_vb->Count); } - } - - assert(nr <= R300_MAX_AOS_ARRAYS); - for (i = 0; i < nr; i++) { - int ci; + r300->radeon.tcl.aos_count = vbuf->num_attribs; - swizzle[i][0] = SWIZZLE_ZERO; - swizzle[i][1] = SWIZZLE_ZERO; - swizzle[i][2] = SWIZZLE_ZERO; - swizzle[i][3] = SWIZZLE_ONE; - - for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { - swizzle[i][ci] = ci; - } - rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i], - vb->AttribPtr[tab[i]]->data, - vb->AttribPtr[tab[i]]->size, - vb->AttribPtr[tab[i]]->stride, count); + /* Fill index buffer info */ + r300->ind_buf.ptr = mesa_vb->Elts; + r300->ind_buf.is_32bit = GL_TRUE; + r300->ind_buf.free_needed = GL_FALSE; } - /* Setup INPUT_ROUTE. */ - if (rmesa->radeon.radeonScreen->kernel_mm) { - R300_STATECHANGE(rmesa, vir[0]); - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= - (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], - vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; - R300_STATECHANGE(rmesa, vir[1]); - rmesa->hw.vir[1].cmd[0] |= - (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, - nr) & 0x3FFF) << 16; - } else { - R300_STATECHANGE(rmesa, vir[0]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = - r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], - vb->AttribPtr, inputs, tab, nr); - R300_STATECHANGE(rmesa, vir[1]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = - r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, - nr); - } - - /* Setup INPUT_CNTL. */ - R300_STATECHANGE(rmesa, vic); - rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - - /* Setup OUTPUT_VTX_FMT. */ - R300_STATECHANGE(rmesa, vof); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = - r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = - r300VAPOutputCntl1(ctx, OutputsWritten); - - rmesa->radeon.tcl.aos_count = nr; + r300SetupVAP(ctx, InputsRead, OutputsWritten); - /* Fill index buffer info */ - rmesa->ind_buf.ptr = vb->Elts; - rmesa->ind_buf.is_32bit = GL_TRUE; - rmesa->ind_buf.free_needed = GL_FALSE; + return GL_TRUE; } void r300EmitCacheFlush(r300ContextPtr rmesa) diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index e6485e9bd75..d88914ce959 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -216,16 +216,13 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) } } -extern void r300EmitArrays(GLcontext * ctx); +extern GLboolean r300EmitArrays(GLcontext * ctx); extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); extern void r300EmitCacheFlush(r300ContextPtr rmesa); -extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, - int *inputs, GLint * tab, GLuint nr); -extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr); extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 4982bc63b94..adda92467a6 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -466,6 +466,16 @@ void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode) fallback_warn |= bit; } rmesa->fallback |= bit; + + /* update only if we change from no tcl fallbacks to some tcl fallbacks */ + if (rmesa->options.hw_tcl_enabled) { + if (((old_fallback & R300_TCL_FALLBACK_MASK) == 0) && + ((bit & R300_TCL_FALLBACK_MASK) > 0)) { + R300_STATECHANGE(rmesa, vap_cntl_status); + rmesa->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS; + } + } + /* update only if we change from no raster fallbacks to some raster fallbacks */ if (((old_fallback & R300_RASTER_FALLBACK_MASK) == 0) && ((bit & R300_RASTER_FALLBACK_MASK) > 0)) { @@ -476,6 +486,15 @@ void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode) } } else { rmesa->fallback &= ~bit; + + /* update only if we have disabled all tcl fallbacks */ + if (rmesa->options.hw_tcl_enabled) { + if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) { + R300_STATECHANGE(rmesa, vap_cntl_status); + rmesa->hw.vap_cntl_status.cmd[1] &= ~R300_VAP_TCL_BYPASS; + } + } + /* update only if we have disabled all raster fallbacks */ if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) { _swrast_flush( ctx ); diff --git a/src/mesa/drivers/dri/r300/r300_render.h b/src/mesa/drivers/dri/r300/r300_render.h index 192d738f5ff..ec785474a67 100644 --- a/src/mesa/drivers/dri/r300/r300_render.h +++ b/src/mesa/drivers/dri/r300/r300_render.h @@ -51,6 +51,15 @@ #define MASK_Z R300_WRITE_ENA_Z #define MASK_W R300_WRITE_ENA_W +#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \ + SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \ + SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \ + SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \ + SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \ + SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE +#error Cannot change these! +#endif + extern const struct tnl_pipeline_stage _r300_render_stage; extern void r300SwitchFallback(GLcontext *ctx, uint32_t bit, GLboolean mode); -- cgit v1.2.3 From a8c7c96be717fb65d23aea7a21f9f3969c4de53f Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 30 May 2009 16:12:53 +0200 Subject: r300: remove unused code --- src/mesa/drivers/dri/r300/r300_context.h | 2 -- src/mesa/drivers/dri/r300/r300_state.c | 5 +--- src/mesa/drivers/dri/r300/r300_vertprog.c | 48 ------------------------------- src/mesa/drivers/dri/r300/r300_vertprog.h | 1 - 4 files changed, 1 insertion(+), 55 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 11cfb55a9b5..026c33c67cb 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -583,8 +583,6 @@ struct r300_swtcl_info { * Offset of the 3UB specular color data within a hardware (swtcl) vertex. */ GLuint specoffset; - - int sw_tcl_inputs[VERT_ATTRIB_MAX]; }; struct r300_vtable { diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index a04326fca97..2fff89c473c 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2295,10 +2295,7 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) rmesa->vtbl.SetupRSUnit(ctx); if (rmesa->options.hw_tcl_enabled) { - if (rmesa->fallback & R300_FALLBACK_VERTEX_PROGRAM) - r300SetupSwtclVertexProgram(rmesa); - else - r300SetupVertexProgram(rmesa); + r300SetupVertexProgram(rmesa); } } diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 35e5ec0f8e7..a74b9156cf9 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -1492,54 +1492,6 @@ static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_ver } } -void r300SetupSwtclVertexProgram(r300ContextPtr rmesa) -{ - struct r300_vertex_shader_hw_code *hw_code; - GLuint o_reg = 0; - GLuint i_reg = 0; - int i; - int inst_count = 0; - int param_count = 0; - int program_end = 0; - - /* Reset state, in case we don't use something */ - ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0; - - hw_code = _mesa_malloc(sizeof(struct r300_vertex_shader_hw_code)); - - for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) { - if (rmesa->swtcl.sw_tcl_inputs[i] != -1) { - hw_code->body.d[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT); - hw_code->body.d[program_end + 1] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_X, - PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - hw_code->body.d[program_end + 2] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, - PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - hw_code->body.d[program_end + 3] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, - PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); - program_end += 4; - i_reg++; - } - } - - hw_code->length = program_end; - - r300EmitVertexProgram(rmesa, R300_PVS_CODE_START, hw_code); - inst_count = (hw_code->length / 4) - 1; - - r300VapCntl(rmesa, i_reg, o_reg, 0); - - R300_STATECHANGE(rmesa, pvs); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = (0 << R300_PVS_FIRST_INST_SHIFT) | (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | - (inst_count << R300_PVS_LAST_INST_SHIFT); - - rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); - - _mesa_free(hw_code); -} - void r300SetupVertexProgram(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.h b/src/mesa/drivers/dri/r300/r300_vertprog.h index 44b5f981a9a..b552e3fb1bd 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.h +++ b/src/mesa/drivers/dri/r300/r300_vertprog.h @@ -33,6 +33,5 @@ #endif void r300SetupVertexProgram(r300ContextPtr rmesa); -void r300SetupSwtclVertexProgram(r300ContextPtr rmesa); #endif -- cgit v1.2.3 From ca13937ef97c7779f639dcfc95b3798a11de01bd Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 31 May 2009 23:00:57 +0200 Subject: r300: GL_(U)SHORT and GL_(U)BYTE with < 4 components can also be HW accelerated MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also when index format is GL_UBYTE, convert it to GL_USHORT not GL_UINT. Fix license header too. Reported by: Nicolai Hähnle --- src/mesa/drivers/dri/r300/r300_draw.c | 49 +++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c index ba748787214..c9588fbb21c 100644 --- a/src/mesa/drivers/dri/r300/r300_draw.c +++ b/src/mesa/drivers/dri/r300/r300_draw.c @@ -17,7 +17,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * IN NO EVENT SHALL THE AUTHOR(S) AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -67,16 +67,16 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) { GLubyte *in = (GLubyte *)src_ptr; - GLuint *out = _mesa_malloc(sizeof(GLuint) * mesa_ind_buf->count); + GLushort *out = _mesa_malloc(sizeof(GLushort) * mesa_ind_buf->count); int i; for (i = 0; i < mesa_ind_buf->count; ++i) { - out[i] = (GLuint) in[i]; + out[i] = (GLushort) in[i]; } ind_buf->ptr = out; ind_buf->free_needed = GL_TRUE; - ind_buf->is_32bit = GL_TRUE; + ind_buf->is_32bit = GL_FALSE; } else if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) { ind_buf->ptr = src_ptr; ind_buf->free_needed = GL_FALSE; @@ -157,7 +157,7 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st } else src_ptr = input->Ptr; - if (input->Type == GL_DOUBLE || ((getTypeSize(input->Type) * input->Size) % 4 > 0)) { + if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || input->StrideB < 4){ if (RADEON_DEBUG & DEBUG_FALLBACKS) { fprintf(stderr, "%s: Converting vertex attributes, attribute data format %x,", __FUNCTION__, input->Type); fprintf(stderr, "stride %d, components %d\n", input->StrideB, input->Size); @@ -189,6 +189,9 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st case GL_BYTE: CONVERT(GLbyte, BYTE_TO_FLOAT); break; + default: + assert(0); + break; } type = GL_FLOAT; @@ -201,7 +204,7 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st r300_attr.free_needed = GL_FALSE; r300_attr.data = (GLvoid *)src_ptr; r300_attr.stride = input->StrideB; - r300_attr.dwords = getTypeSize(type) * input->Size / 4; + r300_attr.dwords = (getTypeSize(type) * input->Size + 3)/ 4; } r300_attr.size = input->Size; @@ -222,15 +225,18 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st case GL_SHORT: r300_attr._signed = 1; r300_attr.normalize = input->Normalized; - if (input->Size == 2) - r300_attr.data_type = R300_DATA_TYPE_SHORT_2; - else if (input->Size == 4) - r300_attr.data_type = R300_DATA_TYPE_SHORT_4; - else - assert(0); + switch (input->Size) { + case 1: + case 2: + r300_attr.data_type = R300_DATA_TYPE_SHORT_2; + break; + case 3: + case 4: + r300_attr.data_type = R300_DATA_TYPE_SHORT_4; + break; + } break; case GL_BYTE: - assert(input->Size == 4); r300_attr._signed = 1; r300_attr.normalize = input->Normalized; r300_attr.data_type = R300_DATA_TYPE_BYTE; @@ -238,15 +244,18 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st case GL_UNSIGNED_SHORT: r300_attr._signed = 0; r300_attr.normalize = input->Normalized; - if (input->Size == 2) - r300_attr.data_type = R300_DATA_TYPE_SHORT_2; - else if (input->Size == 4) - r300_attr.data_type = R300_DATA_TYPE_SHORT_4; - else - assert(0); + switch (input->Size) { + case 1: + case 2: + r300_attr.data_type = R300_DATA_TYPE_SHORT_2; + break; + case 3: + case 4: + r300_attr.data_type = R300_DATA_TYPE_SHORT_4; + break; + } break; case GL_UNSIGNED_BYTE: - assert(input->Size == 4); r300_attr._signed = 0; r300_attr.normalize = input->Normalized; if (input->Format == GL_BGRA) -- cgit v1.2.3 From 58982f8af1496c4860fb7bf3e815977ed4a753ff Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 5 Jun 2009 17:58:04 +0200 Subject: r300: vertex array stride = 0 means that data are tightly packed in the array --- src/mesa/drivers/dri/r300/r300_draw.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c index c9588fbb21c..684b1d0ef84 100644 --- a/src/mesa/drivers/dri/r300/r300_draw.c +++ b/src/mesa/drivers/dri/r300/r300_draw.c @@ -123,7 +123,7 @@ static int getTypeSize(GLenum type) *dst_ptr++ = MACRO(*in); \ in++; \ } \ - src_ptr += input->StrideB; \ + src_ptr += stride; \ } \ } else { \ for (i = 0; i < count; i++) { \ @@ -132,7 +132,7 @@ static int getTypeSize(GLenum type) *dst_ptr++ = (GLfloat)(*in); \ in++; \ } \ - src_ptr += input->StrideB; \ + src_ptr += stride; \ } \ } \ } while (0) @@ -144,6 +144,7 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st struct vertex_attribute r300_attr; const void *src_ptr; GLenum type; + GLuint stride; if (input->BufferObj->Name) { if (!input->BufferObj->Pointer) { @@ -157,10 +158,12 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st } else src_ptr = input->Ptr; - if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || input->StrideB < 4){ + stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB; + + if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || stride < 4){ if (RADEON_DEBUG & DEBUG_FALLBACKS) { fprintf(stderr, "%s: Converting vertex attributes, attribute data format %x,", __FUNCTION__, input->Type); - fprintf(stderr, "stride %d, components %d\n", input->StrideB, input->Size); + fprintf(stderr, "stride %d, components %d\n", stride, input->Size); } GLfloat *dst_ptr, *tmp; @@ -203,7 +206,7 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st type = input->Type; r300_attr.free_needed = GL_FALSE; r300_attr.data = (GLvoid *)src_ptr; - r300_attr.stride = input->StrideB; + r300_attr.stride = stride; r300_attr.dwords = (getTypeSize(type) * input->Size + 3)/ 4; } -- cgit v1.2.3 From e2aedfa62079ff1a333e1f4e56faea303cc36edb Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 4 Jun 2009 08:42:29 +0200 Subject: r300: Endianness fixes for recent vertex path changes. Signed-off-by: Maciej Cencora --- src/mesa/drivers/dri/r300/r300_draw.c | 38 ++++++++++++++++++++++++++++----- src/mesa/drivers/dri/r300/r300_render.c | 8 +++---- 2 files changed, 37 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c index 684b1d0ef84..cc5650fb7c8 100644 --- a/src/mesa/drivers/dri/r300/r300_draw.c +++ b/src/mesa/drivers/dri/r300/r300_draw.c @@ -67,19 +67,43 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) { GLubyte *in = (GLubyte *)src_ptr; - GLushort *out = _mesa_malloc(sizeof(GLushort) * mesa_ind_buf->count); + GLuint *out = _mesa_malloc(sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1)); int i; - for (i = 0; i < mesa_ind_buf->count; ++i) { - out[i] = (GLushort) in[i]; + ind_buf->ptr = out; + + for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) { + *out++ = in[i] | in[i + 1] << 16; + } + + if (i < mesa_ind_buf->count) { + *out++ = in[i]; } - ind_buf->ptr = out; ind_buf->free_needed = GL_TRUE; ind_buf->is_32bit = GL_FALSE; } else if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) { +#if MESA_BIG_ENDIAN + GLushort *in = (GLushort *)src_ptr; + GLuint *out = _mesa_malloc(sizeof(GLushort) * + ((mesa_ind_buf->count + 1) & ~1)); + int i; + + ind_buf->ptr = out; + + for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) { + *out++ = in[i] | in[i + 1] << 16; + } + + if (i < mesa_ind_buf->count) { + *out++ = in[i]; + } + + ind_buf->free_needed = GL_TRUE; +#else ind_buf->ptr = src_ptr; ind_buf->free_needed = GL_FALSE; +#endif ind_buf->is_32bit = GL_FALSE; } else { ind_buf->ptr = src_ptr; @@ -160,7 +184,11 @@ static void r300TranslateAttrib(GLcontext *ctx, GLuint attr, int count, const st stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB; - if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || stride < 4){ + if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || +#if MESA_BIG_ENDIAN + getTypeSize(input->Type) != 4 || +#endif + stride < 4) { if (RADEON_DEBUG & DEBUG_FALLBACKS) { fprintf(stderr, "%s: Converting vertex attributes, attribute data format %x,", __FUNCTION__, input->Type); fprintf(stderr, "stride %d, components %d\n", stride, input->Size); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index adda92467a6..dfbd79a3895 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -176,15 +176,15 @@ static void r300EmitElts(GLcontext * ctx, unsigned long n_elts) { r300ContextPtr rmesa = R300_CONTEXT(ctx); void *out; - GLbyte el_size; + GLuint size; - el_size = rmesa->ind_buf.is_32bit ? 4 : 2; + size = ((rmesa->ind_buf.is_32bit ? 4 : 2) * n_elts + 3) & ~3; radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, - &rmesa->radeon.tcl.elt_dma_offset, n_elts * el_size, 4); + &rmesa->radeon.tcl.elt_dma_offset, size, 4); radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; - memcpy(out, rmesa->ind_buf.ptr, n_elts * el_size); + memcpy(out, rmesa->ind_buf.ptr, size); radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); } -- cgit v1.2.3 From db63f638974f90557a52c66b0f2e9d5a92e697d0 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 7 Jun 2009 22:51:46 +0200 Subject: r300: fix regression caused by 056bc77547c304021a0faf204897ed238a5cf424 Fixes GPU hangs in software TCL path --- src/mesa/drivers/dri/r300/r300_swtcl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index ecc837745d3..4a820648145 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -219,6 +219,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ ADD_ATTR(VERT_ATTRIB_FOG, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0); } + R300_NEWPRIM(rmesa); rmesa->vbuf.num_attribs = num_attrs; *_InputsRead = InputsRead; *_OutputsWritten = OutputsWritten; -- cgit v1.2.3 From 18b3cbcede292ce7b90b818b6abb064869072ff3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 9 Jun 2009 13:52:58 +1000 Subject: radeon: fix mipmap_limits crasher. This gets the correct srclvl image map when uploading images to the new mipmap. --- src/mesa/drivers/dri/radeon/radeon_texture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 564da19f58e..0d87f152e99 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -830,7 +830,7 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag * In fact, that memcpy() could be done by the hardware in many * cases, provided that we have a proper memory manager. */ - radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; + radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel-image->mt->firstLevel]; assert(srclvl->size == dstlvl->size); assert(srclvl->rowstride == dstlvl->rowstride); -- cgit v1.2.3 From 316598b96f07a38752c0c0f534feb025ee2a3235 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 10 Jun 2009 14:59:33 +0200 Subject: r300: make sure indexed rendering doesn't try to use more than the num of vertices When with memory manager we need to make sure the GPU won't try to access beyond vertex buffer size, do so by enforcing that the maximun index is the last vertex of the buffer. --- src/mesa/drivers/dri/r300/r300_render.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index dfbd79a3895..c2c532a9a86 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -351,6 +351,7 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) { r300ContextPtr rmesa = R300_CONTEXT(ctx); + BATCH_LOCALS(&rmesa->radeon); int type, num_verts; type = r300PrimitiveType(rmesa, prim); @@ -384,6 +385,12 @@ void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) */ r300EmitElts(ctx, num_verts); r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); + if (rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1); + OUT_BATCH(num_verts); + END_BATCH(); + } r300FireEB(rmesa, num_verts, type); } else { r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); -- cgit v1.2.3 From b445e5486804581ba4a7d1fce80c3ad2ed773325 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 11 Jun 2009 11:06:14 +0200 Subject: r300: fix indexed primitive rendering when using memory manager --- src/mesa/drivers/dri/r300/r300_render.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index c2c532a9a86..1356305a212 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -364,7 +364,7 @@ void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) * This is supposed to ensure that we can get all rendering * commands into a single command buffer. */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, 64, __FUNCTION__); + rcommonEnsureCmdBufSpace(&rmesa->radeon, 128, __FUNCTION__); if (rmesa->ind_buf.ptr) { if (num_verts > 65535) { @@ -388,7 +388,7 @@ void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) if (rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH_NO_AUTOSTATE(2); OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1); - OUT_BATCH(num_verts); + OUT_BATCH(rmesa->radeon.tcl.aos[0].count); END_BATCH(); } r300FireEB(rmesa, num_verts, type); -- cgit v1.2.3 From b4ebd1c191e6760b334c35fa1df025ad129cc449 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 5 Jun 2009 18:00:58 +0200 Subject: r300: hw doesn't support saturation for tex instructions --- src/mesa/drivers/dri/r300/r300_fragprog.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index ea530fd00e7..55c1cfe6317 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -140,6 +140,8 @@ GLboolean r300_transform_TEX( inst.DstReg.Index = tempreg; inst.DstReg.WriteMask = WRITEMASK_XYZW; destredirect = GL_TRUE; + } else if (inst.SaturateMode) { + destredirect = GL_TRUE; } } @@ -219,6 +221,7 @@ GLboolean r300_transform_TEX( tgt->Opcode = OPCODE_MOV; tgt->DstReg = orig_inst->DstReg; + tgt->SaturateMode = inst.SaturateMode; tgt->SrcReg[0].File = PROGRAM_TEMPORARY; tgt->SrcReg[0].Index = inst.DstReg.Index; } -- cgit v1.2.3 From 28724b575d2c003d7f10f55dcb03ac969df94389 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 5 Jun 2009 18:14:15 +0200 Subject: r300: fix output register allocation for vertex shaders If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases. --- src/mesa/drivers/dri/r300/r300_vertprog.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index a74b9156cf9..1cacebf3666 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -955,26 +955,36 @@ static void t_inputs_outputs(struct r300_vertex_program *vp) vp->outputs[VERT_RESULT_PSIZ] = cur_reg++; } + /* If we're writing back facing colors we need to send + * four colors to make front/back face colors selection work. + * If the vertex program doesn't write all 4 colors, lets + * pretend it does by skipping output index reg so the colors + * get written into appropriate output vectors. + */ if (vp->key.OutputsWritten & (1 << VERT_RESULT_COL0)) { vp->outputs[VERT_RESULT_COL0] = cur_reg++; + } else if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC0) || + vp->key.OutputsWritten & (1 << VERT_RESULT_BFC1)) { + cur_reg++; } if (vp->key.OutputsWritten & (1 << VERT_RESULT_COL1)) { - vp->outputs[VERT_RESULT_COL1] = - vp->outputs[VERT_RESULT_COL0] + 1; - cur_reg = vp->outputs[VERT_RESULT_COL1] + 1; + vp->outputs[VERT_RESULT_COL1] = cur_reg++; + } else if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC0) || + vp->key.OutputsWritten & (1 << VERT_RESULT_BFC1)) { + cur_reg++; } if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC0)) { - vp->outputs[VERT_RESULT_BFC0] = - vp->outputs[VERT_RESULT_COL0] + 2; - cur_reg = vp->outputs[VERT_RESULT_BFC0] + 2; + vp->outputs[VERT_RESULT_BFC0] = cur_reg++; + } else if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC1)) { + cur_reg++; } if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC1)) { - vp->outputs[VERT_RESULT_BFC1] = - vp->outputs[VERT_RESULT_COL0] + 3; - cur_reg = vp->outputs[VERT_RESULT_BFC1] + 1; + vp->outputs[VERT_RESULT_BFC1] = cur_reg++; + } else if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC0)) { + cur_reg++; } for (i = VERT_RESULT_TEX0; i <= VERT_RESULT_TEX7; i++) { -- cgit v1.2.3 From 52645c46475bf959f43adb2a8244568b2f607f98 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 5 Jun 2009 18:23:55 +0200 Subject: r300: print vertex program when debugging is enabled --- src/mesa/drivers/dri/r300/r300_vertprog.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 1cacebf3666..46e1527ba27 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -34,6 +34,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "shader/program.h" #include "shader/prog_instruction.h" #include "shader/prog_parameter.h" +#include "shader/prog_print.h" #include "shader/prog_statevars.h" #include "tnl/tnl.h" @@ -1383,6 +1384,12 @@ static struct r300_vertex_program *build_program(struct r300_vertex_program_key pos_as_texcoord(vp, &mesa_vp->Base); } + if (RADEON_DEBUG & DEBUG_VERTS) { + fprintf(stderr, "Vertex program after native rewrite:\n"); + _mesa_print_program(&mesa_vp->Base); + fflush(stdout); + } + assert(mesa_vp->Base.NumInstructions); vp->num_temporaries = mesa_vp->Base.NumTemporaries; r300TranslateVertexShader(vp, mesa_vp->Base.Instructions); @@ -1456,7 +1463,12 @@ void r300SelectVertexShader(r300ContextPtr r300) r300->selected_vp = vp; return; } - //_mesa_print_program(&vpc->mesa_program.Base); + + if (RADEON_DEBUG & DEBUG_VERTS) { + fprintf(stderr, "Initial vertex program:\n"); + _mesa_print_program(&vpc->mesa_program.Base); + fflush(stdout); + } vp = build_program(&wanted_key, &vpc->mesa_program, wpos_idx); vp->next = vpc->progs; @@ -1518,8 +1530,7 @@ void r300SetupVertexProgram(r300ContextPtr rmesa) param_count = r300VertexProgUpdateParams(ctx, (struct r300_vertex_program_cont *) ctx->VertexProgram._Current, - (float *)&rmesa->hw.vpp. - cmd[R300_VPP_PARAM_0]); + (float *)&rmesa->hw.vpp.cmd[R300_VPP_PARAM_0]); bump_vpu_count(rmesa->hw.vpp.cmd, param_count); param_count /= 4; -- cgit v1.2.3 From 2611e92da59ed3aedb0627889e185b63d4e5a532 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 5 Jun 2009 18:27:00 +0200 Subject: r300: move some code for easier debugging --- src/mesa/drivers/dri/r300/r300_vertprog.c | 54 +++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 46e1527ba27..66750b1c659 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -1185,23 +1185,6 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp, } } - /* Some outputs may be artificially added, to match the inputs - of the fragment program. Blank the outputs here. */ - for (i = 0; i < VERT_RESULT_MAX; i++) { - if (vp->key.OutputsAdded & (1 << i)) { - inst[0] = PVS_OP_DST_OPERAND(VE_ADD, - GL_FALSE, - GL_FALSE, - vp->outputs[i], - VSF_FLAG_ALL, - PVS_DST_REG_OUT); - inst[1] = __CONST(0, SWIZZLE_ZERO); - inst[2] = __CONST(0, SWIZZLE_ZERO); - inst[3] = __CONST(0, SWIZZLE_ZERO); - inst += 4; - } - } - vp->hw_code.length = (inst - vp->hw_code.body.d); if (vp->hw_code.length >= VSF_MAX_FRAGMENT_LENGTH) { vp->error = GL_TRUE; @@ -1390,6 +1373,43 @@ static struct r300_vertex_program *build_program(struct r300_vertex_program_key fflush(stdout); } + /* Some outputs may be artificially added, to match the inputs of the fragment program. + * Issue 16 of vertex program spec says that all vertex attributes that are unwritten by + * vertex program are undefined, so just use MOV [vertex_result], CONST[0] + */ + { + int i, count = 0; + for (i = 0; i < VERT_RESULT_MAX; ++i) { + if (vp->key.OutputsAdded & (1 << i)) { + ++count; + } + } + + if (count > 0) { + struct prog_instruction *inst; + + _mesa_insert_instructions(&mesa_vp->Base, mesa_vp->Base.NumInstructions - 1, count); + inst = &mesa_vp->Base.Instructions[mesa_vp->Base.NumInstructions - 1 - count]; + + for (i = 0; i < VERT_RESULT_MAX; ++i) { + if (vp->key.OutputsAdded & (1 << i)) { + inst->Opcode = OPCODE_MOV; + + inst->DstReg.File = PROGRAM_OUTPUT; + inst->DstReg.Index = i; + inst->DstReg.WriteMask = WRITEMASK_XYZW; + inst->DstReg.CondMask = COND_TR; + + inst->SrcReg[0].File = PROGRAM_CONSTANT; + inst->SrcReg[0].Index = 0; + inst->SrcReg[0].Swizzle = SWIZZLE_XYZW; + + ++inst; + } + } + } + } + assert(mesa_vp->Base.NumInstructions); vp->num_temporaries = mesa_vp->Base.NumTemporaries; r300TranslateVertexShader(vp, mesa_vp->Base.Instructions); -- cgit v1.2.3 From de19eb0b0dba08b2ad3829b7ced94931139af843 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 5 Jun 2009 18:32:05 +0200 Subject: r300: fix vertex program bug If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests. --- src/mesa/drivers/dri/r300/r300_vertprog.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 66750b1c659..c41a8fdd621 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -1456,7 +1456,12 @@ void r300SelectVertexShader(r300ContextPtr r300) wpos_idx = i; } - add_outputs(&wanted_key, VERT_RESULT_HPOS); + if (vpc->mesa_program.IsPositionInvariant) { + wanted_key.InputsRead |= (1 << VERT_ATTRIB_POS); + wanted_key.OutputsWritten |= (1 << VERT_RESULT_HPOS); + } else { + add_outputs(&wanted_key, VERT_RESULT_HPOS); + } if (InputsRead & FRAG_BIT_COL0) { add_outputs(&wanted_key, VERT_RESULT_COL0); @@ -1466,17 +1471,16 @@ void r300SelectVertexShader(r300ContextPtr r300) add_outputs(&wanted_key, VERT_RESULT_COL1); } + if (InputsRead & FRAG_BIT_FOGC) { + add_outputs(&wanted_key, VERT_RESULT_FOGC); + } + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (InputsRead & (FRAG_BIT_TEX0 << i)) { add_outputs(&wanted_key, VERT_RESULT_TEX0 + i); } } - if (vpc->mesa_program.IsPositionInvariant) { - /* we wan't position don't we ? */ - wanted_key.InputsRead |= (1 << VERT_ATTRIB_POS); - } - for (vp = vpc->progs; vp; vp = vp->next) if (_mesa_memcmp(&vp->key, &wanted_key, sizeof(wanted_key)) == 0) { -- cgit v1.2.3 From 9abc72d1fc0aada59a76bd602ebc36db9a729b5b Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 7 Jun 2009 21:34:44 +0200 Subject: r300: fix a GPU lock up Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK. --- src/mesa/drivers/dri/r300/r300_emit.c | 33 ++++++++++++++++++--------------- src/mesa/drivers/dri/r300/r300_emit.h | 4 ++-- src/mesa/drivers/dri/r300/r300_state.c | 8 ++++---- 3 files changed, 24 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index cf31596d9b8..4017224b10a 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -81,49 +81,52 @@ GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) return vic_1; } -GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten) +GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint vp_writes, GLuint fp_reads) { GLuint ret = 0; - if (OutputsWritten & (1 << VERT_RESULT_HPOS)) + if (vp_writes & (1 << VERT_RESULT_HPOS)) ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; - if (OutputsWritten & (1 << VERT_RESULT_COL0)) + if (vp_writes & (1 << VERT_RESULT_COL0) && fp_reads & FRAG_BIT_COL0) ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT; - if (OutputsWritten & (1 << VERT_RESULT_COL1)) + if (vp_writes & (1 << VERT_RESULT_COL1) && fp_reads & FRAG_BIT_COL1) ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; - if (OutputsWritten & (1 << VERT_RESULT_BFC0) - || OutputsWritten & (1 << VERT_RESULT_BFC1)) - ret |= - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; + /* Two sided lighting works only if all 4 colors are written */ + if (vp_writes & (1 << VERT_RESULT_BFC0) || vp_writes & (1 << VERT_RESULT_BFC1)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT | + R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; - if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) + if (vp_writes & (1 << VERT_RESULT_PSIZ)) ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; return ret; } -GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) +GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint vp_writes, GLuint fp_reads) { GLuint i, ret = 0, first_free_texcoord = 0; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (OutputsWritten & (1 << (VERT_RESULT_TEX0 + i))) { + if (vp_writes & (1 << (VERT_RESULT_TEX0 + i)) && fp_reads & FRAG_BIT_TEX(i)) { ret |= (4 << (3 * i)); ++first_free_texcoord; } } - if (OutputsWritten & (1 << VERT_RESULT_FOGC)) { + if (fp_reads & FRAG_BIT_WPOS) { + ret |= (4 << (3 * first_free_texcoord)); + ++first_free_texcoord; + } + + if (vp_writes & (1 << VERT_RESULT_FOGC) && fp_reads & FRAG_BIT_FOGC) { if (first_free_texcoord > 8) { fprintf(stderr, "\tout of free texcoords to write fog coord\n"); _mesa_exit(-1); } - ret |= 1 << (3 * first_free_texcoord); + ret |= 4 << (3 * first_free_texcoord); } return ret; diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index d88914ce959..2fb8b82d3a1 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -225,7 +225,7 @@ extern void r300EmitCacheFlush(r300ContextPtr rmesa); extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); -extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); -extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten); +extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint vp_writes, GLuint fp_reads); +extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint vp_writes, GLuint fp_reads); #endif diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 2fff89c473c..b509c13b432 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1536,7 +1536,7 @@ static void r300SetupRSUnit(GLcontext * ctx) r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_Q(R300_RS_SEL_K1) | R300_RS_TEX_PTR(rs_tex_count); r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_FOGC; - rs_tex_count += 1; + rs_tex_count += 4; ++tex_ip; ++fp_reg; } else { @@ -1662,7 +1662,7 @@ static void r500SetupRSUnit(GLcontext * ctx) r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_FOGC; - rs_tex_count += 1; + rs_tex_count += 4; ++tex_ip; ++fp_reg; } else { @@ -2270,8 +2270,8 @@ void r300SetupVAP(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); + rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten, ctx->FragmentProgram._Current->Base.InputsRead); + rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten, ctx->FragmentProgram._Current->Base.InputsRead); } void r300UpdateShaderStates(r300ContextPtr rmesa) -- cgit v1.2.3 From e21e82f42549aa78214f3339a13b79791406dde0 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 7 Jun 2009 21:27:52 +0200 Subject: radeon: increase max bo count --- src/mesa/drivers/dri/radeon/radeon_common_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index e995062657f..061168fe96b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -378,7 +378,7 @@ typedef void (*radeon_line_func) (radeonContextPtr, typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); -#define RADEON_MAX_BOS 24 +#define RADEON_MAX_BOS 32 struct radeon_state { struct radeon_colorbuffer_state color; struct radeon_depthbuffer_state depth; -- cgit v1.2.3 From 34cb4b6be36ccb03b4c0c76ecc3587984dd284dc Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 10 Jun 2009 04:09:33 +0200 Subject: r300: r500 fragment program fixes - when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory --- src/mesa/drivers/dri/r300/r500_fragprog.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 8f0b70ad3a3..4d58cf21622 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -196,22 +196,20 @@ GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) if (reg.Abs) return GL_FALSE; + if (opcode == OPCODE_KIL && (reg.Swizzle != SWIZZLE_NOOP || reg.Negate != NEGATE_NONE)) + return GL_FALSE; + if (reg.Negate) reg.Negate ^= NEGATE_XYZW; - if (opcode == OPCODE_KIL) { - if (reg.Swizzle != SWIZZLE_NOOP) - return GL_FALSE; - } else { - for(i = 0; i < 4; ++i) { - GLuint swz = GET_SWZ(reg.Swizzle, i); - if (swz == SWIZZLE_NIL) { - reg.Negate &= ~(1 << i); - continue; - } - if (swz >= 4) - return GL_FALSE; + for(i = 0; i < 4; ++i) { + GLuint swz = GET_SWZ(reg.Swizzle, i); + if (swz == SWIZZLE_NIL) { + reg.Negate &= ~(1 << i); + continue; } + if (swz >= 4) + return GL_FALSE; } if (reg.Negate) @@ -273,6 +271,7 @@ void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, inst->DstReg = dst; inst->DstReg.WriteMask = negatebase[i]; inst->SrcReg[0] = src; + inst->SrcReg[0].Negate = (i == 0) ? NEGATE_NONE : NEGATE_XYZW; inst++; s->IP++; } -- cgit v1.2.3 From 2b5f8d2b5514cf6239e822b8fd24a752e35cf7eb Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 11 Jun 2009 00:43:55 +0200 Subject: r300: fix RS setup when no colors and textures are sent to FP RS_COL_FMT field is part of RS_IP_* reg not RS_INST_* --- src/mesa/drivers/dri/r300/r300_state.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index b509c13b432..06dba2a6508 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1546,7 +1546,8 @@ static void r300SetupRSUnit(GLcontext * ctx) /* Setup default color if no color or tex was set */ if (rs_tex_count == 0 && col_ip == 0) { - r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001); + r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_ADDR(0); + r300->hw.ri.cmd[R300_RI_INTERP_0] = R300_RS_COL_PTR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001); ++col_ip; } @@ -1672,13 +1673,14 @@ static void r500SetupRSUnit(GLcontext * ctx) /* Setup default color if no color or tex was set */ if (rs_tex_count == 0 && col_ip == 0) { - r300->hw.rr.cmd[R300_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001); + r300->hw.rr.cmd[R300_RR_INST_0] = R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_ADDR(0); + r300->hw.ri.cmd[R300_RI_INTERP_0] = R500_RS_COL_PTR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001); ++col_ip; } high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; - r300->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1); + r300->hw.rc.cmd[1] = (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; + r300->hw.rc.cmd[2] = 0xC0 | (high_rr - 1); r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr); -- cgit v1.2.3 From b5d49cb195eef4c0bf8288c3d675513244b46dbb Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 10 Jun 2009 16:04:35 +0200 Subject: r300: send only RS_IP_* regs that we are going to use --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 12 ++---------- src/mesa/drivers/dri/r300/r300_state.c | 2 ++ 2 files changed, 4 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index b949c3b5b21..0261a5b1d8a 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -479,7 +479,6 @@ void r300InitCmdBuf(r300ContextPtr r300) int mtu; int has_tcl; int is_r500 = 0; - int i; has_tcl = r300->options.hw_tcl_enabled; @@ -589,19 +588,12 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0); r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2); if (is_r500) { - ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0); + ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0); r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16); - for (i = 0; i < 8; i++) { - r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); - } ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1); } else { - ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0); + ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0); r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8); ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 06dba2a6508..c0eda977db8 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1556,6 +1556,7 @@ static void r300SetupRSUnit(GLcontext * ctx) r300->hw.rc.cmd[2] |= high_rr - 1; r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr); + r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, high_rr); if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); @@ -1683,6 +1684,7 @@ static void r500SetupRSUnit(GLcontext * ctx) r300->hw.rc.cmd[2] = 0xC0 | (high_rr - 1); r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr); + r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, high_rr); if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); -- cgit v1.2.3 From 8d728b8fe73d935308275ad0a21c67e2e22029c4 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 10 Jun 2009 16:56:51 +0200 Subject: r300: don't send unused attributes for SW TCL path --- src/mesa/drivers/dri/r300/r300_swtcl.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 4a820648145..f3171c081eb 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -76,6 +76,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ GLuint InputsRead = 0; GLuint OutputsWritten = 0; int num_attrs = 0; + GLuint fp_reads = ctx->FragmentProgram._Current->Base.InputsRead; struct vertex_attribute *attrs = rmesa->vbuf.attribs; rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0; @@ -84,15 +85,14 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ /* We always want non Ndc coords format */ VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS)) { - InputsRead |= 1 << VERT_ATTRIB_POS; - OutputsWritten |= 1 << VERT_RESULT_HPOS; - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0); - rmesa->swtcl.coloroffset = 4; - } + /* Always write position vector */ + InputsRead |= 1 << VERT_ATTRIB_POS; + OutputsWritten |= 1 << VERT_RESULT_HPOS; + EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); + ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0); + rmesa->swtcl.coloroffset = 4; - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR0)) { + if (fp_reads & FRAG_BIT_COL0) { InputsRead |= 1 << VERT_ATTRIB_COLOR0; OutputsWritten |= 1 << VERT_RESULT_COL0; #if MESA_LITTLE_ENDIAN @@ -104,7 +104,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ #endif } - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 )) { + if (fp_reads & FRAG_BIT_COL1) { GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); InputsRead |= 1 << VERT_ATTRIB_COLOR1; OutputsWritten |= 1 << VERT_RESULT_COL1; @@ -128,7 +128,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR ); ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1); #endif - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 )) { + if (fp_reads & FRAG_BIT_COL1) { VB->AttribPtr[VERT_ATTRIB_GENERIC1] = VB->SecondaryColorPtr[1]; GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); OutputsWritten |= 1 << VERT_RESULT_BFC1; @@ -154,11 +154,11 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ * Sending only one texcoord component may lead to lock up, * so for all textures always output 4 texcoord components to RS. */ - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { + { int i; GLuint swiz, format, hw_format; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { + if (fp_reads & FRAG_BIT_TEX(i)) { switch (VB->TexCoordPtr[i]->size) { case 1: format = EMIT_1F; @@ -193,7 +193,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ } /* RS can't put fragment position on the pixel stack, so stuff it in texcoord if needed */ - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS) && (ctx->FragmentProgram._Current->Base.InputsRead & FRAG_BIT_WPOS)) { + if (fp_reads & FRAG_BIT_WPOS) { if (first_free_tex >= ctx->Const.MaxTextureUnits) { fprintf(stderr, "\tout of free texcoords to write w pos\n"); _mesa_exit(-1); @@ -206,7 +206,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ ++first_free_tex; } - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_FOG)) { + if (fp_reads & FRAG_BIT_FOGC) { if (first_free_tex >= ctx->Const.MaxTextureUnits) { fprintf(stderr, "\tout of free texcoords to write fog coordinate\n"); _mesa_exit(-1); -- cgit v1.2.3 From 234797564dea00c1463faa7a7791df466f52a91b Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 10 Jun 2009 16:58:15 +0200 Subject: r300: fix for SW TCL path We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8. --- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index f3171c081eb..ce4179208eb 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -186,7 +186,7 @@ void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_ InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); - ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(i), swiz, MASK_XYZW, 0); + ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0); ++first_free_tex; } } -- cgit v1.2.3 From 67bbfb9c68d0bf459f706a4cb50caf8245a37a34 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 10 Jun 2009 17:05:38 +0200 Subject: r300: fix VAP setup If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang. --- src/mesa/drivers/dri/r300/r300_emit.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4017224b10a..c3817721dc4 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -111,7 +111,7 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint vp_writes, GLuint fp_reads) for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (vp_writes & (1 << (VERT_RESULT_TEX0 + i)) && fp_reads & FRAG_BIT_TEX(i)) { - ret |= (4 << (3 * i)); + ret |= (4 << (3 * first_free_texcoord)); ++first_free_texcoord; } } @@ -122,13 +122,14 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint vp_writes, GLuint fp_reads) } if (vp_writes & (1 << VERT_RESULT_FOGC) && fp_reads & FRAG_BIT_FOGC) { - if (first_free_texcoord > 8) { - fprintf(stderr, "\tout of free texcoords to write fog coord\n"); - _mesa_exit(-1); - } ret |= 4 << (3 * first_free_texcoord); } + if (first_free_texcoord > 8) { + fprintf(stderr, "\tout of free texcoords\n"); + _mesa_exit(-1); + } + return ret; } -- cgit v1.2.3