From 8f4340c5e63d5bb2dd69a09d044832390ea47e14 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Tue, 12 Apr 2016 15:19:31 -0400 Subject: radeon/uvd: fix tonga feedback buffer size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This only applies to tonga Signed-off-by: Leo Liu Reviewed-by: Christian König Cc: "11.1 11.2" --- src/gallium/drivers/radeon/radeon_uvd.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 098baf20797..b775cd34083 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -57,6 +57,7 @@ #define FB_BUFFER_OFFSET 0x1000 #define FB_BUFFER_SIZE 2048 +#define FB_BUFFER_SIZE_TONGA (2048 * 64) #define IT_SCALING_TABLE_SIZE 992 /* UVD decoder representation */ @@ -78,6 +79,7 @@ struct ruvd_decoder { struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS]; struct ruvd_msg *msg; uint32_t *fb; + unsigned fb_size; uint8_t *it; struct rvid_buffer bs_buffers[NUM_BUFFERS]; @@ -148,7 +150,7 @@ static void map_msg_fb_it_buf(struct ruvd_decoder *dec) dec->msg = (struct ruvd_msg *)ptr; dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET); if (have_it(dec)) - dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE); + dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size); } /* unmap and send a message command to the VCPU */ @@ -1050,7 +1052,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, dec->msg->body.decode.extension_support = 0x1; /* set at least the feedback buffer size */ - dec->fb[0] = FB_BUFFER_SIZE; + dec->fb[0] = dec->fb_size; send_msg_buf(dec); @@ -1068,7 +1070,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT); if (have_it(dec)) send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf, - FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT); + FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT); set_reg(dec, RUVD_ENGINE_CNTL, 1); flush(dec); @@ -1148,9 +1150,11 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context, goto error; } + dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA : + FB_BUFFER_SIZE; bs_buf_size = width * height * 512 / (16 * 16); for (i = 0; i < NUM_BUFFERS; ++i) { - unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE; + unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size; STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET); if (have_it(dec)) msg_fb_it_size += IT_SCALING_TABLE_SIZE; -- cgit v1.2.3 From 7a835b3fd9b171eedecfdb23d326eae4bc0cb6d4 Mon Sep 17 00:00:00 2001 From: Chad Versace Date: Mon, 11 Apr 2016 15:12:15 -0700 Subject: dri: Fix robust context creation via EGL attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit driCreateContextAttribs() emits an error if bit __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS is set for an ES context. But, EGL_EXT_create_context_robustness and EGL 1.5 both allow creation of robust ES contexts. One requests a robust ES context by setting the EGL_CONTEXT_OPENGL_ROBUST_ACCESS *attribute*, which Mesa's EGL layer translates into the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS *bit*. Reviewed-by: Marek Olšák --- src/mesa/drivers/dri/common/dri_util.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index a6545084e31..79cb0506dd8 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -376,11 +376,32 @@ driCreateContextAttribs(__DRIscreen *screen, int api, * EGL_CONTEXT_FLAGS_KHR, then a will be created. * [...] This bit is supported for OpenGL and OpenGL ES contexts. * - * None of the other flags have any meaning in an ES context, so this seems safe. + * No other EGL_CONTEXT_OPENGL_*_BIT is legal for an ES context. + * + * However, Mesa's EGL layer translates the context attribute + * EGL_CONTEXT_OPENGL_ROBUST_ACCESS into the context flag + * __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS. That attribute is legal for ES + * (with EGL 1.5 or EGL_EXT_create_context_robustness) and GL (only with + * EGL 1.5). + * + * From the EGL_EXT_create_context_robustness spec: + * + * This extension is written against the OpenGL ES 2.0 Specification + * but can apply to OpenGL ES 1.1 and up. + * + * From the EGL 1.5 (2014.08.27) spec, p55: + * + * If the EGL_CONTEXT_OPENGL_ROBUST_ACCESS attribute is set to + * EGL_TRUE, a context supporting robust buffer access will be created. + * OpenGL contexts must support the GL_ARB_robustness extension, or + * equivalent core API functional- ity. OpenGL ES contexts must support + * the GL_EXT_robustness extension, or equivalent core API + * functionality. */ if (mesa_api != API_OPENGL_COMPAT && mesa_api != API_OPENGL_CORE - && (flags & ~__DRI_CTX_FLAG_DEBUG)) { + && (flags & ~(__DRI_CTX_FLAG_DEBUG | + __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS))) { *error = __DRI_CTX_ERROR_BAD_FLAG; return NULL; } -- cgit v1.2.3 From 1e0012e3e41e09c33f7f9d6671a803b7b0a7d9b8 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 25 Mar 2016 10:16:23 -0700 Subject: nir: Add a descriptor_set field to nir_variable This is needed for supporting the Vulkan binding model Reviewed-by: Rob Clark --- src/compiler/nir/nir.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 9d48356c6de..8f353773571 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -265,6 +265,11 @@ typedef struct nir_variable { */ int index; + /** + * Descriptor set binding for sampler or UBO. + */ + int descriptor_set; + /** * Initial binding point for a sampler or UBO. * -- cgit v1.2.3 From c825e29a826bf9f03303d1527a2aeef8bcd80dea Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 25 Mar 2016 10:17:28 -0700 Subject: nir/intrinsics: Add a vulkan_resource_index intrinsic This is used to facilitate the Vulkan binding model where each resource is described by a (descriptor set, binding, array index) tuple. Reviewed-by: Rob Clark --- src/compiler/nir/nir.h | 12 ++++++++++++ src/compiler/nir/nir_intrinsics.h | 20 ++++++++++++++++++++ src/compiler/nir/nir_print.c | 2 ++ 3 files changed, 34 insertions(+) (limited to 'src') diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 8f353773571..bbbc2089db3 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -976,6 +976,16 @@ typedef enum { */ NIR_INTRINSIC_RANGE = 5, + /** + * The Vulkan descriptor set for vulkan_resource_index intrinsic. + */ + NIR_INTRINSIC_DESC_SET = 6, + + /** + * The Vulkan descriptor set binding for vulkan_resource_index intrinsic. + */ + NIR_INTRINSIC_BINDING = 7, + NIR_INTRINSIC_NUM_INDEX_FLAGS, } nir_intrinsic_index_flag; @@ -1040,6 +1050,8 @@ INTRINSIC_IDX_ACCESSORS(base, BASE, int) INTRINSIC_IDX_ACCESSORS(stream_id, STREAM_ID, unsigned) INTRINSIC_IDX_ACCESSORS(ucp_id, UCP_ID, unsigned) INTRINSIC_IDX_ACCESSORS(range, RANGE, unsigned) +INTRINSIC_IDX_ACCESSORS(desc_set, DESC_SET, unsigned) +INTRINSIC_IDX_ACCESSORS(binding, BINDING, unsigned) /** * \group texture information diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h index 05507dc6579..66a169c019b 100644 --- a/src/compiler/nir/nir_intrinsics.h +++ b/src/compiler/nir/nir_intrinsics.h @@ -175,6 +175,26 @@ INTRINSIC(image_size, 0, ARR(0), true, 4, 1, 0, xx, xx, xx, INTRINSIC(image_samples, 0, ARR(0), true, 1, 1, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) +/* + * Vulkan descriptor set intrinsic + * + * The Vulkan API uses a different binding model from GL. In the Vulkan + * API, all external resources are represented by a tuple: + * + * (descriptor set, binding, array index) + * + * where the array index is the only thing allowed to be indirect. The + * vulkan_surface_index intrinsic takes the descriptor set and binding as + * its first two indices and the array index as its source. The third + * index is a nir_variable_mode in case that's useful to the backend. + * + * The intended usage is that the shader will call vulkan_surface_index to + * get an index and then pass that as the buffer index ubo/ssbo calls. + */ +INTRINSIC(vulkan_resource_index, 1, ARR(1), true, 1, 0, 2, + DESC_SET, BINDING, xx, + NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) + /* * variable atomic intrinsics * diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index bbb4edf3260..84e926905b4 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -518,6 +518,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr, print_state *state) [NIR_INTRINSIC_STREAM_ID] = "stream-id", [NIR_INTRINSIC_UCP_ID] = "ucp-id", [NIR_INTRINSIC_RANGE] = "range", + [NIR_INTRINSIC_DESC_SET] = "desc-set", + [NIR_INTRINSIC_BINDING] = "binding", }; for (unsigned idx = 1; idx < NIR_INTRINSIC_NUM_INDEX_FLAGS; idx++) { if (!info->index_map[idx]) -- cgit v1.2.3 From d7cddbd6d66120899ffcb5735ee436f13432ed64 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 14 Apr 2016 10:31:27 -0700 Subject: nir/lower_io: Add UBOs and SSBOs to get_io_offset_src Reviewed-by: Kenneth Graunke --- src/compiler/nir/nir_lower_io.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index 6d4a3d8cd89..df1f7a5d765 100644 --- a/src/compiler/nir/nir_lower_io.c +++ b/src/compiler/nir/nir_lower_io.c @@ -430,10 +430,13 @@ nir_get_io_offset_src(nir_intrinsic_instr *instr) case nir_intrinsic_load_output: case nir_intrinsic_load_uniform: return &instr->src[0]; + case nir_intrinsic_load_ubo: + case nir_intrinsic_load_ssbo: case nir_intrinsic_load_per_vertex_input: case nir_intrinsic_load_per_vertex_output: case nir_intrinsic_store_output: return &instr->src[1]; + case nir_intrinsic_store_ssbo: case nir_intrinsic_store_per_vertex_output: return &instr->src[2]; default: -- cgit v1.2.3 From eeff13315858fcb09eefba9a94e6bae5820572e0 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 14 Apr 2016 10:42:29 -0700 Subject: i965: Expose the surface format table Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_surface_formats.c | 22 +++---------- src/mesa/drivers/dri/i965/brw_surface_formats.h | 43 +++++++++++++++++++++++++ 3 files changed, 48 insertions(+), 18 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/brw_surface_formats.h (limited to 'src') diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index 2619e4360bc..c314d7470bb 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -54,6 +54,7 @@ i965_compiler_FILES = \ brw_shader.cpp \ brw_shader.h \ brw_surface_formats.c \ + brw_surface_formats.h \ brw_util.c \ brw_util.h \ brw_vec4_builder.h \ diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index ba9b5b90b63..118b18dcd7c 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -25,21 +25,7 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" - -struct surface_format_info { - bool exists; - int sampling; - int filtering; - int shadow_compare; - int chroma_key; - int render_target; - int alpha_blend; - int input_vb; - int streamed_output_vb; - int color_processing; - int lossless_compression; - const char *name; -}; +#include "brw_surface_formats.h" /* This macro allows us to write the table almost as it appears in the PRM, * while restructuring it to turn it into the C code we want. @@ -86,7 +72,7 @@ struct surface_format_info { * - VOL4_Part1 section 3.9.11 Render Target Write. * - Render Target Surface Types [SKL+] */ -const struct surface_format_info surface_formats[] = { +const struct brw_surface_format_info surface_formats[] = { /* smpl filt shad CK RT AB VB SO color ccs_e */ SF( Y, 50, x, x, Y, Y, Y, Y, x, 90, R32G32B32A32_FLOAT) SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32G32B32A32_SINT) @@ -618,7 +604,7 @@ brw_init_surface_formats(struct brw_context *brw) for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) { uint32_t texture, render; - const struct surface_format_info *rinfo, *tinfo; + const struct brw_surface_format_info *rinfo, *tinfo; bool is_integer = _mesa_is_format_integer_color(format); render = texture = brw_format_for_mesa_format(format); @@ -828,7 +814,7 @@ bool brw_losslessly_compressible_format(const struct brw_context *brw, uint32_t brw_format) { - const struct surface_format_info * const sinfo = + const struct brw_surface_format_info * const sinfo = &surface_formats[brw_format]; const int gen = brw->gen * 10; diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.h b/src/mesa/drivers/dri/i965/brw_surface_formats.h new file mode 100644 index 00000000000..8e4d35e5512 --- /dev/null +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.h @@ -0,0 +1,43 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include + +struct brw_surface_format_info { + bool exists; + int sampling; + int filtering; + int shadow_compare; + int chroma_key; + int render_target; + int alpha_blend; + int input_vb; + int streamed_output_vb; + int color_processing; + int lossless_compression; + const char *name; +}; + +extern const struct brw_surface_format_info surface_formats[]; -- cgit v1.2.3