From 5115c25bb877d62781c23a31735cb3f70811383b Mon Sep 17 00:00:00 2001 From: Boyuan Zhang Date: Mon, 17 Jun 2019 15:00:53 -0400 Subject: radeon/uvd: enable rate control for hevc encoding Set cu_qp_delta_enable_flag on when rate control is enabled, and set it off when rate control is disabled (e.g. constant qp). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673 Cc: mesa-stable@lists.freedesktop.org V2: fix typo and add bugzilla info Signed-off-by: Boyuan Zhang Acked-by: Leo Liu --- src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c index b1b49c28801..7e5be33ec54 100644 --- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c +++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c @@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc) enc->enc_pic.hevc_spec_misc. constrained_intra_pred_flag, 1); radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); - radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); + if (enc->enc_pic.rc_session_init.rate_control_method == + RENC_UVD_RATE_CONTROL_METHOD_NONE) + radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); + else { + radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1); + radeon_uvd_enc_code_ue(enc, 0x0); + } radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); -- cgit v1.2.3