From 233c0faaddd1c9039083af1536aeba6eae01a15f Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 24 Jul 2019 12:54:59 -0700 Subject: pan/midgard: Enable RA for st_vary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that all the piping is in place to do so without regressions, we flip on automatic register allocation for varyings. Hooray! total instructions in shared programs: 4025 -> 3915 (-2.73%) instructions in affected programs: 1667 -> 1557 (-6.60%) helped: 62 HURT: 0 helped stats (abs) min: 1 max: 3 x̄: 1.77 x̃: 2 helped stats (rel) min: 0.93% max: 20.00% x̄: 10.80% x̃: 10.64% 95% mean confidence interval for instructions value: -1.89 -1.66 95% mean confidence interval for instructions %-change: -12.50% -9.11% Instructions are helped. total bundles in shared programs: 2683 -> 2520 (-6.08%) bundles in affected programs: 1066 -> 903 (-15.29%) helped: 62 HURT: 0 helped stats (abs) min: 1 max: 3 x̄: 2.63 x̃: 3 helped stats (rel) min: 2.94% max: 42.86% x̄: 23.85% x̃: 22.50% 95% mean confidence interval for bundles value: -2.83 -2.43 95% mean confidence interval for bundles %-change: -27.73% -19.97% Bundles are helped. total quadwords in shared programs: 4192 -> 4027 (-3.94%) quadwords in affected programs: 1584 -> 1419 (-10.42%) helped: 62 HURT: 0 helped stats (abs) min: 1 max: 4 x̄: 2.66 x̃: 3 helped stats (rel) min: 1.85% max: 30.00% x̄: 16.49% x̃: 16.52% 95% mean confidence interval for quadwords value: -2.87 -2.46 95% mean confidence interval for quadwords %-change: -19.14% -13.84% Quadwords are helped. total registers in shared programs: 433 -> 411 (-5.08%) registers in affected programs: 67 -> 45 (-32.84%) helped: 23 HURT: 1 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 25.00% max: 50.00% x̄: 41.30% x̃: 50.00% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 14.29% max: 14.29% x̄: 14.29% x̃: 14.29% 95% mean confidence interval for registers value: -1.09 -0.74 95% mean confidence interval for registers %-change: -45.45% -32.52% Registers are helped. Signed-off-by: Alyssa Rosenzweig --- src/panfrost/midgard/midgard_compile.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'src/panfrost') diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 6cd06bc001f..63191cec0e4 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -1401,25 +1401,19 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) ctx->fragment_output = reg; } else if (ctx->stage == MESA_SHADER_VERTEX) { - /* Varyings are written into one of two special - * varying register, r26 or r27. The register itself is - * selected as the register in the st_vary instruction, - * minus the base of 26. E.g. write into r27 and then - * call st_vary(1) */ - - midgard_instruction ins = v_mov(reg, blank_alu_src, SSA_FIXED_REGISTER(26)); - emit_mir_instruction(ctx, ins); - /* We should have been vectorized, though we don't * currently check that st_vary is emitted only once * per slot (this is relevant, since there's not a mask * parameter available on the store [set to 0 by the * blob]). We do respect the component by adjusting the - * swizzle. */ + * swizzle. If this is a constant source, we'll need to + * emit that explicitly. */ + + emit_explicit_constant(ctx, reg, reg); unsigned component = nir_intrinsic_component(instr); - midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset); + midgard_instruction st = m_st_vary_32(reg, offset); st.load_store.unknown = 0x1E9E; /* XXX: What is this? */ st.load_store.swizzle = SWIZZLE_XYZW << (2*component); emit_mir_instruction(ctx, st); -- cgit v1.2.3