From febad1779ae5cb5c85d66c2635baea62da52d2fa Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 26 Oct 2011 12:58:37 -0700 Subject: i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_defines.h | 14 +++++++------ src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +++++----- src/mesa/drivers/dri/i965/brw_fs.h | 10 +++++----- src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 30 ++++++++++++++-------------- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 30 ++++++++++++++-------------- 5 files changed, 48 insertions(+), 46 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 95039aa65bc..0eb75124934 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -636,18 +636,20 @@ enum opcode { SHADER_OPCODE_INT_REMAINDER, SHADER_OPCODE_SIN, SHADER_OPCODE_COS, + + SHADER_OPCODE_TEX, + SHADER_OPCODE_TXD, + SHADER_OPCODE_TXF, + SHADER_OPCODE_TXL, + SHADER_OPCODE_TXS, + FS_OPCODE_TXB, + FS_OPCODE_DDX, FS_OPCODE_DDY, FS_OPCODE_PIXEL_X, FS_OPCODE_PIXEL_Y, FS_OPCODE_CINTERP, FS_OPCODE_LINTERP, - FS_OPCODE_TEX, - FS_OPCODE_TXB, - FS_OPCODE_TXD, - FS_OPCODE_TXF, - FS_OPCODE_TXL, - FS_OPCODE_TXS, FS_OPCODE_DISCARD, FS_OPCODE_SPILL, FS_OPCODE_UNSPILL, diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 2a5f5105bd5..339044ca11a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -155,12 +155,12 @@ fs_visitor::implied_mrf_writes(fs_inst *inst) case SHADER_OPCODE_INT_QUOTIENT: case SHADER_OPCODE_INT_REMAINDER: return 2 * c->dispatch_width / 8; - case FS_OPCODE_TEX: + case SHADER_OPCODE_TEX: case FS_OPCODE_TXB: - case FS_OPCODE_TXD: - case FS_OPCODE_TXF: - case FS_OPCODE_TXL: - case FS_OPCODE_TXS: + case SHADER_OPCODE_TXD: + case SHADER_OPCODE_TXF: + case SHADER_OPCODE_TXL: + case SHADER_OPCODE_TXS: return 1; case FS_OPCODE_FB_WRITE: return 2; diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index cb93885efe7..d6233167e7a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -288,12 +288,12 @@ public: bool is_tex() { - return (opcode == FS_OPCODE_TEX || + return (opcode == SHADER_OPCODE_TEX || opcode == FS_OPCODE_TXB || - opcode == FS_OPCODE_TXD || - opcode == FS_OPCODE_TXF || - opcode == FS_OPCODE_TXL || - opcode == FS_OPCODE_TXS); + opcode == SHADER_OPCODE_TXD || + opcode == SHADER_OPCODE_TXF || + opcode == SHADER_OPCODE_TXL || + opcode == SHADER_OPCODE_TXS); } bool is_math() diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index 819c1ef7b66..7f0e58e20b4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -275,7 +275,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) if (intel->gen >= 5) { switch (inst->opcode) { - case FS_OPCODE_TEX: + case SHADER_OPCODE_TEX: if (inst->shadow_compare) { msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; } else { @@ -289,21 +289,21 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; } break; - case FS_OPCODE_TXL: + case SHADER_OPCODE_TXL: if (inst->shadow_compare) { msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; } else { msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; } break; - case FS_OPCODE_TXS: + case SHADER_OPCODE_TXS: msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; break; - case FS_OPCODE_TXD: + case SHADER_OPCODE_TXD: /* There is no sample_d_c message; comparisons are done manually */ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; break; - case FS_OPCODE_TXF: + case SHADER_OPCODE_TXF: msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; break; default: @@ -312,7 +312,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) } } else { switch (inst->opcode) { - case FS_OPCODE_TEX: + case SHADER_OPCODE_TEX: /* Note that G45 and older determines shadow compare and dispatch width * from message length for most messages. */ @@ -334,7 +334,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; } break; - case FS_OPCODE_TXL: + case SHADER_OPCODE_TXL: if (inst->shadow_compare) { assert(inst->mlen == 6); msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE; @@ -344,17 +344,17 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; } break; - case FS_OPCODE_TXD: + case SHADER_OPCODE_TXD: /* There is no sample_d_c message; comparisons are done manually */ assert(inst->mlen == 7 || inst->mlen == 10); msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS; break; - case FS_OPCODE_TXF: + case SHADER_OPCODE_TXF: assert(inst->mlen == 9); msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD; simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; break; - case FS_OPCODE_TXS: + case SHADER_OPCODE_TXS: assert(inst->mlen == 3); msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO; simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; @@ -884,12 +884,12 @@ fs_visitor::generate_code() case FS_OPCODE_LINTERP: generate_linterp(inst, dst, src); break; - case FS_OPCODE_TEX: + case SHADER_OPCODE_TEX: case FS_OPCODE_TXB: - case FS_OPCODE_TXD: - case FS_OPCODE_TXF: - case FS_OPCODE_TXL: - case FS_OPCODE_TXS: + case SHADER_OPCODE_TXD: + case SHADER_OPCODE_TXF: + case SHADER_OPCODE_TXL: + case SHADER_OPCODE_TXS: generate_tex(inst, dst, src[0]); break; case FS_OPCODE_DISCARD: diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 718ca52cd7f..9ce66967f37 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -764,22 +764,22 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, fs_inst *inst = NULL; switch (ir->op) { case ir_tex: - inst = emit(FS_OPCODE_TEX, dst); + inst = emit(SHADER_OPCODE_TEX, dst); break; case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; case ir_txl: - inst = emit(FS_OPCODE_TXL, dst); + inst = emit(SHADER_OPCODE_TXL, dst); break; case ir_txd: - inst = emit(FS_OPCODE_TXD, dst); + inst = emit(SHADER_OPCODE_TXD, dst); break; case ir_txs: - inst = emit(FS_OPCODE_TXS, dst); + inst = emit(SHADER_OPCODE_TXS, dst); break; case ir_txf: - inst = emit(FS_OPCODE_TXF, dst); + inst = emit(SHADER_OPCODE_TXF, dst); break; } inst->base_mrf = base_mrf; @@ -847,7 +847,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, fs_inst *inst = NULL; switch (ir->op) { case ir_tex: - inst = emit(FS_OPCODE_TEX, dst); + inst = emit(SHADER_OPCODE_TEX, dst); break; case ir_txb: ir->lod_info.bias->accept(this); @@ -864,7 +864,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); mlen += reg_width; - inst = emit(FS_OPCODE_TXL, dst); + inst = emit(SHADER_OPCODE_TXL, dst); break; case ir_txd: { ir->lod_info.grad.dPdx->accept(this); @@ -894,14 +894,14 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, mlen += reg_width; } - inst = emit(FS_OPCODE_TXD, dst); + inst = emit(SHADER_OPCODE_TXD, dst); break; } case ir_txs: ir->lod_info.lod->accept(this); emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); mlen += reg_width; - inst = emit(FS_OPCODE_TXS, dst); + inst = emit(SHADER_OPCODE_TXS, dst); break; case ir_txf: mlen = header_present + 4 * reg_width; @@ -910,7 +910,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), this->result); - inst = emit(FS_OPCODE_TXF, dst); + inst = emit(SHADER_OPCODE_TXF, dst); break; } inst->base_mrf = base_mrf; @@ -1033,12 +1033,12 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, /* Generate the SEND */ fs_inst *inst = NULL; switch (ir->op) { - case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; + case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break; case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; - case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; - case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; - case ir_txf: inst = emit(FS_OPCODE_TXF, dst); break; - case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; + case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break; + case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break; + case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break; + case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break; } inst->base_mrf = base_mrf; inst->mlen = mlen; -- cgit v1.2.3