From d586540eaf43a61e53a0c0e4b087d2757f0f4ca5 Mon Sep 17 00:00:00 2001 From: Nicolai Haehnle Date: Sun, 24 Oct 2004 05:52:10 +0000 Subject: Hardware accelerated depth clear --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 7 +++-- src/mesa/drivers/dri/r300/r300_context.h | 1 + src/mesa/drivers/dri/r300/r300_ioctl.c | 52 +++++++++++++++++++++++++++----- src/mesa/drivers/dri/r300/r300_state.c | 9 +++--- src/mesa/drivers/dri/r300/radeon_span.c | 9 ++++-- 5 files changed, 62 insertions(+), 16 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 7c68f33cff1..7bf2df5a8e9 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -376,8 +376,10 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.unk4E88.cmd[0] = cmducs(0x4E88, 1); ALLOC_STATE( zc, always, R300_ZC_CMDSIZE, "zc", 0 ); r300->hw.zc.cmd[R300_ZC_CMD_0] = cmducs(R300_RB3D_ZCNTL_0, 2); - ALLOC_STATE( unk4F08, always, 6, "unk4F08", 0 ); - r300->hw.unk4F08.cmd[0] = cmducs(0x4F08, 5); + ALLOC_STATE( unk4F08, always, 2, "unk4F08", 0 ); + r300->hw.unk4F08.cmd[0] = cmducs(0x4F08, 1); + ALLOC_STATE( unk4F10, always, 5, "unk4F10", 0 ); + r300->hw.unk4F10.cmd[0] = cmducs(0x4F10, 4); ALLOC_STATE( zb, always, R300_ZB_CMDSIZE, "zb", 0 ); r300->hw.zb.cmd[R300_ZB_CMD_0] = cmducs(R300_RB3D_DEPTHOFFSET, 2); ALLOC_STATE( unk4F28, always, 2, "unk4F28", 0 ); @@ -451,6 +453,7 @@ void r300InitCmdBuf(r300ContextPtr r300) insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E88); insert_at_tail(&r300->hw.atomlist, &r300->hw.zc); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F08); + insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F10); insert_at_tail(&r300->hw.atomlist, &r300->hw.zb); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F28); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F30); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index ce7ccd95d9a..ada6e4a5a2d 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -269,6 +269,7 @@ struct r300_hw_state { struct r300_state_atom unk4E88; /* (4E88) */ struct r300_state_atom zc; /* z control (4F00) */ struct r300_state_atom unk4F08; /* (4F08) */ + struct r300_state_atom unk4F10; /* (4F10) */ struct r300_state_atom zb; /* z buffer (4F20) */ struct r300_state_atom unk4F28; /* (4F28) */ struct r300_state_atom unk4F30; /* (4F30) */ diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 8463e4eff3a..8ce1bd22e65 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -55,7 +55,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" -static void r300ClearBuffer(r300ContextPtr r300, int buffer) +#define CLEARBUFFER_COLOR 0x1 +#define CLEARBUFFER_DEPTH 0x2 + +static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer) { GLcontext* ctx = r300->radeon.glCtx; __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; @@ -107,7 +110,10 @@ static void r300ClearBuffer(r300ContextPtr r300, int buffer) r300->hw.rr.cmd[1] = 0x00004000; R300_STATECHANGE(r300, cmk); - r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF; + if (flags & CLEARBUFFER_COLOR) + r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF; + else + r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0; R300_STATECHANGE(r300, fp); r300->hw.fp.cmd[R300_FP_CNTL0] = 0; /* 1 pass, no textures */ @@ -157,6 +163,24 @@ static void r300ClearBuffer(r300ContextPtr r300, int buffer) r300->hw.vpi.cmd[7] = VP_ZERO(); r300->hw.vpi.cmd[8] = 0; + R300_STATECHANGE(r300, zc); + if (flags & CLEARBUFFER_DEPTH) { + r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0x6; // test and write + r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_RB3D_Z_TEST_ALWAYS; +/* + R300_STATECHANGE(r300, zb); + r300->hw.zb.cmd[R300_ZB_OFFSET] = + 1024*4*300 + + r300->radeon.radeonScreen->frontOffset + + r300->radeon.radeonScreen->fbLocation; + r300->hw.zb.cmd[R300_ZB_PITCH] = + r300->radeon.radeonScreen->depthPitch; +*/ + } else { + r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0; // disable + r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0; + } + /* Make sure we have enough space */ r300EnsureCmdBufSpace(r300, r300->hw.max_state_size + 9, __FUNCTION__); @@ -167,7 +191,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int buffer) cmd[0].packet3.packet = R300_CMD_PACKET3_CLEAR; cmd[1].u = r300PackFloat32(dPriv->w / 2.0); cmd[2].u = r300PackFloat32(dPriv->h / 2.0); - cmd[3].u = r300PackFloat32(0.0); + cmd[3].u = r300PackFloat32(ctx->Depth.Clear); cmd[4].u = r300PackFloat32(1.0); cmd[5].u = r300PackFloat32(ctx->Color.ClearColor[0]); cmd[6].u = r300PackFloat32(ctx->Color.ClearColor[1]); @@ -185,6 +209,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all, r300ContextPtr r300 = R300_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; int flags = 0; + int bits = 0; int swapped; if (RADEON_DEBUG & DEBUG_IOCTL) @@ -208,6 +233,12 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all, mask &= ~DD_BACK_LEFT_BIT; } + if (mask & DD_DEPTH_BIT) { + if (ctx->Depth.Mask) + bits |= CLEARBUFFER_DEPTH; + mask &= ~DD_DEPTH_BIT; + } + if (mask) { if (RADEON_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "%s: swrast clear, mask: %x\n", @@ -217,11 +248,18 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all, swapped = r300->radeon.doPageFlip && (r300->radeon.sarea->pfCurrentPage == 1); - if (flags & DD_FRONT_LEFT_BIT) - r300ClearBuffer(r300, swapped); + if (flags & DD_FRONT_LEFT_BIT) { + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped); + bits = 0; + } + + if (flags & DD_BACK_LEFT_BIT) { + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped ^ 1); + bits = 0; + } - if (flags & DD_BACK_LEFT_BIT) - r300ClearBuffer(r300, swapped ^ 1); + if (bits) + r300ClearBuffer(r300, bits, 0); /* Recalculate the hardware state. This could be done more efficiently, * but do keep it like this for now. diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 9c5138c2790..f28c677bf10 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -295,10 +295,11 @@ void r300ResetHwState(r300ContextPtr r300) r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0; r300->hw.unk4F08.cmd[1] = 0x00FFFF00; - r300->hw.unk4F08.cmd[2] = 0x00000002; - r300->hw.unk4F08.cmd[3] = 0x00000000; - r300->hw.unk4F08.cmd[4] = 0x00000003; - r300->hw.unk4F08.cmd[5] = 0x00000000; + + r300->hw.unk4F10.cmd[1] = 0x00000002; // depthbuffer format? + r300->hw.unk4F10.cmd[2] = 0x00000000; + r300->hw.unk4F10.cmd[3] = 0x00000003; + r300->hw.unk4F10.cmd[4] = 0x00000000; r300->hw.zb.cmd[R300_ZB_OFFSET] = r300->radeon.radeonScreen->depthOffset + diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c index 93c4da9085b..efc5a01c37b 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -257,18 +257,21 @@ do { \ #include "depthtmp.h" /* 24 bit depth, 8 bit stencil depthbuffer functions + * + * Careful: It looks like the R300 uses ZZZS byte order while the R200 + * uses SZZZ for 24 bit depth, 8 bit stencil mode. */ #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \ GLuint tmp = *(GLuint *)(buf + offset); \ - tmp &= 0xff000000; \ - tmp |= ((d) & 0x00ffffff); \ + tmp &= 0x000000ff; \ + tmp |= ((d << 8) & 0xffffff00); \ *(GLuint *)(buf + offset) = tmp; \ } while (0) #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0x00ffffff; + d = (*(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0xffffff00) >> 8; #define TAG(x) radeon##x##_24_8_LINEAR #include "depthtmp.h" -- cgit v1.2.3