From a0fe569e53f779b5a8497ff669c1b277d1c13796 Mon Sep 17 00:00:00 2001 From: Mathias Fröhlich Date: Sun, 22 May 2016 14:10:19 +0200 Subject: radeon/r200: Use bitmask/ffs to iterate enabled clip planes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replaces an iterate and test bit in a bitmask loop by a loop only iterating over the bits set in the bitmask. v2: Use _mesa_bit_scan{,64} instead of open coding. v3: Use u_bit_scan{,64} instead of _mesa_bit_scan{,64}. Reviewed-by: Brian Paul Signed-off-by: Mathias Fröhlich --- src/mesa/drivers/dri/r200/r200_state.c | 19 +++++++++---------- src/mesa/drivers/dri/radeon/radeon_state.c | 19 +++++++++---------- 2 files changed, 18 insertions(+), 20 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 0e38afc919d..367123157df 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1360,18 +1360,17 @@ static void r200ClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat * static void r200UpdateClipPlanes( struct gl_context *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint p; + GLbitfield mask = ctx->Transform.ClipPlanesEnabled; - for (p = 0; p < ctx->Const.MaxClipPlanes; p++) { - if (ctx->Transform.ClipPlanesEnabled & (1 << p)) { - GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; + while (mask) { + const int p = u_bit_scan(&mask); + GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - R200_STATECHANGE( rmesa, ucp[p] ); - rmesa->hw.ucp[p].cmd[UCP_X] = ip[0]; - rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1]; - rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2]; - rmesa->hw.ucp[p].cmd[UCP_W] = ip[3]; - } + R200_STATECHANGE( rmesa, ucp[p] ); + rmesa->hw.ucp[p].cmd[UCP_X] = ip[0]; + rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1]; + rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2]; + rmesa->hw.ucp[p].cmd[UCP_W] = ip[3]; } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 93bc0f9dedf..c6b1f38dd02 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1134,18 +1134,17 @@ static void radeonClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat static void radeonUpdateClipPlanes( struct gl_context *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - GLuint p; + GLbitfield mask = ctx->Transform.ClipPlanesEnabled; - for (p = 0; p < ctx->Const.MaxClipPlanes; p++) { - if (ctx->Transform.ClipPlanesEnabled & (1 << p)) { - GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; + while (mask) { + const int p = u_bit_scan(&mask); + GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - RADEON_STATECHANGE( rmesa, ucp[p] ); - rmesa->hw.ucp[p].cmd[UCP_X] = ip[0]; - rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1]; - rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2]; - rmesa->hw.ucp[p].cmd[UCP_W] = ip[3]; - } + RADEON_STATECHANGE( rmesa, ucp[p] ); + rmesa->hw.ucp[p].cmd[UCP_X] = ip[0]; + rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1]; + rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2]; + rmesa->hw.ucp[p].cmd[UCP_W] = ip[3]; } } -- cgit v1.2.3