From 8379bff6c4456f8a77041eee225dcd44e5e00a76 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 9 Mar 2018 21:23:23 -0800 Subject: i965: Emit texture cache invalidates around blorp_copy This is a terrible hack but it fixes CTS regressions. It's still incredibly unclear exactly what is going wrong in the hardware to cause this to be an issue so this isn't a good fix by any means. However, it does fix tests so there is that. Fixes: fb0e9b5197 "i965: Track the depth and render caches separately" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103746 Acked-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_blorp.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 1d586e5ef38..72c5d194efe 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -428,6 +428,18 @@ brw_blorp_copy_miptrees(struct brw_context *brw, blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true, &dst_level, dst_layer, 1, &tmp_surfs[1]); + /* The hardware seems to have issues with having a two different format + * views of the same texture in the sampler cache at the same time. It's + * unclear exactly what the issue is but it hurts glCopyImageSubData + * particularly badly because it does a lot of format reinterprets. We + * badly need better understanding of the issue and a better fix but this + * works for now and fixes CTS tests. + * + * TODO: Remove this hack! + */ + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); + struct blorp_batch batch; blorp_batch_init(&brw->blorp, &batch, brw, 0); blorp_copy(&batch, &src_surf, src_level, src_layer, @@ -435,6 +447,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw, src_x, src_y, dst_x, dst_y, src_width, src_height); blorp_batch_finish(&batch); + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); + intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1, dst_aux_usage); } -- cgit v1.2.3