From 5ce405ba0ffd44653b2cdf96fefdad30d218e224 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Sun, 8 May 2016 21:15:04 -0700 Subject: i965: Actually assign binding table offsets for the TCS. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As far as I can tell, this was just entirely missing...honestly, I'm not sure how anything worked at all. Caught by noticing GPU hangs in image load store tests with scalar TCS, but probably has broader implications. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_tcs.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c index 98ed2b253a6..e8178c6daab 100644 --- a/src/mesa/drivers/dri/i965/brw_tcs.c +++ b/src/mesa/drivers/dri/i965/brw_tcs.c @@ -168,6 +168,7 @@ brw_codegen_tcs_prog(struct brw_context *brw, { struct gl_context *ctx = &brw->ctx; const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_device_info *devinfo = compiler->devinfo; struct brw_stage_state *stage_state = &brw->tcs.base; nir_shader *nir; struct brw_tcs_prog_data prog_data; @@ -209,6 +210,10 @@ brw_codegen_tcs_prog(struct brw_context *brw, prog_data.base.base.nr_params = param_count; if (tcs) { + brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo, + shader_prog, &tcp->program.Base, + &prog_data.base.base, 0); + prog_data.base.base.image_param = rzalloc_array(NULL, struct brw_image_param, tcs->NumImages); prog_data.base.base.nr_image_params = tcs->NumImages; -- cgit v1.2.3