From 5bad948fa8a4fe812d254b6251e5e5dbd8a64e1c Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 27 Feb 2013 15:05:24 +0000 Subject: i965/skl: Emit depth stall workaround for gen9 as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The docs say that we shouldn't need this workaround for gen8+, but just removing it, causes gpu hangs. We'll revisit this, but for now, just extend the workaround to gen9. Signed-off-by: Damien Lespiau Reviewed-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index cd45af6fbe2..2bd11d7a63e 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -535,7 +535,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, void intel_emit_depth_stall_flushes(struct brw_context *brw) { - assert(brw->gen >= 6 && brw->gen <= 8); + assert(brw->gen >= 6 && brw->gen <= 9); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH); -- cgit v1.2.3