From 544869377d6ec8c150d4d91d17a01f22cd84d479 Mon Sep 17 00:00:00 2001 From: Chris Forbes Date: Sun, 8 Dec 2013 20:29:43 +1300 Subject: i965/fs: add support for gl_SampleMaskIn[] v2: - add assert so we don't run into trouble on Gen6. - adjust for Tapani's rearrangement of ir_variable Signed-off-by: Chris Forbes Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 23 ++++++++++++++++++++++- src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 ++ src/mesa/drivers/dri/i965/brw_wm.h | 1 + src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 ++++ 5 files changed, 30 insertions(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 63b005e33c0..baf9220125c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1255,6 +1255,16 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir) return reg; } +fs_reg * +fs_visitor::emit_samplemaskin_setup(ir_variable *ir) +{ + assert(brw->gen >= 7); + this->current_annotation = "compute gl_SampleMaskIn"; + fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); + emit(MOV(*reg, fs_reg(retype(brw_vec8_grf(c->sample_mask_reg, 0), BRW_REGISTER_TYPE_D)))); + return reg; +} + fs_reg fs_visitor::fix_math_operand(fs_reg src) { @@ -3073,7 +3083,18 @@ fs_visitor::setup_payload_gen6() c->nr_payload_regs++; } - /* R32-: bary for 32-pixel. */ + /* R32: MSAA input coverage mask */ + if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) { + assert(brw->gen >= 7); + c->sample_mask_reg = c->nr_payload_regs; + c->nr_payload_regs++; + if (dispatch_width == 16) { + /* R33: input coverage mask if not 8-wide. */ + c->nr_payload_regs++; + } + } + + /* R34-: bary for 32-pixel. */ /* R58-59: interp W for 32-pixel. */ if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index e516046686f..9bef07c276c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -340,6 +340,7 @@ public: fs_reg *emit_frontfacing_interpolation(ir_variable *ir); fs_reg *emit_samplepos_setup(ir_variable *ir); fs_reg *emit_sampleid_setup(ir_variable *ir); + fs_reg *emit_samplemaskin_setup(ir_variable *ir); fs_reg *emit_general_interpolation(ir_variable *ir); void emit_interpolation_setup_gen4(); void emit_interpolation_setup_gen6(); diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 47cf71e3c53..8e516a5812b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -136,6 +136,8 @@ fs_visitor::visit(ir_variable *ir) reg = emit_samplepos_setup(ir); } else if (ir->data.location == SYSTEM_VALUE_SAMPLE_ID) { reg = emit_sampleid_setup(ir); + } else if (ir->data.location == SYSTEM_VALUE_SAMPLE_MASK_IN) { + reg = emit_samplemaskin_setup(ir); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 556b5aee672..2ee126ba0d9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -88,6 +88,7 @@ struct brw_wm_compile { uint8_t aa_dest_stencil_reg; uint8_t dest_depth_reg; uint8_t sample_pos_reg; + uint8_t sample_mask_reg; uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; uint8_t nr_payload_regs; GLuint source_depth_to_render_target:1; diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index abbc73c2142..b6561bbaf2b 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -112,6 +112,10 @@ upload_wm_state(struct brw_context *brw) dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; } + if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) { + dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK; + } + BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); OUT_BATCH(dw1); -- cgit v1.2.3