From 353abb294b10aa18bf98a772b380ccbed318c239 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 26 Nov 2015 16:42:43 +0200 Subject: i965: Define and use REG_MASK macro to make masked MMIO writes slightly more readable. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Samuel Iglesias Gonsálvez Reviewed-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_defines.h | 6 ++++++ src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- src/mesa/drivers/dri/i965/gen7_l3_state.c | 2 +- src/mesa/drivers/dri/i965/intel_reg.h | 2 +- 4 files changed, 9 insertions(+), 3 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 97ef6d45ad2..ba6290d4cd7 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -41,6 +41,12 @@ #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low)) #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) +/** + * For use with masked MMIO registers where the upper 16 bits control which + * of the lower bits are committed to the register. + */ +#define REG_MASK(value) ((value) << 16) + #ifndef BRW_DEFINES_H #define BRW_DEFINES_H diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 750eb75fcd3..58be242d55d 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -387,7 +387,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw) BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(GEN7_CACHE_MODE_1); - OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) | + OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 141d4812a21..05bc7aa8dda 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -268,7 +268,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg) OUT_BATCH(HSW_SCRATCH1); OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE); OUT_BATCH(HSW_ROW_CHICKEN3); - OUT_BATCH(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE << 16 | + OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) | (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE)); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index 0b167d50460..8888d6f776c 100644 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ b/src/mesa/drivers/dri/i965/intel_reg.h @@ -183,7 +183,7 @@ # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13) # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1) # define GEN8_HIZ_PMA_MASK_BITS \ - ((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16) + REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) /* Predicate registers */ #define MI_PREDICATE_SRC0 0x2400 -- cgit v1.2.3