From 01dda0758e31ec62145488d9880a991674521054 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 23 Sep 2011 23:32:56 -0700 Subject: i965: Fix incorrect maximum PS thread count shift on Ivybridge. At one point, the documentation said that max thread count in 3DSTATE_PS was at bit offset 23, but it's actually 24 on Ivybridge. Not only did this halve our thread count, it caused us to write 1 into a bit 23, which is marked as MBZ (must be zero). Furthermore, it made us write an even number into this field, which is apparently not allowed. Apparently we were just lucky it worked. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_defines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 055aa4a6c5a..05a13375fe0 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1304,7 +1304,7 @@ enum opcode { # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW3: scratch space */ /* DW4 */ -# define GEN7_PS_MAX_THREADS_SHIFT 23 +# define GEN7_PS_MAX_THREADS_SHIFT 24 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) -- cgit v1.2.3