From dcd0261affc293b75d231e612091ec7b1076fff6 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 5 Oct 2010 10:20:16 -0700 Subject: i965: Enable the constant propagation code. A debug disable had slipped in. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index f42c4696410..0c9f17f8fdc 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2548,8 +2548,6 @@ fs_visitor::propagate_constants() { bool progress = false; - return false; - foreach_iter(exec_list_iterator, iter, this->instructions) { fs_inst *inst = (fs_inst *)iter.get(); -- cgit v1.2.3 From 634abbf7b2e6ea21db30aafc0de9472ee31d4173 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 5 Oct 2010 10:25:22 -0700 Subject: i965: Also do constant propagation for the second operand of CMP. We could do the first operand as well by flipping the comparison, but this covered several CMPs in code I was looking at. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 0c9f17f8fdc..914141a3978 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2607,6 +2607,11 @@ fs_visitor::propagate_constants() scan_inst->src[1] = inst->src[0]; } break; + case BRW_OPCODE_CMP: + if (i == 1) { + scan_inst->src[i] = inst->src[0]; + progress = true; + } } } -- cgit v1.2.3 From 3c97c00e3810d31c3aa26173eb9fdef91b3e7c87 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 09:57:55 -0700 Subject: i965: Add back gen6 headerless FB writes to the new FS backend. It's not that hard to detect when we need the header. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 43 +++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 914141a3978..a380eb44525 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -324,6 +324,7 @@ public: this->sampler = 0; this->target = 0; this->eot = false; + this->header_present = false; this->shadow_compare = false; } @@ -376,6 +377,7 @@ public: int sampler; int target; /**< MRT target. */ bool eot; + bool header_present; bool shadow_compare; /** @{ @@ -420,7 +422,10 @@ public: this->virtual_grf_array_size = 0; this->virtual_grf_def = NULL; this->virtual_grf_use = NULL; + + this->kill_emitted = false; } + ~fs_visitor() { talloc_free(this->mem_ctx); @@ -503,6 +508,7 @@ public: ir_variable *frag_color, *frag_data, *frag_depth; int first_non_payload_grf; int urb_setup[FRAG_ATTRIB_MAX]; + bool kill_emitted; /** @{ debug annotation info */ const char *current_annotation; @@ -1509,6 +1515,7 @@ fs_visitor::visit(ir_discard *ir) assert(ir->condition == NULL); /* FINISHME */ emit(fs_inst(FS_OPCODE_DISCARD, temp, temp)); + kill_emitted = true; } void @@ -1843,10 +1850,19 @@ void fs_visitor::emit_fb_writes() { this->current_annotation = "FB write header"; + GLboolean header_present = GL_TRUE; int nr = 0; - /* m0, m1 header */ - nr += 2; + if (intel->gen >= 6 && + !this->kill_emitted && + c->key.nr_color_regions == 1) { + header_present = false; + } + + if (header_present) { + /* m0, m1 header */ + nr += 2; + } if (c->key.aa_dest_stencil_reg) { emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), @@ -1911,6 +1927,7 @@ fs_visitor::emit_fb_writes() reg_undef, reg_undef)); inst->mlen = nr; inst->eot = true; + inst->header_present = header_present; } this->current_annotation = NULL; @@ -1929,19 +1946,23 @@ fs_visitor::generate_fb_write(fs_inst *inst) brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_compression_control(p, BRW_COMPRESSION_NONE); - if (intel->gen >= 6) { + if (inst->header_present) { + if (intel->gen >= 6) { + brw_MOV(p, + brw_message_reg(0), + brw_vec8_grf(0, 0)); + implied_header = brw_null_reg(); + } else { + implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); + } + brw_MOV(p, - brw_message_reg(0), - brw_vec8_grf(0, 0)); - implied_header = brw_null_reg(); + brw_message_reg(1), + brw_vec8_grf(1, 0)); } else { - implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); + implied_header = brw_null_reg(); } - brw_MOV(p, - brw_message_reg(1), - brw_vec8_grf(1, 0)); - brw_pop_insn_state(p); brw_fb_WRITE(p, -- cgit v1.2.3 From f7cb28fad9855020e9fbd1481df03bb09346d4be Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 4 Oct 2010 15:09:18 -0700 Subject: i965: Gen6 no longer has the IFF instruction; always use IF. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 59541353214..fbc6894d054 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -899,9 +899,11 @@ void brw_ENDIF(struct brw_compile *p, * instruction respectively. */ if (patch_insn->header.opcode == BRW_OPCODE_IF) { - /* Automagically turn it into an IFF: - */ - patch_insn->header.opcode = BRW_OPCODE_IFF; + if (intel->gen < 6) { + /* Automagically turn it into an IFF: + */ + patch_insn->header.opcode = BRW_OPCODE_IFF; + } patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); patch_insn->bits3.if_else.pop_count = 0; patch_insn->bits3.if_else.pad0 = 0; -- cgit v1.2.3 From feca6609390d4642418cf7aab878e654964510c4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 4 Oct 2010 15:08:03 -0700 Subject: i965: Fix up IF/ELSE/ENDIF for gen6. The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet). --- src/mesa/drivers/dri/i965/brw_disasm.c | 5 ++ src/mesa/drivers/dri/i965/brw_eu_emit.c | 86 ++++++++++++++++++++++++--------- src/mesa/drivers/dri/i965/brw_structs.h | 12 +++++ 3 files changed, 79 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 3a93b253777..be27f9226c3 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -892,7 +892,12 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen) if (opcode[inst->header.opcode].ndst > 0) { pad (file, 16); err |= dest (file, inst); + } else if (gen >= 6 && (inst->header.opcode == BRW_OPCODE_IF || + inst->header.opcode == BRW_OPCODE_ELSE || + inst->header.opcode == BRW_OPCODE_ENDIF)) { + format (file, " %d", inst->bits1.branch_gen6.jump_count); } + if (opcode[inst->header.opcode].nsrc > 0) { pad (file, 32); err |= src0 (file, inst); diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index fbc6894d054..419b40ba84b 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -787,6 +787,7 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p, */ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; if (p->single_program_flow) { @@ -800,9 +801,15 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) /* Override the defaults for this instruction: */ - brw_set_dest(insn, brw_ip_reg()); - brw_set_src0(insn, brw_ip_reg()); - brw_set_src1(insn, brw_imm_d(0x0)); + if (intel->gen < 6) { + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); + brw_set_src1(insn, brw_imm_d(0x0)); + } else { + brw_set_dest(insn, brw_imm_w(0)); + brw_set_src0(insn, brw_null_reg()); + brw_set_src1(insn, brw_null_reg()); + } insn->header.execution_size = execute_size; insn->header.compression_control = BRW_COMPRESSION_NONE; @@ -835,9 +842,15 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p, insn = next_insn(p, BRW_OPCODE_ELSE); } - brw_set_dest(insn, brw_ip_reg()); - brw_set_src0(insn, brw_ip_reg()); - brw_set_src1(insn, brw_imm_d(0x0)); + if (intel->gen < 6) { + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); + brw_set_src1(insn, brw_imm_d(0x0)); + } else { + brw_set_dest(insn, brw_imm_w(0)); + brw_set_src0(insn, brw_null_reg()); + brw_set_src1(insn, brw_null_reg()); + } insn->header.compression_control = BRW_COMPRESSION_NONE; insn->header.execution_size = if_insn->header.execution_size; @@ -854,9 +867,13 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p, } else { assert(if_insn->header.opcode == BRW_OPCODE_IF); - if_insn->bits3.if_else.jump_count = br * (insn - if_insn); - if_insn->bits3.if_else.pop_count = 0; - if_insn->bits3.if_else.pad0 = 0; + if (intel->gen < 6) { + if_insn->bits3.if_else.jump_count = br * (insn - if_insn); + if_insn->bits3.if_else.pop_count = 0; + if_insn->bits3.if_else.pad0 = 0; + } else { + if_insn->bits1.branch_gen6.jump_count = br * (insn - if_insn + 1); + } } return insn; @@ -884,9 +901,15 @@ void brw_ENDIF(struct brw_compile *p, } else { struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF); - brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); - brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); - brw_set_src1(insn, brw_imm_d(0x0)); + if (intel->gen < 6) { + brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); + brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); + brw_set_src1(insn, brw_imm_d(0x0)); + } else { + brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_W)); + brw_set_src0(insn, brw_null_reg()); + brw_set_src1(insn, brw_null_reg()); + } insn->header.compression_control = BRW_COMPRESSION_NONE; insn->header.execution_size = patch_insn->header.execution_size; @@ -900,26 +923,41 @@ void brw_ENDIF(struct brw_compile *p, */ if (patch_insn->header.opcode == BRW_OPCODE_IF) { if (intel->gen < 6) { - /* Automagically turn it into an IFF: + /* Turn it into an IFF, which means no mask stack operations for + * all-false and jumping past the ENDIF. */ patch_insn->header.opcode = BRW_OPCODE_IFF; + patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); + patch_insn->bits3.if_else.pop_count = 0; + patch_insn->bits3.if_else.pad0 = 0; + } else { + /* As of gen6, there is no IFF and IF must point to the ENDIF. */ + patch_insn->bits1.branch_gen6.jump_count = br * (insn - patch_insn); } - patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); - patch_insn->bits3.if_else.pop_count = 0; - patch_insn->bits3.if_else.pad0 = 0; - } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) { - patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); - patch_insn->bits3.if_else.pop_count = 1; - patch_insn->bits3.if_else.pad0 = 0; } else { - assert(0); + assert(patch_insn->header.opcode == BRW_OPCODE_ELSE); + if (intel->gen < 6) { + /* BRW_OPCODE_ELSE pre-gen6 should point just past the + * matching ENDIF. + */ + patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); + patch_insn->bits3.if_else.pop_count = 1; + patch_insn->bits3.if_else.pad0 = 0; + } else { + /* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */ + patch_insn->bits1.branch_gen6.jump_count = br * (insn - patch_insn); + } } /* Also pop item off the stack in the endif instruction: */ - insn->bits3.if_else.jump_count = 0; - insn->bits3.if_else.pop_count = 1; - insn->bits3.if_else.pad0 = 0; + if (intel->gen < 6) { + insn->bits3.if_else.jump_count = 0; + insn->bits3.if_else.pop_count = 1; + insn->bits3.if_else.pad0 = 0; + } else { + insn->bits1.branch_gen6.jump_count = 2; + } } } diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 7b919872c40..8ce9af9c4fe 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1381,6 +1381,18 @@ struct brw_instruction GLuint dest_horiz_stride:2; GLuint dest_address_mode:1; } ia16; + + struct { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint src1_reg_file:2; + GLuint src1_reg_type:3; + GLuint pad:1; + + GLint jump_count:16; + } branch_gen6; } bits1; -- cgit v1.2.3 From 5eeaf3671e2f913d38187fd1401c4b22a2900d57 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 11:25:05 -0700 Subject: i965: Fix botch in the header_present case in the new FS. I only set it on the color_regions == 0 case, missing the important case, causing GPU hangs on pre-gen6. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a380eb44525..6e5ea0782e1 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1920,6 +1920,7 @@ fs_visitor::emit_fb_writes() inst->mlen = nr; if (target == c->key.nr_color_regions - 1) inst->eot = true; + inst->header_present = header_present; } if (c->key.nr_color_regions == 0) { -- cgit v1.2.3 From 5d99b01501128c7179cdd6aa29bc8953d0d81e75 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 10:22:22 -0700 Subject: i965: Add some clarification of the WECtrl field. --- src/mesa/drivers/dri/i965/brw_defines.h | 21 +++++++++++++++++++-- src/mesa/drivers/dri/i965/brw_disasm.c | 4 ++-- 2 files changed, 21 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index f9c12e15558..9633c95ff50 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -501,9 +501,26 @@ #define BRW_MASK_ENABLE 0 #define BRW_MASK_DISABLE 1 -/* Sandybridge is WECtrl (Write enable control) */ +/** @{ + * + * Gen6 has replaced "mask enable/disable" with WECtrl, which is + * effectively the same but much simpler to think about. Now, there + * are two contributors ANDed together to whether channels are + * executed: The predication on the instruction, and the channel write + * enable. + */ +/** + * This is the default value. It means that a channel's write enable is set + * if the per-channel IP is pointing at this instruction. + */ #define BRW_WE_NORMAL 0 -#define BRW_WE_KILL_PRED 1 +/** + * This is used like BRW_MASK_DISABLE, and causes all channels to have + * their write enable set. Note that predication still contributes to + * whether the channel actually gets written. + */ +#define BRW_WE_ALL 1 +/** @} */ #define BRW_OPCODE_MOV 1 #define BRW_OPCODE_SEL 2 diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index be27f9226c3..12b8f2e4678 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -165,8 +165,8 @@ char *accwr[2] = { }; char *wectrl[2] = { - [0] = "WEnormal", - [1] = "WEpredicted" + [0] = "WE_normal", + [1] = "WE_all" }; char *exec_size[8] = { -- cgit v1.2.3 From fe6efc25ed3c1edf26073c4e6b6a3a45c857c1eb Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 11:00:31 -0700 Subject: i965: Don't do 1/w multiplication in new FS for gen6 Not needed now that we're doing barycentric. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 6e5ea0782e1..7327c3a700e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -810,12 +810,14 @@ fs_visitor::emit_general_interpolation(ir_variable *ir) } attr.reg_offset -= type->vector_elements; - for (unsigned int c = 0; c < type->vector_elements; c++) { - emit(fs_inst(BRW_OPCODE_MUL, - attr, - attr, - this->pixel_w)); - attr.reg_offset++; + if (intel->gen < 6) { + for (unsigned int c = 0; c < type->vector_elements; c++) { + emit(fs_inst(BRW_OPCODE_MUL, + attr, + attr, + this->pixel_w)); + attr.reg_offset++; + } } location++; } -- cgit v1.2.3 From 75270f705f319b0ecf297d1bdd328e52a8a956aa Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 11:04:02 -0700 Subject: i965: Gen6's sampler messages are the same as Ironlake. This should fix texturing in the new FS backend. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 7327c3a700e..19739901619 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2054,7 +2054,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) int rlen = 4; uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; - if (intel->gen == 5) { + if (intel->gen >= 5) { switch (inst->opcode) { case FS_OPCODE_TEX: if (inst->shadow_compare) { -- cgit v1.2.3 From a760b5b509f85991a10400977576afabcedbb3c5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 11:13:22 -0700 Subject: i965: Refactor gl_FrontFacing setup out of general variable setup. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 53 +++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 22 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 19739901619..c5013f05745 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -474,8 +474,9 @@ public: void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src); void emit_dummy_fs(); - void emit_fragcoord_interpolation(ir_variable *ir); - void emit_general_interpolation(ir_variable *ir); + fs_reg *emit_fragcoord_interpolation(ir_variable *ir); + fs_reg *emit_frontfacing_interpolation(ir_variable *ir); + fs_reg *emit_general_interpolation(ir_variable *ir); void emit_interpolation_setup_gen4(); void emit_interpolation_setup_gen6(); fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate); @@ -721,7 +722,7 @@ fs_visitor::setup_builtin_uniform_values(ir_variable *ir) } } -void +fs_reg * fs_visitor::emit_fragcoord_interpolation(ir_variable *ir) { fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); @@ -761,11 +762,10 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir) /* gl_FragCoord.w: Already set up in emit_interpolation */ emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w)); - hash_table_insert(this->variable_ht, reg, ir); + return reg; } - -void +fs_reg * fs_visitor::emit_general_interpolation(ir_variable *ir) { fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); @@ -823,7 +823,25 @@ fs_visitor::emit_general_interpolation(ir_variable *ir) } } - hash_table_insert(this->variable_ht, reg, ir); + return reg; +} + +fs_reg * +fs_visitor::emit_frontfacing_interpolation(ir_variable *ir) +{ + fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); + struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); + /* bit 31 is "primitive is back face", so checking < (1 << 31) gives + * us front face + */ + fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, + *reg, + fs_reg(r1_6ud), + fs_reg(1u << 31))); + inst->conditional_mod = BRW_CONDITIONAL_L; + emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); + + return reg; } void @@ -844,24 +862,15 @@ fs_visitor::visit(ir_variable *ir) if (ir->mode == ir_var_in) { if (!strcmp(ir->name, "gl_FragCoord")) { - emit_fragcoord_interpolation(ir); - return; + reg = emit_fragcoord_interpolation(ir); } else if (!strcmp(ir->name, "gl_FrontFacing")) { - reg = new(this->mem_ctx) fs_reg(this, ir->type); - struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); - /* bit 31 is "primitive is back face", so checking < (1 << 31) gives - * us front face - */ - fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, - *reg, - fs_reg(r1_6ud), - fs_reg(1u << 31))); - inst->conditional_mod = BRW_CONDITIONAL_L; - emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); + reg = emit_frontfacing_interpolation(ir); } else { - emit_general_interpolation(ir); - return; + reg = emit_general_interpolation(ir); } + assert(reg); + hash_table_insert(this->variable_ht, reg, ir); + return; } if (ir->mode == ir_var_uniform) { -- cgit v1.2.3 From 1fdc8c007ea66b4c9866bf2c679653a005307fa5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 11:19:48 -0700 Subject: i965: Add support for gl_FrontFacing on gen6. Fixes glsl1-gl_FrontFacing var (2) with new FS. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 49 ++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 10 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index c5013f05745..1ccf695a597 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -830,16 +830,33 @@ fs_reg * fs_visitor::emit_frontfacing_interpolation(ir_variable *ir) { fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); - struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); - /* bit 31 is "primitive is back face", so checking < (1 << 31) gives - * us front face - */ - fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, - *reg, - fs_reg(r1_6ud), - fs_reg(1u << 31))); - inst->conditional_mod = BRW_CONDITIONAL_L; - emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); + + /* The frontfacing comes in as a bit in the thread payload. */ + if (intel->gen >= 6) { + emit(fs_inst(BRW_OPCODE_ASR, + *reg, + fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)), + fs_reg(15))); + emit(fs_inst(BRW_OPCODE_NOT, + *reg, + *reg)); + emit(fs_inst(BRW_OPCODE_AND, + *reg, + *reg, + fs_reg(1))); + } else { + fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); + struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); + /* bit 31 is "primitive is back face", so checking < (1 << 31) gives + * us front face + */ + fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, + *reg, + fs_reg(r1_6ud), + fs_reg(1u << 31))); + inst->conditional_mod = BRW_CONDITIONAL_L; + emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); + } return reg; } @@ -2818,6 +2835,18 @@ fs_visitor::generate_code() case BRW_OPCODE_XOR: brw_XOR(p, dst, src[0], src[1]); break; + case BRW_OPCODE_NOT: + brw_NOT(p, dst, src[0]); + break; + case BRW_OPCODE_ASR: + brw_ASR(p, dst, src[0], src[1]); + break; + case BRW_OPCODE_SHR: + brw_SHR(p, dst, src[0], src[1]); + break; + case BRW_OPCODE_SHL: + brw_SHL(p, dst, src[0], src[1]); + break; case BRW_OPCODE_CMP: brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); -- cgit v1.2.3 From b380531fd40e0876218b1116502bafea7911bd3d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 12:10:31 -0700 Subject: i965: Don't assume that WPOS is always provided on gen6 in the new FS. We sensibly only provide it if the FS asks for it. We could actually skip WPOS unless the FS needed WPOS.zw, but that's something for later. Fixes: glsl-texture2d and probably many others. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 1ccf695a597..b93c27ec8ff 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2258,8 +2258,7 @@ fs_visitor::calculate_urb_setup() /* Figure out where each of the incoming setup attributes lands. */ if (intel->gen >= 6) { for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { - if (i == FRAG_ATTRIB_WPOS || - (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i))) { + if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)) { urb_setup[i] = urb_next++; } } -- cgit v1.2.3 From d3163912c1f15fcb44beb33c5069799d56e1dc16 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 6 Oct 2010 17:29:29 -0700 Subject: i965: Fix gen6 pointsize handling to match pre-gen6. Fixes point-line-no-cull. Bug #30532 --- src/mesa/drivers/dri/i965/gen6_sf_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c index 6c883381958..b2a6bd04e2f 100644 --- a/src/mesa/drivers/dri/i965/gen6_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c @@ -125,7 +125,8 @@ upload_sf_state(struct brw_context *brw) } /* _NEW_POINT */ - if (ctx->Point._Attenuated) + if (!(ctx->VertexProgram.PointSizeEnabled || + ctx->Point._Attenuated)) dw4 |= GEN6_SF_USE_STATE_POINT_WIDTH; dw4 |= U_FIXED(CLAMP(ctx->Point.Size, 0.125, 225.875), 3) << -- cgit v1.2.3 From 1d595c7cd4aefc7baf1942626f53bec8f6699f7f Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Thu, 7 Oct 2010 17:03:53 -0400 Subject: gles2: Add GL_EXT_texture_format_BGRA8888 support --- src/mesa/drivers/dri/intel/intel_extensions_es2.c | 1 + src/mesa/main/APIspec.xml | 11 ++++++++++- src/mesa/main/extensions.c | 4 ++++ src/mesa/main/mtypes.h | 1 + 4 files changed, 16 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/intel/intel_extensions_es2.c b/src/mesa/drivers/dri/intel/intel_extensions_es2.c index 24f64045ef8..ed5db20e38a 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions_es2.c +++ b/src/mesa/drivers/dri/intel/intel_extensions_es2.c @@ -69,6 +69,7 @@ static const char *es2_extensions[] = { "GL_ARB_depth_texture", "GL_EXT_packed_depth_stencil", "GL_EXT_framebuffer_object", + "GL_EXT_texture_format_BGRA8888", #if FEATURE_OES_EGL_image "GL_OES_EGL_image", diff --git a/src/mesa/main/APIspec.xml b/src/mesa/main/APIspec.xml index 4c5fd59d4fb..4dc0b0d4851 100644 --- a/src/mesa/main/APIspec.xml +++ b/src/mesa/main/APIspec.xml @@ -383,6 +383,7 @@ + @@ -458,11 +459,18 @@ - + + + + + + + +