From d4da253b298677c63def5f2f774608d660be31a1 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Wed, 29 Sep 2010 15:18:37 +0800 Subject: Revert "i965: Always set tiling for depth buffer on sandybridge" This reverts commit 0a1910c26760762eb8d67f68dfd87494ab479e38. oops, shouldn't apply tiling depth buffer for other chips as well. --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers') diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 7a334126f2b..6eeaba77720 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -289,7 +289,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | (BRW_TILEWALK_YMAJOR << 26) | - (1 << 27) | + ((region->tiling != I915_TILING_NONE) << 27) | (BRW_SURFACE_2D << 29)); OUT_RELOC(region->buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, -- cgit v1.2.3