From 94e3864707e48d4b1d5fb5f88a01370a73ddb0cb Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 15 May 2015 09:58:42 -0700 Subject: i965: Add and fix comments in brw_vue_map.c. Signed-off-by: Kenneth Graunke Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_vue_map.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_vue_map.c b/src/mesa/drivers/dri/i965/brw_vue_map.c index ff92bd266a4..76875789ba8 100644 --- a/src/mesa/drivers/dri/i965/brw_vue_map.c +++ b/src/mesa/drivers/dri/i965/brw_vue_map.c @@ -24,6 +24,15 @@ /** * @file brw_vue_map.c * + * This file computes the "VUE map" for a (non-fragment) shader stage, which + * describes the layout of its output varyings. The VUE map is used to match + * outputs from one stage with the inputs of the next. + * + * Largely, varyings can be placed however we like - producers/consumers simply + * have to agree on the layout. However, there is also a "VUE Header" that + * prescribes a fixed-layout for items that interact with fixed function + * hardware, such as the clipper and rasterizer. + * * Authors: * Paul Berry * Chris Forbes @@ -45,7 +54,7 @@ assign_vue_slot(struct brw_vue_map *vue_map, int varying) } /** - * Compute the VUE map for vertex shader program. + * Compute the VUE map for a shader stage. */ void brw_compute_vue_map(const struct brw_device_info *devinfo, @@ -76,6 +85,9 @@ brw_compute_vue_map(const struct brw_device_info *devinfo, /* VUE header: format depends on chip generation and whether clipping is * enabled. + * + * See the Sandybridge PRM, Volume 2 Part 1, section 1.5.1 (page 30), + * "Vertex URB Entry (VUE) Formats" which describes the VUE header layout. */ if (devinfo->gen < 6) { /* There are 8 dwords in VUE header pre-Ironlake: -- cgit v1.2.3