From f7285bdffcd8cca1c7d3066d38907a5987e844ea Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Tue, 29 Sep 2009 09:46:29 +0300 Subject: r600: clear position enable bit when when wpos is not used by FP Makes doom3 alot nicer.. --- src/mesa/drivers/dri/r600/r700_fragprog.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 78ce3ae4366..62a1ea1a22a 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -341,6 +341,11 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit); SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); } + else + { + CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit); + CLEARbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); + } ui = (unNumOfReg < ui) ? ui : unNumOfReg; -- cgit v1.2.3 From 5101215a64a69a212241eadba7f097cef33a0b5c Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 28 Sep 2009 10:42:35 +0300 Subject: r600: user correct alpha blend factor Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r700_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 98f116d0a6a..0d1f906d84f 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -467,10 +467,10 @@ static void r700SetBlendState(GLcontext * ctx) eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask); SETfield(blend_reg, - blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE), + blend_factor(ctx->Color.BlendSrcA, GL_TRUE), ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask); SETfield(blend_reg, - blend_factor(ctx->Color.BlendDstRGB, GL_FALSE), + blend_factor(ctx->Color.BlendDstA, GL_FALSE), ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask); switch (ctx->Color.BlendEquationA) { -- cgit v1.2.3 From bf68e54a4d69bdd9a01656919d3cd752c96157b3 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 28 Sep 2009 11:23:49 +0300 Subject: r600: use CB_TARGET_MASK instead of CB_SHADER_MASK for setting color mask makes blend functions work better Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r700_state.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 0d1f906d84f..244a016e07e 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -745,9 +745,9 @@ static void r700ColorMask(GLcontext * ctx, (b ? 4 : 0) | (a ? 8 : 0)); - if (mask != r700->CB_SHADER_MASK.u32All) { + if (mask != r700->CB_TARGET_MASK.u32All) { R600_STATECHANGE(context, cb); - SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); + SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); } } @@ -1758,7 +1758,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF; /* screen/window/view */ - SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); + SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask); context->radeon.hw.all_dirty = GL_TRUE; -- cgit v1.2.3 From 95851d8cb232cbd1312d2b8de471ba2aeb276911 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 9 Oct 2009 10:46:12 +0300 Subject: r600: fixup KIL instruction a bit - KILLGT takes 2 arguments - arb KIL has no dst register - add TODO about clause ending but currently piglit fp-kil passes and does not hang the card --- src/mesa/drivers/dri/r600/r700_assembler.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 00eda544d4c..e79c256c6b7 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -336,7 +336,8 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) switch (pAsm->D.dst.opcode) { - case SQ_OP2_INST_ADD: + case SQ_OP2_INST_ADD: + case SQ_OP2_INST_KILLGT: case SQ_OP2_INST_MUL: case SQ_OP2_INST_MAX: case SQ_OP2_INST_MIN: @@ -356,7 +357,6 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_MOV: case SQ_OP2_INST_FRACT: case SQ_OP2_INST_FLOOR: - case SQ_OP2_INST_KILLGT: case SQ_OP2_INST_EXP_IEEE: case SQ_OP2_INST_LOG_CLAMPED: case SQ_OP2_INST_LOG_IEEE: @@ -2617,15 +2617,15 @@ GLboolean assemble_FRC(r700_AssemblerBase *pAsm) GLboolean assemble_KIL(r700_AssemblerBase *pAsm) { + /* TODO: doc says KILL has to be last(end) ALU clause */ + checkop1(pAsm); pAsm->D.dst.opcode = SQ_OP2_INST_KILLGT; - - if ( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = 0; pAsm->D.dst.writex = 0; pAsm->D.dst.writey = 0; pAsm->D.dst.writez = 0; @@ -2638,20 +2638,11 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm) setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - - if(PROGRAM_TEMPORARY == pAsm->pILInst[pAsm->uiCurInst].DstReg.File) + if ( GL_FALSE == assemble_src(pAsm, 0, 1) ) { - pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].DstReg.Index + pAsm->starting_temp_register_number; - } - else - { //PROGRAM_OUTPUT - pAsm->S[1].src.reg = pAsm->uiFP_OutputMap[pAsm->pILInst[pAsm->uiCurInst].DstReg.Index]; + return GL_FALSE; } - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - noswizzle_PVSSRC(&(pAsm->S[1].src)); - if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; -- cgit v1.2.3 From 74c31e5d05f7ed342fb143cb6f637b54e8961973 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 12:20:26 +0300 Subject: r600: DPH adds w comp of second operand, so set first one to 1 instead --- src/mesa/drivers/dri/r600/r700_assembler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index e79c256c6b7..18377128835 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2508,7 +2508,7 @@ GLboolean assemble_DOT(r700_AssemblerBase *pAsm) } else if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_DPH) { - onecomp_PVSSRC(&(pAsm->S[1].src), 3); + onecomp_PVSSRC(&(pAsm->S[0].src), 3); } if ( GL_FALSE == next_ins(pAsm) ) -- cgit v1.2.3 From 606becc7f3513354548f587d84db731046616401 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 12:58:40 +0300 Subject: r600: LIT dst.y gets value from src.x seems I overlooked this when removing hardcoded swizzles for this one previously --- src/mesa/drivers/dri/r600/r700_assembler.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 18377128835..25b27cd8297 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2899,6 +2899,7 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = tmp; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); -- cgit v1.2.3 From a3fec141017a39916d07000a3aa00eef3c9ac8a7 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 14:57:45 +0300 Subject: r600: implement ProgramStringNotify need this to properly test with piglit/glean vert/fragprog tests copied mostly from r300, many thanks to osiris, nha, airlied, others... --- src/mesa/drivers/dri/r600/r700_oglprog.c | 55 ++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index 5290ef31be3..0d476fcd863 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -40,6 +40,24 @@ #include "r700_vertprog.h" +static void freeVertProgCache(GLcontext *ctx, struct r700_vertex_program_cont *cache) +{ + struct r700_vertex_program *tmp, *vp = cache->progs; + + while (vp) { + tmp = vp->next; + /* Release DMA region */ + r600DeleteShader(ctx, vp->shaderbo); + /* Clean up */ + Clean_Up_Assembler(&(vp->r700AsmCode)); + Clean_Up_Shader(&(vp->r700Shader)); + + _mesa_reference_vertprog(ctx, &vp->mesa_program, NULL); + _mesa_free(vp); + vp = tmp; + } +} + static struct gl_program *r700NewProgram(GLcontext * ctx, GLenum target, GLuint id) @@ -84,8 +102,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { - struct r700_vertex_program_cont * vpc; - struct r700_vertex_program *vp, *tmp; + struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog; struct r700_fragment_program * fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -95,20 +112,7 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vpc = (struct r700_vertex_program_cont*)prog; - vp = vpc->progs; - while (vp) { - tmp = vp->next; - /* Release DMA region */ - - r600DeleteShader(ctx, vp->shaderbo); - - /* Clean up */ - Clean_Up_Assembler(&(vp->r700AsmCode)); - Clean_Up_Shader(&(vp->r700Shader)); - _mesa_free(vp); - vp = tmp; - } + freeVertProgCache(ctx, vpc); break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -131,7 +135,24 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) static void r700ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) { - + struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog; + struct r700_fragment_program * fp = (struct r700_fragment_program*)prog; + + switch (target) { + case GL_VERTEX_PROGRAM_ARB: + freeVertProgCache(ctx, vpc); + vpc->progs = NULL; + break; + case GL_FRAGMENT_PROGRAM_ARB: + r600DeleteShader(ctx, fp->shaderbo); + Clean_Up_Assembler(&(fp->r700AsmCode)); + Clean_Up_Shader(&(fp->r700Shader)); + fp->translated = GL_FALSE; + fp->loaded = GL_FALSE; + fp->shaderbo = NULL; + break; + } + } static GLboolean r700IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) -- cgit v1.2.3 From 22a0029a68cf6a17e5d799c7d8eb8a699ccdeabb Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Thu, 15 Oct 2009 11:24:49 -0400 Subject: r600: fix tfp1 bo size Setting the wrong bo size resulting in an incomplete read cache flush when reading the texture. This fixes the compiz text corruption. [agd5f: take hw pitch alignment into account] --- src/mesa/drivers/dri/r600/r600_texstate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index bcb8d7c73d7..61ff7e8158e 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -721,7 +721,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t = radeon_tex_obj(tObj); - uint32_t pitch_val, size; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + const struct gl_texture_image *firstImage; + uint32_t pitch_val, size, row_align; if (!tObj) return; @@ -731,7 +733,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - size = pitch;//h * w * (depth / 8); + firstImage = t->base.Image[0][firstlevel]; + row_align = rmesa->radeon.texture_row_align - 1; + size = ((firstImage->Width * (depth / 8) + row_align) & ~row_align) * firstImage->Height; if (t->bo) { radeon_bo_unref(t->bo); t->bo = NULL; -- cgit v1.2.3 From e5d6450c2c85cc7d645cb0736194f41e5393802d Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Wed, 14 Oct 2009 13:58:56 -0500 Subject: radeon: return EINVAL for 0 length buffers. Signed-off-by: Robert Noland --- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 3e7547d2f9d..ce60a2f7eae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -710,6 +710,10 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo, bo, bo->size, bo_legacy->map_count); return -EINVAL; } + if(bo->size == 0) { + fprintf(stderr, "bo(%p) has size 0.\n", bo); + return -EINVAL; + } if (bo_legacy->static_bo || bo_legacy->validated) { *soffset = bo_legacy->offset; *eoffset = bo_legacy->offset + bo->size; -- cgit v1.2.3 From a176b1c5d8b14601ec7e6ca9599c55fcc4797a7d Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Wed, 14 Oct 2009 14:02:12 -0500 Subject: r600: cleanup in r600_cs_process_relocs(). Signed-off-by: Robert Noland --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 3cfe03a45f7..d27a3245a39 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -254,7 +254,7 @@ static int r600_cs_process_relocs(struct radeon_cs *cs, relocs = (struct r600_cs_reloc_legacy *)cs->relocs; restart: for (i = 0; i < cs->crelocs; i++) { - uint32_t soffset, eoffset, asicoffset; + uint32_t soffset, eoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); @@ -262,24 +262,12 @@ restart: goto restart; } if (r) { - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + fprintf(stderr, "invalid bo(%p) [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); return r; } - asicoffset = soffset; for (j = 0; j < relocs[i].cindices; j++) { - if (asicoffset >= eoffset) { - /* radeon_bo_debug(relocs[i].base.bo, 12); */ - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", - relocs[i].base.bo, soffset, eoffset); - fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", - relocs[i].base.bo, - cs->packets[relocs[i].indices[j]], - eoffset); - exit(0); - return -EINVAL; - } /* pkt3 nop header in ib chunk */ cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; /* reloc index in ib chunk */ @@ -287,7 +275,7 @@ restart: } /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ - reloc_chunk[offset_dw] = asicoffset; + reloc_chunk[offset_dw] = soffset; reloc_chunk[offset_dw + 3] = 0; offset_dw += 4; -- cgit v1.2.3 From 16c6a3b71e6be04b6bb3d08fcb658194c5251fc7 Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Wed, 14 Oct 2009 14:04:24 -0500 Subject: r600: FRAG_ATTRIB_WPOS and FRAG_ATTRIB_FOGC appear to be supported. Report unsupported attributes while I'm here. Signed-off-by: Robert Noland --- src/mesa/drivers/dri/r600/r700_assembler.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 25b27cd8297..a683008746d 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1180,8 +1180,10 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) case PROGRAM_INPUT: switch (pILInst->SrcReg[0].Index) { + case FRAG_ATTRIB_WPOS: case FRAG_ATTRIB_COL0: case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_FOGC: case FRAG_ATTRIB_TEX0: case FRAG_ATTRIB_TEX1: case FRAG_ATTRIB_TEX2: @@ -1194,7 +1196,16 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; pAsm->S[0].src.rtype = SRC_REG_INPUT; - break; + break; + case FRAG_ATTRIB_FACE: + fprintf(stderr, "FRAG_ATTRIB_FACE unsupported\n"); + break; + case FRAG_ATTRIB_PNTC: + fprintf(stderr, "FRAG_ATTRIB_PNTC unsupported\n"); + break; + case FRAG_ATTRIB_VAR0: + fprintf(stderr, "FRAG_ATTRIB_VAR0 unsupported\n"); + break; } break; } -- cgit v1.2.3 From 3f30b0709b5a71915df336194f9f805e4c306cef Mon Sep 17 00:00:00 2001 From: Owen Taylor Date: Wed, 14 Oct 2009 16:20:07 -0400 Subject: Use the right pitch when rendering to a texture We need to get the pitch from the texture level we are rendering to, rather than just using the base texel width. --- src/mesa/drivers/dri/radeon/radeon_fbo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index d83b166742c..2012cbcf838 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -445,7 +445,6 @@ restart: goto restart; } - rrb->pitch = texImage->Width * rrb->cpp; rrb->base.InternalFormat = rrb->base._ActualFormat; rrb->base.Width = texImage->Width; rrb->base.Height = texImage->Height; @@ -555,8 +554,10 @@ radeon_render_texture(GLcontext * ctx, imageOffset += offsets[att->Zoffset]; } - /* store that offset in the region */ + /* store that offset in the region, along with the correct pitch for + * the image we are rendering to */ rrb->draw_offset = imageOffset; + rrb->pitch = radeon_image->mt->levels[att->TextureLevel].rowstride; /* update drawing region, etc */ radeon_draw_buffer(ctx, fb); -- cgit v1.2.3 From 3594b53c0173ac810106f667604bf94b5cfc4a1e Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Fri, 16 Oct 2009 20:21:17 +0200 Subject: r300: fix vertex program parameters limits --- src/mesa/drivers/dri/r300/r300_vertprog.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c index 2f7b67c1431..ed8b7881081 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ b/src/mesa/drivers/dri/r300/r300_vertprog.c @@ -62,12 +62,6 @@ static int r300VertexProgUpdateParams(GLcontext * ctx, struct r300_vertex_progra } } - if (vp->code.constants.Count * 4 > VSF_MAX_FRAGMENT_LENGTH) { - /* Should have checked this earlier... */ - fprintf(stderr, "%s:Params exhausted\n", __FUNCTION__); - _mesa_exit(-1); - } - for(i = 0; i < vp->code.constants.Count; ++i) { const float * src = 0; const struct rc_constant * constant = &vp->code.constants.Constants[i]; @@ -281,6 +275,11 @@ static struct r300_vertex_program *build_program(GLcontext *ctx, } r3xx_compile_vertex_program(&compiler); + + if (vp->code.constants.Count > ctx->Const.VertexProgram.MaxParameters) { + rc_error(&compiler.Base, "Program exceeds constant buffer size limit\n"); + } + vp->error = compiler.Base.Error; vp->Base->Base.InputsRead = vp->code.InputsRead; @@ -334,7 +333,6 @@ struct r300_vertex_program * r300SelectAndTranslateVertexShader(GLcontext *ctx) #define bump_vpu_count(ptr, new_count) do { \ drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr)); \ int _nc=(new_count)/4; \ - assert(_nc < 256); \ if(_nc>_p->vpu.count)_p->vpu.count=_nc; \ } while(0) -- cgit v1.2.3 From 8123180ea649540fb7319bc79ad77dca0d5d68cd Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Mon, 19 Oct 2009 09:47:39 -0500 Subject: r600: Fix size calculation for 24 bit depth size was being calculated based on 3 bytes per pixel with 24 bit depth instead of 4 bytes. This caused corruption in the bottom 25% of objects. This finishes fixing the menu/text corruption in compiz/kde4. Signed-off-by: Robert Noland --- src/mesa/drivers/dri/r600/r600_texstate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 61ff7e8158e..a30703e41b0 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -723,7 +723,7 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, radeonTexObjPtr t = radeon_tex_obj(tObj); int firstlevel = t->mt ? t->mt->firstLevel : 0; const struct gl_texture_image *firstImage; - uint32_t pitch_val, size, row_align; + uint32_t pitch_val, size, row_align, bpp; if (!tObj) return; @@ -733,9 +733,13 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; + bpp = depth / 8; + if (bpp == 3) + bpp = 4; + firstImage = t->base.Image[0][firstlevel]; row_align = rmesa->radeon.texture_row_align - 1; - size = ((firstImage->Width * (depth / 8) + row_align) & ~row_align) * firstImage->Height; + size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height; if (t->bo) { radeon_bo_unref(t->bo); t->bo = NULL; -- cgit v1.2.3 From 16e21191e26084848c7e6e3ffd9e15ef670855c5 Mon Sep 17 00:00:00 2001 From: Mathias Fröhlich Date: Mon, 19 Oct 2009 11:47:21 -0400 Subject: r300: fix texture size handling with size > 2048 The in kernel texture check fails because of both bit11 flags being set on 16x16 textures. It tuns out that these bits are still set and not cleared in the pp_txpitch field of the texture. The attached patch at least helps for this case on my machine. It clears the bit 11 from the pitch field if the texture is smaller and masks out that hight bits on the conventional width and height field. Fixes bug 24584 --- src/mesa/drivers/dri/r300/r300_texstate.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index f030451b282..65cabccdc1e 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -225,10 +225,10 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) if (t->image_override && t->bo) return; - t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) - | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT) - | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT) - | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT)); + t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT))) + | ((R300_TX_HEIGHTMASK_MASK & ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT))) + | ((R300_TX_DEPTHMASK_MASK & ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT))) + | ((R300_TX_MAX_MIP_LEVEL_MASK & ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT)))); t->tile_bits = 0; @@ -248,8 +248,12 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { if (firstImage->Width > 2048) t->pp_txpitch |= R500_TXWIDTH_BIT11; + else + t->pp_txpitch &= ~R500_TXWIDTH_BIT11; if (firstImage->Height > 2048) t->pp_txpitch |= R500_TXHEIGHT_BIT11; + else + t->pp_txpitch &= ~R500_TXHEIGHT_BIT11; } } @@ -479,16 +483,20 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo break; } pitch_val--; - t->pp_txsize = ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT) | - ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT); + t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT))) + | ((R300_TX_HEIGHTMASK_MASK & ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT)))); t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; t->pp_txpitch |= pitch_val; if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { if (rb->base.Width > 2048) t->pp_txpitch |= R500_TXWIDTH_BIT11; + else + t->pp_txpitch &= ~R500_TXWIDTH_BIT11; if (rb->base.Height > 2048) t->pp_txpitch |= R500_TXHEIGHT_BIT11; + else + t->pp_txpitch &= ~R500_TXHEIGHT_BIT11; } t->validated = GL_TRUE; _mesa_unlock_texture(radeon->glCtx, texObj); -- cgit v1.2.3