From 532b1fecd93fd30d3b1b101b55fd2c6e074088ad Mon Sep 17 00:00:00 2001 From: Paul Berry Date: Tue, 7 Jan 2014 06:29:47 -0800 Subject: i965: Fix clears of layered framebuffers with mismatched layer counts. Previously, Mesa enforced the following rule (from ARB_geometry_shader4's list of criteria for framebuffer completeness): * If any framebuffer attachment is layered, all attachments must have the same layer count. For three-dimensional textures, the layer count is the depth of the attached volume. For cube map textures, the layer count is always six. For one- and two-dimensional array textures, the layer count is simply the number of layers in the array texture. { FRAMEBUFFER_INCOMPLETE_LAYER_COUNT_ARB } However, when ARB_geometry_shader4 was adopted into GL 3.2, this rule was dropped; GL 3.2 permits different attachments to have different layer counts. This patch brings Mesa in line with GL 3.2. In order to ensure that layered clears properly clear all layers, we now have to keep track of the maximum number of layers in a layered framebuffer. Fixes the following piglit tests in spec/!OpenGL 3.2/layered-rendering: - clear-color-all-types 1d_array mipmapped - clear-color-all-types 1d_array single_level - clear-color-mismatched-layer-count - framebuffer-layer-count-mismatch Reviewed-by: Anuj Phogat Reviewed-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 8 ++++---- src/mesa/drivers/dri/i965/brw_clear.c | 6 +++--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index 072ad5581e6..c55108a69fd 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp @@ -573,14 +573,14 @@ brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb, if (rb == NULL) continue; - if (fb->NumLayers > 0) { + if (fb->MaxNumLayers > 0) { unsigned layer_multiplier = (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ? irb->mt->num_samples : 1; - assert(fb->NumLayers * layer_multiplier == - irb->mt->level[irb->mt_level].depth); - for (unsigned layer = 0; layer < fb->NumLayers; layer++) { + unsigned num_layers = + irb->mt->level[irb->mt_level].depth / layer_multiplier; + for (unsigned layer = 0; layer < num_layers; layer++) { if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear, layer * layer_multiplier)) { return false; diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 1cac996482d..fe68d9efcb9 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -181,9 +181,9 @@ brw_fast_clear_depth(struct gl_context *ctx) */ intel_batchbuffer_emit_mi_flush(brw); - if (fb->NumLayers > 0) { - assert(fb->NumLayers == depth_irb->mt->level[depth_irb->mt_level].depth); - for (unsigned layer = 0; layer < fb->NumLayers; layer++) { + if (fb->MaxNumLayers > 0) { + unsigned num_layers = depth_irb->mt->level[depth_irb->mt_level].depth; + for (unsigned layer = 0; layer < num_layers; layer++) { intel_hiz_exec(brw, mt, depth_irb->mt_level, layer, GEN6_HIZ_OP_DEPTH_CLEAR); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index acb1a40e632..e83763137d7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -700,7 +700,7 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw) for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], - ctx->DrawBuffer->NumLayers > 0, i); + ctx->DrawBuffer->MaxNumLayers > 0, i); } else { brw->vtbl.update_null_renderbuffer_surface(brw, i); } diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index 37a39b83fb7..6cec0ff21ac 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -121,7 +121,7 @@ upload_clip_state(struct brw_context *brw) dw2); OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT | U_FIXED(255.875, 3) << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT | - (fb->NumLayers > 0 ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX)); + (fb->MaxNumLayers > 0 ? 0 : GEN6_CLIP_FORCE_ZERO_RTAINDEX)); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 42519494d3c..8fb0eec7765 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -81,7 +81,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, break; } - if (fb->NumLayers > 0 || !irb) { + if (fb->MaxNumLayers > 0 || !irb) { min_array_element = 0; } else if (irb->mt->num_samples > 1) { /* Convert physical layer to logical layer. */ -- cgit v1.2.3