From 49a938a265f5959c9b558995cc658f80acb6eb18 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Fri, 20 Feb 2015 12:12:25 -0800 Subject: i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data The brw_imm_ud will yield a HW_REG which then will introduce a barrier for certain optimization opportunities. No piglit regressions seen with gen8 (simd8vs). Suggested-by: Matt Turner Signed-off-by: Jordan Justen Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index fa7d32cdab2..b1b75821c73 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -3016,7 +3016,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, */ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xffff)))->force_writemask_all = true; + fs_reg(0xffff)))->force_writemask_all = true; } length++; @@ -3079,7 +3079,7 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, */ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xffff)))->force_writemask_all = true; + fs_reg(0xffff)))->force_writemask_all = true; } /* Set the surface read offset. */ -- cgit v1.2.3