From 05362682672f5edbd57437fa29c3d5d7d2ad7aba Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Tue, 22 Aug 2006 23:29:03 +0800
Subject: adding pci id of Crestline

---
 src/mesa/drivers/dri/i965/intel_context.c | 3 +++
 src/mesa/drivers/dri/i965/intel_context.h | 1 +
 2 files changed, 4 insertions(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index d13e287fa76..5fc3d7150c3 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -117,6 +117,9 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
       case PCI_CHIP_I946_GZ:
 	 chipset = "Intel(R) 946GZ"; break;
          break;
+      case PCI_CHIP_CRESTLINE:
+	 chipset = "Intel(R) Crestline"; break;
+         break;
       default:
 	 chipset = "Unknown Intel Chipset"; break;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 8367a957109..85e574cdaf4 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -383,6 +383,7 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I965_Q			0x2992
 #define PCI_CHIP_I965_G_1		0x2982
 #define PCI_CHIP_I946_GZ		0x2972
+#define PCI_CHIP_CRESTLINE		0x2A02
 
 
 /* ================================================================
-- 
cgit v1.2.3


From 183abbcd6b48178a3412ee8992131ce8c7e7b69d Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 11 Oct 2006 12:16:09 -0700
Subject: Connect INTEL_DEBUG=sync up to cmd/batch ioctls.

---
 src/mesa/drivers/dri/i965/intel_ioctl.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/intel_ioctl.c b/src/mesa/drivers/dri/i965/intel_ioctl.c
index d1f2e3f27ca..d8176c559e5 100644
--- a/src/mesa/drivers/dri/i965/intel_ioctl.c
+++ b/src/mesa/drivers/dri/i965/intel_ioctl.c
@@ -43,6 +43,26 @@
 #include "drm.h"
 #include "bufmgr.h"
 
+static int intelWaitIdleLocked( struct intel_context *intel )
+{
+   static int in_wait_idle = 0;
+   unsigned int fence;
+
+   if (!in_wait_idle) {
+      if (INTEL_DEBUG & DEBUG_SYNC) {
+	 fprintf(stderr, "waiting for idle\n");
+      }
+
+      in_wait_idle = 1;
+      fence = bmSetFence(intel);
+      intelWaitIrq(intel, fence);
+      in_wait_idle = 0;
+
+      return bmTestFence(intel, fence);
+   } else {
+      return 1;
+   }
+}
 
 int intelEmitIrqLocked( struct intel_context *intel )
 {
@@ -139,7 +159,11 @@ void intel_batch_ioctl( struct intel_context *intel,
 	 UNLOCK_HARDWARE(intel);
 	 exit(1);
       }
-   }      
+
+      if (INTEL_DEBUG & DEBUG_SYNC) {
+	intelWaitIdleLocked(intel);
+      }
+   }
 }
 
 void intel_cmd_ioctl( struct intel_context *intel, 
@@ -171,5 +195,9 @@ void intel_cmd_ioctl( struct intel_context *intel,
 	 UNLOCK_HARDWARE(intel);
 	 exit(1);
       }
-   }      
+
+      if (INTEL_DEBUG & DEBUG_SYNC) {
+	intelWaitIdleLocked(intel);
+      }
+   }
 }
-- 
cgit v1.2.3


From 9a94dae4c292bfc2aa94a3f86865550e2217b870 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 18 Oct 2006 00:24:01 -0700
Subject: Avoid branch instructions while in single program flow mode.

There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn.  In single program flow mode, those
stacks are not writable, so we can't initialize them.  However, they do get
read during ELSE and ENDIF instructions.  So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail.  This is also a minor optimization as no ENDIF equivalent is necessary.
---
 src/mesa/drivers/dri/i965/brw_clip.c    |   2 +
 src/mesa/drivers/dri/i965/brw_eu.h      |   1 +
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 155 ++++++++++++++++++++------------
 src/mesa/drivers/dri/i965/brw_gs.c      |   4 +-
 src/mesa/drivers/dri/i965/brw_structs.h |  22 ++++-
 5 files changed, 125 insertions(+), 59 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 0e8591aaa8d..3bec153075a 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -62,6 +62,8 @@ static void compile_clip_prog( struct brw_context *brw,
     */
    brw_init_compile(&c.func);
 
+   c.func.single_program_flow = 1;
+
    c.key = *key;
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 1afa0f816b8..d4dbcf38a7a 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -104,6 +104,7 @@ struct brw_compile {
    struct brw_instruction *current;
 
    GLuint flag_value;
+   GLboolean single_program_flow;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6425c91450c..9992b47d8ae 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -464,7 +464,6 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p,
    return insn;
 }
 
-
 /* EU takes the value from the flag register and pushes it onto some
  * sort of a stack (presumably merging with any flag value already on
  * the stack).  Within an if block, the flags at the top of the stack
@@ -482,7 +481,16 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p,
  */
 struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_IF);   
+   struct brw_instruction *insn;
+
+   if (p->single_program_flow) {
+      assert(execute_size == BRW_EXECUTE_1);
+
+      insn = next_insn(p, BRW_OPCODE_ADD);
+      insn->header.predicate_inverse = 1;
+   } else {
+      insn = next_insn(p, BRW_OPCODE_IF);
+   }
 
    /* Override the defaults for this instruction:
     */
@@ -504,7 +512,13 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
 struct brw_instruction *brw_ELSE(struct brw_compile *p, 
 				 struct brw_instruction *if_insn)
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ELSE);   
+   struct brw_instruction *insn;
+
+   if (p->single_program_flow) {
+      insn = next_insn(p, BRW_OPCODE_ADD);
+   } else {
+      insn = next_insn(p, BRW_OPCODE_ELSE);
+   }
 
    brw_set_dest(insn, brw_ip_reg());
    brw_set_src0(insn, brw_ip_reg());
@@ -516,11 +530,17 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
 
    /* Patch the if instruction to point at this instruction.
     */
-   assert(if_insn->header.opcode == BRW_OPCODE_IF);
+   if (p->single_program_flow) {
+      assert(if_insn->header.opcode == BRW_OPCODE_ADD);
 
-   if_insn->bits3.if_else.jump_count = insn - if_insn; 
-   if_insn->bits3.if_else.pop_count = 1;
-   if_insn->bits3.if_else.pad0 = 0;
+      if_insn->bits3.ud = (insn - if_insn + 1) * 16;
+   } else {
+      assert(if_insn->header.opcode == BRW_OPCODE_IF);
+
+      if_insn->bits3.if_else.jump_count = insn - if_insn;
+      if_insn->bits3.if_else.pop_count = 1;
+      if_insn->bits3.if_else.pad0 = 0;
+   }
 
    return insn;
 }
@@ -528,63 +548,76 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
 void brw_ENDIF(struct brw_compile *p, 
 	       struct brw_instruction *patch_insn)
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);   
+   if (p->single_program_flow) {
+      /* In single program flow mode, there's no need to execute an ENDIF,
+       * since we don't need to do any stack operations, and if we're executing
+       * currently, we want to just continue executing.
+       */
+      struct brw_instruction *next = &p->store[p->nr_insn];
 
-   brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
-   brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
-   brw_set_src1(insn, brw_imm_d(0x0));
+      assert(patch_insn->header.opcode == BRW_OPCODE_ADD);
 
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.execution_size = patch_insn->header.execution_size;
-   insn->header.mask_control = BRW_MASK_ENABLE;
+      patch_insn->bits3.ud = (next - patch_insn) * 16;
+   } else {
+      struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
 
-   assert(patch_insn->bits3.if_else.jump_count == 0);
-      
-   /* Patch the if or else instructions to point at this or the next
-    * instruction respectively.
-    */
-   if (patch_insn->header.opcode == BRW_OPCODE_IF) {
-      /* Automagically turn it into an IFF:
+      brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+      brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+      brw_set_src1(insn, brw_imm_d(0x0));
+
+      insn->header.compression_control = BRW_COMPRESSION_NONE;
+      insn->header.execution_size = patch_insn->header.execution_size;
+      insn->header.mask_control = BRW_MASK_ENABLE;
+
+      assert(patch_insn->bits3.if_else.jump_count == 0);
+
+      /* Patch the if or else instructions to point at this or the next
+       * instruction respectively.
        */
-      patch_insn->header.opcode = BRW_OPCODE_IFF;
-      patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
-      patch_insn->bits3.if_else.pop_count = 0;
-      patch_insn->bits3.if_else.pad0 = 0;
+      if (patch_insn->header.opcode == BRW_OPCODE_IF) {
+	 /* Automagically turn it into an IFF:
+	  */
+	 patch_insn->header.opcode = BRW_OPCODE_IFF;
+	 patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
+	 patch_insn->bits3.if_else.pop_count = 0;
+	 patch_insn->bits3.if_else.pad0 = 0;
+      } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
+	 patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
+	 patch_insn->bits3.if_else.pop_count = 1;
+	 patch_insn->bits3.if_else.pad0 = 0;
+      } else {
+	 assert(0);
+      }
 
+      /* Also pop item off the stack in the endif instruction:
+       */
+      insn->bits3.if_else.jump_count = 0;
+      insn->bits3.if_else.pop_count = 1;
+      insn->bits3.if_else.pad0 = 0;
    }
-   else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
-      patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
-      patch_insn->bits3.if_else.pop_count = 1;
-      patch_insn->bits3.if_else.pad0 = 0;
-   }
-   else {
-      assert(0);
-   }
-
-   /* Also pop item off the stack in the endif instruction:
-    */
-   insn->bits3.if_else.jump_count = 0;
-   insn->bits3.if_else.pop_count = 1; 
-   insn->bits3.if_else.pad0 = 0;
 }
 
 /* DO/WHILE loop:
  */
 struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);   
+   if (p->single_program_flow) {
+      return &p->store[p->nr_insn];
+   } else {
+      struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
 
-   /* Override the defaults for this instruction:
-    */
-   brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
-   brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
-   brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+      /* Override the defaults for this instruction:
+       */
+      brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+      brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+      brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
 
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.execution_size = execute_size;
-/*    insn->header.mask_control = BRW_MASK_ENABLE; */
+      insn->header.compression_control = BRW_COMPRESSION_NONE;
+      insn->header.execution_size = execute_size;
+      /* insn->header.mask_control = BRW_MASK_ENABLE; */
 
-   return insn;
+      return insn;
+   }
 }
 
 
@@ -592,19 +625,31 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
 void brw_WHILE(struct brw_compile *p, 
 	       struct brw_instruction *do_insn)
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WHILE);
+   struct brw_instruction *insn;
+
+   if (p->single_program_flow)
+      insn = next_insn(p, BRW_OPCODE_ADD);
+   else
+      insn = next_insn(p, BRW_OPCODE_WHILE);
 
    brw_set_dest(insn, brw_ip_reg());
    brw_set_src0(insn, brw_ip_reg());
    brw_set_src1(insn, brw_imm_d(0x0));
 
    insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.execution_size = do_insn->header.execution_size;
 
-   assert(do_insn->header.opcode == BRW_OPCODE_DO);
-   insn->bits3.if_else.jump_count = do_insn - insn;
-   insn->bits3.if_else.pop_count = 0;
-   insn->bits3.if_else.pad0 = 0;
+   if (p->single_program_flow) {
+      insn->header.execution_size = BRW_EXECUTE_1;
+
+      insn->bits3.d = (do_insn - insn) * 16;
+   } else {
+      insn->header.execution_size = do_insn->header.execution_size;
+
+      assert(do_insn->header.opcode == BRW_OPCODE_DO);
+      insn->bits3.if_else.jump_count = do_insn - insn;
+      insn->bits3.if_else.pop_count = 0;
+      insn->bits3.if_else.pad0 = 0;
+   }
 
 /*    insn->header.mask_control = BRW_MASK_ENABLE; */
 
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 7d3f9dd5e3b..9066e42252d 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -66,7 +66,9 @@ static void compile_gs_prog( struct brw_context *brw,
    /* Begin the compilation:
     */
    brw_init_compile(&c.func);
-	
+
+   c.func.single_program_flow = 1;
+
    /* For some reason the thread is spawned with only 4 channels
     * unmasked.  
     */
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 25acdcfe947..10fee944e8d 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -519,7 +519,22 @@ struct thread3
 struct brw_clip_unit_state
 {
    struct thread0 thread0;
-   struct thread1 thread1;
+   struct
+   {
+      GLuint pad0:7;
+      GLuint sw_exception_enable:1;
+      GLuint pad1:3;
+      GLuint mask_stack_exception_enable:1;
+      GLuint pad2:1;
+      GLuint illegal_op_exception_enable:1;
+      GLuint pad3:2;
+      GLuint floating_point_mode:1;
+      GLuint thread_priority:1;
+      GLuint binding_table_entry_count:8;
+      GLuint pad4:5;
+      GLuint single_program_flow:1;
+   } thread1;
+
    struct thread2 thread2;
    struct thread3 thread3;
 
@@ -532,8 +547,8 @@ struct brw_clip_unit_state
       GLuint pad1:1;
       GLuint urb_entry_allocation_size:5; 
       GLuint pad2:1;
-      GLuint max_threads:6; 	/* may be less */
-      GLuint pad3:1;
+      GLuint max_threads:1; 	/* may be less */
+      GLuint pad3:6;
    } thread4;   
       
    struct
@@ -1322,6 +1337,7 @@ struct brw_instruction
 	 GLuint end_of_thread:1;
       } generic;
 
+      GLint d;
       GLuint ud;
    } bits3;
 };
-- 
cgit v1.2.3


From 696fe3f52e0e7893740b430835f8c95611de3dd3 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Wed, 13 Dec 2006 13:24:35 -0800
Subject: if (tex width < 4), mipmap calculation will be out of range

---
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1353325afff..bf7047f644e 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -138,7 +138,7 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
 	 
 	 /* Layout_below: step right after second mipmap.
 	  */
-	 if (level == mt->first_level + 1) {
+	 if (level == mt->first_level + 1 && mt->pitch > 4) {
 	    x += mt->pitch / 2;
 	    x = (x + 3) & ~ 3;
 	 }
-- 
cgit v1.2.3


From aeda4c589ada4e6304577e55d55b5c50bc274793 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Wed, 13 Dec 2006 13:25:12 -0800
Subject: ARB_occlusion_query support

---
 src/mesa/drivers/dri/i965/brw_wm_state.c       |  2 +-
 src/mesa/drivers/dri/i965/intel_context.c      | 34 ++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/intel_context.h      |  1 +
 src/mesa/drivers/dri/i965/server/i830_common.h | 19 ++++++++++++++
 4 files changed, 55 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 4707a709e77..e41042d6d27 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -168,7 +168,7 @@ static void upload_wm_unit(struct brw_context *brw )
       wm.wm5.line_stipple = 1;
    }
 
-   if (INTEL_DEBUG & DEBUG_STATS)
+   if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
       wm.wm4.stats_enable = 1;
 
    brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 5fc3d7150c3..6bcc984285c 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -70,6 +70,7 @@ int INTEL_DEBUG = (0);
 #define need_GL_ARB_vertex_buffer_object
 #define need_GL_ARB_vertex_program
 #define need_GL_ARB_window_pos
+#define need_GL_ARB_occlusion_query
 #define need_GL_EXT_blend_color
 #define need_GL_EXT_blend_equation_separate
 #define need_GL_EXT_blend_func_separate
@@ -160,6 +161,7 @@ const struct dri_extension card_extensions[] =
     { "GL_ARB_vertex_buffer_object",       GL_ARB_vertex_buffer_object_functions },
     { "GL_ARB_vertex_program",             GL_ARB_vertex_program_functions },
     { "GL_ARB_window_pos",                 GL_ARB_window_pos_functions },
+    { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
     { "GL_EXT_blend_color",                GL_EXT_blend_color_functions },
     { "GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions },
     { "GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions },
@@ -244,6 +246,36 @@ void intelFinish( GLcontext *ctx )
    bmFinishFence(intel, bmLockAndFence(intel));
 }
 
+static void
+intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+	struct intel_context *intel = intel_context( ctx );
+	GLuint64EXT tmp = 0;	
+	drmI830MMIO io = {
+		.read_write = MMIO_WRITE,
+		.reg = MMIO_REGS_PS_DEPTH_COUNT,
+		.data = &tmp 
+	};
+	intel->stats_wm = GL_TRUE;
+	intelFinish(&intel->ctx);
+	drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+}
+
+static void
+intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+	struct intel_context *intel = intel_context( ctx );
+	drmI830MMIO io = {
+		.read_write = MMIO_READ,
+		.reg = MMIO_REGS_PS_DEPTH_COUNT,
+		.data = &q->Result
+	};
+	intelFinish(&intel->ctx);
+	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	q->Ready = GL_TRUE;
+	intel->stats_wm = GL_FALSE;
+}
+
 
 void intelInitDriverFunctions( struct dd_function_table *functions )
 {
@@ -253,6 +285,8 @@ void intelInitDriverFunctions( struct dd_function_table *functions )
    functions->Finish = intelFinish;
    functions->GetString = intelGetString;
    functions->UpdateState = intelInvalidateState;
+   functions->BeginQuery = intelBeginQuery;
+   functions->EndQuery = intelEndQuery;
 
    /* CopyPixels can be accelerated even with the current memory
     * manager:
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 85e574cdaf4..39eb7753017 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -177,6 +177,7 @@ struct intel_context
    GLuint second_last_swap_fence;
    
    GLboolean aub_wrap;
+   GLboolean stats_wm;
 
    struct intel_batchbuffer *batch;
 
diff --git a/src/mesa/drivers/dri/i965/server/i830_common.h b/src/mesa/drivers/dri/i965/server/i830_common.h
index e3bbdc79070..f320378c2a5 100644
--- a/src/mesa/drivers/dri/i965/server/i830_common.h
+++ b/src/mesa/drivers/dri/i965/server/i830_common.h
@@ -52,6 +52,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define DRM_I830_INIT_HEAP                0x0a
 #define DRM_I830_CMDBUFFER                0x0b
 #define DRM_I830_DESTROY_HEAP             0x0c
+#define DRM_I830_MMIO		       	  0x10
 
 typedef struct {
    enum {
@@ -199,5 +200,23 @@ typedef struct {
 	int region;
 } drmI830MemDestroyHeap;
 
+#define MMIO_READ  0
+#define MMIO_WRITE 1
+
+#define MMIO_REGS_IA_PRIMATIVES_COUNT           0
+#define MMIO_REGS_IA_VERTICES_COUNT             1
+#define MMIO_REGS_VS_INVOCATION_COUNT           2
+#define MMIO_REGS_GS_PRIMITIVES_COUNT           3
+#define MMIO_REGS_GS_INVOCATION_COUNT           4
+#define MMIO_REGS_CL_PRIMITIVES_COUNT           5
+#define MMIO_REGS_CL_INVOCATION_COUNT           6
+#define MMIO_REGS_PS_INVOCATION_COUNT           7
+#define MMIO_REGS_PS_DEPTH_COUNT                8
+
+typedef struct {
+        unsigned int read_write:1;
+        unsigned int reg:31;
+        void __user *data;
+} drmI830MMIO;
 
 #endif /* _I830_DRM_H_ */
-- 
cgit v1.2.3


From 4720cd00507f2c13becf318709f7c1fe24ba5146 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Tue, 12 Dec 2006 14:56:59 +0800
Subject:   fix bug #99.   prim_count overflow when there is more than 1
 cliprect (cherry picked from 84b958d66fe7d3fe03ed12b493e3f3197f656531 commit)

---
 src/mesa/drivers/dri/i965/brw_exec_api.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_exec_api.c b/src/mesa/drivers/dri/i965/brw_exec_api.c
index 470fa6f4177..8b243c60842 100644
--- a/src/mesa/drivers/dri/i965/brw_exec_api.c
+++ b/src/mesa/drivers/dri/i965/brw_exec_api.c
@@ -42,6 +42,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "dispatch.h"
 
 #include "brw_exec.h"
+#include "intel_context.h"
+
 
 static void reset_attrfv( struct brw_exec_context *exec );
 
@@ -522,6 +524,14 @@ static void GLAPIENTRY brw_exec_Begin( GLenum mode )
       
 }
 
+static GLuint brw_max_prim( GLcontext *ctx )
+{
+        struct intel_context *intel = intel_context( ctx );
+        if (intel->numClipRects <= 1)
+                return BRW_MAX_PRIM;
+        return BRW_MAX_PRIM/intel->numClipRects;
+}
+
 static void GLAPIENTRY brw_exec_End( void )
 {
    GET_CURRENT_CONTEXT( ctx ); 
@@ -536,7 +546,7 @@ static void GLAPIENTRY brw_exec_End( void )
 
       ctx->Driver.CurrentExecPrimitive = GL_POLYGON+1;
 
-      if (exec->vtx.prim_count == BRW_MAX_PRIM)
+      if (exec->vtx.prim_count >= brw_max_prim(ctx))
 	 brw_exec_vtx_flush( exec );	
    }
    else 
-- 
cgit v1.2.3


From ed7fbad2066f846bf9466b13b184a50d6f87f972 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Wed, 13 Dec 2006 15:22:45 +0800
Subject:   Fix bug #93, i965 driver not thread safe.   I am not confident of
 it is 100% thread safe now.   bufmgr_fake.c need a total rewrite later
 (cherry picked from 606632ca27558ee1335be2f4a5906f2baa240a6a commit)

---
 src/mesa/drivers/dri/i965/bufmgr.h      |  2 ++
 src/mesa/drivers/dri/i965/bufmgr_fake.c | 16 ++++++++++++++--
 src/mesa/drivers/dri/i965/intel_blit.c  |  4 ++--
 3 files changed, 18 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/bufmgr.h b/src/mesa/drivers/dri/i965/bufmgr.h
index 6932522d3d3..e748c0d6d0b 100644
--- a/src/mesa/drivers/dri/i965/bufmgr.h
+++ b/src/mesa/drivers/dri/i965/bufmgr.h
@@ -199,9 +199,11 @@ void *bmFindVirtual( struct intel_context *intel,
  * For now they can stay, but will likely change/move before final:
  */
 unsigned bmSetFence( struct intel_context * );
+unsigned bmSetFenceLock( struct intel_context * );
 unsigned bmLockAndFence( struct intel_context *intel );
 int bmTestFence( struct intel_context *, unsigned fence );
 void bmFinishFence( struct intel_context *, unsigned fence );
+void bmFinishFenceLock( struct intel_context *, unsigned fence );
 
 void bm_fake_NotifyContendedLockTake( struct intel_context * );
 
diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c
index ed88ab3797a..205dc722c06 100644
--- a/src/mesa/drivers/dri/i965/bufmgr_fake.c
+++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c
@@ -338,7 +338,6 @@ static int evict_mru( struct intel_context *intel, GLuint *pool )
 }
 
 
-
 static int check_fenced( struct intel_context *intel )
 {
    struct bufmgr *bm = intel->bm;
@@ -1328,11 +1327,19 @@ unsigned bmSetFence( struct intel_context *intel )
    return intel->bm->last_fence;
 }
 
+unsigned bmSetFenceLock( struct intel_context *intel )
+{
+  LOCK(intel->bm);
+  bmSetFence(intel);
+  UNLOCK(intel->bm);
+}
 unsigned bmLockAndFence( struct intel_context *intel )
 {
    if (intel->bm->need_fence) {
       LOCK_HARDWARE(intel);
+      LOCK(intel->bm);
       bmSetFence(intel);
+      UNLOCK(intel->bm);
       UNLOCK_HARDWARE(intel);
    }
 
@@ -1350,7 +1357,12 @@ void bmFinishFence( struct intel_context *intel, unsigned fence )
    check_fenced(intel);
 }
 
-
+void bmFinishFenceLock( struct intel_context *intel, unsigned fence )
+{
+   LOCK(intel->bm);
+   bmFinishFence(intel, fence);
+   UNLOCK(intel->bm);
+}
 
 
 /* Specifically ignore texture memory sharing.
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index c8c5bf93c95..173d1d5b6c2 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -66,7 +66,7 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
    intelFlush( &intel->ctx );
 
 
-   bmFinishFence(intel, intel->last_swap_fence);
+   bmFinishFenceLock(intel, intel->last_swap_fence);
 
    /* The LOCK_HARDWARE is required for the cliprects.  Buffer offsets
     * should work regardless.
@@ -155,7 +155,7 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
 
    intel_batchbuffer_flush( intel->batch );
    intel->second_last_swap_fence = intel->last_swap_fence;
-   intel->last_swap_fence = bmSetFence( intel );
+   intel->last_swap_fence = bmSetFenceLock( intel );
    UNLOCK_HARDWARE( intel );
 
    if (!rect)
-- 
cgit v1.2.3


From adccb084df57ea5aef1b2ff9c21038ce1b89f7e3 Mon Sep 17 00:00:00 2001
From: Haihao Xiang <haihao.xiang@intel.com>
Date: Tue, 26 Dec 2006 16:45:02 -0800
Subject: Support linear format in i965. Fix bug #117 #118

---
 src/mesa/drivers/dri/i965/intel_context.c | 6 +++---
 src/mesa/drivers/dri/i965/intel_screen.c  | 6 +++++-
 src/mesa/drivers/dri/i965/intel_screen.h  | 1 +
 3 files changed, 9 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 6bcc984285c..1546b33108c 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -440,7 +440,7 @@ GLboolean intelInitContext( struct intel_context *intel,
 				 intelScreen->cpp,
 				 intelScreen->front.pitch / intelScreen->cpp,
 				 intelScreen->height,
-				 GL_FALSE);
+				 intelScreen->front.tiled != 0); /* 0: LINEAR */
 
 
    intel->back_region = 
@@ -451,7 +451,7 @@ GLboolean intelInitContext( struct intel_context *intel,
 				 intelScreen->cpp,
 				 intelScreen->back.pitch / intelScreen->cpp,
 				 intelScreen->height,
-				 (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+                                 intelScreen->back.tiled != 0);
 
    /* Still assuming front.cpp == depth.cpp
     *
@@ -467,7 +467,7 @@ GLboolean intelInitContext( struct intel_context *intel,
 				 intelScreen->cpp,
 				 intelScreen->depth.pitch / intelScreen->cpp,
 				 intelScreen->height,
-				 (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+                                 intelScreen->depth.tiled != 0);
    
    intel_bufferobj_init( intel );
    intel->batch = intel_batchbuffer_alloc( intel );
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 56e6a792fa2..8269deba664 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -230,16 +230,19 @@ intelUpdateScreenFromSAREA(intelScreenPrivate *intelScreen,
    intelScreen->front.pitch = sarea->pitch * intelScreen->cpp;
    intelScreen->front.handle = sarea->front_handle;
    intelScreen->front.size = sarea->front_size;
+   intelScreen->front.tiled = sarea->front_tiled;
 
    intelScreen->back.offset = sarea->back_offset;
    intelScreen->back.pitch = sarea->pitch * intelScreen->cpp;
    intelScreen->back.handle = sarea->back_handle;
    intelScreen->back.size = sarea->back_size;
-			 
+   intelScreen->back.tiled = sarea->back_tiled;
+
    intelScreen->depth.offset = sarea->depth_offset;
    intelScreen->depth.pitch = sarea->pitch * intelScreen->cpp;
    intelScreen->depth.handle = sarea->depth_handle;
    intelScreen->depth.size = sarea->depth_size;
+   intelScreen->depth.tiled = sarea->depth_tiled;
 
    intelScreen->tex.offset = sarea->tex_offset;
    intelScreen->logTextureGranularity = sarea->log_tex_granularity;
@@ -249,6 +252,7 @@ intelUpdateScreenFromSAREA(intelScreenPrivate *intelScreen,
    intelScreen->rotated.offset = sarea->rotated_offset;
    intelScreen->rotated.pitch = sarea->rotated_pitch * intelScreen->cpp;
    intelScreen->rotated.size = sarea->rotated_size;
+   intelScreen->rotated.tiled = sarea->rotated_tiled;
    intelScreen->current_rotation = sarea->rotation;
 #if 0
    matrix23Rotate(&intelScreen->rotMatrix,
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index 094158afd85..bf9a716082d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -42,6 +42,7 @@ typedef struct {
    char *map;           /* memory map */
    int offset;          /* from start of video mem, in bytes */
    int pitch;           /* row stride, in pixels */
+   unsigned int tiled; 
 } intelRegion;
 
 typedef struct 
-- 
cgit v1.2.3


From c171166987167db5e8ff67a09327283c0ef1b222 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Thu, 18 Jan 2007 14:41:38 +0800
Subject: 1. Fix bug #155 2. I notice multiple ARB_occlusion_query should be
 able to overlap according to spec.

3. Declaring extern variables in a .c file is evil, fix it.
---
 src/mesa/drivers/dri/i965/intel_context.c | 27 ++++++++++++++++-----------
 src/mesa/drivers/dri/i965/intel_context.h |  2 +-
 src/mesa/drivers/dri/i965/intel_screen.c  |  6 ++----
 3 files changed, 19 insertions(+), 16 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 0daa0ecb7e1..f730ea0582b 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -187,9 +187,17 @@ const struct dri_extension card_extensions[] =
     { NULL,                                NULL }
 };
 
-static const struct dri_extension arb_oc_extension = 
+const struct dri_extension arb_oc_extension = 
     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions};
 
+void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging)
+{	     
+	struct intel_context *intel = ctx?intel_context(ctx):NULL;
+	driInitExtensions(ctx, card_extensions, enable_imaging);
+	if (!ctx || intel->intelScreen->drmMinor >= 8)
+		driInitSingleExtension (ctx, &arb_oc_extension);
+}
+
 static const struct dri_debug_control debug_control[] =
 {
     { "fall",  DEBUG_FALLBACKS },
@@ -251,28 +259,29 @@ static void
 intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
 {
 	struct intel_context *intel = intel_context( ctx );
-	GLuint64EXT tmp = 0;	
 	drmI830MMIO io = {
 		.read_write = MMIO_WRITE,
 		.reg = MMIO_REGS_PS_DEPTH_COUNT,
-		.data = &tmp 
+		.data = &q->Result 
 	};
 	intel->stats_wm = GL_TRUE;
 	intelFinish(&intel->ctx);
-	drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
 }
 
 static void
 intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
 {
 	struct intel_context *intel = intel_context( ctx );
+	GLuint64EXT tmp;	
 	drmI830MMIO io = {
 		.read_write = MMIO_READ,
 		.reg = MMIO_REGS_PS_DEPTH_COUNT,
-		.data = &q->Result
+		.data = &tmp
 	};
 	intelFinish(&intel->ctx);
 	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	q->Result = tmp - q->Result;
 	q->Ready = GL_TRUE;
 	intel->stats_wm = GL_FALSE;
 }
@@ -412,12 +421,7 @@ GLboolean intelInitContext( struct intel_context *intel,
       _mesa_printf("IRQs not active.  Exiting\n");
       exit(1);
    }
- 
-   driInitExtensions( ctx, card_extensions, 
-		      GL_TRUE );
-
-   if (intel->intelScreen->drmMinor >= 8)
-      driInitSingleExtension (ctx, &arb_oc_extension);
+   intelInitExtensions(ctx, GL_TRUE); 
 
    INTEL_DEBUG  = driParseDebugString( getenv( "INTEL_DEBUG" ),
 				       debug_control );
@@ -696,3 +700,4 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
    _glthread_UNLOCK_MUTEX(lockMutex); 
 }
 
+
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 39eb7753017..d971b7ed419 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -501,6 +501,7 @@ void intelBitmap(GLcontext * ctx,
 		 const struct gl_pixelstore_attrib *unpack,
 		 const GLubyte * pixels);
 
+void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging);
 #define _NEW_WINDOW_POS 0x40000000
 
 
@@ -523,6 +524,5 @@ static inline struct intel_texture_image *intel_texture_image( struct gl_texture
    return (struct intel_texture_image *)img;
 }
 
-
 #endif
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 8269deba664..08f0bb340f7 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -38,6 +38,7 @@
 
 #include "intel_screen.h"
 
+#include "intel_context.h"
 #include "intel_tex.h"
 #include "intel_span.h"
 #include "intel_ioctl.h"
@@ -61,8 +62,6 @@ const GLuint __driNConfigOptions = 4;
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE*/
 
-extern const struct dri_extension card_extensions[];
-
 /**
  * Map all the memory regions described by the screen.
  * \return GL_TRUE if success, GL_FALSE if error.
@@ -687,7 +686,6 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc
 					(dri_priv->cpp == 2) ? 16 : 24,
 					(dri_priv->cpp == 2) ? 0  : 8,
 					GL_TRUE );
-
       /* Calling driInitExtensions here, with a NULL context pointer, does not actually
        * enable the extensions.  It just makes sure that all the dispatch offsets for all
        * the extensions that *might* be enables are known.  This is needed because the
@@ -696,7 +694,7 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc
        *
        * Hello chicken.  Hello egg.  How are you two today?
        */
-      driInitExtensions( NULL, card_extensions, GL_FALSE );
+      intelInitExtensions(NULL, GL_FALSE);
    }
 
    return (void *) psp;
-- 
cgit v1.2.3


From 6b6760d6bc23b98ee1de27ba78189e56e248ce9b Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Fri, 2 Feb 2007 10:01:42 +0800
Subject: Revert origin crestline pci id patch

---
 src/mesa/drivers/dri/i965/intel_context.c | 3 ---
 src/mesa/drivers/dri/i965/intel_context.h | 1 -
 2 files changed, 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index f730ea0582b..388600dbbe5 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -119,9 +119,6 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
       case PCI_CHIP_I946_GZ:
 	 chipset = "Intel(R) 946GZ"; break;
          break;
-      case PCI_CHIP_CRESTLINE:
-	 chipset = "Intel(R) Crestline"; break;
-         break;
       default:
 	 chipset = "Unknown Intel Chipset"; break;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index d971b7ed419..d51536c3fe8 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -384,7 +384,6 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I965_Q			0x2992
 #define PCI_CHIP_I965_G_1		0x2982
 #define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_CRESTLINE		0x2A02
 
 
 /* ================================================================
-- 
cgit v1.2.3


From 51bfb8fc8c78bb066d24e6ecbc20f00af7210386 Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Fri, 2 Feb 2007 10:04:48 +0800
Subject: Add Intel 965GM chipset info

---
 src/mesa/drivers/dri/i965/intel_context.c | 3 +++
 src/mesa/drivers/dri/i965/intel_context.h | 1 +
 2 files changed, 4 insertions(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 388600dbbe5..fea6e44f0b5 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -119,6 +119,9 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
       case PCI_CHIP_I946_GZ:
 	 chipset = "Intel(R) 946GZ"; break;
          break;
+      case PCI_CHIP_I965_GM:
+	 chipset = "Intel(R) 965GM"; break;
+         break;
       default:
 	 chipset = "Unknown Intel Chipset"; break;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index d51536c3fe8..74a795c96d2 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -384,6 +384,7 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I965_Q			0x2992
 #define PCI_CHIP_I965_G_1		0x2982
 #define PCI_CHIP_I946_GZ		0x2972
+#define PCI_CHIP_I965_GM                0x2A02
 
 
 /* ================================================================
-- 
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