From 822e791321c387cadcec562820a0521aae90cc77 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 21 Apr 2014 16:37:04 -0700 Subject: i965/skl: Set mask bits in PIPELINE_SELECT on Skylake. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Skylake has some extra bits in PIPELINE_SELECT, none of which are interesting for a 3D driver. In order to selectively change them, it also introduces new "mask bits" in 15:8. We care about the "Pipeline Selection" bits (1:0), so set the mask to 0x3. Signed-off-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg Reviewed-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e3980fc3408..99fcddc6a21 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -902,7 +902,7 @@ brw_upload_invariant_state(struct brw_context *brw) const uint32_t _3DSTATE_PIPELINE_SELECT = is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; BEGIN_BATCH(1); - OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0); + OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0)); ADVANCE_BATCH(); if (brw->gen < 6) { -- cgit v1.2.3