From 357495b94dad4101a5491ed30782574162de58db Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 25 Apr 2016 17:02:25 -0700 Subject: i965: Update compute workgroup size limit calculation for SIMD32. This should have the side effect of enabling the ARB_compute_shader extension on Gen8+ hardware and all Gen7 platforms that didn't previously expose it (VLV and IVB GT1) due to the number of hardware threads per subslice being insufficient in SIMD16 mode. v2: Bump workgroup size limit for GLES too (Jordan). Reviewed-by: Jason Ekstrand Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 552e5ec8925..2504dceb6a6 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -709,18 +709,10 @@ static void brw_initialize_cs_context_constants(struct brw_context *brw, unsigned max_threads) { struct gl_context *ctx = &brw->ctx; - - /* For ES, we set these constants based on SIMD8. - * - * TODO: Once we can always generate SIMD16, we should update this. - * - * For GL, we assume we can generate a SIMD16 program, but this currently - * is not always true. This allows us to run more test cases, and will be - * required based on desktop GL compute shader requirements. + /* Maximum number of scalar compute shader invocations that can be run in + * parallel in the same subslice assuming SIMD32 dispatch. */ - const int simd_size = ctx->API == API_OPENGL_CORE ? 16 : 8; - - const uint32_t max_invocations = simd_size * max_threads; + const uint32_t max_invocations = 32 * max_threads; ctx->Const.MaxComputeWorkGroupSize[0] = max_invocations; ctx->Const.MaxComputeWorkGroupSize[1] = max_invocations; ctx->Const.MaxComputeWorkGroupSize[2] = max_invocations; -- cgit v1.2.3