From 27f5fa7a3777332b2e60ccf10dc636ad84a3c478 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 28 May 2014 09:05:37 -0700 Subject: i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen Reviewed-by: Topi Pohjolainen Acked-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/intel_tex_validate.c') diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 38cee2a11d0..0bf0393803f 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -137,7 +137,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) depth, true, 0 /* num_samples */, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); if (!intelObj->mt) return false; } -- cgit v1.2.3