From 31f3dfd59b6687214402c395ee03e7498fd6c79a Mon Sep 17 00:00:00 2001 From: Paul Berry Date: Tue, 8 May 2012 15:30:33 -0700 Subject: i965/msaa: Validate Gen7 surface state constraints. When a Gen7 SURFACE_STATE is configured for MSAA, a number of additional constaints come in to play. This patch adds a function gen7_check_surface_setup() which verifies that all of those constraints are met. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965/gen7_blorp.cpp') diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 58da3893d0a..c860cbf7c78 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -136,7 +136,8 @@ static uint32_t gen7_blorp_emit_surface_state(struct brw_context *brw, const brw_blorp_params *params, const brw_blorp_surface_info *surface, - uint32_t read_domains, uint32_t write_domain) + uint32_t read_domains, uint32_t write_domain, + bool is_render_target) { struct intel_context *intel = &brw->intel; @@ -204,6 +205,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, surf->ss1.base_addr - region->bo->offset, read_domains, write_domain); + gen7_check_surface_setup(surf, is_render_target); + return wm_surf_offset; } @@ -758,10 +761,12 @@ gen7_blorp_exec(struct intel_context *intel, wm_surf_offset_renderbuffer = gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + I915_GEM_DOMAIN_RENDER, + true /* is_render_target */); wm_surf_offset_texture = gen7_blorp_emit_surface_state(brw, params, ¶ms->src, - I915_GEM_DOMAIN_SAMPLER, 0); + I915_GEM_DOMAIN_SAMPLER, 0, + false /* is_render_target */); wm_bind_bo_offset = gen6_blorp_emit_binding_table(brw, params, wm_surf_offset_renderbuffer, -- cgit v1.2.3