From 588ec545acc930470c605005292c8ef10adf4919 Mon Sep 17 00:00:00 2001 From: Paul Berry Date: Sat, 31 Aug 2013 20:23:49 -0700 Subject: i965/gen7.5: Fix lower bound on number of VS URB entries. Haswell GT2 and GT3 require the number of vertex shader URB entries to be at least 64, not 32. At the moment, we always meet this requirement automatically, because in the absence of a geometry shader, we assign all available URB space to the vertex shader. But when we turn on support for geometry shaders, this lower limit will become important. Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/gen6_urb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/gen6_urb.c') diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index e16d30aa13a..bb4cfa80a49 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -83,7 +83,7 @@ gen6_upload_urb( struct brw_context *brw ) brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); - assert(brw->urb.nr_vs_entries >= 24); + assert(brw->urb.nr_vs_entries >= brw->urb.min_vs_entries); assert(brw->urb.nr_vs_entries % 4 == 0); assert(brw->urb.nr_gs_entries % 4 == 0); assert(vs_size < 5); -- cgit v1.2.3