From a16d47465ecdbaef0548207c1bc037493a67ebec Mon Sep 17 00:00:00 2001 From: Chad Versace Date: Thu, 18 Jul 2013 09:58:06 -0700 Subject: i965/hsw: Change L3 MOCS of 3DSTATE_VERTEX_BUFFERS Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. Reviewed-by: Kenneth Graunke Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mesa/drivers/dri/i965/gen6_blorp.cpp') diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 8056bf557a1..a4a90817a8c 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -163,6 +163,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw, if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; + if (brw->is_haswell) + dw0 |= GEN7_MOCS_L3 << 16; + BEGIN_BATCH(batch_length); OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); OUT_BATCH(dw0); -- cgit v1.2.3