From 56cdb55e38ca352a0d521d7aa69b46ffbd855192 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Tue, 9 Jul 2013 15:36:32 -0700 Subject: i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface (bf25ee2 for gen6) Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. We also must disable brw_workaround_depthstencil_alignment for gen >= 6. Now the hardware will handle alignment when rendering to additional slices/LODs. v3: * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2 Signed-off-by: Jordan Justen Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127 Reviewed-by: Topi Pohjolainen Acked-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c') diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 76e22bd5ac9..e3980fc3408 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -261,10 +261,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, if (stencil_irb) brw->depthstencil.stencil_mt = get_stencil_miptree(stencil_irb); - /* Gen7+ doesn't require the workarounds, since we always program the + /* Gen6+ doesn't require the workarounds, since we always program the * surface state at the start of the whole surface. */ - if (brw->gen >= 7) + if (brw->gen >= 6) return; /* Check if depth buffer is in depth/stencil format. If so, then it's only -- cgit v1.2.3