From f7ef8ec9d8f56b77029534952628c3204c4d5f63 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 27 Aug 2014 11:32:08 -0700 Subject: i965/fs: Implement support for ir_barrier Signed-off-by: Jordan Justen Reviewed-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_fs_visitor.cpp') diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 588966b66f1..4770838b26f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1953,6 +1953,29 @@ fs_visitor::emit_cs_terminate() inst->eot = true; } +void +fs_visitor::emit_barrier() +{ + assert(brw->gen >= 7); + + /* We are getting the barrier ID from the compute shader header */ + assert(stage == MESA_SHADER_COMPUTE); + + fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); + + /* Clear the message payload */ + fs_inst *inst = bld.exec_all().MOV(payload, fs_reg(0u)); + + /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */ + fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)); + inst = bld.exec_all().AND(component(payload, 2), r0_2, fs_reg(0x0f000000u)); + + /* Emit a gateway "barrier" message using the payload we set up, followed + * by a wait instruction. + */ + bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload); +} + fs_visitor::fs_visitor(struct brw_context *brw, void *mem_ctx, gl_shader_stage stage, -- cgit v1.2.3