From ea681a0d64ecde3a2e729fe3b71d3f3fe4cedff0 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 9 Nov 2012 01:05:47 -0800 Subject: i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt Reviewed-by: Paul Berry --- src/mesa/drivers/dri/i965/brw_fs.h | 110 +++++++++++++++++++++++++------------ 1 file changed, 76 insertions(+), 34 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_fs.h') diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 8225e66eaa8..489b9700523 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -180,6 +180,11 @@ public: /** @} */ }; +/** + * The fragment shader front-end. + * + * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR. + */ class fs_visitor : public backend_visitor { public: @@ -293,40 +298,6 @@ public: void push_force_sechalf(); void pop_force_sechalf(); - void generate_code(); - void generate_fb_write(fs_inst *inst); - void generate_pixel_xy(struct brw_reg dst, bool is_x); - void generate_linterp(fs_inst *inst, struct brw_reg dst, - struct brw_reg *src); - void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src); - void generate_math1_gen7(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src); - void generate_math2_gen7(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - void generate_math1_gen6(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src); - void generate_math2_gen6(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - void generate_math_gen4(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src); - void generate_discard(fs_inst *inst); - void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src); - void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src, - bool negate_value); - void generate_spill(fs_inst *inst, struct brw_reg src); - void generate_unspill(fs_inst *inst, struct brw_reg dst); - void generate_pull_constant_load(fs_inst *inst, struct brw_reg dst, - struct brw_reg index, - struct brw_reg offset); - void generate_mov_dispatch_to_flags(); - void emit_dummy_fs(); fs_reg *emit_fragcoord_interpolation(ir_variable *ir); fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp, @@ -456,6 +427,77 @@ public: int force_sechalf_stack; }; +/** + * The fragment shader code generator. + * + * Translates FS IR to actual i965 assembly code. + */ +class fs_generator +{ +public: + fs_generator(struct brw_context *brw, + struct brw_wm_compile *c, + struct gl_shader_program *prog, + struct gl_fragment_program *fp, + bool dual_source_output); + ~fs_generator(); + + const unsigned *generate_assembly(exec_list *simd8_instructions, + exec_list *simd16_instructions, + unsigned *assembly_size); + +private: + void generate_code(exec_list *instructions); + void generate_fb_write(fs_inst *inst); + void generate_pixel_xy(struct brw_reg dst, bool is_x); + void generate_linterp(fs_inst *inst, struct brw_reg dst, + struct brw_reg *src); + void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src); + void generate_math1_gen7(fs_inst *inst, + struct brw_reg dst, + struct brw_reg src); + void generate_math2_gen7(fs_inst *inst, + struct brw_reg dst, + struct brw_reg src0, + struct brw_reg src1); + void generate_math1_gen6(fs_inst *inst, + struct brw_reg dst, + struct brw_reg src); + void generate_math2_gen6(fs_inst *inst, + struct brw_reg dst, + struct brw_reg src0, + struct brw_reg src1); + void generate_math_gen4(fs_inst *inst, + struct brw_reg dst, + struct brw_reg src); + void generate_discard(fs_inst *inst); + void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src); + void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src, + bool negate_value); + void generate_spill(fs_inst *inst, struct brw_reg src); + void generate_unspill(fs_inst *inst, struct brw_reg dst); + void generate_pull_constant_load(fs_inst *inst, struct brw_reg dst, + struct brw_reg index, + struct brw_reg offset); + void generate_mov_dispatch_to_flags(); + + struct brw_context *brw; + struct intel_context *intel; + struct gl_context *ctx; + + struct brw_compile *p; + struct brw_wm_compile *c; + + struct gl_shader_program *prog; + struct gl_shader *shader; + const struct gl_fragment_program *fp; + + unsigned dispatch_width; /**< 8 or 16 */ + + bool dual_source_output; + void *mem_ctx; +}; + bool brw_do_channel_expressions(struct exec_list *instructions); bool brw_do_vector_splitting(struct exec_list *instructions); bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog); -- cgit v1.2.3