From 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Mon, 13 Jul 2009 10:48:43 +0800 Subject: i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai ) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout --- src/mesa/drivers/dri/i965/brw_clip.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/brw_clip.h') diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index e06747864b5..12e8548df1f 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -117,6 +117,7 @@ struct brw_clip_compile { GLuint header_position_offset; GLuint offset[VERT_ATTRIB_MAX]; + GLboolean need_ff_sync; }; #define ATTR_SIZE (4*4) @@ -171,5 +172,5 @@ struct brw_reg get_tmp( struct brw_clip_compile *c ); void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos ); - +void brw_clip_ff_sync(struct brw_clip_compile *c); #endif -- cgit v1.2.3