From 309c156bae59124be17137d0f559d2c054231f7c Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sat, 26 Dec 2009 15:55:38 -0800 Subject: i915: Fix assert. --- src/mesa/drivers/dri/i915/i915_program.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i915') diff --git a/src/mesa/drivers/dri/i915/i915_program.c b/src/mesa/drivers/dri/i915/i915_program.c index e87700f8e0a..ce2c9756116 100644 --- a/src/mesa/drivers/dri/i915/i915_program.c +++ b/src/mesa/drivers/dri/i915/i915_program.c @@ -239,7 +239,7 @@ GLuint i915_emit_texld( struct i915_fragment_program *p, } else { assert(GET_UREG_TYPE(dest) != REG_TYPE_CONST); - assert(dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest))); + assert(dest == UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest))); /* Can't use unsaved temps for coords, as the phase boundary would result * in the contents becoming undefined. */ -- cgit v1.2.3 From c67bb15d4e3da430d511444bd7d159ccb0c84b73 Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Mon, 28 Dec 2009 18:46:15 -0800 Subject: intel: Silence compiler warnings. --- src/mesa/drivers/dri/i915/intel_render.c | 4 ++-- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 ++++-- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 +- src/mesa/drivers/dri/intel/intel_context.h | 8 ++++---- src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 2 +- src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +- 9 files changed, 16 insertions(+), 14 deletions(-) (limited to 'src/mesa/drivers/dri/i915') diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c index 410052b3c2b..ec209391ab4 100644 --- a/src/mesa/drivers/dri/i915/intel_render.c +++ b/src/mesa/drivers/dri/i915/intel_render.c @@ -117,7 +117,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim) intel_set_prim(intel, hw_prim[prim]); } -static inline GLuint intel_get_vb_max(struct intel_context *intel) +static INLINE GLuint intel_get_vb_max(struct intel_context *intel) { GLuint ret; @@ -129,7 +129,7 @@ static inline GLuint intel_get_vb_max(struct intel_context *intel) return ret; } -static inline GLuint intel_get_current_max(struct intel_context *intel) +static INLINE GLuint intel_get_current_max(struct intel_context *intel) { if (intel->intelScreen->no_vbo) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 271a88dae0b..c66f43abae1 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -249,8 +249,10 @@ static void wrap_buffers( struct brw_context *brw, */ /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH FAKE TO PUSH THIS STUFF */ -// if (!brw->intel.ttm) -// dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); + /* + if (!brw->intel.ttm) + dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); + */ } static void get_space( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 7a4c046a49b..c8fb0a288f2 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -199,7 +199,7 @@ void brw_set_src1( struct brw_instruction *insn, * in the future: */ assert (reg.address_mode == BRW_ADDRESS_DIRECT); - //assert (reg.file == BRW_GENERAL_REGISTER_FILE); + /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */ if (insn->header.access_mode == BRW_ALIGN_1) { insn->bits3.da1.src1_subreg_nr = reg.subnr; diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index b129b1f1c3f..14d5319796a 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -35,7 +35,7 @@ #include "brw_context.h" -static inline void +static INLINE void brw_add_validated_bo(struct brw_context *brw, dri_bo *bo) { assert(brw->state.validated_bo_count < ARRAY_SIZE(brw->state.validated_bos)); diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 5390fd25849..66fb611d506 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1084,7 +1084,7 @@ static void emit_kil_nv( struct brw_wm_compile *c ) brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK + brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ brw_AND(p, r0uw, c->emit_mask_reg, r0uw); brw_pop_insn_state(p); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index e8c2cb66ec3..7e5533e258e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -743,7 +743,7 @@ static void emit_kil(struct brw_wm_compile *c) struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK + brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ brw_AND(p, depth, c->emit_mask_reg, depth); brw_pop_insn_state(p); } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index eb7be7ddd0f..1afec09a34f 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -354,14 +354,14 @@ extern char *__progname; #define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) #define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0) -static inline uint32_t +static INLINE uint32_t U_FIXED(float value, uint32_t frac_bits) { value *= (1 << frac_bits); return value < 0 ? 0 : value; } -static inline uint32_t +static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) { return value * (1 << frac_bits); @@ -588,7 +588,7 @@ is_power_of_two(uint32_t value) return (value & (value - 1)) == 0; } -static inline void +static INLINE void intel_bo_map_gtt_preferred(struct intel_context *intel, drm_intel_bo *bo, GLboolean write) @@ -599,7 +599,7 @@ intel_bo_map_gtt_preferred(struct intel_context *intel, drm_intel_bo_map(bo, write); } -static inline void +static INLINE void intel_bo_unmap_gtt_preferred(struct intel_context *intel, drm_intel_bo *bo) { diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index 9545ef4b49d..19ca5152429 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -166,7 +166,7 @@ static GLuint get_bitmap_rect(GLsizei width, GLsizei height, * Returns the low Y value of the vertical range given, flipped according to * whether the framebuffer is or not. */ -static inline int +static INLINE int y_flip(struct gl_framebuffer *fb, int y, int height) { if (fb->Name != 0) diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 767d04d2f4b..ee953cfbe78 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -109,7 +109,7 @@ do_copy_texsubimage(struct intel_context *intel, return GL_FALSE; } - // intelFlush(ctx); + /* intelFlush(ctx); */ LOCK_HARDWARE(intel); { drm_intel_bo *dst_bo = intel_region_buffer(intel, -- cgit v1.2.3