From 89a96c8f43370cc84adf92ab32e3de302a1fa1d0 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 12 Sep 2016 12:58:38 -0700 Subject: anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW Without this bit set, the value in "L3 Atomic Disable" won't get applied by the hardware so we won't properly get L3 atomic caching. Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of the dEQP-VK.image.atomic_operations.* tests on HSW Signed-off-by: Jason Ekstrand Reviewed-by: Francisco Jerez --- src/intel/vulkan/genX_cmd_buffer.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/intel/vulkan/genX_cmd_buffer.c') diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b6f93e7740d..6a84383c9ad 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -296,6 +296,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, anv_pack_struct(&scratch1, GENX(SCRATCH1), .L3AtomicDisable = !has_dc); anv_pack_struct(&chicken3, GENX(CHICKEN3), + .L3AtomicDisableMask = true, .L3AtomicDisable = !has_dc); emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1); emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3); -- cgit v1.2.3