From c3bd7114113e959a185f7cdb8c884b4a10a199c8 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 1 Sep 2016 22:25:50 -0700 Subject: intel/isl: Remove tiling checks from choose_msaa_layout We already do those checks in filter_tiling. There's no good reason to repeat them in choose_msaa_layout. If anything they should have been asserts and not "return false" checks. Also, this check was causing us to outright reject multisampled HiZ surfaces which wasn't intended. Signed-off-by: Jason Ekstrand Reviewed-by: Chad Versace Reviewed-by: Nanley Chery --- src/intel/isl/isl_gen7.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/intel/isl/isl_gen7.c') diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index 022dd866a74..805b62badaf 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -249,9 +249,13 @@ gen6_filter_tiling(const struct isl_device *dev, * For multisample render targets, this field must be 1 (true). MSRTs * can only be tiled. * - * Multisample surfaces never require X tiling, and Y tiling generally - * performs better than X. So choose Y. (Unless it's stencil, then it - * must be W). + * From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Tile Mode: + * + * If Number of Multisamples is not MULTISAMPLECOUNT_1, this field + * must be YMAJOR. + * + * As usual, though, stencil is special and requires W-tiling. */ *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT); } -- cgit v1.2.3