From ceed55e7bba30b60a727309616d6f7e3c2e48a5a Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 5 Jun 2017 08:31:01 -0700 Subject: intel/genxml: Add Gen10 CACHE_MODE_1 definitions Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat Reviewed-by: Rafael Antognolli --- src/intel/genxml/gen10.xml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/intel/genxml') diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index d2bb130004e..a19674a435f 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -3734,4 +3734,22 @@ + + + + + + + + + + + + + + + + + + -- cgit v1.2.3