From 1811cbdc25371362fcc7ab3dfe49bb020f7cc849 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 25 Apr 2016 17:29:57 -0700 Subject: intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flow The hardware's control flow logic is 16-wide so we're out of luck here. We could, in theory, support SIMD32 if we know the control-flow is uniform but we don't have that information at this point. Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- src/intel/compiler/brw_fs_nir.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/intel/compiler') diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index e324519afc1..9273b300241 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -385,6 +385,10 @@ fs_visitor::nir_emit_if(nir_if *if_stmt) nir_emit_cf_list(&if_stmt->else_list); bld.emit(BRW_OPCODE_ENDIF); + + if (devinfo->gen < 7) + limit_dispatch_width(16, "Non-uniform control flow unsupported " + "in SIMD32 mode."); } void @@ -395,6 +399,10 @@ fs_visitor::nir_emit_loop(nir_loop *loop) nir_emit_cf_list(&loop->body); bld.emit(BRW_OPCODE_WHILE); + + if (devinfo->gen < 7) + limit_dispatch_width(16, "Non-uniform control flow unsupported " + "in SIMD32 mode."); } void -- cgit v1.2.3