From 812ede088f5f6bea4e6fba991bd59d5cce264212 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 6 Dec 2018 14:11:34 -0800 Subject: intel/fs: Implement quad swizzles on ICL+. Align16 is no longer a thing, so a new implementation is provided using Align1 instead. Not all possible swizzles can be represented as a single Align1 region, but some fast paths are provided for frequently used swizzles that can be represented efficiently in Align1 mode. Fixes ~90 subgroup quad swap Vulkan CTS tests. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Iago Toral Quiroga --- src/intel/compiler/brw_fs.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/intel/compiler/brw_fs.h') diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 53d9b6ce7bf..dc36ecc21ac 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -480,6 +480,10 @@ private: struct brw_reg src, struct brw_reg idx); + void generate_quad_swizzle(const fs_inst *inst, + struct brw_reg dst, struct brw_reg src, + unsigned swiz); + bool patch_discard_jumps_to_fb_writes(); const struct brw_compiler *compiler; -- cgit v1.2.3