From 4588f4a6048af2ae1b3a2eb33fd23227c1edf593 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Thu, 26 Apr 2018 10:26:22 +0200 Subject: intel/compiler: handle extended math restrictions for half-float Extended math with half-float operands is only supported since gen9, but it is limited to SIMD8. In gen8 we lower it to 32-bit. v2: quashed together the following patches (Jason): - intel/compiler: allow extended math functions with HF operands - intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 - intel/compiler: extended Math is limited to SIMD8 on half-float Reviewed-by: Jason Ekstrand Reviewed-by: Topi Pohjolainen (allow extended math functions with HF operands, extended Math is limited to SIMD8 on half-float) --- src/intel/compiler/brw_eu_emit.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/intel/compiler/brw_eu_emit.c') diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 94e247e1a39..d58919638d5 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -1916,8 +1916,10 @@ void gen6_math(struct brw_codegen *p, assert(src1.file == BRW_GENERAL_REGISTER_FILE || (devinfo->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE)); } else { - assert(src0.type == BRW_REGISTER_TYPE_F); - assert(src1.type == BRW_REGISTER_TYPE_F); + assert(src0.type == BRW_REGISTER_TYPE_F || + (src0.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9)); + assert(src1.type == BRW_REGISTER_TYPE_F || + (src1.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9)); } /* Source modifiers are ignored for extended math instructions on Gen6. */ -- cgit v1.2.3