From 03c07ac5480886ef5f5bd4cff4a7b6d20e142bc9 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 28 Apr 2017 01:22:39 -0700 Subject: anv: Add support for SPIR-V 1.3 subgroup operations This requires us to bump the subgroup size to 32 for all shader stages because Vulkan requires that to be a physical device query. Reviewed-by: Iago Toral Quiroga --- src/intel/compiler/brw_compiler.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/intel/compiler/brw_compiler.h') diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index d8287dca69a..0e27c898203 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -113,6 +113,14 @@ struct brw_compiler { bool supports_pull_constants; }; +/** + * We use a constant subgroup size of 32. It really only needs to be a + * maximum and, since we do SIMD32 for compute shaders in some cases, it + * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a + * subgroup size of 32 but will act as if 16 or 24 of those channels are + * disabled. + */ +#define BRW_SUBGROUP_SIZE 32 /** * Program key structures. -- cgit v1.2.3