From e551040c602d392019e68f54d9a3a310d2a937a3 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Thu, 14 Feb 2019 23:08:39 -0800 Subject: nir/glsl: Add another way of doing lower_imul64 for gen8+ On Gen 8 and 9, "mul" instruction supports 64 bit destination type. We can reduce our 64x64 int multiplication from 4 instructions to 3. Also instead of emitting two mul instructions, we can emit single mul instuction and extract low/high 32 bits from 64 bit result for [i/u]mulExtended v2: 1) Allow lower_mul_high64 to use new opcode (Jason Ekstrand) 2) Add lower_mul_2x32_64 flag (Matt Turner) 3) Remove associative property as bit size is different (Connor Abbott) v3: Fix indentation and variable naming convention (Jason Ekstrand) Signed-off-by: Sagar Ghuge Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_compiler.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/intel/compiler/brw_compiler.c') diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index b3df0d9fa23..28793b1f0e6 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -171,6 +171,13 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) fp64_options |= nir_lower_fp64_full_software; } + /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that + * destination type can be Quadword and source type Doubleword for Gen8 and + * Gen9. So, lower 64 bit multiply instruction on rest of the platforms. + */ + if (devinfo->gen < 8 || devinfo->gen > 9) + int64_options |= nir_lower_imul_2x32_64; + /* We want the GLSL compiler to emit code that uses condition codes */ for (int i = 0; i < MESA_SHADER_STAGES; i++) { compiler->glsl_compiler_options[i].MaxUnrollIterations = 0; -- cgit v1.2.3